drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc_features.h"
  27 #include "display_mode_enums.h"
  28
  29 /**
  30  * DOC: overview
  31  *
  32  * Most of the DML code is automatically generated and tested via hardware
  33  * description language. Usually, we use the reference _vcs_dpi in the code
  34  * where VCS means "Verilog Compiled Simulator" and DPI stands for "Direct
  35  * Programmer Interface". In other words, those structs can be used to
  36  * interface with Verilog with other languages such as C.
  37  */
  38
  39 #ifndef __DISPLAY_MODE_STRUCTS_H__
  40 #define __DISPLAY_MODE_STRUCTS_H__
  41
  42 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
  43 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
  44 typedef struct _vcs_dpi_ip_params_st ip_params_st;
  45 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
  46 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
  47 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
  48 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
  49 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
  50 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
  51 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
  52 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
  53 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
  54 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
  55 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
  56 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
  57 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
  58 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
  59 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
  60 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
  61 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
  62 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
  63 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
  64 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
  65 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
  66
  67 typedef struct {
  68         double UrgentWatermark;
  69         double WritebackUrgentWatermark;
  70         double DRAMClockChangeWatermark;
  71         double FCLKChangeWatermark;
  72         double WritebackDRAMClockChangeWatermark;
  73         double WritebackFCLKChangeWatermark;
  74         double StutterExitWatermark;
  75         double StutterEnterPlusExitWatermark;
  76         double Z8StutterExitWatermark;
  77         double Z8StutterEnterPlusExitWatermark;
  78         double USRRetrainingWatermark;
  79 } Watermarks;
  80
  81 typedef struct {
  82         double UrgentLatency;
  83         double ExtraLatency;
  84         double WritebackLatency;
  85         double DRAMClockChangeLatency;
  86         double FCLKChangeLatency;
  87         double SRExitTime;
  88         double SREnterPlusExitTime;
  89         double SRExitZ8Time;
  90         double SREnterPlusExitZ8Time;
  91         double USRRetrainingLatencyPlusSMNLatency;
  92 } Latencies;
  93
  94 typedef struct {
  95         double Dppclk;
  96         double Dispclk;
  97         double PixelClock;
  98         double DCFClkDeepSleep;
  99         unsigned int DPPPerSurface;
 100         bool ScalerEnabled;
 101         enum dm_rotation_angle SourceRotation;
 102         unsigned int ViewportHeight;
 103         unsigned int ViewportHeightChroma;
 104         unsigned int BlockWidth256BytesY;
 105         unsigned int BlockHeight256BytesY;
 106         unsigned int BlockWidth256BytesC;
 107         unsigned int BlockHeight256BytesC;
 108         unsigned int BlockWidthY;
 109         unsigned int BlockHeightY;
 110         unsigned int BlockWidthC;
 111         unsigned int BlockHeightC;
 112         unsigned int InterlaceEnable;
 113         unsigned int NumberOfCursors;
 114         unsigned int VBlank;
 115         unsigned int HTotal;
 116         unsigned int HActive;
 117         bool DCCEnable;
 118         enum odm_combine_mode ODMMode;
 119         enum source_format_class SourcePixelFormat;
 120         enum dm_swizzle_mode SurfaceTiling;
 121         unsigned int BytePerPixelY;
 122         unsigned int BytePerPixelC;
 123         bool ProgressiveToInterlaceUnitInOPP;
 124         double VRatio;
 125         double VRatioChroma;
 126         unsigned int VTaps;
 127         unsigned int VTapsChroma;
 128         unsigned int PitchY;
 129         unsigned int DCCMetaPitchY;
 130         unsigned int PitchC;
 131         unsigned int DCCMetaPitchC;
 132         bool ViewportStationary;
 133         unsigned int ViewportXStart;
 134         unsigned int ViewportYStart;
 135         unsigned int ViewportXStartC;
 136         unsigned int ViewportYStartC;
 137         bool FORCE_ONE_ROW_FOR_FRAME;
 138         unsigned int SwathHeightY;
 139         unsigned int SwathHeightC;
 140 } DmlPipe;
 141
 142 typedef struct {
 143         double UrgentLatency;
 144         double ExtraLatency;
 145         double WritebackLatency;
 146         double DRAMClockChangeLatency;
 147         double FCLKChangeLatency;
 148         double SRExitTime;
 149         double SREnterPlusExitTime;
 150         double SRExitZ8Time;
 151         double SREnterPlusExitZ8Time;
 152         double USRRetrainingLatency;
 153         double SMNLatency;
 154 } SOCParametersList;
 155
 156 struct _vcs_dpi_voltage_scaling_st {
 157         int state;
 158         double dscclk_mhz;
 159         double dcfclk_mhz;
 160         double socclk_mhz;
 161         double phyclk_d18_mhz;
 162         double phyclk_d32_mhz;
 163         double dram_speed_mts;
 164         double fabricclk_mhz;
 165         double dispclk_mhz;
 166         double dram_bw_per_chan_gbps;
 167         double phyclk_mhz;
 168         double dppclk_mhz;
 169         double dtbclk_mhz;
 170         float net_bw_in_kbytes_sec;
 171 };
 172
 173 /**
 174  * _vcs_dpi_soc_bounding_box_st: SOC definitions
 175  *
 176  * This struct maintains the SOC Bounding Box information for the ASIC; it
 177  * defines things such as clock, voltage, performance, etc. Usually, we load
 178  * these values from VBIOS; if something goes wrong, we use some hard-coded
 179  * values, which will enable the ASIC to light up with limitations.
 180  */
 181 struct _vcs_dpi_soc_bounding_box_st {
 182         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 183         /**
 184          * @num_states: It represents the total of Display Power Management
 185          * (DPM) supported by the specific ASIC.
 186          */
 187         unsigned int num_states;
 188         double sr_exit_time_us;
 189         double sr_enter_plus_exit_time_us;
 190         double sr_exit_z8_time_us;
 191         double sr_enter_plus_exit_z8_time_us;
 192         double urgent_latency_us;
 193         double urgent_latency_pixel_data_only_us;
 194         double urgent_latency_pixel_mixed_with_vm_data_us;
 195         double urgent_latency_vm_data_only_us;
 196         double usr_retraining_latency_us;
 197         double smn_latency_us;
 198         double fclk_change_latency_us;
 199         double mall_allocated_for_dcn_mbytes;
 200         double pct_ideal_fabric_bw_after_urgent;
 201         double pct_ideal_dram_bw_after_urgent_strobe;
 202         double max_avg_fabric_bw_use_normal_percent;
 203         double max_avg_dram_bw_use_normal_strobe_percent;
 204         enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final;
 205         bool dram_clock_change_requirement_final;
 206         double writeback_latency_us;
 207         double ideal_dram_bw_after_urgent_percent;
 208         double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
 209         double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
 210         double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
 211         double pct_ideal_sdp_bw_after_urgent;
 212         double max_avg_sdp_bw_use_normal_percent;
 213         double max_avg_dram_bw_use_normal_percent;
 214         unsigned int max_request_size_bytes;
 215         double downspread_percent;
 216         double dram_page_open_time_ns;
 217         double dram_rw_turnaround_time_ns;
 218         double dram_return_buffer_per_channel_bytes;
 219         double dram_channel_width_bytes;
 220         double fabric_datapath_to_dcn_data_return_bytes;
 221         double dcn_downspread_percent;
 222         double dispclk_dppclk_vco_speed_mhz;
 223         double dfs_vco_period_ps;
 224         unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
 225         unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
 226         unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
 227         unsigned int round_trip_ping_latency_dcfclk_cycles;
 228         unsigned int urgent_out_of_order_return_per_channel_bytes;
 229         unsigned int channel_interleave_bytes;
 230         unsigned int num_banks;
 231         unsigned int num_chans;
 232         unsigned int vmm_page_size_bytes;
 233         unsigned int hostvm_min_page_size_bytes;
 234         unsigned int gpuvm_min_page_size_bytes;
 235         double dram_clock_change_latency_us;
 236         double dummy_pstate_latency_us;
 237         double writeback_dram_clock_change_latency_us;
 238         unsigned int return_bus_width_bytes;
 239         unsigned int voltage_override;
 240         double xfc_bus_transport_time_us;
 241         double xfc_xbuf_latency_tolerance_us;
 242         int use_urgent_burst_bw;
 243         double min_dcfclk;
 244         bool do_urgent_latency_adjustment;
 245         double urgent_latency_adjustment_fabric_clock_component_us;
 246         double urgent_latency_adjustment_fabric_clock_reference_mhz;
 247         bool disable_dram_clock_change_vactive_support;
 248         bool allow_dram_clock_one_display_vactive;
 249         enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank;
 250         double max_vratio_pre;
 251 };
 252
 253 /**
 254  * @_vcs_dpi_ip_params_st: IP configuraion for DCN blocks
 255  *
 256  * In this struct you can find the DCN configuration associated to the specific
 257  * ASIC. For example, here we can save how many DPPs the ASIC is using and it
 258  * is available.
 259  *
 260  */
 261 struct _vcs_dpi_ip_params_st {
 262         bool use_min_dcfclk;
 263         bool clamp_min_dcfclk;
 264         bool gpuvm_enable;
 265         bool hostvm_enable;
 266         bool dsc422_native_support;
 267         unsigned int gpuvm_max_page_table_levels;
 268         unsigned int hostvm_max_page_table_levels;
 269         unsigned int hostvm_cached_page_table_levels;
 270         unsigned int pte_group_size_bytes;
 271         unsigned int max_inter_dcn_tile_repeaters;
 272         unsigned int num_dsc;
 273         unsigned int odm_capable;
 274         unsigned int rob_buffer_size_kbytes;
 275         unsigned int det_buffer_size_kbytes;
 276         unsigned int min_comp_buffer_size_kbytes;
 277         unsigned int dpte_buffer_size_in_pte_reqs_luma;
 278         unsigned int dpte_buffer_size_in_pte_reqs_chroma;
 279         unsigned int pde_proc_buffer_size_64k_reqs;
 280         unsigned int dpp_output_buffer_pixels;
 281         unsigned int opp_output_buffer_lines;
 282         unsigned int pixel_chunk_size_kbytes;
 283         unsigned int alpha_pixel_chunk_size_kbytes;
 284         unsigned int min_pixel_chunk_size_bytes;
 285         unsigned int dcc_meta_buffer_size_bytes;
 286         unsigned char pte_enable;
 287         unsigned int pte_chunk_size_kbytes;
 288         unsigned int meta_chunk_size_kbytes;
 289         unsigned int min_meta_chunk_size_bytes;
 290         unsigned int writeback_chunk_size_kbytes;
 291         unsigned int line_buffer_size_bits;
 292         unsigned int max_line_buffer_lines;
 293         unsigned int writeback_luma_buffer_size_kbytes;
 294         unsigned int writeback_chroma_buffer_size_kbytes;
 295         unsigned int writeback_chroma_line_buffer_width_pixels;
 296
 297         unsigned int writeback_interface_buffer_size_kbytes;
 298         unsigned int writeback_line_buffer_buffer_size;
 299
 300         unsigned int writeback_10bpc420_supported;
 301         double writeback_max_hscl_ratio;
 302         double writeback_max_vscl_ratio;
 303         double writeback_min_hscl_ratio;
 304         double writeback_min_vscl_ratio;
 305         unsigned int maximum_dsc_bits_per_component;
 306         unsigned int maximum_pixels_per_line_per_dsc_unit;
 307         unsigned int writeback_max_hscl_taps;
 308         unsigned int writeback_max_vscl_taps;
 309         unsigned int writeback_line_buffer_luma_buffer_size;
 310         unsigned int writeback_line_buffer_chroma_buffer_size;
 311
 312         unsigned int max_page_table_levels;
 313         /**
 314          * @max_num_dpp: Maximum number of DPP supported in the target ASIC.
 315          */
 316         unsigned int max_num_dpp;
 317         unsigned int max_num_otg;
 318         unsigned int cursor_chunk_size;
 319         unsigned int cursor_buffer_size;
 320         unsigned int max_num_wb;
 321         unsigned int max_dchub_pscl_bw_pix_per_clk;
 322         unsigned int max_pscl_lb_bw_pix_per_clk;
 323         unsigned int max_lb_vscl_bw_pix_per_clk;
 324         unsigned int max_vscl_hscl_bw_pix_per_clk;
 325         double max_hscl_ratio;
 326         double max_vscl_ratio;
 327         unsigned int hscl_mults;
 328         unsigned int vscl_mults;
 329         unsigned int max_hscl_taps;
 330         unsigned int max_vscl_taps;
 331         unsigned int xfc_supported;
 332         unsigned int ptoi_supported;
 333         unsigned int gfx7_compat_tiling_supported;
 334
 335         bool odm_combine_4to1_supported;
 336         bool dynamic_metadata_vm_enabled;
 337         unsigned int max_num_hdmi_frl_outputs;
 338
 339         unsigned int xfc_fill_constant_bytes;
 340         double dispclk_ramp_margin_percent;
 341         double xfc_fill_bw_overhead_percent;
 342         double underscan_factor;
 343         unsigned int min_vblank_lines;
 344         unsigned int dppclk_delay_subtotal;
 345         unsigned int dispclk_delay_subtotal;
 346         double dcfclk_cstate_latency;
 347         unsigned int dppclk_delay_scl;
 348         unsigned int dppclk_delay_scl_lb_only;
 349         unsigned int dppclk_delay_cnvc_formatter;
 350         unsigned int dppclk_delay_cnvc_cursor;
 351         unsigned int is_line_buffer_bpp_fixed;
 352         unsigned int line_buffer_fixed_bpp;
 353         unsigned int dcc_supported;
 354         unsigned int config_return_buffer_size_in_kbytes;
 355         unsigned int compressed_buffer_segment_size_in_kbytes;
 356         unsigned int meta_fifo_size_in_kentries;
 357         unsigned int zero_size_buffer_entries;
 358         unsigned int compbuf_reserved_space_64b;
 359         unsigned int compbuf_reserved_space_zs;
 360
 361         unsigned int IsLineBufferBppFixed;
 362         unsigned int LineBufferFixedBpp;
 363         unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 364         unsigned int bug_forcing_LC_req_same_size_fixed;
 365         unsigned int number_of_cursors;
 366         unsigned int max_num_dp2p0_outputs;
 367         unsigned int max_num_dp2p0_streams;
 368         unsigned int VBlankNomDefaultUS;
 369
 370         /* DM workarounds */
 371         double dsc_delay_factor_wa; // TODO: Remove after implementing root cause fix
 372         double min_prefetch_in_strobe_us;
 373 };
 374
 375 struct _vcs_dpi_display_xfc_params_st {
 376         double xfc_tslv_vready_offset_us;
 377         double xfc_tslv_vupdate_width_us;
 378         double xfc_tslv_vupdate_offset_us;
 379         int xfc_slv_chunk_size_bytes;
 380 };
 381
 382 struct _vcs_dpi_display_pipe_source_params_st {
 383         int source_format;
 384         double dcc_fraction_of_zs_req_luma;
 385         double dcc_fraction_of_zs_req_chroma;
 386         unsigned char dcc;
 387         unsigned int dcc_rate;
 388         unsigned int dcc_rate_chroma;
 389         unsigned char dcc_use_global;
 390         unsigned char vm;
 391         bool unbounded_req_mode;
 392         bool gpuvm;    // gpuvm enabled
 393         bool hostvm;    // hostvm enabled
 394         bool gpuvm_levels_force_en;
 395         unsigned int gpuvm_levels_force;
 396         bool hostvm_levels_force_en;
 397         unsigned int hostvm_levels_force;
 398         int source_scan;
 399         int source_rotation; // new in dml32
 400         unsigned int det_size_override; // use to populate DETSizeOverride in vba struct
 401         int sw_mode;
 402         int macro_tile_size;
 403         unsigned int surface_width_y;
 404         unsigned int surface_height_y;
 405         unsigned int surface_width_c;
 406         unsigned int surface_height_c;
 407         unsigned int viewport_width;
 408         unsigned int viewport_height;
 409         unsigned int viewport_y_y;
 410         unsigned int viewport_y_c;
 411         unsigned int viewport_width_c;
 412         unsigned int viewport_height_c;
 413         unsigned int viewport_width_max;
 414         unsigned int viewport_height_max;
 415         unsigned int viewport_x_y;
 416         unsigned int viewport_x_c;
 417         bool viewport_stationary;
 418         unsigned int dcc_rate_luma;
 419         unsigned int gpuvm_min_page_size_kbytes;
 420         unsigned int use_mall_for_pstate_change;
 421         unsigned int use_mall_for_static_screen;
 422         bool force_one_row_for_frame;
 423         bool pte_buffer_mode;
 424         unsigned int data_pitch;
 425         unsigned int data_pitch_c;
 426         unsigned int meta_pitch;
 427         unsigned int meta_pitch_c;
 428         unsigned int cur0_src_width;
 429         int cur0_bpp;
 430         unsigned int cur1_src_width;
 431         int cur1_bpp;
 432         int num_cursors;
 433         unsigned char is_hsplit;
 434         unsigned char dynamic_metadata_enable;
 435         unsigned int dynamic_metadata_lines_before_active;
 436         unsigned int dynamic_metadata_xmit_bytes;
 437         unsigned int hsplit_grp;
 438         unsigned char xfc_enable;
 439         unsigned char xfc_slave;
 440         unsigned char immediate_flip;
 441         struct _vcs_dpi_display_xfc_params_st xfc_params;
 442         //for vstartuplines calculation freesync
 443         unsigned char v_total_min;
 444         unsigned char v_total_max;
 445 };
 446 struct writeback_st {
 447         int wb_src_height;
 448         int wb_src_width;
 449         int wb_dst_width;
 450         int wb_dst_height;
 451         int wb_pixel_format;
 452         int wb_htaps_luma;
 453         int wb_vtaps_luma;
 454         int wb_htaps_chroma;
 455         int wb_vtaps_chroma;
 456         unsigned int wb_htaps;
 457         unsigned int wb_vtaps;
 458         double wb_hratio;
 459         double wb_vratio;
 460 };
 461
 462 struct display_audio_params_st {
 463         unsigned int   audio_sample_rate_khz;
 464         int                audio_sample_layout;
 465 };
 466
 467 struct _vcs_dpi_display_output_params_st {
 468         int dp_lanes;
 469         double output_bpp;
 470         unsigned int dsc_input_bpc;
 471         int dsc_enable;
 472         int wb_enable;
 473         int num_active_wb;
 474         int output_type;
 475         int is_virtual;
 476         int output_format;
 477         int dsc_slices;
 478         int max_audio_sample_rate;
 479         struct writeback_st wb;
 480         struct display_audio_params_st audio;
 481         unsigned int output_bpc;
 482         int dp_rate;
 483         unsigned int dp_multistream_id;
 484         bool dp_multistream_en;
 485 };
 486
 487 struct _vcs_dpi_scaler_ratio_depth_st {
 488         double hscl_ratio;
 489         double vscl_ratio;
 490         double hscl_ratio_c;
 491         double vscl_ratio_c;
 492         double vinit;
 493         double vinit_c;
 494         double vinit_bot;
 495         double vinit_bot_c;
 496         int lb_depth;
 497         int scl_enable;
 498 };
 499
 500 struct _vcs_dpi_scaler_taps_st {
 501         unsigned int htaps;
 502         unsigned int vtaps;
 503         unsigned int htaps_c;
 504         unsigned int vtaps_c;
 505 };
 506
 507 struct _vcs_dpi_display_pipe_dest_params_st {
 508         unsigned int recout_width;
 509         unsigned int recout_height;
 510         unsigned int full_recout_width;
 511         unsigned int full_recout_height;
 512         unsigned int hblank_start;
 513         unsigned int hblank_end;
 514         unsigned int vblank_start;
 515         unsigned int vblank_end;
 516         unsigned int htotal;
 517         unsigned int vtotal;
 518         unsigned int vfront_porch;
 519         unsigned int vblank_nom;
 520         unsigned int vactive;
 521         unsigned int hactive;
 522         unsigned int vstartup_start;
 523         unsigned int vupdate_offset;
 524         unsigned int vupdate_width;
 525         unsigned int vready_offset;
 526         unsigned int pstate_keepout;
 527         unsigned char interlaced;
 528         double pixel_rate_mhz;
 529         unsigned char synchronized_vblank_all_planes;
 530         unsigned char otg_inst;
 531         unsigned int odm_combine;
 532         unsigned char use_maximum_vstartup;
 533         unsigned int vtotal_max;
 534         unsigned int vtotal_min;
 535         unsigned int refresh_rate;
 536         bool synchronize_timings;
 537         unsigned int odm_combine_policy;
 538         bool drr_display;
 539 };
 540
 541 struct _vcs_dpi_display_pipe_params_st {
 542         display_pipe_source_params_st src;
 543         display_pipe_dest_params_st dest;
 544         scaler_ratio_depth_st scale_ratio_depth;
 545         scaler_taps_st scale_taps;
 546 };
 547
 548 struct _vcs_dpi_display_clocks_and_cfg_st {
 549         int voltage;
 550         double dppclk_mhz;
 551         double refclk_mhz;
 552         double dispclk_mhz;
 553         double dcfclk_mhz;
 554         double socclk_mhz;
 555 };
 556
 557 struct _vcs_dpi_display_e2e_pipe_params_st {
 558         display_pipe_params_st pipe;
 559         display_output_params_st dout;
 560         display_clocks_and_cfg_st clks_cfg;
 561 };
 562
 563 struct _vcs_dpi_display_data_rq_misc_params_st {
 564         unsigned int full_swath_bytes;
 565         unsigned int stored_swath_bytes;
 566         unsigned int blk256_height;
 567         unsigned int blk256_width;
 568         unsigned int req_height;
 569         unsigned int req_width;
 570 };
 571
 572 struct _vcs_dpi_display_data_rq_sizing_params_st {
 573         unsigned int chunk_bytes;
 574         unsigned int min_chunk_bytes;
 575         unsigned int meta_chunk_bytes;
 576         unsigned int min_meta_chunk_bytes;
 577         unsigned int mpte_group_bytes;
 578         unsigned int dpte_group_bytes;
 579 };
 580
 581 struct _vcs_dpi_display_data_rq_dlg_params_st {
 582         unsigned int swath_width_ub;
 583         unsigned int swath_height;
 584         unsigned int req_per_swath_ub;
 585         unsigned int meta_pte_bytes_per_frame_ub;
 586         unsigned int dpte_req_per_row_ub;
 587         unsigned int dpte_groups_per_row_ub;
 588         unsigned int dpte_row_height;
 589         unsigned int dpte_bytes_per_row_ub;
 590         unsigned int meta_chunks_per_row_ub;
 591         unsigned int meta_req_per_row_ub;
 592         unsigned int meta_row_height;
 593         unsigned int meta_bytes_per_row_ub;
 594 };
 595
 596 struct _vcs_dpi_display_rq_dlg_params_st {
 597         display_data_rq_dlg_params_st rq_l;
 598         display_data_rq_dlg_params_st rq_c;
 599 };
 600
 601 struct _vcs_dpi_display_rq_sizing_params_st {
 602         display_data_rq_sizing_params_st rq_l;
 603         display_data_rq_sizing_params_st rq_c;
 604 };
 605
 606 struct _vcs_dpi_display_rq_misc_params_st {
 607         display_data_rq_misc_params_st rq_l;
 608         display_data_rq_misc_params_st rq_c;
 609 };
 610
 611 struct _vcs_dpi_display_rq_params_st {
 612         unsigned char yuv420;
 613         unsigned char yuv420_10bpc;
 614         unsigned char rgbe_alpha;
 615         display_rq_misc_params_st misc;
 616         display_rq_sizing_params_st sizing;
 617         display_rq_dlg_params_st dlg;
 618 };
 619
 620 struct _vcs_dpi_display_dlg_regs_st {
 621         unsigned int refcyc_h_blank_end;
 622         unsigned int dlg_vblank_end;
 623         unsigned int min_dst_y_next_start;
 624         unsigned int min_dst_y_next_start_us;
 625         unsigned int refcyc_per_htotal;
 626         unsigned int refcyc_x_after_scaler;
 627         unsigned int dst_y_after_scaler;
 628         unsigned int dst_y_prefetch;
 629         unsigned int dst_y_per_vm_vblank;
 630         unsigned int dst_y_per_row_vblank;
 631         unsigned int dst_y_per_vm_flip;
 632         unsigned int dst_y_per_row_flip;
 633         unsigned int ref_freq_to_pix_freq;
 634         unsigned int vratio_prefetch;
 635         unsigned int vratio_prefetch_c;
 636         unsigned int refcyc_per_tdlut_group;
 637         unsigned int refcyc_per_pte_group_vblank_l;
 638         unsigned int refcyc_per_pte_group_vblank_c;
 639         unsigned int refcyc_per_meta_chunk_vblank_l;
 640         unsigned int refcyc_per_meta_chunk_vblank_c;
 641         unsigned int refcyc_per_pte_group_flip_l;
 642         unsigned int refcyc_per_pte_group_flip_c;
 643         unsigned int refcyc_per_meta_chunk_flip_l;
 644         unsigned int refcyc_per_meta_chunk_flip_c;
 645         unsigned int dst_y_per_pte_row_nom_l;
 646         unsigned int dst_y_per_pte_row_nom_c;
 647         unsigned int refcyc_per_pte_group_nom_l;
 648         unsigned int refcyc_per_pte_group_nom_c;
 649         unsigned int dst_y_per_meta_row_nom_l;
 650         unsigned int dst_y_per_meta_row_nom_c;
 651         unsigned int refcyc_per_meta_chunk_nom_l;
 652         unsigned int refcyc_per_meta_chunk_nom_c;
 653         unsigned int refcyc_per_line_delivery_pre_l;
 654         unsigned int refcyc_per_line_delivery_pre_c;
 655         unsigned int refcyc_per_line_delivery_l;
 656         unsigned int refcyc_per_line_delivery_c;
 657         unsigned int chunk_hdl_adjust_cur0;
 658         unsigned int chunk_hdl_adjust_cur1;
 659         unsigned int vready_after_vcount0;
 660         unsigned int dst_y_offset_cur0;
 661         unsigned int dst_y_offset_cur1;
 662         unsigned int xfc_reg_transfer_delay;
 663         unsigned int xfc_reg_precharge_delay;
 664         unsigned int xfc_reg_remote_surface_flip_latency;
 665         unsigned int xfc_reg_prefetch_margin;
 666         unsigned int dst_y_delta_drq_limit;
 667         unsigned int refcyc_per_vm_group_vblank;
 668         unsigned int refcyc_per_vm_group_flip;
 669         unsigned int refcyc_per_vm_req_vblank;
 670         unsigned int refcyc_per_vm_req_flip;
 671         unsigned int refcyc_per_vm_dmdata;
 672         unsigned int dmdata_dl_delta;
 673 };
 674
 675 struct _vcs_dpi_display_ttu_regs_st {
 676         unsigned int qos_level_low_wm;
 677         unsigned int qos_level_high_wm;
 678         unsigned int min_ttu_vblank;
 679         unsigned int qos_level_flip;
 680         unsigned int refcyc_per_req_delivery_l;
 681         unsigned int refcyc_per_req_delivery_c;
 682         unsigned int refcyc_per_req_delivery_cur0;
 683         unsigned int refcyc_per_req_delivery_cur1;
 684         unsigned int refcyc_per_req_delivery_pre_l;
 685         unsigned int refcyc_per_req_delivery_pre_c;
 686         unsigned int refcyc_per_req_delivery_pre_cur0;
 687         unsigned int refcyc_per_req_delivery_pre_cur1;
 688         unsigned int qos_level_fixed_l;
 689         unsigned int qos_level_fixed_c;
 690         unsigned int qos_level_fixed_cur0;
 691         unsigned int qos_level_fixed_cur1;
 692         unsigned int qos_ramp_disable_l;
 693         unsigned int qos_ramp_disable_c;
 694         unsigned int qos_ramp_disable_cur0;
 695         unsigned int qos_ramp_disable_cur1;
 696 };
 697
 698 struct _vcs_dpi_display_data_rq_regs_st {
 699         unsigned int chunk_size;
 700         unsigned int min_chunk_size;
 701         unsigned int meta_chunk_size;
 702         unsigned int min_meta_chunk_size;
 703         unsigned int dpte_group_size;
 704         unsigned int mpte_group_size;
 705         unsigned int swath_height;
 706         unsigned int pte_row_height_linear;
 707 };
 708
 709 struct _vcs_dpi_display_rq_regs_st {
 710         display_data_rq_regs_st rq_regs_l;
 711         display_data_rq_regs_st rq_regs_c;
 712         unsigned int drq_expansion_mode;
 713         unsigned int prq_expansion_mode;
 714         unsigned int mrq_expansion_mode;
 715         unsigned int crq_expansion_mode;
 716         unsigned int plane1_base_address;
 717         unsigned int aperture_low_addr;   // bits [47:18]
 718         unsigned int aperture_high_addr;  // bits [47:18]
 719 };
 720
 721 struct _vcs_dpi_display_dlg_sys_params_st {
 722         double t_mclk_wm_us;
 723         double t_urg_wm_us;
 724         double t_sr_wm_us;
 725         double t_extra_us;
 726         double mem_trip_us;
 727         double deepsleep_dcfclk_mhz;
 728         double total_flip_bw;
 729         unsigned int total_flip_bytes;
 730 };
 731
 732 struct _vcs_dpi_display_arb_params_st {
 733         int max_req_outstanding;
 734         int min_req_outstanding;
 735         int sat_level_us;
 736         int hvm_min_req_outstand_commit_threshold;
 737         int hvm_max_qos_commit_threshold;
 738         int compbuf_reserved_space_kbytes;
 739 };
 740
 741 #endif /*__DISPLAY_MODE_STRUCTS_H__*/