drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string_helpers.h>
  27 #include <linux/uaccess.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_debugfs.h"
  33 #include "amdgpu_dm_replay.h"
  34 #include "dm_helpers.h"
  35 #include "dmub/dmub_srv.h"
  36 #include "resource.h"
  37 #include "dsc.h"
  38 #include "link_hwss.h"
  39 #include "dc/dc_dmub_srv.h"
  40 #include "link/protocols/link_dp_capability.h"
  41 #include "inc/hw/dchubbub.h"
  42
  43 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
  44 #include "amdgpu_dm_psr.h"
  45 #endif
  46
  47 struct dmub_debugfs_trace_header {
  48         uint32_t entry_count;
  49         uint32_t reserved[3];
  50 };
  51
  52 struct dmub_debugfs_trace_entry {
  53         uint32_t trace_code;
  54         uint32_t tick_count;
  55         uint32_t param0;
  56         uint32_t param1;
  57 };
  58
  59 static const char *const mst_progress_status[] = {
  60         "probe",
  61         "remote_edid",
  62         "allocate_new_payload",
  63         "clear_allocated_payload",
  64 };
  65
  66 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  67  *
  68  * Function takes in attributes passed to debugfs write entry
  69  * and writes into param array.
  70  * The user passes max_param_num to identify maximum number of
  71  * parameters that could be parsed.
  72  *
  73  */
  74 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  75                                           long *param, const char __user *buf,
  76                                           int max_param_num,
  77                                           uint8_t *param_nums)
  78 {
  79         char *wr_buf_ptr = NULL;
  80         uint32_t wr_buf_count = 0;
  81         int r;
  82         char *sub_str = NULL;
  83         const char delimiter[3] = {' ', '\n', '\0'};
  84         uint8_t param_index = 0;
  85
  86         *param_nums = 0;
  87
  88         wr_buf_ptr = wr_buf;
  89
  90         /* r is bytes not be copied */
  91         if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
  92                 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
  93                 return -EFAULT;
  94         }
  95
  96         /* check number of parameters. isspace could not differ space and \n */
  97         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  98                 /* skip space*/
  99                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 100                         wr_buf_ptr++;
 101                         wr_buf_count++;
 102                         }
 103
 104                 if (wr_buf_count == wr_buf_size)
 105                         break;
 106
 107                 /* skip non-space*/
 108                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 109                         wr_buf_ptr++;
 110                         wr_buf_count++;
 111                 }
 112
 113                 (*param_nums)++;
 114
 115                 if (wr_buf_count == wr_buf_size)
 116                         break;
 117         }
 118
 119         if (*param_nums > max_param_num)
 120                 *param_nums = max_param_num;
 121
 122         wr_buf_ptr = wr_buf; /* reset buf pointer */
 123         wr_buf_count = 0; /* number of char already checked */
 124
 125         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 126                 wr_buf_ptr++;
 127                 wr_buf_count++;
 128         }
 129
 130         while (param_index < *param_nums) {
 131                 /* after strsep, wr_buf_ptr will be moved to after space */
 132                 sub_str = strsep(&wr_buf_ptr, delimiter);
 133
 134                 r = kstrtol(sub_str, 16, &(param[param_index]));
 135
 136                 if (r)
 137                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 138
 139                 param_index++;
 140         }
 141
 142         return 0;
 143 }
 144
 145 /* function description
 146  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 147  *
 148  * valid lane count value: 1, 2, 4
 149  * valid link rate value:
 150  * 06h = 1.62Gbps per lane
 151  * 0Ah = 2.7Gbps per lane
 152  * 0Ch = 3.24Gbps per lane
 153  * 14h = 5.4Gbps per lane
 154  * 1Eh = 8.1Gbps per lane
 155  *
 156  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 157  *
 158  * --- to get dp configuration
 159  *
 160  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 161  *
 162  * It will list current, verified, reported, preferred dp configuration.
 163  * current -- for current video mode
 164  * verified --- maximum configuration which pass link training
 165  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 166  * preferred --- user force settings
 167  *
 168  * --- set (or force) dp configuration
 169  *
 170  * echo <lane_count>  <link_rate> > link_settings
 171  *
 172  * for example, to force to  2 lane, 2.7GHz,
 173  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 174  *
 175  * spread_spectrum could not be changed dynamically.
 176  *
 177  * in case invalid lane count, link rate are force, no hw programming will be
 178  * done. please check link settings after force operation to see if HW get
 179  * programming.
 180  *
 181  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 182  *
 183  * check current and preferred settings.
 184  *
 185  */
 186 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 187                                  size_t size, loff_t *pos)
 188 {
 189         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 190         struct dc_link *link = connector->dc_link;
 191         char *rd_buf = NULL;
 192         char *rd_buf_ptr = NULL;
 193         const uint32_t rd_buf_size = 100;
 194         uint32_t result = 0;
 195         uint8_t str_len = 0;
 196         int r;
 197
 198         if (*pos & 3 || size & 3)
 199                 return -EINVAL;
 200
 201         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 202         if (!rd_buf)
 203                 return 0;
 204
 205         rd_buf_ptr = rd_buf;
 206
 207         str_len = strlen("Current:  %d  0x%x  %d  ");
 208         snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 209                         link->cur_link_settings.lane_count,
 210                         link->cur_link_settings.link_rate,
 211                         link->cur_link_settings.link_spread);
 212         rd_buf_ptr += str_len;
 213
 214         str_len = strlen("Verified:  %d  0x%x  %d  ");
 215         snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 216                         link->verified_link_cap.lane_count,
 217                         link->verified_link_cap.link_rate,
 218                         link->verified_link_cap.link_spread);
 219         rd_buf_ptr += str_len;
 220
 221         str_len = strlen("Reported:  %d  0x%x  %d  ");
 222         snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 223                         link->reported_link_cap.lane_count,
 224                         link->reported_link_cap.link_rate,
 225                         link->reported_link_cap.link_spread);
 226         rd_buf_ptr += str_len;
 227
 228         str_len = strlen("Preferred:  %d  0x%x  %d  ");
 229         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 230                         link->preferred_link_setting.lane_count,
 231                         link->preferred_link_setting.link_rate,
 232                         link->preferred_link_setting.link_spread);
 233
 234         while (size) {
 235                 if (*pos >= rd_buf_size)
 236                         break;
 237
 238                 r = put_user(*(rd_buf + result), buf);
 239                 if (r) {
 240                         kfree(rd_buf);
 241                         return r; /* r = -EFAULT */
 242                 }
 243
 244                 buf += 1;
 245                 size -= 1;
 246                 *pos += 1;
 247                 result += 1;
 248         }
 249
 250         kfree(rd_buf);
 251         return result;
 252 }
 253
 254 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 255                                  size_t size, loff_t *pos)
 256 {
 257         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 258         struct dc_link *link = connector->dc_link;
 259         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
 260         struct dc *dc = (struct dc *)link->dc;
 261         struct dc_link_settings prefer_link_settings;
 262         char *wr_buf = NULL;
 263         const uint32_t wr_buf_size = 40;
 264         /* 0: lane_count; 1: link_rate */
 265         int max_param_num = 2;
 266         uint8_t param_nums = 0;
 267         long param[2];
 268         bool valid_input = true;
 269
 270         if (size == 0)
 271                 return -EINVAL;
 272
 273         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 274         if (!wr_buf)
 275                 return -ENOSPC;
 276
 277         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 278                                            (long *)param, buf,
 279                                            max_param_num,
 280                                            &param_nums)) {
 281                 kfree(wr_buf);
 282                 return -EINVAL;
 283         }
 284
 285         if (param_nums <= 0) {
 286                 kfree(wr_buf);
 287                 DRM_DEBUG_DRIVER("user data not be read\n");
 288                 return -EINVAL;
 289         }
 290
 291         switch (param[0]) {
 292         case LANE_COUNT_ONE:
 293         case LANE_COUNT_TWO:
 294         case LANE_COUNT_FOUR:
 295                 break;
 296         default:
 297                 valid_input = false;
 298                 break;
 299         }
 300
 301         switch (param[1]) {
 302         case LINK_RATE_LOW:
 303         case LINK_RATE_HIGH:
 304         case LINK_RATE_RBR2:
 305         case LINK_RATE_HIGH2:
 306         case LINK_RATE_HIGH3:
 307         case LINK_RATE_UHBR10:
 308         case LINK_RATE_UHBR13_5:
 309         case LINK_RATE_UHBR20:
 310                 break;
 311         default:
 312                 valid_input = false;
 313                 break;
 314         }
 315
 316         if (!valid_input) {
 317                 kfree(wr_buf);
 318                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 319                 mutex_lock(&adev->dm.dc_lock);
 320                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 321                 mutex_unlock(&adev->dm.dc_lock);
 322                 return size;
 323         }
 324
 325         /* save user force lane_count, link_rate to preferred settings
 326          * spread spectrum will not be changed
 327          */
 328         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 329         prefer_link_settings.use_link_rate_set = false;
 330         prefer_link_settings.lane_count = param[0];
 331         prefer_link_settings.link_rate = param[1];
 332
 333         mutex_lock(&adev->dm.dc_lock);
 334         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
 335         mutex_unlock(&adev->dm.dc_lock);
 336
 337         kfree(wr_buf);
 338         return size;
 339 }
 340
 341 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
 342 {
 343         bool is_end_device = false;
 344         struct drm_dp_mst_topology_mgr *mgr = NULL;
 345         struct drm_dp_mst_port *port = NULL;
 346
 347         if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) {
 348                 mgr = &aconnector->mst_root->mst_mgr;
 349                 port = aconnector->mst_output_port;
 350
 351                 drm_modeset_lock(&mgr->base.lock, NULL);
 352                 if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
 353                         port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV)
 354                         is_end_device = true;
 355                 drm_modeset_unlock(&mgr->base.lock);
 356         }
 357
 358         return is_end_device;
 359 }
 360
 361 /* Change MST link setting
 362  *
 363  * valid lane count value: 1, 2, 4
 364  * valid link rate value:
 365  * 06h = 1.62Gbps per lane
 366  * 0Ah = 2.7Gbps per lane
 367  * 0Ch = 3.24Gbps per lane
 368  * 14h = 5.4Gbps per lane
 369  * 1Eh = 8.1Gbps per lane
 370  * 3E8h = 10.0Gbps per lane
 371  * 546h = 13.5Gbps per lane
 372  * 7D0h = 20.0Gbps per lane
 373  *
 374  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings
 375  *
 376  * for example, to force to  2 lane, 10.0GHz,
 377  * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings
 378  *
 379  * Valid input will trigger hotplug event to get new link setting applied
 380  * Invalid input will trigger training setting reset
 381  *
 382  * The usage can be referred to link_settings entry
 383  *
 384  */
 385 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,
 386                                  size_t size, loff_t *pos)
 387 {
 388         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 389         struct dc_link *link = aconnector->dc_link;
 390         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
 391         struct dc *dc = (struct dc *)link->dc;
 392         struct dc_link_settings prefer_link_settings;
 393         char *wr_buf = NULL;
 394         const uint32_t wr_buf_size = 40;
 395         /* 0: lane_count; 1: link_rate */
 396         int max_param_num = 2;
 397         uint8_t param_nums = 0;
 398         long param[2];
 399         bool valid_input = true;
 400
 401         if (!dp_mst_is_end_device(aconnector))
 402                 return -EINVAL;
 403
 404         if (size == 0)
 405                 return -EINVAL;
 406
 407         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 408         if (!wr_buf)
 409                 return -ENOSPC;
 410
 411         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 412                                            (long *)param, buf,
 413                                            max_param_num,
 414                                            &param_nums)) {
 415                 kfree(wr_buf);
 416                 return -EINVAL;
 417         }
 418
 419         if (param_nums <= 0) {
 420                 kfree(wr_buf);
 421                 DRM_DEBUG_DRIVER("user data not be read\n");
 422                 return -EINVAL;
 423         }
 424
 425         switch (param[0]) {
 426         case LANE_COUNT_ONE:
 427         case LANE_COUNT_TWO:
 428         case LANE_COUNT_FOUR:
 429                 break;
 430         default:
 431                 valid_input = false;
 432                 break;
 433         }
 434
 435         switch (param[1]) {
 436         case LINK_RATE_LOW:
 437         case LINK_RATE_HIGH:
 438         case LINK_RATE_RBR2:
 439         case LINK_RATE_HIGH2:
 440         case LINK_RATE_HIGH3:
 441         case LINK_RATE_UHBR10:
 442         case LINK_RATE_UHBR13_5:
 443         case LINK_RATE_UHBR20:
 444                 break;
 445         default:
 446                 valid_input = false;
 447                 break;
 448         }
 449
 450         if (!valid_input) {
 451                 kfree(wr_buf);
 452                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 453                 mutex_lock(&adev->dm.dc_lock);
 454                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 455                 mutex_unlock(&adev->dm.dc_lock);
 456                 return -EINVAL;
 457         }
 458
 459         /* save user force lane_count, link_rate to preferred settings
 460          * spread spectrum will not be changed
 461          */
 462         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 463         prefer_link_settings.use_link_rate_set = false;
 464         prefer_link_settings.lane_count = param[0];
 465         prefer_link_settings.link_rate = param[1];
 466
 467         /* skip immediate retrain, and train to new link setting after hotplug event triggered */
 468         mutex_lock(&adev->dm.dc_lock);
 469         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
 470         mutex_unlock(&adev->dm.dc_lock);
 471
 472         mutex_lock(&aconnector->base.dev->mode_config.mutex);
 473         aconnector->base.force = DRM_FORCE_OFF;
 474         mutex_unlock(&aconnector->base.dev->mode_config.mutex);
 475         drm_kms_helper_hotplug_event(aconnector->base.dev);
 476
 477         msleep(100);
 478
 479         mutex_lock(&aconnector->base.dev->mode_config.mutex);
 480         aconnector->base.force = DRM_FORCE_UNSPECIFIED;
 481         mutex_unlock(&aconnector->base.dev->mode_config.mutex);
 482         drm_kms_helper_hotplug_event(aconnector->base.dev);
 483
 484         kfree(wr_buf);
 485         return size;
 486 }
 487
 488 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 489  * post-cursor2 (defined by VESA DP specification)
 490  *
 491  * valid values
 492  * voltage swing: 0,1,2,3
 493  * pre-emphasis : 0,1,2,3
 494  * post cursor2 : 0,1,2,3
 495  *
 496  *
 497  * how to use this debugfs
 498  *
 499  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 500  *
 501  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 502  *
 503  * To figure out which DP-x is the display for DP to be check,
 504  * cd DP-x
 505  * ls -ll
 506  * There should be debugfs file, like link_settings, phy_settings.
 507  * cat link_settings
 508  * from lane_count, link_rate to figure which DP-x is for display to be worked
 509  * on
 510  *
 511  * To get current DP PHY settings,
 512  * cat phy_settings
 513  *
 514  * To change DP PHY settings,
 515  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 516  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 517  * 0,
 518  * echo 2 3 0 > phy_settings
 519  *
 520  * To check if change be applied, get current phy settings by
 521  * cat phy_settings
 522  *
 523  * In case invalid values are set by user, like
 524  * echo 1 4 0 > phy_settings
 525  *
 526  * HW will NOT be programmed by these settings.
 527  * cat phy_settings will show the previous valid settings.
 528  */
 529 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 530                                  size_t size, loff_t *pos)
 531 {
 532         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 533         struct dc_link *link = connector->dc_link;
 534         char *rd_buf = NULL;
 535         const uint32_t rd_buf_size = 20;
 536         uint32_t result = 0;
 537         int r;
 538
 539         if (*pos & 3 || size & 3)
 540                 return -EINVAL;
 541
 542         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 543         if (!rd_buf)
 544                 return -EINVAL;
 545
 546         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 547                         link->cur_lane_setting[0].VOLTAGE_SWING,
 548                         link->cur_lane_setting[0].PRE_EMPHASIS,
 549                         link->cur_lane_setting[0].POST_CURSOR2);
 550
 551         while (size) {
 552                 if (*pos >= rd_buf_size)
 553                         break;
 554
 555                 r = put_user((*(rd_buf + result)), buf);
 556                 if (r) {
 557                         kfree(rd_buf);
 558                         return r; /* r = -EFAULT */
 559                 }
 560
 561                 buf += 1;
 562                 size -= 1;
 563                 *pos += 1;
 564                 result += 1;
 565         }
 566
 567         kfree(rd_buf);
 568         return result;
 569 }
 570
 571 static int dp_lttpr_status_show(struct seq_file *m, void *unused)
 572 {
 573         struct drm_connector *connector = m->private;
 574         struct amdgpu_dm_connector *aconnector =
 575                 to_amdgpu_dm_connector(connector);
 576         struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
 577
 578         if (connector->status != connector_status_connected)
 579                 return -ENODEV;
 580
 581         seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n",
 582                    dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt),
 583                    caps.phy_repeater_cnt);
 584
 585         seq_puts(m, "phy repeater mode: ");
 586
 587         switch (caps.mode) {
 588         case DP_PHY_REPEATER_MODE_TRANSPARENT:
 589                 seq_puts(m, "transparent");
 590                 break;
 591         case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
 592                 seq_puts(m, "non-transparent");
 593                 break;
 594         case 0x00:
 595                 seq_puts(m, "non lttpr");
 596                 break;
 597         default:
 598                 seq_printf(m, "read error (raw: 0x%x)", caps.mode);
 599                 break;
 600         }
 601
 602         seq_puts(m, "\n");
 603         return 0;
 604 }
 605
 606 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 607                                  size_t size, loff_t *pos)
 608 {
 609         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 610         struct dc_link *link = connector->dc_link;
 611         struct dc *dc = (struct dc *)link->dc;
 612         char *wr_buf = NULL;
 613         uint32_t wr_buf_size = 40;
 614         long param[3];
 615         bool use_prefer_link_setting;
 616         struct link_training_settings link_lane_settings;
 617         int max_param_num = 3;
 618         uint8_t param_nums = 0;
 619         int r = 0;
 620
 621
 622         if (size == 0)
 623                 return -EINVAL;
 624
 625         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 626         if (!wr_buf)
 627                 return -ENOSPC;
 628
 629         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 630                                            (long *)param, buf,
 631                                            max_param_num,
 632                                            &param_nums)) {
 633                 kfree(wr_buf);
 634                 return -EINVAL;
 635         }
 636
 637         if (param_nums <= 0) {
 638                 kfree(wr_buf);
 639                 DRM_DEBUG_DRIVER("user data not be read\n");
 640                 return -EINVAL;
 641         }
 642
 643         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 644                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 645                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 646                 kfree(wr_buf);
 647                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 648                 return size;
 649         }
 650
 651         /* get link settings: lane count, link rate */
 652         use_prefer_link_setting =
 653                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 654                 (link->test_pattern_enabled));
 655
 656         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 657
 658         if (use_prefer_link_setting) {
 659                 link_lane_settings.link_settings.lane_count =
 660                                 link->preferred_link_setting.lane_count;
 661                 link_lane_settings.link_settings.link_rate =
 662                                 link->preferred_link_setting.link_rate;
 663                 link_lane_settings.link_settings.link_spread =
 664                                 link->preferred_link_setting.link_spread;
 665         } else {
 666                 link_lane_settings.link_settings.lane_count =
 667                                 link->cur_link_settings.lane_count;
 668                 link_lane_settings.link_settings.link_rate =
 669                                 link->cur_link_settings.link_rate;
 670                 link_lane_settings.link_settings.link_spread =
 671                                 link->cur_link_settings.link_spread;
 672         }
 673
 674         /* apply phy settings from user */
 675         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 676                 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 677                                 (enum dc_voltage_swing) (param[0]);
 678                 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 679                                 (enum dc_pre_emphasis) (param[1]);
 680                 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 681                                 (enum dc_post_cursor2) (param[2]);
 682         }
 683
 684         /* program ASIC registers and DPCD registers */
 685         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 686
 687         kfree(wr_buf);
 688         return size;
 689 }
 690
 691 /* function description
 692  *
 693  * set PHY layer or Link layer test pattern
 694  * PHY test pattern is used for PHY SI check.
 695  * Link layer test will not affect PHY SI.
 696  *
 697  * Reset Test Pattern:
 698  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 699  *
 700  * PHY test pattern supported:
 701  * 1 = DP_TEST_PATTERN_D102
 702  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 703  * 3 = DP_TEST_PATTERN_PRBS7
 704  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 705  * 5 = DP_TEST_PATTERN_CP2520_1
 706  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 707  * 7 = DP_TEST_PATTERN_CP2520_3
 708  *
 709  * DP PHY Link Training Patterns
 710  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 711  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 712  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 713  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 714  *
 715  * DP Link Layer Test pattern
 716  * c = DP_TEST_PATTERN_COLOR_SQUARES
 717  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 718  * e = DP_TEST_PATTERN_VERTICAL_BARS
 719  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 720  * 10= DP_TEST_PATTERN_COLOR_RAMP
 721  *
 722  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 723  *
 724  * --- set test pattern
 725  * echo <test pattern #> > test_pattern
 726  *
 727  * If test pattern # is not supported, NO HW programming will be done.
 728  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 729  * for the user pattern. input 10 bytes data are separated by space
 730  *
 731  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 732  *
 733  * --- reset test pattern
 734  * echo 0 > test_pattern
 735  *
 736  * --- HPD detection is disabled when set PHY test pattern
 737  *
 738  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 739  * is disable. User could unplug DP display from DP connected and plug scope to
 740  * check test pattern PHY SI.
 741  * If there is need unplug scope and plug DP display back, do steps below:
 742  * echo 0 > phy_test_pattern
 743  * unplug scope
 744  * plug DP display.
 745  *
 746  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 747  * driver could detect "unplug scope" and "plug DP display"
 748  */
 749 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 750                                  size_t size, loff_t *pos)
 751 {
 752         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 753         struct dc_link *link = connector->dc_link;
 754         char *wr_buf = NULL;
 755         uint32_t wr_buf_size = 100;
 756         long param[11] = {0x0};
 757         int max_param_num = 11;
 758         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 759         bool disable_hpd = false;
 760         bool valid_test_pattern = false;
 761         uint8_t param_nums = 0;
 762         /* init with default 80bit custom pattern */
 763         uint8_t custom_pattern[10] = {
 764                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 765                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 766                         };
 767         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 768                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 769         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 770                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 771         struct link_training_settings link_training_settings;
 772         int i;
 773
 774         if (size == 0)
 775                 return -EINVAL;
 776
 777         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 778         if (!wr_buf)
 779                 return -ENOSPC;
 780
 781         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 782                                            (long *)param, buf,
 783                                            max_param_num,
 784                                            &param_nums)) {
 785                 kfree(wr_buf);
 786                 return -EINVAL;
 787         }
 788
 789         if (param_nums <= 0) {
 790                 kfree(wr_buf);
 791                 DRM_DEBUG_DRIVER("user data not be read\n");
 792                 return -EINVAL;
 793         }
 794
 795
 796         test_pattern = param[0];
 797
 798         switch (test_pattern) {
 799         case DP_TEST_PATTERN_VIDEO_MODE:
 800         case DP_TEST_PATTERN_COLOR_SQUARES:
 801         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 802         case DP_TEST_PATTERN_VERTICAL_BARS:
 803         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 804         case DP_TEST_PATTERN_COLOR_RAMP:
 805                 valid_test_pattern = true;
 806                 break;
 807
 808         case DP_TEST_PATTERN_D102:
 809         case DP_TEST_PATTERN_SYMBOL_ERROR:
 810         case DP_TEST_PATTERN_PRBS7:
 811         case DP_TEST_PATTERN_80BIT_CUSTOM:
 812         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 813         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 814                 disable_hpd = true;
 815                 valid_test_pattern = true;
 816                 break;
 817
 818         default:
 819                 valid_test_pattern = false;
 820                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 821                 break;
 822         }
 823
 824         if (!valid_test_pattern) {
 825                 kfree(wr_buf);
 826                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 827                 return size;
 828         }
 829
 830         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 831                 for (i = 0; i < 10; i++) {
 832                         if ((uint8_t) param[i + 1] != 0x0)
 833                                 break;
 834                 }
 835
 836                 if (i < 10) {
 837                         /* not use default value */
 838                         for (i = 0; i < 10; i++)
 839                                 custom_pattern[i] = (uint8_t) param[i + 1];
 840                 }
 841         }
 842
 843         /* Usage: set DP physical test pattern using debugfs with normal DP
 844          * panel. Then plug out DP panel and connect a scope to measure
 845          * For normal video mode and test pattern generated from CRCT,
 846          * they are visibile to user. So do not disable HPD.
 847          * Video Mode is also set to clear the test pattern, so enable HPD
 848          * because it might have been disabled after a test pattern was set.
 849          * AUX depends on HPD * sequence dependent, do not move!
 850          */
 851         if (!disable_hpd)
 852                 dc_link_enable_hpd(link);
 853
 854         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 855         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 856         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 857
 858         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 859         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 860         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 861
 862         link_training_settings.link_settings = cur_link_settings;
 863
 864
 865         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 866                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 867                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 868                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 869                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 870                         link_training_settings.link_settings = prefer_link_settings;
 871         }
 872
 873         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 874                 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 875
 876         dc_link_dp_set_test_pattern(
 877                 link,
 878                 test_pattern,
 879                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 880                 &link_training_settings,
 881                 custom_pattern,
 882                 10);
 883
 884         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 885          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 886          * Need disable interrupt to avoid SW driver disable DP output. This is
 887          * done after the test pattern is set.
 888          */
 889         if (valid_test_pattern && disable_hpd)
 890                 dc_link_disable_hpd(link);
 891
 892         kfree(wr_buf);
 893
 894         return size;
 895 }
 896
 897 /*
 898  * Returns the DMCUB tracebuffer contents.
 899  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 900  */
 901 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 902 {
 903         struct amdgpu_device *adev = m->private;
 904         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 905         struct dmub_debugfs_trace_entry *entries;
 906         uint8_t *tbuf_base;
 907         uint32_t tbuf_size, max_entries, num_entries, i;
 908
 909         if (!fb_info)
 910                 return 0;
 911
 912         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 913         if (!tbuf_base)
 914                 return 0;
 915
 916         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 917         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 918                       sizeof(struct dmub_debugfs_trace_entry);
 919
 920         num_entries =
 921                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 922
 923         num_entries = min(num_entries, max_entries);
 924
 925         entries = (struct dmub_debugfs_trace_entry
 926                            *)(tbuf_base +
 927                               sizeof(struct dmub_debugfs_trace_header));
 928
 929         for (i = 0; i < num_entries; ++i) {
 930                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 931
 932                 seq_printf(m,
 933                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 934                            entry->trace_code, entry->tick_count, entry->param0,
 935                            entry->param1);
 936         }
 937
 938         return 0;
 939 }
 940
 941 /*
 942  * Returns the DMCUB firmware state contents.
 943  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 944  */
 945 static int dmub_fw_state_show(struct seq_file *m, void *data)
 946 {
 947         struct amdgpu_device *adev = m->private;
 948         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 949         uint8_t *state_base;
 950         uint32_t state_size;
 951
 952         if (!fb_info)
 953                 return 0;
 954
 955         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 956         if (!state_base)
 957                 return 0;
 958
 959         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 960
 961         return seq_write(m, state_base, state_size);
 962 }
 963
 964 /* replay_capability_show() - show eDP panel replay capability
 965  *
 966  * The read function: replay_capability_show
 967  * Shows if sink and driver has Replay capability or not.
 968  *
 969  *      cat /sys/kernel/debug/dri/0/eDP-X/replay_capability
 970  *
 971  * Expected output:
 972  * "Sink support: no\n" - if panel doesn't support Replay
 973  * "Sink support: yes\n" - if panel supports Replay
 974  * "Driver support: no\n" - if driver doesn't support Replay
 975  * "Driver support: yes\n" - if driver supports Replay
 976  */
 977 static int replay_capability_show(struct seq_file *m, void *data)
 978 {
 979         struct drm_connector *connector = m->private;
 980         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 981         struct dc_link *link = aconnector->dc_link;
 982         bool sink_support_replay = false;
 983         bool driver_support_replay = false;
 984
 985         if (!link)
 986                 return -ENODEV;
 987
 988         if (link->type == dc_connection_none)
 989                 return -ENODEV;
 990
 991         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
 992                 return -ENODEV;
 993
 994         /* If Replay is already set to support, skip the checks */
 995         if (link->replay_settings.config.replay_supported) {
 996                 sink_support_replay = true;
 997                 driver_support_replay = true;
 998         } else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
 999                 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1000         } else {
1001                 struct dc *dc = link->ctx->dc;
1002
1003                 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1004                 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)
1005                         driver_support_replay =
1006                                 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
1007         }
1008
1009         seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));
1010         seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay));
1011         seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported));
1012
1013         return 0;
1014 }
1015
1016 /* psr_capability_show() - show eDP panel PSR capability
1017  *
1018  * The read function: sink_psr_capability_show
1019  * Shows if sink has PSR capability or not.
1020  * If yes - the PSR version is appended
1021  *
1022  *      cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
1023  *
1024  * Expected output:
1025  * "Sink support: no\n" - if panel doesn't support PSR
1026  * "Sink support: yes [0x01]\n" - if panel supports PSR1
1027  * "Driver support: no\n" - if driver doesn't support PSR
1028  * "Driver support: yes [0x01]\n" - if driver supports PSR1
1029  */
1030 static int psr_capability_show(struct seq_file *m, void *data)
1031 {
1032         struct drm_connector *connector = m->private;
1033         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1034         struct dc_link *link = aconnector->dc_link;
1035
1036         if (!link)
1037                 return -ENODEV;
1038
1039         if (link->type == dc_connection_none)
1040                 return -ENODEV;
1041
1042         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1043                 return -ENODEV;
1044
1045         seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
1046         if (link->dpcd_caps.psr_info.psr_version)
1047                 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
1048         seq_puts(m, "\n");
1049
1050         seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
1051         if (link->psr_settings.psr_version)
1052                 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
1053         seq_puts(m, "\n");
1054
1055         return 0;
1056 }
1057
1058 /*
1059  * Returns the current bpc for the crtc.
1060  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
1061  */
1062 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
1063 {
1064         struct drm_crtc *crtc = m->private;
1065         struct drm_device *dev = crtc->dev;
1066         struct dm_crtc_state *dm_crtc_state = NULL;
1067         int res = -ENODEV;
1068         unsigned int bpc;
1069
1070         mutex_lock(&dev->mode_config.mutex);
1071         drm_modeset_lock(&crtc->mutex, NULL);
1072         if (crtc->state == NULL)
1073                 goto unlock;
1074
1075         dm_crtc_state = to_dm_crtc_state(crtc->state);
1076         if (dm_crtc_state->stream == NULL)
1077                 goto unlock;
1078
1079         switch (dm_crtc_state->stream->timing.display_color_depth) {
1080         case COLOR_DEPTH_666:
1081                 bpc = 6;
1082                 break;
1083         case COLOR_DEPTH_888:
1084                 bpc = 8;
1085                 break;
1086         case COLOR_DEPTH_101010:
1087                 bpc = 10;
1088                 break;
1089         case COLOR_DEPTH_121212:
1090                 bpc = 12;
1091                 break;
1092         case COLOR_DEPTH_161616:
1093                 bpc = 16;
1094                 break;
1095         default:
1096                 goto unlock;
1097         }
1098
1099         seq_printf(m, "Current: %u\n", bpc);
1100         res = 0;
1101
1102 unlock:
1103         drm_modeset_unlock(&crtc->mutex);
1104         mutex_unlock(&dev->mode_config.mutex);
1105
1106         return res;
1107 }
1108 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
1109
1110 /*
1111  * Returns the current colorspace for the crtc.
1112  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
1113  */
1114 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
1115 {
1116         struct drm_crtc *crtc = m->private;
1117         struct drm_device *dev = crtc->dev;
1118         struct dm_crtc_state *dm_crtc_state = NULL;
1119         int res = -ENODEV;
1120
1121         mutex_lock(&dev->mode_config.mutex);
1122         drm_modeset_lock(&crtc->mutex, NULL);
1123         if (crtc->state == NULL)
1124                 goto unlock;
1125
1126         dm_crtc_state = to_dm_crtc_state(crtc->state);
1127         if (dm_crtc_state->stream == NULL)
1128                 goto unlock;
1129
1130         switch (dm_crtc_state->stream->output_color_space) {
1131         case COLOR_SPACE_SRGB:
1132                 seq_puts(m, "sRGB");
1133                 break;
1134         case COLOR_SPACE_YCBCR601:
1135         case COLOR_SPACE_YCBCR601_LIMITED:
1136                 seq_puts(m, "BT601_YCC");
1137                 break;
1138         case COLOR_SPACE_YCBCR709:
1139         case COLOR_SPACE_YCBCR709_LIMITED:
1140                 seq_puts(m, "BT709_YCC");
1141                 break;
1142         case COLOR_SPACE_ADOBERGB:
1143                 seq_puts(m, "opRGB");
1144                 break;
1145         case COLOR_SPACE_2020_RGB_FULLRANGE:
1146                 seq_puts(m, "BT2020_RGB");
1147                 break;
1148         case COLOR_SPACE_2020_YCBCR:
1149                 seq_puts(m, "BT2020_YCC");
1150                 break;
1151         default:
1152                 goto unlock;
1153         }
1154         res = 0;
1155
1156 unlock:
1157         drm_modeset_unlock(&crtc->mutex);
1158         mutex_unlock(&dev->mode_config.mutex);
1159
1160         return res;
1161 }
1162 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
1163
1164
1165 /*
1166  * Example usage:
1167  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1168  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1169  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1170  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1171  */
1172 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
1173                                  size_t size, loff_t *pos)
1174 {
1175         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1176         char *wr_buf = NULL;
1177         uint32_t wr_buf_size = 42;
1178         int max_param_num = 1;
1179         long param;
1180         uint8_t param_nums = 0;
1181
1182         if (size == 0)
1183                 return -EINVAL;
1184
1185         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1186
1187         if (!wr_buf) {
1188                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1189                 return -ENOSPC;
1190         }
1191
1192         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1193                                            &param, buf,
1194                                            max_param_num,
1195                                            &param_nums)) {
1196                 kfree(wr_buf);
1197                 return -EINVAL;
1198         }
1199
1200         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
1201
1202         kfree(wr_buf);
1203         return 0;
1204 }
1205
1206 /*
1207  * Returns the HDCP capability of the Display (1.4 for now).
1208  *
1209  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
1210  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
1211  *
1212  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
1213  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
1214  */
1215 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
1216 {
1217         struct drm_connector *connector = m->private;
1218         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1219         bool hdcp_cap, hdcp2_cap;
1220
1221         if (connector->status != connector_status_connected)
1222                 return -ENODEV;
1223
1224         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
1225
1226         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1227         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1228
1229
1230         if (hdcp_cap)
1231                 seq_printf(m, "%s ", "HDCP1.4");
1232         if (hdcp2_cap)
1233                 seq_printf(m, "%s ", "HDCP2.2");
1234
1235         if (!hdcp_cap && !hdcp2_cap)
1236                 seq_printf(m, "%s ", "None");
1237
1238         seq_puts(m, "\n");
1239
1240         return 0;
1241 }
1242
1243 /*
1244  * Returns whether the connected display is internal and not hotpluggable.
1245  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1246  */
1247 static int internal_display_show(struct seq_file *m, void *data)
1248 {
1249         struct drm_connector *connector = m->private;
1250         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1251         struct dc_link *link = aconnector->dc_link;
1252
1253         seq_printf(m, "Internal: %u\n", link->is_internal_display);
1254
1255         return 0;
1256 }
1257
1258 /*
1259  * Returns the number of segments used if ODM Combine mode is enabled.
1260  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments
1261  */
1262 static int odm_combine_segments_show(struct seq_file *m, void *unused)
1263 {
1264         struct drm_connector *connector = m->private;
1265         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1266         struct dc_link *link = aconnector->dc_link;
1267         struct pipe_ctx *pipe_ctx = NULL;
1268         int i, segments = -EOPNOTSUPP;
1269
1270         for (i = 0; i < MAX_PIPES; i++) {
1271                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
1272                 if (pipe_ctx->stream &&
1273                     pipe_ctx->stream->link == link)
1274                         break;
1275         }
1276
1277         if (connector->status != connector_status_connected)
1278                 return -ENODEV;
1279
1280         if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)
1281                 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);
1282
1283         seq_printf(m, "%d\n", segments);
1284         return 0;
1285 }
1286
1287 /* function description
1288  *
1289  * generic SDP message access for testing
1290  *
1291  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1292  *
1293  * SDP header
1294  * Hb0 : Secondary-Data Packet ID
1295  * Hb1 : Secondary-Data Packet type
1296  * Hb2 : Secondary-Data-packet-specific header, Byte 0
1297  * Hb3 : Secondary-Data-packet-specific header, Byte 1
1298  *
1299  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1300  */
1301 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1302                                  size_t size, loff_t *pos)
1303 {
1304         int r;
1305         uint8_t data[36] = {0};
1306         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1307         struct dm_crtc_state *acrtc_state;
1308         uint32_t write_size = 36;
1309
1310         if (connector->base.status != connector_status_connected)
1311                 return -ENODEV;
1312
1313         if (size == 0)
1314                 return 0;
1315
1316         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1317
1318         r = copy_from_user(data, buf, write_size);
1319
1320         write_size -= r;
1321
1322         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1323
1324         return write_size;
1325 }
1326
1327 /* function: Read link's DSC & FEC capabilities
1328  *
1329  *
1330  * Access it with the following command (you need to specify
1331  * connector like DP-1):
1332  *
1333  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1334  *
1335  */
1336 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1337 {
1338         struct drm_connector *connector = m->private;
1339         struct drm_modeset_acquire_ctx ctx;
1340         struct drm_device *dev = connector->dev;
1341         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1342         int ret = 0;
1343         bool try_again = false;
1344         bool is_fec_supported = false;
1345         bool is_dsc_supported = false;
1346         struct dpcd_caps dpcd_caps;
1347
1348         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1349         do {
1350                 try_again = false;
1351                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1352                 if (ret) {
1353                         if (ret == -EDEADLK) {
1354                                 ret = drm_modeset_backoff(&ctx);
1355                                 if (!ret) {
1356                                         try_again = true;
1357                                         continue;
1358                                 }
1359                         }
1360                         break;
1361                 }
1362                 if (connector->status != connector_status_connected) {
1363                         ret = -ENODEV;
1364                         break;
1365                 }
1366                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1367                 if (aconnector->mst_output_port) {
1368                         /* aconnector sets dsc_aux during get_modes call
1369                          * if MST connector has it means it can either
1370                          * enable DSC on the sink device or on MST branch
1371                          * its connected to.
1372                          */
1373                         if (aconnector->dsc_aux) {
1374                                 is_fec_supported = true;
1375                                 is_dsc_supported = true;
1376                         }
1377                 } else {
1378                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1379                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1380                 }
1381         } while (try_again);
1382
1383         drm_modeset_drop_locks(&ctx);
1384         drm_modeset_acquire_fini(&ctx);
1385
1386         seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1387         seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1388
1389         return ret;
1390 }
1391
1392 /* function: Trigger virtual HPD redetection on connector
1393  *
1394  * This function will perform link rediscovery, link disable
1395  * and enable, and dm connector state update.
1396  *
1397  * Retrigger HPD on an existing connector by echoing 1 into
1398  * its respectful "trigger_hotplug" debugfs entry:
1399  *
1400  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1401  *
1402  * This function can perform HPD unplug:
1403  *
1404  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1405  *
1406  */
1407 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1408                                                         size_t size, loff_t *pos)
1409 {
1410         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1411         struct drm_connector *connector = &aconnector->base;
1412         struct dc_link *link = NULL;
1413         struct drm_device *dev = connector->dev;
1414         struct amdgpu_device *adev = drm_to_adev(dev);
1415         enum dc_connection_type new_connection_type = dc_connection_none;
1416         char *wr_buf = NULL;
1417         uint32_t wr_buf_size = 42;
1418         int max_param_num = 1;
1419         long param[1] = {0};
1420         uint8_t param_nums = 0;
1421         bool ret = false;
1422
1423         if (!aconnector->dc_link)
1424                 return -EINVAL;
1425
1426         if (size == 0)
1427                 return -EINVAL;
1428
1429         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1430
1431         if (!wr_buf) {
1432                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1433                 return -ENOSPC;
1434         }
1435
1436         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1437                                                 (long *)param, buf,
1438                                                 max_param_num,
1439                                                 &param_nums)) {
1440                 kfree(wr_buf);
1441                 return -EINVAL;
1442         }
1443
1444         kfree(wr_buf);
1445
1446         if (param_nums <= 0) {
1447                 DRM_DEBUG_DRIVER("user data not be read\n");
1448                 return -EINVAL;
1449         }
1450
1451         mutex_lock(&aconnector->hpd_lock);
1452
1453         /* Don't support for mst end device*/
1454         if (aconnector->mst_root) {
1455                 mutex_unlock(&aconnector->hpd_lock);
1456                 return -EINVAL;
1457         }
1458
1459         if (param[0] == 1) {
1460
1461                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) &&
1462                         new_connection_type != dc_connection_none)
1463                         goto unlock;
1464
1465                 mutex_lock(&adev->dm.dc_lock);
1466                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1467                 mutex_unlock(&adev->dm.dc_lock);
1468
1469                 if (!ret)
1470                         goto unlock;
1471
1472                 amdgpu_dm_update_connector_after_detect(aconnector);
1473
1474                 drm_modeset_lock_all(dev);
1475                 dm_restore_drm_connector_state(dev, connector);
1476                 drm_modeset_unlock_all(dev);
1477
1478                 drm_kms_helper_connector_hotplug_event(connector);
1479         } else if (param[0] == 0) {
1480                 if (!aconnector->dc_link)
1481                         goto unlock;
1482
1483                 link = aconnector->dc_link;
1484
1485                 if (link->local_sink) {
1486                         dc_sink_release(link->local_sink);
1487                         link->local_sink = NULL;
1488                 }
1489
1490                 link->dpcd_sink_count = 0;
1491                 link->type = dc_connection_none;
1492                 link->dongle_max_pix_clk = 0;
1493
1494                 amdgpu_dm_update_connector_after_detect(aconnector);
1495
1496                 /* If the aconnector is the root node in mst topology */
1497                 if (aconnector->mst_mgr.mst_state == true)
1498                         dc_link_reset_cur_dp_mst_topology(link);
1499
1500                 drm_modeset_lock_all(dev);
1501                 dm_restore_drm_connector_state(dev, connector);
1502                 drm_modeset_unlock_all(dev);
1503
1504                 drm_kms_helper_connector_hotplug_event(connector);
1505         }
1506
1507 unlock:
1508         mutex_unlock(&aconnector->hpd_lock);
1509
1510         return size;
1511 }
1512
1513 /* function: read DSC status on the connector
1514  *
1515  * The read function: dp_dsc_clock_en_read
1516  * returns current status of DSC clock on the connector.
1517  * The return is a boolean flag: 1 or 0.
1518  *
1519  * Access it with the following command (you need to specify
1520  * connector like DP-1):
1521  *
1522  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1523  *
1524  * Expected output:
1525  * 1 - means that DSC is currently enabled
1526  * 0 - means that DSC is disabled
1527  */
1528 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1529                                     size_t size, loff_t *pos)
1530 {
1531         char *rd_buf = NULL;
1532         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1533         struct display_stream_compressor *dsc;
1534         struct dcn_dsc_state dsc_state = {0};
1535         const uint32_t rd_buf_size = 10;
1536         struct pipe_ctx *pipe_ctx;
1537         ssize_t result = 0;
1538         int i, r, str_len = 10;
1539
1540         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1541
1542         if (!rd_buf)
1543                 return -ENOMEM;
1544
1545         for (i = 0; i < MAX_PIPES; i++) {
1546                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1547                 if (pipe_ctx->stream &&
1548                     pipe_ctx->stream->link == aconnector->dc_link &&
1549                     pipe_ctx->stream->sink &&
1550                     pipe_ctx->stream->sink == aconnector->dc_sink)
1551                         break;
1552         }
1553
1554         dsc = pipe_ctx->stream_res.dsc;
1555         if (dsc)
1556                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1557
1558         snprintf(rd_buf, str_len,
1559                 "%d\n",
1560                 dsc_state.dsc_clock_en);
1561
1562         while (size) {
1563                 if (*pos >= rd_buf_size)
1564                         break;
1565
1566                 r = put_user(*(rd_buf + result), buf);
1567                 if (r) {
1568                         kfree(rd_buf);
1569                         return r; /* r = -EFAULT */
1570                 }
1571
1572                 buf += 1;
1573                 size -= 1;
1574                 *pos += 1;
1575                 result += 1;
1576         }
1577
1578         kfree(rd_buf);
1579         return result;
1580 }
1581
1582 /* function: write force DSC on the connector
1583  *
1584  * The write function: dp_dsc_clock_en_write
1585  * enables to force DSC on the connector.
1586  * User can write to either force enable or force disable DSC
1587  * on the next modeset or set it to driver default
1588  *
1589  * Accepted inputs:
1590  * 0 - default DSC enablement policy
1591  * 1 - force enable DSC on the connector
1592  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1593  *
1594  * Writing DSC settings is done with the following command:
1595  * - To force enable DSC (you need to specify
1596  * connector like DP-1):
1597  *
1598  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1599  *
1600  * - To return to default state set the flag to zero and
1601  * let driver deal with DSC automatically
1602  * (you need to specify connector like DP-1):
1603  *
1604  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1605  *
1606  */
1607 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1608                                      size_t size, loff_t *pos)
1609 {
1610         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1611         struct drm_connector *connector = &aconnector->base;
1612         struct drm_device *dev = connector->dev;
1613         struct drm_crtc *crtc = NULL;
1614         struct dm_crtc_state *dm_crtc_state = NULL;
1615         struct pipe_ctx *pipe_ctx;
1616         int i;
1617         char *wr_buf = NULL;
1618         uint32_t wr_buf_size = 42;
1619         int max_param_num = 1;
1620         long param[1] = {0};
1621         uint8_t param_nums = 0;
1622
1623         if (size == 0)
1624                 return -EINVAL;
1625
1626         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1627
1628         if (!wr_buf) {
1629                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1630                 return -ENOSPC;
1631         }
1632
1633         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1634                                             (long *)param, buf,
1635                                             max_param_num,
1636                                             &param_nums)) {
1637                 kfree(wr_buf);
1638                 return -EINVAL;
1639         }
1640
1641         if (param_nums <= 0) {
1642                 DRM_DEBUG_DRIVER("user data not be read\n");
1643                 kfree(wr_buf);
1644                 return -EINVAL;
1645         }
1646
1647         for (i = 0; i < MAX_PIPES; i++) {
1648                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1649                 if (pipe_ctx->stream &&
1650                     pipe_ctx->stream->link == aconnector->dc_link &&
1651                     pipe_ctx->stream->sink &&
1652                     pipe_ctx->stream->sink == aconnector->dc_sink)
1653                         break;
1654         }
1655
1656         if (!pipe_ctx->stream)
1657                 goto done;
1658
1659         // Get CRTC state
1660         mutex_lock(&dev->mode_config.mutex);
1661         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1662
1663         if (connector->state == NULL)
1664                 goto unlock;
1665
1666         crtc = connector->state->crtc;
1667         if (crtc == NULL)
1668                 goto unlock;
1669
1670         drm_modeset_lock(&crtc->mutex, NULL);
1671         if (crtc->state == NULL)
1672                 goto unlock;
1673
1674         dm_crtc_state = to_dm_crtc_state(crtc->state);
1675         if (dm_crtc_state->stream == NULL)
1676                 goto unlock;
1677
1678         if (param[0] == 1)
1679                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1680         else if (param[0] == 2)
1681                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1682         else
1683                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1684
1685         dm_crtc_state->dsc_force_changed = true;
1686
1687 unlock:
1688         if (crtc)
1689                 drm_modeset_unlock(&crtc->mutex);
1690         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1691         mutex_unlock(&dev->mode_config.mutex);
1692
1693 done:
1694         kfree(wr_buf);
1695         return size;
1696 }
1697
1698 /* function: read DSC slice width parameter on the connector
1699  *
1700  * The read function: dp_dsc_slice_width_read
1701  * returns dsc slice width used in the current configuration
1702  * The return is an integer: 0 or other positive number
1703  *
1704  * Access the status with the following command:
1705  *
1706  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1707  *
1708  * 0 - means that DSC is disabled
1709  *
1710  * Any other number more than zero represents the
1711  * slice width currently used by DSC in pixels
1712  *
1713  */
1714 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1715                                     size_t size, loff_t *pos)
1716 {
1717         char *rd_buf = NULL;
1718         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1719         struct display_stream_compressor *dsc;
1720         struct dcn_dsc_state dsc_state = {0};
1721         const uint32_t rd_buf_size = 100;
1722         struct pipe_ctx *pipe_ctx;
1723         ssize_t result = 0;
1724         int i, r, str_len = 30;
1725
1726         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1727
1728         if (!rd_buf)
1729                 return -ENOMEM;
1730
1731         for (i = 0; i < MAX_PIPES; i++) {
1732                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1733                 if (pipe_ctx->stream &&
1734                     pipe_ctx->stream->link == aconnector->dc_link &&
1735                     pipe_ctx->stream->sink &&
1736                     pipe_ctx->stream->sink == aconnector->dc_sink)
1737                         break;
1738         }
1739
1740         dsc = pipe_ctx->stream_res.dsc;
1741         if (dsc)
1742                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1743
1744         snprintf(rd_buf, str_len,
1745                 "%d\n",
1746                 dsc_state.dsc_slice_width);
1747
1748         while (size) {
1749                 if (*pos >= rd_buf_size)
1750                         break;
1751
1752                 r = put_user(*(rd_buf + result), buf);
1753                 if (r) {
1754                         kfree(rd_buf);
1755                         return r; /* r = -EFAULT */
1756                 }
1757
1758                 buf += 1;
1759                 size -= 1;
1760                 *pos += 1;
1761                 result += 1;
1762         }
1763
1764         kfree(rd_buf);
1765         return result;
1766 }
1767
1768 /* function: write DSC slice width parameter
1769  *
1770  * The write function: dp_dsc_slice_width_write
1771  * overwrites automatically generated DSC configuration
1772  * of slice width.
1773  *
1774  * The user has to write the slice width divisible by the
1775  * picture width.
1776  *
1777  * Also the user has to write width in hexidecimal
1778  * rather than in decimal.
1779  *
1780  * Writing DSC settings is done with the following command:
1781  * - To force overwrite slice width: (example sets to 1920 pixels)
1782  *
1783  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1784  *
1785  *  - To stop overwriting and let driver find the optimal size,
1786  * set the width to zero:
1787  *
1788  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1789  *
1790  */
1791 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1792                                      size_t size, loff_t *pos)
1793 {
1794         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1795         struct pipe_ctx *pipe_ctx;
1796         struct drm_connector *connector = &aconnector->base;
1797         struct drm_device *dev = connector->dev;
1798         struct drm_crtc *crtc = NULL;
1799         struct dm_crtc_state *dm_crtc_state = NULL;
1800         int i;
1801         char *wr_buf = NULL;
1802         uint32_t wr_buf_size = 42;
1803         int max_param_num = 1;
1804         long param[1] = {0};
1805         uint8_t param_nums = 0;
1806
1807         if (size == 0)
1808                 return -EINVAL;
1809
1810         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1811
1812         if (!wr_buf) {
1813                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1814                 return -ENOSPC;
1815         }
1816
1817         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1818                                             (long *)param, buf,
1819                                             max_param_num,
1820                                             &param_nums)) {
1821                 kfree(wr_buf);
1822                 return -EINVAL;
1823         }
1824
1825         if (param_nums <= 0) {
1826                 DRM_DEBUG_DRIVER("user data not be read\n");
1827                 kfree(wr_buf);
1828                 return -EINVAL;
1829         }
1830
1831         for (i = 0; i < MAX_PIPES; i++) {
1832                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1833                 if (pipe_ctx->stream &&
1834                     pipe_ctx->stream->link == aconnector->dc_link &&
1835                     pipe_ctx->stream->sink &&
1836                     pipe_ctx->stream->sink == aconnector->dc_sink)
1837                         break;
1838         }
1839
1840         if (!pipe_ctx->stream)
1841                 goto done;
1842
1843         // Safely get CRTC state
1844         mutex_lock(&dev->mode_config.mutex);
1845         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1846
1847         if (connector->state == NULL)
1848                 goto unlock;
1849
1850         crtc = connector->state->crtc;
1851         if (crtc == NULL)
1852                 goto unlock;
1853
1854         drm_modeset_lock(&crtc->mutex, NULL);
1855         if (crtc->state == NULL)
1856                 goto unlock;
1857
1858         dm_crtc_state = to_dm_crtc_state(crtc->state);
1859         if (dm_crtc_state->stream == NULL)
1860                 goto unlock;
1861
1862         if (param[0] > 0)
1863                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1864                                         pipe_ctx->stream->timing.h_addressable,
1865                                         param[0]);
1866         else
1867                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1868
1869         dm_crtc_state->dsc_force_changed = true;
1870
1871 unlock:
1872         if (crtc)
1873                 drm_modeset_unlock(&crtc->mutex);
1874         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1875         mutex_unlock(&dev->mode_config.mutex);
1876
1877 done:
1878         kfree(wr_buf);
1879         return size;
1880 }
1881
1882 /* function: read DSC slice height parameter on the connector
1883  *
1884  * The read function: dp_dsc_slice_height_read
1885  * returns dsc slice height used in the current configuration
1886  * The return is an integer: 0 or other positive number
1887  *
1888  * Access the status with the following command:
1889  *
1890  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1891  *
1892  * 0 - means that DSC is disabled
1893  *
1894  * Any other number more than zero represents the
1895  * slice height currently used by DSC in pixels
1896  *
1897  */
1898 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1899                                     size_t size, loff_t *pos)
1900 {
1901         char *rd_buf = NULL;
1902         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1903         struct display_stream_compressor *dsc;
1904         struct dcn_dsc_state dsc_state = {0};
1905         const uint32_t rd_buf_size = 100;
1906         struct pipe_ctx *pipe_ctx;
1907         ssize_t result = 0;
1908         int i, r, str_len = 30;
1909
1910         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1911
1912         if (!rd_buf)
1913                 return -ENOMEM;
1914
1915         for (i = 0; i < MAX_PIPES; i++) {
1916                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1917                 if (pipe_ctx->stream &&
1918                     pipe_ctx->stream->link == aconnector->dc_link &&
1919                     pipe_ctx->stream->sink &&
1920                     pipe_ctx->stream->sink == aconnector->dc_sink)
1921                         break;
1922         }
1923
1924         dsc = pipe_ctx->stream_res.dsc;
1925         if (dsc)
1926                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1927
1928         snprintf(rd_buf, str_len,
1929                 "%d\n",
1930                 dsc_state.dsc_slice_height);
1931
1932         while (size) {
1933                 if (*pos >= rd_buf_size)
1934                         break;
1935
1936                 r = put_user(*(rd_buf + result), buf);
1937                 if (r) {
1938                         kfree(rd_buf);
1939                         return r; /* r = -EFAULT */
1940                 }
1941
1942                 buf += 1;
1943                 size -= 1;
1944                 *pos += 1;
1945                 result += 1;
1946         }
1947
1948         kfree(rd_buf);
1949         return result;
1950 }
1951
1952 /* function: write DSC slice height parameter
1953  *
1954  * The write function: dp_dsc_slice_height_write
1955  * overwrites automatically generated DSC configuration
1956  * of slice height.
1957  *
1958  * The user has to write the slice height divisible by the
1959  * picture height.
1960  *
1961  * Also the user has to write height in hexidecimal
1962  * rather than in decimal.
1963  *
1964  * Writing DSC settings is done with the following command:
1965  * - To force overwrite slice height (example sets to 128 pixels):
1966  *
1967  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1968  *
1969  *  - To stop overwriting and let driver find the optimal size,
1970  * set the height to zero:
1971  *
1972  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1973  *
1974  */
1975 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1976                                      size_t size, loff_t *pos)
1977 {
1978         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1979         struct drm_connector *connector = &aconnector->base;
1980         struct drm_device *dev = connector->dev;
1981         struct drm_crtc *crtc = NULL;
1982         struct dm_crtc_state *dm_crtc_state = NULL;
1983         struct pipe_ctx *pipe_ctx;
1984         int i;
1985         char *wr_buf = NULL;
1986         uint32_t wr_buf_size = 42;
1987         int max_param_num = 1;
1988         uint8_t param_nums = 0;
1989         long param[1] = {0};
1990
1991         if (size == 0)
1992                 return -EINVAL;
1993
1994         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1995
1996         if (!wr_buf) {
1997                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1998                 return -ENOSPC;
1999         }
2000
2001         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2002                                             (long *)param, buf,
2003                                             max_param_num,
2004                                             &param_nums)) {
2005                 kfree(wr_buf);
2006                 return -EINVAL;
2007         }
2008
2009         if (param_nums <= 0) {
2010                 DRM_DEBUG_DRIVER("user data not be read\n");
2011                 kfree(wr_buf);
2012                 return -EINVAL;
2013         }
2014
2015         for (i = 0; i < MAX_PIPES; i++) {
2016                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2017                 if (pipe_ctx->stream &&
2018                     pipe_ctx->stream->link == aconnector->dc_link &&
2019                     pipe_ctx->stream->sink &&
2020                     pipe_ctx->stream->sink == aconnector->dc_sink)
2021                         break;
2022         }
2023
2024         if (!pipe_ctx->stream)
2025                 goto done;
2026
2027         // Get CRTC state
2028         mutex_lock(&dev->mode_config.mutex);
2029         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2030
2031         if (connector->state == NULL)
2032                 goto unlock;
2033
2034         crtc = connector->state->crtc;
2035         if (crtc == NULL)
2036                 goto unlock;
2037
2038         drm_modeset_lock(&crtc->mutex, NULL);
2039         if (crtc->state == NULL)
2040                 goto unlock;
2041
2042         dm_crtc_state = to_dm_crtc_state(crtc->state);
2043         if (dm_crtc_state->stream == NULL)
2044                 goto unlock;
2045
2046         if (param[0] > 0)
2047                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
2048                                         pipe_ctx->stream->timing.v_addressable,
2049                                         param[0]);
2050         else
2051                 aconnector->dsc_settings.dsc_num_slices_v = 0;
2052
2053         dm_crtc_state->dsc_force_changed = true;
2054
2055 unlock:
2056         if (crtc)
2057                 drm_modeset_unlock(&crtc->mutex);
2058         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2059         mutex_unlock(&dev->mode_config.mutex);
2060
2061 done:
2062         kfree(wr_buf);
2063         return size;
2064 }
2065
2066 /* function: read DSC target rate on the connector in bits per pixel
2067  *
2068  * The read function: dp_dsc_bits_per_pixel_read
2069  * returns target rate of compression in bits per pixel
2070  * The return is an integer: 0 or other positive integer
2071  *
2072  * Access it with the following command:
2073  *
2074  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2075  *
2076  *  0 - means that DSC is disabled
2077  */
2078 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
2079                                     size_t size, loff_t *pos)
2080 {
2081         char *rd_buf = NULL;
2082         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2083         struct display_stream_compressor *dsc;
2084         struct dcn_dsc_state dsc_state = {0};
2085         const uint32_t rd_buf_size = 100;
2086         struct pipe_ctx *pipe_ctx;
2087         ssize_t result = 0;
2088         int i, r, str_len = 30;
2089
2090         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2091
2092         if (!rd_buf)
2093                 return -ENOMEM;
2094
2095         for (i = 0; i < MAX_PIPES; i++) {
2096                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2097                 if (pipe_ctx->stream &&
2098                     pipe_ctx->stream->link == aconnector->dc_link &&
2099                     pipe_ctx->stream->sink &&
2100                     pipe_ctx->stream->sink == aconnector->dc_sink)
2101                         break;
2102         }
2103
2104         dsc = pipe_ctx->stream_res.dsc;
2105         if (dsc)
2106                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2107
2108         snprintf(rd_buf, str_len,
2109                 "%d\n",
2110                 dsc_state.dsc_bits_per_pixel);
2111
2112         while (size) {
2113                 if (*pos >= rd_buf_size)
2114                         break;
2115
2116                 r = put_user(*(rd_buf + result), buf);
2117                 if (r) {
2118                         kfree(rd_buf);
2119                         return r; /* r = -EFAULT */
2120                 }
2121
2122                 buf += 1;
2123                 size -= 1;
2124                 *pos += 1;
2125                 result += 1;
2126         }
2127
2128         kfree(rd_buf);
2129         return result;
2130 }
2131
2132 /* function: write DSC target rate in bits per pixel
2133  *
2134  * The write function: dp_dsc_bits_per_pixel_write
2135  * overwrites automatically generated DSC configuration
2136  * of DSC target bit rate.
2137  *
2138  * Also the user has to write bpp in hexidecimal
2139  * rather than in decimal.
2140  *
2141  * Writing DSC settings is done with the following command:
2142  * - To force overwrite rate (example sets to 256 bpp x 1/16):
2143  *
2144  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2145  *
2146  *  - To stop overwriting and let driver find the optimal rate,
2147  * set the rate to zero:
2148  *
2149  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2150  *
2151  */
2152 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
2153                                      size_t size, loff_t *pos)
2154 {
2155         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2156         struct drm_connector *connector = &aconnector->base;
2157         struct drm_device *dev = connector->dev;
2158         struct drm_crtc *crtc = NULL;
2159         struct dm_crtc_state *dm_crtc_state = NULL;
2160         struct pipe_ctx *pipe_ctx;
2161         int i;
2162         char *wr_buf = NULL;
2163         uint32_t wr_buf_size = 42;
2164         int max_param_num = 1;
2165         uint8_t param_nums = 0;
2166         long param[1] = {0};
2167
2168         if (size == 0)
2169                 return -EINVAL;
2170
2171         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2172
2173         if (!wr_buf) {
2174                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2175                 return -ENOSPC;
2176         }
2177
2178         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2179                                             (long *)param, buf,
2180                                             max_param_num,
2181                                             &param_nums)) {
2182                 kfree(wr_buf);
2183                 return -EINVAL;
2184         }
2185
2186         if (param_nums <= 0) {
2187                 DRM_DEBUG_DRIVER("user data not be read\n");
2188                 kfree(wr_buf);
2189                 return -EINVAL;
2190         }
2191
2192         for (i = 0; i < MAX_PIPES; i++) {
2193                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2194                 if (pipe_ctx->stream &&
2195                     pipe_ctx->stream->link == aconnector->dc_link &&
2196                     pipe_ctx->stream->sink &&
2197                     pipe_ctx->stream->sink == aconnector->dc_sink)
2198                         break;
2199         }
2200
2201         if (!pipe_ctx->stream)
2202                 goto done;
2203
2204         // Get CRTC state
2205         mutex_lock(&dev->mode_config.mutex);
2206         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2207
2208         if (connector->state == NULL)
2209                 goto unlock;
2210
2211         crtc = connector->state->crtc;
2212         if (crtc == NULL)
2213                 goto unlock;
2214
2215         drm_modeset_lock(&crtc->mutex, NULL);
2216         if (crtc->state == NULL)
2217                 goto unlock;
2218
2219         dm_crtc_state = to_dm_crtc_state(crtc->state);
2220         if (dm_crtc_state->stream == NULL)
2221                 goto unlock;
2222
2223         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2224
2225         dm_crtc_state->dsc_force_changed = true;
2226
2227 unlock:
2228         if (crtc)
2229                 drm_modeset_unlock(&crtc->mutex);
2230         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2231         mutex_unlock(&dev->mode_config.mutex);
2232
2233 done:
2234         kfree(wr_buf);
2235         return size;
2236 }
2237
2238 /* function: read DSC picture width parameter on the connector
2239  *
2240  * The read function: dp_dsc_pic_width_read
2241  * returns dsc picture width used in the current configuration
2242  * It is the same as h_addressable of the current
2243  * display's timing
2244  * The return is an integer: 0 or other positive integer
2245  * If 0 then DSC is disabled.
2246  *
2247  * Access it with the following command:
2248  *
2249  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2250  *
2251  * 0 - means that DSC is disabled
2252  */
2253 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2254                                     size_t size, loff_t *pos)
2255 {
2256         char *rd_buf = NULL;
2257         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2258         struct display_stream_compressor *dsc;
2259         struct dcn_dsc_state dsc_state = {0};
2260         const uint32_t rd_buf_size = 100;
2261         struct pipe_ctx *pipe_ctx;
2262         ssize_t result = 0;
2263         int i, r, str_len = 30;
2264
2265         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2266
2267         if (!rd_buf)
2268                 return -ENOMEM;
2269
2270         for (i = 0; i < MAX_PIPES; i++) {
2271                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2272                 if (pipe_ctx->stream &&
2273                     pipe_ctx->stream->link == aconnector->dc_link &&
2274                     pipe_ctx->stream->sink &&
2275                     pipe_ctx->stream->sink == aconnector->dc_sink)
2276                         break;
2277         }
2278
2279         dsc = pipe_ctx->stream_res.dsc;
2280         if (dsc)
2281                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2282
2283         snprintf(rd_buf, str_len,
2284                 "%d\n",
2285                 dsc_state.dsc_pic_width);
2286
2287         while (size) {
2288                 if (*pos >= rd_buf_size)
2289                         break;
2290
2291                 r = put_user(*(rd_buf + result), buf);
2292                 if (r) {
2293                         kfree(rd_buf);
2294                         return r; /* r = -EFAULT */
2295                 }
2296
2297                 buf += 1;
2298                 size -= 1;
2299                 *pos += 1;
2300                 result += 1;
2301         }
2302
2303         kfree(rd_buf);
2304         return result;
2305 }
2306
2307 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2308                                     size_t size, loff_t *pos)
2309 {
2310         char *rd_buf = NULL;
2311         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2312         struct display_stream_compressor *dsc;
2313         struct dcn_dsc_state dsc_state = {0};
2314         const uint32_t rd_buf_size = 100;
2315         struct pipe_ctx *pipe_ctx;
2316         ssize_t result = 0;
2317         int i, r, str_len = 30;
2318
2319         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2320
2321         if (!rd_buf)
2322                 return -ENOMEM;
2323
2324         for (i = 0; i < MAX_PIPES; i++) {
2325                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2326                 if (pipe_ctx->stream &&
2327                     pipe_ctx->stream->link == aconnector->dc_link &&
2328                     pipe_ctx->stream->sink &&
2329                     pipe_ctx->stream->sink == aconnector->dc_sink)
2330                         break;
2331         }
2332
2333         dsc = pipe_ctx->stream_res.dsc;
2334         if (dsc)
2335                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2336
2337         snprintf(rd_buf, str_len,
2338                 "%d\n",
2339                 dsc_state.dsc_pic_height);
2340
2341         while (size) {
2342                 if (*pos >= rd_buf_size)
2343                         break;
2344
2345                 r = put_user(*(rd_buf + result), buf);
2346                 if (r) {
2347                         kfree(rd_buf);
2348                         return r; /* r = -EFAULT */
2349                 }
2350
2351                 buf += 1;
2352                 size -= 1;
2353                 *pos += 1;
2354                 result += 1;
2355         }
2356
2357         kfree(rd_buf);
2358         return result;
2359 }
2360
2361 /* function: read DSC chunk size parameter on the connector
2362  *
2363  * The read function: dp_dsc_chunk_size_read
2364  * returns dsc chunk size set in the current configuration
2365  * The value is calculated automatically by DSC code
2366  * and depends on slice parameters and bpp target rate
2367  * The return is an integer: 0 or other positive integer
2368  * If 0 then DSC is disabled.
2369  *
2370  * Access it with the following command:
2371  *
2372  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2373  *
2374  * 0 - means that DSC is disabled
2375  */
2376 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2377                                     size_t size, loff_t *pos)
2378 {
2379         char *rd_buf = NULL;
2380         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2381         struct display_stream_compressor *dsc;
2382         struct dcn_dsc_state dsc_state = {0};
2383         const uint32_t rd_buf_size = 100;
2384         struct pipe_ctx *pipe_ctx;
2385         ssize_t result = 0;
2386         int i, r, str_len = 30;
2387
2388         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2389
2390         if (!rd_buf)
2391                 return -ENOMEM;
2392
2393         for (i = 0; i < MAX_PIPES; i++) {
2394                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2395                 if (pipe_ctx->stream &&
2396                     pipe_ctx->stream->link == aconnector->dc_link &&
2397                     pipe_ctx->stream->sink &&
2398                     pipe_ctx->stream->sink == aconnector->dc_sink)
2399                         break;
2400         }
2401
2402         dsc = pipe_ctx->stream_res.dsc;
2403         if (dsc)
2404                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2405
2406         snprintf(rd_buf, str_len,
2407                 "%d\n",
2408                 dsc_state.dsc_chunk_size);
2409
2410         while (size) {
2411                 if (*pos >= rd_buf_size)
2412                         break;
2413
2414                 r = put_user(*(rd_buf + result), buf);
2415                 if (r) {
2416                         kfree(rd_buf);
2417                         return r; /* r = -EFAULT */
2418                 }
2419
2420                 buf += 1;
2421                 size -= 1;
2422                 *pos += 1;
2423                 result += 1;
2424         }
2425
2426         kfree(rd_buf);
2427         return result;
2428 }
2429
2430 /* function: read DSC slice bpg offset on the connector
2431  *
2432  * The read function: dp_dsc_slice_bpg_offset_read
2433  * returns dsc bpg slice offset set in the current configuration
2434  * The value is calculated automatically by DSC code
2435  * and depends on slice parameters and bpp target rate
2436  * The return is an integer: 0 or other positive integer
2437  * If 0 then DSC is disabled.
2438  *
2439  * Access it with the following command:
2440  *
2441  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2442  *
2443  * 0 - means that DSC is disabled
2444  */
2445 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2446                                     size_t size, loff_t *pos)
2447 {
2448         char *rd_buf = NULL;
2449         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2450         struct display_stream_compressor *dsc;
2451         struct dcn_dsc_state dsc_state = {0};
2452         const uint32_t rd_buf_size = 100;
2453         struct pipe_ctx *pipe_ctx;
2454         ssize_t result = 0;
2455         int i, r, str_len = 30;
2456
2457         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2458
2459         if (!rd_buf)
2460                 return -ENOMEM;
2461
2462         for (i = 0; i < MAX_PIPES; i++) {
2463                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2464                 if (pipe_ctx->stream &&
2465                     pipe_ctx->stream->link == aconnector->dc_link &&
2466                     pipe_ctx->stream->sink &&
2467                     pipe_ctx->stream->sink == aconnector->dc_sink)
2468                         break;
2469         }
2470
2471         dsc = pipe_ctx->stream_res.dsc;
2472         if (dsc)
2473                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2474
2475         snprintf(rd_buf, str_len,
2476                 "%d\n",
2477                 dsc_state.dsc_slice_bpg_offset);
2478
2479         while (size) {
2480                 if (*pos >= rd_buf_size)
2481                         break;
2482
2483                 r = put_user(*(rd_buf + result), buf);
2484                 if (r) {
2485                         kfree(rd_buf);
2486                         return r; /* r = -EFAULT */
2487                 }
2488
2489                 buf += 1;
2490                 size -= 1;
2491                 *pos += 1;
2492                 result += 1;
2493         }
2494
2495         kfree(rd_buf);
2496         return result;
2497 }
2498
2499
2500 /*
2501  * function description: Read max_requested_bpc property from the connector
2502  *
2503  * Access it with the following command:
2504  *
2505  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2506  *
2507  */
2508 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2509                 size_t size, loff_t *pos)
2510 {
2511         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2512         struct drm_connector *connector = &aconnector->base;
2513         struct drm_device *dev = connector->dev;
2514         struct dm_connector_state *state;
2515         ssize_t result = 0;
2516         char *rd_buf = NULL;
2517         char *rd_buf_ptr = NULL;
2518         const uint32_t rd_buf_size = 10;
2519         int r;
2520
2521         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2522
2523         if (!rd_buf)
2524                 return -ENOMEM;
2525
2526         mutex_lock(&dev->mode_config.mutex);
2527         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2528
2529         if (connector->state == NULL)
2530                 goto unlock;
2531
2532         state = to_dm_connector_state(connector->state);
2533
2534         rd_buf_ptr = rd_buf;
2535         snprintf(rd_buf_ptr, rd_buf_size,
2536                 "%u\n",
2537                 state->base.max_requested_bpc);
2538
2539         while (size) {
2540                 if (*pos >= rd_buf_size)
2541                         break;
2542
2543                 r = put_user(*(rd_buf + result), buf);
2544                 if (r) {
2545                         result = r; /* r = -EFAULT */
2546                         goto unlock;
2547                 }
2548                 buf += 1;
2549                 size -= 1;
2550                 *pos += 1;
2551                 result += 1;
2552         }
2553 unlock:
2554         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2555         mutex_unlock(&dev->mode_config.mutex);
2556         kfree(rd_buf);
2557         return result;
2558 }
2559
2560
2561 /*
2562  * function description: Set max_requested_bpc property on the connector
2563  *
2564  * This function will not force the input BPC on connector, it will only
2565  * change the max value. This is equivalent to setting max_bpc through
2566  * xrandr.
2567  *
2568  * The BPC value written must be >= 6 and <= 16. Values outside of this
2569  * range will result in errors.
2570  *
2571  * BPC values:
2572  *      0x6 - 6 BPC
2573  *      0x8 - 8 BPC
2574  *      0xa - 10 BPC
2575  *      0xc - 12 BPC
2576  *      0x10 - 16 BPC
2577  *
2578  * Write the max_bpc in the following way:
2579  *
2580  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2581  *
2582  */
2583 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2584                                      size_t size, loff_t *pos)
2585 {
2586         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2587         struct drm_connector *connector = &aconnector->base;
2588         struct dm_connector_state *state;
2589         struct drm_device *dev = connector->dev;
2590         char *wr_buf = NULL;
2591         uint32_t wr_buf_size = 42;
2592         int max_param_num = 1;
2593         long param[1] = {0};
2594         uint8_t param_nums = 0;
2595
2596         if (size == 0)
2597                 return -EINVAL;
2598
2599         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2600
2601         if (!wr_buf) {
2602                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2603                 return -ENOSPC;
2604         }
2605
2606         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2607                                            (long *)param, buf,
2608                                            max_param_num,
2609                                            &param_nums)) {
2610                 kfree(wr_buf);
2611                 return -EINVAL;
2612         }
2613
2614         if (param_nums <= 0) {
2615                 DRM_DEBUG_DRIVER("user data not be read\n");
2616                 kfree(wr_buf);
2617                 return -EINVAL;
2618         }
2619
2620         if (param[0] < 6 || param[0] > 16) {
2621                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2622                 kfree(wr_buf);
2623                 return -EINVAL;
2624         }
2625
2626         mutex_lock(&dev->mode_config.mutex);
2627         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2628
2629         if (connector->state == NULL)
2630                 goto unlock;
2631
2632         state = to_dm_connector_state(connector->state);
2633         state->base.max_requested_bpc = param[0];
2634 unlock:
2635         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2636         mutex_unlock(&dev->mode_config.mutex);
2637
2638         kfree(wr_buf);
2639         return size;
2640 }
2641
2642 /*
2643  * IPS status.  Read only.
2644  *
2645  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
2646  */
2647 static int ips_status_show(struct seq_file *m, void *unused)
2648 {
2649         struct amdgpu_device *adev = m->private;
2650         struct dc *dc = adev->dm.dc;
2651         struct dc_dmub_srv *dc_dmub_srv;
2652
2653         seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);
2654         seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);
2655
2656         if (adev->dm.idle_workqueue) {
2657                 seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);
2658                 seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running);
2659         }
2660
2661         dc_dmub_srv = dc->ctx->dmub_srv;
2662         if (dc_dmub_srv && dc_dmub_srv->dmub) {
2663                 uint32_t rcg_count, ips1_count, ips2_count;
2664                 volatile const struct dmub_shared_state_ips_fw *ips_fw =
2665                         &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
2666                 rcg_count = ips_fw->rcg_entry_count;
2667                 ips1_count = ips_fw->ips1_entry_count;
2668                 ips2_count = ips_fw->ips2_entry_count;
2669                 seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n",
2670                            rcg_count,
2671                            ips1_count,
2672                            ips2_count);
2673                 rcg_count = ips_fw->rcg_exit_count;
2674                 ips1_count = ips_fw->ips1_exit_count;
2675                 ips2_count = ips_fw->ips2_exit_count;
2676                 seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u",
2677                            rcg_count,
2678                            ips1_count,
2679                            ips2_count);
2680                 seq_puts(m, "\n");
2681         }
2682         return 0;
2683 }
2684
2685 /*
2686  * Backlight at this moment.  Read only.
2687  * As written to display, taking ABM and backlight lut into account.
2688  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2689  *
2690  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2691  */
2692 static int current_backlight_show(struct seq_file *m, void *unused)
2693 {
2694         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2695         struct dc_link *link = aconnector->dc_link;
2696         unsigned int backlight;
2697
2698         backlight = dc_link_get_backlight_level(link);
2699         seq_printf(m, "0x%x\n", backlight);
2700
2701         return 0;
2702 }
2703
2704 /*
2705  * Backlight value that is being approached.  Read only.
2706  * As written to display, taking ABM and backlight lut into account.
2707  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2708  *
2709  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2710  */
2711 static int target_backlight_show(struct seq_file *m, void *unused)
2712 {
2713         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2714         struct dc_link *link = aconnector->dc_link;
2715         unsigned int backlight;
2716
2717         backlight = dc_link_get_target_backlight_pwm(link);
2718         seq_printf(m, "0x%x\n", backlight);
2719
2720         return 0;
2721 }
2722
2723 /*
2724  * function description: Determine if the connector is mst connector
2725  *
2726  * This function helps to determine whether a connector is a mst connector.
2727  * - "root" stands for the root connector of the topology
2728  * - "branch" stands for branch device of the topology
2729  * - "end" stands for leaf node connector of the topology
2730  * - "no" stands for the connector is not a device of a mst topology
2731  * Access it with the following command:
2732  *
2733  *      cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2734  *
2735  */
2736 static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2737 {
2738         struct drm_connector *connector = m->private;
2739         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2740         struct drm_dp_mst_topology_mgr *mgr = NULL;
2741         struct drm_dp_mst_port *port = NULL;
2742         char *role = NULL;
2743
2744         mutex_lock(&aconnector->hpd_lock);
2745
2746         if (aconnector->mst_mgr.mst_state) {
2747                 role = "root";
2748         } else if (aconnector->mst_root &&
2749                 aconnector->mst_root->mst_mgr.mst_state) {
2750
2751                 role = "end";
2752
2753                 mgr = &aconnector->mst_root->mst_mgr;
2754                 port = aconnector->mst_output_port;
2755
2756                 drm_modeset_lock(&mgr->base.lock, NULL);
2757                 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2758                         port->mcs)
2759                         role = "branch";
2760                 drm_modeset_unlock(&mgr->base.lock);
2761
2762         } else {
2763                 role = "no";
2764         }
2765
2766         seq_printf(m, "%s\n", role);
2767
2768         mutex_unlock(&aconnector->hpd_lock);
2769
2770         return 0;
2771 }
2772
2773 /*
2774  * function description: Read out the mst progress status
2775  *
2776  * This function helps to determine the mst progress status of
2777  * a mst connector.
2778  *
2779  * Access it with the following command:
2780  *
2781  *      cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2782  *
2783  */
2784 static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2785 {
2786         struct drm_connector *connector = m->private;
2787         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2788         struct amdgpu_device *adev = drm_to_adev(connector->dev);
2789         int i;
2790
2791         mutex_lock(&aconnector->hpd_lock);
2792         mutex_lock(&adev->dm.dc_lock);
2793
2794         if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2795                 seq_puts(m, "disabled\n");
2796         } else {
2797                 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2798                         seq_printf(m, "%s:%s\n",
2799                                 mst_progress_status[i],
2800                                 aconnector->mst_status & BIT(i) ? "done" : "not_done");
2801         }
2802
2803         mutex_unlock(&adev->dm.dc_lock);
2804         mutex_unlock(&aconnector->hpd_lock);
2805
2806         return 0;
2807 }
2808
2809 /*
2810  * Reports whether the connected display is a USB4 DPIA tunneled display
2811  * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2812  */
2813 static int is_dpia_link_show(struct seq_file *m, void *data)
2814 {
2815         struct drm_connector *connector = m->private;
2816         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2817         struct dc_link *link = aconnector->dc_link;
2818
2819         if (connector->status != connector_status_connected)
2820                 return -ENODEV;
2821
2822         seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2823                                 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2824
2825         return 0;
2826 }
2827
2828 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2829 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2830 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2831 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2832 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2833 DEFINE_SHOW_ATTRIBUTE(internal_display);
2834 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);
2835 DEFINE_SHOW_ATTRIBUTE(replay_capability);
2836 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2837 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2838 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2839 DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
2840
2841 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2842         .owner = THIS_MODULE,
2843         .read = dp_dsc_clock_en_read,
2844         .write = dp_dsc_clock_en_write,
2845         .llseek = default_llseek
2846 };
2847
2848 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2849         .owner = THIS_MODULE,
2850         .read = dp_dsc_slice_width_read,
2851         .write = dp_dsc_slice_width_write,
2852         .llseek = default_llseek
2853 };
2854
2855 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2856         .owner = THIS_MODULE,
2857         .read = dp_dsc_slice_height_read,
2858         .write = dp_dsc_slice_height_write,
2859         .llseek = default_llseek
2860 };
2861
2862 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2863         .owner = THIS_MODULE,
2864         .read = dp_dsc_bits_per_pixel_read,
2865         .write = dp_dsc_bits_per_pixel_write,
2866         .llseek = default_llseek
2867 };
2868
2869 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2870         .owner = THIS_MODULE,
2871         .read = dp_dsc_pic_width_read,
2872         .llseek = default_llseek
2873 };
2874
2875 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2876         .owner = THIS_MODULE,
2877         .read = dp_dsc_pic_height_read,
2878         .llseek = default_llseek
2879 };
2880
2881 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2882         .owner = THIS_MODULE,
2883         .read = dp_dsc_chunk_size_read,
2884         .llseek = default_llseek
2885 };
2886
2887 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2888         .owner = THIS_MODULE,
2889         .read = dp_dsc_slice_bpg_offset_read,
2890         .llseek = default_llseek
2891 };
2892
2893 static const struct file_operations trigger_hotplug_debugfs_fops = {
2894         .owner = THIS_MODULE,
2895         .write = trigger_hotplug,
2896         .llseek = default_llseek
2897 };
2898
2899 static const struct file_operations dp_link_settings_debugfs_fops = {
2900         .owner = THIS_MODULE,
2901         .read = dp_link_settings_read,
2902         .write = dp_link_settings_write,
2903         .llseek = default_llseek
2904 };
2905
2906 static const struct file_operations dp_phy_settings_debugfs_fop = {
2907         .owner = THIS_MODULE,
2908         .read = dp_phy_settings_read,
2909         .write = dp_phy_settings_write,
2910         .llseek = default_llseek
2911 };
2912
2913 static const struct file_operations dp_phy_test_pattern_fops = {
2914         .owner = THIS_MODULE,
2915         .write = dp_phy_test_pattern_debugfs_write,
2916         .llseek = default_llseek
2917 };
2918
2919 static const struct file_operations sdp_message_fops = {
2920         .owner = THIS_MODULE,
2921         .write = dp_sdp_message_debugfs_write,
2922         .llseek = default_llseek
2923 };
2924
2925 static const struct file_operations dp_max_bpc_debugfs_fops = {
2926         .owner = THIS_MODULE,
2927         .read = dp_max_bpc_read,
2928         .write = dp_max_bpc_write,
2929         .llseek = default_llseek
2930 };
2931
2932 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2933         .owner = THIS_MODULE,
2934         .write = dp_dsc_passthrough_set,
2935         .llseek = default_llseek
2936 };
2937
2938 static const struct file_operations dp_mst_link_settings_debugfs_fops = {
2939         .owner = THIS_MODULE,
2940         .write = dp_mst_link_setting,
2941         .llseek = default_llseek
2942 };
2943
2944 static const struct {
2945         char *name;
2946         const struct file_operations *fops;
2947 } dp_debugfs_entries[] = {
2948                 {"link_settings", &dp_link_settings_debugfs_fops},
2949                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2950                 {"lttpr_status", &dp_lttpr_status_fops},
2951                 {"test_pattern", &dp_phy_test_pattern_fops},
2952                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2953                 {"sdp_message", &sdp_message_fops},
2954                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2955                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2956                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2957                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2958                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2959                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2960                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2961                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2962                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2963                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2964                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2965                 {"is_mst_connector", &dp_is_mst_connector_fops},
2966                 {"mst_progress_status", &dp_mst_progress_status_fops},
2967                 {"is_dpia_link", &is_dpia_link_fops},
2968                 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops}
2969 };
2970
2971 static const struct {
2972         char *name;
2973         const struct file_operations *fops;
2974 } hdmi_debugfs_entries[] = {
2975                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2976 };
2977
2978 /*
2979  * Force YUV420 output if available from the given mode
2980  */
2981 static int force_yuv420_output_set(void *data, u64 val)
2982 {
2983         struct amdgpu_dm_connector *connector = data;
2984
2985         connector->force_yuv420_output = (bool)val;
2986
2987         return 0;
2988 }
2989
2990 /*
2991  * Check if YUV420 is forced when available from the given mode
2992  */
2993 static int force_yuv420_output_get(void *data, u64 *val)
2994 {
2995         struct amdgpu_dm_connector *connector = data;
2996
2997         *val = connector->force_yuv420_output;
2998
2999         return 0;
3000 }
3001
3002 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
3003                          force_yuv420_output_set, "%llu\n");
3004
3005 /*
3006  *  Read Replay state
3007  */
3008 static int replay_get_state(void *data, u64 *val)
3009 {
3010         struct amdgpu_dm_connector *connector = data;
3011         struct dc_link *link = connector->dc_link;
3012         uint64_t state = REPLAY_STATE_INVALID;
3013
3014         dc_link_get_replay_state(link, &state);
3015
3016         *val = state;
3017
3018         return 0;
3019 }
3020
3021 /*
3022  *  Read PSR state
3023  */
3024 static int psr_get(void *data, u64 *val)
3025 {
3026         struct amdgpu_dm_connector *connector = data;
3027         struct dc_link *link = connector->dc_link;
3028         enum dc_psr_state state = PSR_STATE0;
3029
3030         dc_link_get_psr_state(link, &state);
3031
3032         *val = state;
3033
3034         return 0;
3035 }
3036
3037 /*
3038  *  Read PSR state residency
3039  */
3040 static int psr_read_residency(void *data, u64 *val)
3041 {
3042         struct amdgpu_dm_connector *connector = data;
3043         struct dc_link *link = connector->dc_link;
3044         u32 residency = 0;
3045
3046         link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
3047
3048         *val = (u64)residency;
3049
3050         return 0;
3051 }
3052
3053 /* read allow_edp_hotplug_detection */
3054 static int allow_edp_hotplug_detection_get(void *data, u64 *val)
3055 {
3056         struct amdgpu_dm_connector *aconnector = data;
3057         struct drm_connector *connector = &aconnector->base;
3058         struct drm_device *dev = connector->dev;
3059         struct amdgpu_device *adev = drm_to_adev(dev);
3060
3061         *val = adev->dm.dc->config.allow_edp_hotplug_detection;
3062
3063         return 0;
3064 }
3065
3066 /* set allow_edp_hotplug_detection */
3067 static int allow_edp_hotplug_detection_set(void *data, u64 val)
3068 {
3069         struct amdgpu_dm_connector *aconnector = data;
3070         struct drm_connector *connector = &aconnector->base;
3071         struct drm_device *dev = connector->dev;
3072         struct amdgpu_device *adev = drm_to_adev(dev);
3073
3074         adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
3075
3076         return 0;
3077 }
3078
3079 /* check if kernel disallow eDP enter psr state
3080  * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3081  * 0: allow edp enter psr; 1: disallow
3082  */
3083 static int disallow_edp_enter_psr_get(void *data, u64 *val)
3084 {
3085         struct amdgpu_dm_connector *aconnector = data;
3086
3087         *val = (u64) aconnector->disallow_edp_enter_psr;
3088         return 0;
3089 }
3090
3091 /* set kernel disallow eDP enter psr state
3092  * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3093  * 0: allow edp enter psr; 1: disallow
3094  *
3095  * usage: test app read crc from PSR eDP rx.
3096  *
3097  * during kernel boot up, kernel write dpcd 0x170 = 5.
3098  * this notify eDP rx psr enable and let rx check crc.
3099  * rx fw will start checking crc for rx internal logic.
3100  * crc read count within dpcd 0x246 is not updated and
3101  * value is 0. when eDP tx driver wants to read rx crc
3102  * from dpcd 0x246, 0x270, read count 0 lead tx driver
3103  * timeout.
3104  *
3105  * to avoid this, we add this debugfs to let test app to disbable
3106  * rx crc checking for rx internal logic. then test app can read
3107  * non-zero crc read count.
3108  *
3109  * expected app sequence is as below:
3110  * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3111  * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3112  * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3113  *    without dpcd 0x170 = 5.
3114  * 4. read crc from rx dpcd 0x270, 0x246, etc.
3115  * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
3116  *    this will let eDP back to normal with psr setup dpcd 0x170 = 5.
3117  */
3118 static int disallow_edp_enter_psr_set(void *data, u64 val)
3119 {
3120         struct amdgpu_dm_connector *aconnector = data;
3121
3122         aconnector->disallow_edp_enter_psr = val ? true : false;
3123         return 0;
3124 }
3125
3126 static int dmub_trace_mask_set(void *data, u64 val)
3127 {
3128         struct amdgpu_device *adev = data;
3129         struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3130         enum dmub_gpint_command cmd;
3131         u64 mask = 0xffff;
3132         u8 shift = 0;
3133         u32 res;
3134         int i;
3135
3136         if (!srv->fw_version)
3137                 return -EINVAL;
3138
3139         for (i = 0;  i < 4; i++) {
3140                 res = (val & mask) >> shift;
3141
3142                 switch (i) {
3143                 case 0:
3144                         cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0;
3145                         break;
3146                 case 1:
3147                         cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1;
3148                         break;
3149                 case 2:
3150                         cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2;
3151                         break;
3152                 case 3:
3153                         cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3;
3154                         break;
3155                 }
3156
3157                 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))
3158                         return -EIO;
3159
3160                 usleep_range(100, 1000);
3161
3162                 mask <<= 16;
3163                 shift += 16;
3164         }
3165
3166         return 0;
3167 }
3168
3169 static int dmub_trace_mask_show(void *data, u64 *val)
3170 {
3171         enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0;
3172         struct amdgpu_device *adev = data;
3173         struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3174         u8 shift = 0;
3175         u64 raw = 0;
3176         u64 res = 0;
3177         int i = 0;
3178
3179         if (!srv->fw_version)
3180                 return -EINVAL;
3181
3182         while (i < 4) {
3183                 uint32_t response;
3184
3185                 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
3186                         return -EIO;
3187
3188                 raw = response;
3189                 usleep_range(100, 1000);
3190
3191                 cmd++;
3192                 res |= (raw << shift);
3193                 shift += 16;
3194                 i++;
3195         }
3196
3197         *val = res;
3198
3199         return 0;
3200 }
3201
3202 DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show,
3203                          dmub_trace_mask_set, "0x%llx\n");
3204
3205 /*
3206  * Set dmcub trace event IRQ enable or disable.
3207  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3208  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3209  */
3210 static int dmcub_trace_event_state_set(void *data, u64 val)
3211 {
3212         struct amdgpu_device *adev = data;
3213
3214         if (val == 1 || val == 0) {
3215                 dc_dmub_trace_event_control(adev->dm.dc, val);
3216                 adev->dm.dmcub_trace_event_en = (bool)val;
3217         } else
3218                 return 0;
3219
3220         return 0;
3221 }
3222
3223 /*
3224  * The interface doesn't need get function, so it will return the
3225  * value of zero
3226  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3227  */
3228 static int dmcub_trace_event_state_get(void *data, u64 *val)
3229 {
3230         struct amdgpu_device *adev = data;
3231
3232         *val = adev->dm.dmcub_trace_event_en;
3233         return 0;
3234 }
3235
3236 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
3237                          dmcub_trace_event_state_set, "%llu\n");
3238
3239 DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n");
3240
3241 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
3242 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
3243                          "%llu\n");
3244
3245 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
3246                         allow_edp_hotplug_detection_get,
3247                         allow_edp_hotplug_detection_set, "%llu\n");
3248
3249 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
3250                         disallow_edp_enter_psr_get,
3251                         disallow_edp_enter_psr_set, "%llu\n");
3252
3253 DEFINE_SHOW_ATTRIBUTE(current_backlight);
3254 DEFINE_SHOW_ATTRIBUTE(target_backlight);
3255 DEFINE_SHOW_ATTRIBUTE(ips_status);
3256
3257 static const struct {
3258         char *name;
3259         const struct file_operations *fops;
3260 } connector_debugfs_entries[] = {
3261                 {"force_yuv420_output", &force_yuv420_output_fops},
3262                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
3263                 {"internal_display", &internal_display_fops},
3264                 {"odm_combine_segments", &odm_combine_segments_fops}
3265 };
3266
3267 /*
3268  * Returns supported customized link rates by this eDP panel.
3269  * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3270  */
3271 static int edp_ilr_show(struct seq_file *m, void *unused)
3272 {
3273         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
3274         struct dc_link *link = aconnector->dc_link;
3275         uint8_t supported_link_rates[16];
3276         uint32_t link_rate_in_khz;
3277         uint32_t entry = 0;
3278         uint8_t dpcd_rev;
3279
3280         memset(supported_link_rates, 0, sizeof(supported_link_rates));
3281         dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3282                 supported_link_rates, sizeof(supported_link_rates));
3283
3284         dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3285
3286         if (dpcd_rev >= DP_DPCD_REV_13 &&
3287                 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
3288
3289                 for (entry = 0; entry < 16; entry += 2) {
3290                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3291                                                                                 supported_link_rates[entry]) * 200;
3292                         seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
3293                 }
3294         } else {
3295                 seq_puts(m, "ILR is not supported by this eDP panel.\n");
3296         }
3297
3298         return 0;
3299 }
3300
3301 /*
3302  * Set supported customized link rate to eDP panel.
3303  *
3304  * echo <lane_count>  <link_rate option> > ilr_setting
3305  *
3306  * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
3307  * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3308  * to set 4 lanes and 2.16 GHz
3309  */
3310 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
3311                                  size_t size, loff_t *pos)
3312 {
3313         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
3314         struct dc_link *link = connector->dc_link;
3315         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3316         struct dc *dc = (struct dc *)link->dc;
3317         struct dc_link_settings prefer_link_settings;
3318         char *wr_buf = NULL;
3319         const uint32_t wr_buf_size = 40;
3320         /* 0: lane_count; 1: link_rate */
3321         int max_param_num = 2;
3322         uint8_t param_nums = 0;
3323         long param[2];
3324         bool valid_input = true;
3325
3326         if (size == 0)
3327                 return -EINVAL;
3328
3329         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3330         if (!wr_buf)
3331                 return -ENOMEM;
3332
3333         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3334                                            (long *)param, buf,
3335                                            max_param_num,
3336                                            &param_nums)) {
3337                 kfree(wr_buf);
3338                 return -EINVAL;
3339         }
3340
3341         if (param_nums <= 0) {
3342                 kfree(wr_buf);
3343                 return -EINVAL;
3344         }
3345
3346         switch (param[0]) {
3347         case LANE_COUNT_ONE:
3348         case LANE_COUNT_TWO:
3349         case LANE_COUNT_FOUR:
3350                 break;
3351         default:
3352                 valid_input = false;
3353                 break;
3354         }
3355
3356         if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
3357                 valid_input = false;
3358
3359         if (!valid_input) {
3360                 kfree(wr_buf);
3361                 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
3362                 prefer_link_settings.use_link_rate_set = false;
3363                 mutex_lock(&adev->dm.dc_lock);
3364                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
3365                 mutex_unlock(&adev->dm.dc_lock);
3366                 return size;
3367         }
3368
3369         /* save user force lane_count, link_rate to preferred settings
3370          * spread spectrum will not be changed
3371          */
3372         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
3373         prefer_link_settings.lane_count = param[0];
3374         prefer_link_settings.use_link_rate_set = true;
3375         prefer_link_settings.link_rate_set = param[1];
3376         prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
3377
3378         mutex_lock(&adev->dm.dc_lock);
3379         dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
3380                                                 NULL, link, false);
3381         mutex_unlock(&adev->dm.dc_lock);
3382
3383         kfree(wr_buf);
3384         return size;
3385 }
3386
3387 static int edp_ilr_open(struct inode *inode, struct file *file)
3388 {
3389         return single_open(file, edp_ilr_show, inode->i_private);
3390 }
3391
3392 static const struct file_operations edp_ilr_debugfs_fops = {
3393         .owner = THIS_MODULE,
3394         .open = edp_ilr_open,
3395         .read = seq_read,
3396         .llseek = seq_lseek,
3397         .release = single_release,
3398         .write = edp_ilr_write
3399 };
3400
3401 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3402 {
3403         int i;
3404         struct dentry *dir = connector->base.debugfs_entry;
3405
3406         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3407             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3408                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3409                         debugfs_create_file(dp_debugfs_entries[i].name,
3410                                             0644, dir, connector,
3411                                             dp_debugfs_entries[i].fops);
3412                 }
3413         }
3414         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3415                 debugfs_create_file("replay_capability", 0444, dir, connector,
3416                                         &replay_capability_fops);
3417                 debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops);
3418                 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3419                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3420                 debugfs_create_file_unsafe("psr_residency", 0444, dir,
3421                                            connector, &psr_residency_fops);
3422                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3423                                     &current_backlight_fops);
3424                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3425                                     &target_backlight_fops);
3426                 debugfs_create_file("ilr_setting", 0644, dir, connector,
3427                                         &edp_ilr_debugfs_fops);
3428                 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3429                                         &allow_edp_hotplug_detection_fops);
3430                 debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
3431                                         &disallow_edp_enter_psr_fops);
3432         }
3433
3434         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3435                 debugfs_create_file(connector_debugfs_entries[i].name,
3436                                     0644, dir, connector,
3437                                     connector_debugfs_entries[i].fops);
3438         }
3439
3440         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3441                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3442                         debugfs_create_file(hdmi_debugfs_entries[i].name,
3443                                             0644, dir, connector,
3444                                             hdmi_debugfs_entries[i].fops);
3445                 }
3446         }
3447 }
3448
3449 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3450 /*
3451  * Set crc window coordinate x start
3452  */
3453 static int crc_win_x_start_set(void *data, u64 val)
3454 {
3455         struct drm_crtc *crtc = data;
3456         struct drm_device *drm_dev = crtc->dev;
3457         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3458
3459         spin_lock_irq(&drm_dev->event_lock);
3460         acrtc->dm_irq_params.window_param.x_start = (uint16_t) val;
3461         acrtc->dm_irq_params.window_param.update_win = false;
3462         spin_unlock_irq(&drm_dev->event_lock);
3463
3464         return 0;
3465 }
3466
3467 /*
3468  * Get crc window coordinate x start
3469  */
3470 static int crc_win_x_start_get(void *data, u64 *val)
3471 {
3472         struct drm_crtc *crtc = data;
3473         struct drm_device *drm_dev = crtc->dev;
3474         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3475
3476         spin_lock_irq(&drm_dev->event_lock);
3477         *val = acrtc->dm_irq_params.window_param.x_start;
3478         spin_unlock_irq(&drm_dev->event_lock);
3479
3480         return 0;
3481 }
3482
3483 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3484                          crc_win_x_start_set, "%llu\n");
3485
3486
3487 /*
3488  * Set crc window coordinate y start
3489  */
3490 static int crc_win_y_start_set(void *data, u64 val)
3491 {
3492         struct drm_crtc *crtc = data;
3493         struct drm_device *drm_dev = crtc->dev;
3494         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3495
3496         spin_lock_irq(&drm_dev->event_lock);
3497         acrtc->dm_irq_params.window_param.y_start = (uint16_t) val;
3498         acrtc->dm_irq_params.window_param.update_win = false;
3499         spin_unlock_irq(&drm_dev->event_lock);
3500
3501         return 0;
3502 }
3503
3504 /*
3505  * Get crc window coordinate y start
3506  */
3507 static int crc_win_y_start_get(void *data, u64 *val)
3508 {
3509         struct drm_crtc *crtc = data;
3510         struct drm_device *drm_dev = crtc->dev;
3511         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3512
3513         spin_lock_irq(&drm_dev->event_lock);
3514         *val = acrtc->dm_irq_params.window_param.y_start;
3515         spin_unlock_irq(&drm_dev->event_lock);
3516
3517         return 0;
3518 }
3519
3520 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3521                          crc_win_y_start_set, "%llu\n");
3522
3523 /*
3524  * Set crc window coordinate x end
3525  */
3526 static int crc_win_x_end_set(void *data, u64 val)
3527 {
3528         struct drm_crtc *crtc = data;
3529         struct drm_device *drm_dev = crtc->dev;
3530         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3531
3532         spin_lock_irq(&drm_dev->event_lock);
3533         acrtc->dm_irq_params.window_param.x_end = (uint16_t) val;
3534         acrtc->dm_irq_params.window_param.update_win = false;
3535         spin_unlock_irq(&drm_dev->event_lock);
3536
3537         return 0;
3538 }
3539
3540 /*
3541  * Get crc window coordinate x end
3542  */
3543 static int crc_win_x_end_get(void *data, u64 *val)
3544 {
3545         struct drm_crtc *crtc = data;
3546         struct drm_device *drm_dev = crtc->dev;
3547         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3548
3549         spin_lock_irq(&drm_dev->event_lock);
3550         *val = acrtc->dm_irq_params.window_param.x_end;
3551         spin_unlock_irq(&drm_dev->event_lock);
3552
3553         return 0;
3554 }
3555
3556 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3557                          crc_win_x_end_set, "%llu\n");
3558
3559 /*
3560  * Set crc window coordinate y end
3561  */
3562 static int crc_win_y_end_set(void *data, u64 val)
3563 {
3564         struct drm_crtc *crtc = data;
3565         struct drm_device *drm_dev = crtc->dev;
3566         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3567
3568         spin_lock_irq(&drm_dev->event_lock);
3569         acrtc->dm_irq_params.window_param.y_end = (uint16_t) val;
3570         acrtc->dm_irq_params.window_param.update_win = false;
3571         spin_unlock_irq(&drm_dev->event_lock);
3572
3573         return 0;
3574 }
3575
3576 /*
3577  * Get crc window coordinate y end
3578  */
3579 static int crc_win_y_end_get(void *data, u64 *val)
3580 {
3581         struct drm_crtc *crtc = data;
3582         struct drm_device *drm_dev = crtc->dev;
3583         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3584
3585         spin_lock_irq(&drm_dev->event_lock);
3586         *val = acrtc->dm_irq_params.window_param.y_end;
3587         spin_unlock_irq(&drm_dev->event_lock);
3588
3589         return 0;
3590 }
3591
3592 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3593                          crc_win_y_end_set, "%llu\n");
3594 /*
3595  * Trigger to commit crc window
3596  */
3597 static int crc_win_update_set(void *data, u64 val)
3598 {
3599         struct drm_crtc *crtc = data;
3600         struct amdgpu_crtc *acrtc;
3601         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3602
3603         if (val) {
3604                 acrtc = to_amdgpu_crtc(crtc);
3605                 mutex_lock(&adev->dm.dc_lock);
3606                 /* PSR may write to OTG CRC window control register,
3607                  * so close it before starting secure_display.
3608                  */
3609                 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream);
3610
3611                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3612
3613                 acrtc->dm_irq_params.window_param.activated = true;
3614                 acrtc->dm_irq_params.window_param.update_win = true;
3615                 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
3616
3617                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3618                 mutex_unlock(&adev->dm.dc_lock);
3619         }
3620
3621         return 0;
3622 }
3623
3624 /*
3625  * Get crc window update flag
3626  */
3627 static int crc_win_update_get(void *data, u64 *val)
3628 {
3629         *val = 0;
3630         return 0;
3631 }
3632
3633 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3634                          crc_win_update_set, "%llu\n");
3635 #endif
3636 void crtc_debugfs_init(struct drm_crtc *crtc)
3637 {
3638 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3639         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3640
3641         if (!dir)
3642                 return;
3643
3644         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3645                                    &crc_win_x_start_fops);
3646         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3647                                    &crc_win_y_start_fops);
3648         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3649                                    &crc_win_x_end_fops);
3650         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3651                                    &crc_win_y_end_fops);
3652         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3653                                    &crc_win_update_fops);
3654         dput(dir);
3655 #endif
3656         debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3657                             crtc, &amdgpu_current_bpc_fops);
3658         debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry,
3659                             crtc, &amdgpu_current_colorspace_fops);
3660 }
3661
3662 /*
3663  * Writes DTN log state to the user supplied buffer.
3664  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3665  */
3666 static ssize_t dtn_log_read(
3667         struct file *f,
3668         char __user *buf,
3669         size_t size,
3670         loff_t *pos)
3671 {
3672         struct amdgpu_device *adev = file_inode(f)->i_private;
3673         struct dc *dc = adev->dm.dc;
3674         struct dc_log_buffer_ctx log_ctx = { 0 };
3675         ssize_t result = 0;
3676
3677         if (!buf || !size)
3678                 return -EINVAL;
3679
3680         if (!dc->hwss.log_hw_state)
3681                 return 0;
3682
3683         dc->hwss.log_hw_state(dc, &log_ctx);
3684
3685         if (*pos < log_ctx.pos) {
3686                 size_t to_copy = log_ctx.pos - *pos;
3687
3688                 to_copy = min(to_copy, size);
3689
3690                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3691                         *pos += to_copy;
3692                         result = to_copy;
3693                 }
3694         }
3695
3696         kfree(log_ctx.buf);
3697
3698         return result;
3699 }
3700
3701 /*
3702  * Writes DTN log state to dmesg when triggered via a write.
3703  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3704  */
3705 static ssize_t dtn_log_write(
3706         struct file *f,
3707         const char __user *buf,
3708         size_t size,
3709         loff_t *pos)
3710 {
3711         struct amdgpu_device *adev = file_inode(f)->i_private;
3712         struct dc *dc = adev->dm.dc;
3713
3714         /* Write triggers log output via dmesg. */
3715         if (size == 0)
3716                 return 0;
3717
3718         if (dc->hwss.log_hw_state)
3719                 dc->hwss.log_hw_state(dc, NULL);
3720
3721         return size;
3722 }
3723
3724 static int mst_topo_show(struct seq_file *m, void *unused)
3725 {
3726         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3727         struct drm_device *dev = adev_to_drm(adev);
3728         struct drm_connector *connector;
3729         struct drm_connector_list_iter conn_iter;
3730         struct amdgpu_dm_connector *aconnector;
3731
3732         drm_connector_list_iter_begin(dev, &conn_iter);
3733         drm_for_each_connector_iter(connector, &conn_iter) {
3734                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3735                         continue;
3736
3737                 aconnector = to_amdgpu_dm_connector(connector);
3738
3739                 /* Ensure we're only dumping the topology of a root mst node */
3740                 if (!aconnector->mst_mgr.mst_state)
3741                         continue;
3742
3743                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3744                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3745         }
3746         drm_connector_list_iter_end(&conn_iter);
3747
3748         return 0;
3749 }
3750
3751 /*
3752  * Sets trigger hpd for MST topologies.
3753  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3754  * All topologies will be disconnected if val of 0 is set .
3755  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3756  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3757  */
3758 static int trigger_hpd_mst_set(void *data, u64 val)
3759 {
3760         struct amdgpu_device *adev = data;
3761         struct drm_device *dev = adev_to_drm(adev);
3762         struct drm_connector_list_iter iter;
3763         struct amdgpu_dm_connector *aconnector;
3764         struct drm_connector *connector;
3765         struct dc_link *link = NULL;
3766         int ret;
3767
3768         if (val == 1) {
3769                 drm_connector_list_iter_begin(dev, &iter);
3770                 drm_for_each_connector_iter(connector, &iter) {
3771                         aconnector = to_amdgpu_dm_connector(connector);
3772                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3773                             aconnector->mst_mgr.aux) {
3774                                 mutex_lock(&adev->dm.dc_lock);
3775                                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3776                                 mutex_unlock(&adev->dm.dc_lock);
3777
3778                                 if (!ret)
3779                                         DRM_ERROR("DM_MST: Failed to detect dc link!");
3780
3781                                 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3782                                 if (ret < 0)
3783                                         DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
3784                         }
3785                 }
3786         } else if (val == 0) {
3787                 drm_connector_list_iter_begin(dev, &iter);
3788                 drm_for_each_connector_iter(connector, &iter) {
3789                         aconnector = to_amdgpu_dm_connector(connector);
3790                         if (!aconnector->dc_link)
3791                                 continue;
3792
3793                         if (!aconnector->mst_root)
3794                                 continue;
3795
3796                         link = aconnector->dc_link;
3797                         dc_link_dp_receiver_power_ctrl(link, false);
3798                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
3799                         link->mst_stream_alloc_table.stream_count = 0;
3800                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3801                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3802                 }
3803         } else {
3804                 return 0;
3805         }
3806         drm_kms_helper_hotplug_event(dev);
3807
3808         return 0;
3809 }
3810
3811 /*
3812  * The interface doesn't need get function, so it will return the
3813  * value of zero
3814  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3815  */
3816 static int trigger_hpd_mst_get(void *data, u64 *val)
3817 {
3818         *val = 0;
3819         return 0;
3820 }
3821
3822 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3823                          trigger_hpd_mst_set, "%llu\n");
3824
3825
3826 /*
3827  * Sets the force_timing_sync debug option from the given string.
3828  * All connected displays will be force synchronized immediately.
3829  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3830  */
3831 static int force_timing_sync_set(void *data, u64 val)
3832 {
3833         struct amdgpu_device *adev = data;
3834
3835         adev->dm.force_timing_sync = (bool)val;
3836
3837         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3838
3839         return 0;
3840 }
3841
3842 /*
3843  * Gets the force_timing_sync debug option value into the given buffer.
3844  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3845  */
3846 static int force_timing_sync_get(void *data, u64 *val)
3847 {
3848         struct amdgpu_device *adev = data;
3849
3850         *val = adev->dm.force_timing_sync;
3851
3852         return 0;
3853 }
3854
3855 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3856                          force_timing_sync_set, "%llu\n");
3857
3858
3859 /*
3860  * Disables all HPD and HPD RX interrupt handling in the
3861  * driver when set to 1. Default is 0.
3862  */
3863 static int disable_hpd_set(void *data, u64 val)
3864 {
3865         struct amdgpu_device *adev = data;
3866
3867         adev->dm.disable_hpd_irq = (bool)val;
3868
3869         return 0;
3870 }
3871
3872
3873 /*
3874  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3875  * 0 otherwise.
3876  */
3877 static int disable_hpd_get(void *data, u64 *val)
3878 {
3879         struct amdgpu_device *adev = data;
3880
3881         *val = adev->dm.disable_hpd_irq;
3882
3883         return 0;
3884 }
3885
3886 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3887                          disable_hpd_set, "%llu\n");
3888
3889 /*
3890  * Prints hardware capabilities. These are used for IGT testing.
3891  */
3892 static int capabilities_show(struct seq_file *m, void *unused)
3893 {
3894         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3895         struct dc *dc = adev->dm.dc;
3896         bool mall_supported = dc->caps.mall_size_total;
3897         bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
3898         unsigned int mall_in_use = false;
3899         unsigned int subvp_in_use = false;
3900
3901         struct hubbub *hubbub = dc->res_pool->hubbub;
3902
3903         if (hubbub->funcs->get_mall_en)
3904                 hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
3905
3906         if (dc->cap_funcs.get_subvp_en)
3907                 subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
3908
3909         seq_printf(m, "mall supported: %s, enabled: %s\n",
3910                            mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
3911         seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",
3912                            subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no");
3913
3914         return 0;
3915 }
3916
3917 DEFINE_SHOW_ATTRIBUTE(capabilities);
3918
3919 /*
3920  * Temporary w/a to force sst sequence in M42D DP2 mst receiver
3921  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
3922  */
3923 static int dp_force_sst_set(void *data, u64 val)
3924 {
3925         struct amdgpu_device *adev = data;
3926
3927         adev->dm.dc->debug.set_mst_en_for_sst = val;
3928
3929         return 0;
3930 }
3931
3932 static int dp_force_sst_get(void *data, u64 *val)
3933 {
3934         struct amdgpu_device *adev = data;
3935
3936         *val = adev->dm.dc->debug.set_mst_en_for_sst;
3937
3938         return 0;
3939 }
3940 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
3941                          dp_force_sst_set, "%llu\n");
3942
3943 /*
3944  * Force DP2 sequence without VESA certified cable.
3945  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
3946  */
3947 static int dp_ignore_cable_id_set(void *data, u64 val)
3948 {
3949         struct amdgpu_device *adev = data;
3950
3951         adev->dm.dc->debug.ignore_cable_id = val;
3952
3953         return 0;
3954 }
3955
3956 static int dp_ignore_cable_id_get(void *data, u64 *val)
3957 {
3958         struct amdgpu_device *adev = data;
3959
3960         *val = adev->dm.dc->debug.ignore_cable_id;
3961
3962         return 0;
3963 }
3964 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
3965                          dp_ignore_cable_id_set, "%llu\n");
3966
3967 /*
3968  * Sets the DC visual confirm debug option from the given string.
3969  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3970  */
3971 static int visual_confirm_set(void *data, u64 val)
3972 {
3973         struct amdgpu_device *adev = data;
3974
3975         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3976
3977         return 0;
3978 }
3979
3980 /*
3981  * Reads the DC visual confirm debug option value into the given buffer.
3982  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3983  */
3984 static int visual_confirm_get(void *data, u64 *val)
3985 {
3986         struct amdgpu_device *adev = data;
3987
3988         *val = adev->dm.dc->debug.visual_confirm;
3989
3990         return 0;
3991 }
3992
3993 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3994 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3995                          visual_confirm_set, "%llu\n");
3996
3997
3998 /*
3999  * Sets the DC skip_detection_link_training debug option from the given string.
4000  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
4001  */
4002 static int skip_detection_link_training_set(void *data, u64 val)
4003 {
4004         struct amdgpu_device *adev = data;
4005
4006         if (val == 0)
4007                 adev->dm.dc->debug.skip_detection_link_training = false;
4008         else
4009                 adev->dm.dc->debug.skip_detection_link_training = true;
4010
4011         return 0;
4012 }
4013
4014 /*
4015  * Reads the DC skip_detection_link_training debug option value into the given buffer.
4016  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
4017  */
4018 static int skip_detection_link_training_get(void *data, u64 *val)
4019 {
4020         struct amdgpu_device *adev = data;
4021
4022         *val = adev->dm.dc->debug.skip_detection_link_training;
4023
4024         return 0;
4025 }
4026
4027 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
4028                          skip_detection_link_training_get,
4029                          skip_detection_link_training_set, "%llu\n");
4030
4031 /*
4032  * Dumps the DCC_EN bit for each pipe.
4033  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
4034  */
4035 static ssize_t dcc_en_bits_read(
4036         struct file *f,
4037         char __user *buf,
4038         size_t size,
4039         loff_t *pos)
4040 {
4041         struct amdgpu_device *adev = file_inode(f)->i_private;
4042         struct dc *dc = adev->dm.dc;
4043         char *rd_buf = NULL;
4044         const uint32_t rd_buf_size = 32;
4045         uint32_t result = 0;
4046         int offset = 0;
4047         int num_pipes = dc->res_pool->pipe_count;
4048         int *dcc_en_bits;
4049         int i, r;
4050
4051         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
4052         if (!dcc_en_bits)
4053                 return -ENOMEM;
4054
4055         if (!dc->hwss.get_dcc_en_bits) {
4056                 kfree(dcc_en_bits);
4057                 return 0;
4058         }
4059
4060         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
4061
4062         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
4063         if (!rd_buf) {
4064                 kfree(dcc_en_bits);
4065                 return -ENOMEM;
4066         }
4067
4068         for (i = 0; i < num_pipes; i++)
4069                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
4070                                    "%d  ", dcc_en_bits[i]);
4071         rd_buf[strlen(rd_buf)] = '\n';
4072
4073         kfree(dcc_en_bits);
4074
4075         while (size) {
4076                 if (*pos >= rd_buf_size)
4077                         break;
4078                 r = put_user(*(rd_buf + result), buf);
4079                 if (r) {
4080                         kfree(rd_buf);
4081                         return r; /* r = -EFAULT */
4082                 }
4083                 buf += 1;
4084                 size -= 1;
4085                 *pos += 1;
4086                 result += 1;
4087         }
4088
4089         kfree(rd_buf);
4090         return result;
4091 }
4092
4093 void dtn_debugfs_init(struct amdgpu_device *adev)
4094 {
4095         static const struct file_operations dtn_log_fops = {
4096                 .owner = THIS_MODULE,
4097                 .read = dtn_log_read,
4098                 .write = dtn_log_write,
4099                 .llseek = default_llseek
4100         };
4101         static const struct file_operations dcc_en_bits_fops = {
4102                 .owner = THIS_MODULE,
4103                 .read = dcc_en_bits_read,
4104                 .llseek = default_llseek
4105         };
4106
4107         struct drm_minor *minor = adev_to_drm(adev)->primary;
4108         struct dentry *root = minor->debugfs_root;
4109
4110         debugfs_create_file("amdgpu_mst_topology", 0444, root,
4111                             adev, &mst_topo_fops);
4112         debugfs_create_file("amdgpu_dm_capabilities", 0444, root,
4113                             adev, &capabilities_fops);
4114         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
4115                             &dtn_log_fops);
4116         debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
4117                                 &dp_set_mst_en_for_sst_ops);
4118         debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
4119                                 &dp_ignore_cable_id_ops);
4120
4121         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
4122                                    &visual_confirm_fops);
4123
4124         debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
4125                                    &skip_detection_link_training_fops);
4126
4127         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
4128                                    adev, &dmub_tracebuffer_fops);
4129
4130         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
4131                                    adev, &dmub_fw_state_fops);
4132
4133         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
4134                                    adev, &force_timing_sync_ops);
4135
4136         debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root,
4137                                    adev, &dmub_trace_mask_fops);
4138
4139         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
4140                                    adev, &dmcub_trace_event_state_fops);
4141
4142         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
4143                                    adev, &trigger_hpd_mst_ops);
4144
4145         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
4146                                    &dcc_en_bits_fops);
4147
4148         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
4149                                    &disable_hpd_ops);
4150
4151         if (adev->dm.dc->caps.ips_support)
4152                 debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
4153                                            &ips_status_fops);
4154 }