]> Git Repo - J-linux.git/blob - drivers/clk/stm32/clk-stm32mp13.c
Merge tag 'vfs-6.13-rc7.fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs
[J-linux.git] / drivers / clk / stm32 / clk-stm32mp13.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4  * Author: Gabriel Fernandez <[email protected]> for STMicroelectronics.
5  */
6
7 #include <linux/clk.h>
8 #include <linux/module.h>
9 #include <linux/of_address.h>
10 #include <linux/platform_device.h>
11 #include <dt-bindings/clock/stm32mp13-clks.h>
12 #include "clk-stm32-core.h"
13 #include "reset-stm32.h"
14 #include "stm32mp13_rcc.h"
15
16 #define STM32MP1_RESET_ID_MASK GENMASK(15, 0)
17 #define RCC_CLR_OFFSET          0x4
18
19 /* STM32 Gates definition */
20 enum enum_gate_cfg {
21         GATE_MCO1,
22         GATE_MCO2,
23         GATE_DBGCK,
24         GATE_TRACECK,
25         GATE_DDRC1,
26         GATE_DDRC1LP,
27         GATE_DDRPHYC,
28         GATE_DDRPHYCLP,
29         GATE_DDRCAPB,
30         GATE_DDRCAPBLP,
31         GATE_AXIDCG,
32         GATE_DDRPHYCAPB,
33         GATE_DDRPHYCAPBLP,
34         GATE_TIM2,
35         GATE_TIM3,
36         GATE_TIM4,
37         GATE_TIM5,
38         GATE_TIM6,
39         GATE_TIM7,
40         GATE_LPTIM1,
41         GATE_SPI2,
42         GATE_SPI3,
43         GATE_USART3,
44         GATE_UART4,
45         GATE_UART5,
46         GATE_UART7,
47         GATE_UART8,
48         GATE_I2C1,
49         GATE_I2C2,
50         GATE_SPDIF,
51         GATE_TIM1,
52         GATE_TIM8,
53         GATE_SPI1,
54         GATE_USART6,
55         GATE_SAI1,
56         GATE_SAI2,
57         GATE_DFSDM,
58         GATE_ADFSDM,
59         GATE_FDCAN,
60         GATE_LPTIM2,
61         GATE_LPTIM3,
62         GATE_LPTIM4,
63         GATE_LPTIM5,
64         GATE_VREF,
65         GATE_DTS,
66         GATE_PMBCTRL,
67         GATE_HDP,
68         GATE_SYSCFG,
69         GATE_DCMIPP,
70         GATE_DDRPERFM,
71         GATE_IWDG2APB,
72         GATE_USBPHY,
73         GATE_STGENRO,
74         GATE_LTDC,
75         GATE_RTCAPB,
76         GATE_TZC,
77         GATE_ETZPC,
78         GATE_IWDG1APB,
79         GATE_BSEC,
80         GATE_STGENC,
81         GATE_USART1,
82         GATE_USART2,
83         GATE_SPI4,
84         GATE_SPI5,
85         GATE_I2C3,
86         GATE_I2C4,
87         GATE_I2C5,
88         GATE_TIM12,
89         GATE_TIM13,
90         GATE_TIM14,
91         GATE_TIM15,
92         GATE_TIM16,
93         GATE_TIM17,
94         GATE_DMA1,
95         GATE_DMA2,
96         GATE_DMAMUX1,
97         GATE_DMA3,
98         GATE_DMAMUX2,
99         GATE_ADC1,
100         GATE_ADC2,
101         GATE_USBO,
102         GATE_TSC,
103         GATE_GPIOA,
104         GATE_GPIOB,
105         GATE_GPIOC,
106         GATE_GPIOD,
107         GATE_GPIOE,
108         GATE_GPIOF,
109         GATE_GPIOG,
110         GATE_GPIOH,
111         GATE_GPIOI,
112         GATE_PKA,
113         GATE_SAES,
114         GATE_CRYP1,
115         GATE_HASH1,
116         GATE_RNG1,
117         GATE_BKPSRAM,
118         GATE_AXIMC,
119         GATE_MCE,
120         GATE_ETH1CK,
121         GATE_ETH1TX,
122         GATE_ETH1RX,
123         GATE_ETH1MAC,
124         GATE_FMC,
125         GATE_QSPI,
126         GATE_SDMMC1,
127         GATE_SDMMC2,
128         GATE_CRC1,
129         GATE_USBH,
130         GATE_ETH2CK,
131         GATE_ETH2TX,
132         GATE_ETH2RX,
133         GATE_ETH2MAC,
134         GATE_ETH1STP,
135         GATE_ETH2STP,
136         GATE_MDMA,
137         GATE_NB
138 };
139
140 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\
141         [(_id)] = {\
142                 .offset         = (_offset),\
143                 .bit_idx        = (_bit_idx),\
144                 .set_clr        = (_offset_clr),\
145         }
146
147 #define CFG_GATE(_id, _offset, _bit_idx)\
148         _CFG_GATE(_id, _offset, _bit_idx, 0)
149
150 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\
151         _CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
152
153 static struct stm32_gate_cfg stm32mp13_gates[] = {
154         CFG_GATE(GATE_MCO1,             RCC_MCO1CFGR,           12),
155         CFG_GATE(GATE_MCO2,             RCC_MCO2CFGR,           12),
156         CFG_GATE(GATE_DBGCK,            RCC_DBGCFGR,            8),
157         CFG_GATE(GATE_TRACECK,          RCC_DBGCFGR,            9),
158         CFG_GATE(GATE_DDRC1,            RCC_DDRITFCR,           0),
159         CFG_GATE(GATE_DDRC1LP,          RCC_DDRITFCR,           1),
160         CFG_GATE(GATE_DDRPHYC,          RCC_DDRITFCR,           4),
161         CFG_GATE(GATE_DDRPHYCLP,        RCC_DDRITFCR,           5),
162         CFG_GATE(GATE_DDRCAPB,          RCC_DDRITFCR,           6),
163         CFG_GATE(GATE_DDRCAPBLP,        RCC_DDRITFCR,           7),
164         CFG_GATE(GATE_AXIDCG,           RCC_DDRITFCR,           8),
165         CFG_GATE(GATE_DDRPHYCAPB,       RCC_DDRITFCR,           9),
166         CFG_GATE(GATE_DDRPHYCAPBLP,     RCC_DDRITFCR,           10),
167         CFG_GATE_SETCLR(GATE_TIM2,      RCC_MP_APB1ENSETR,      0),
168         CFG_GATE_SETCLR(GATE_TIM3,      RCC_MP_APB1ENSETR,      1),
169         CFG_GATE_SETCLR(GATE_TIM4,      RCC_MP_APB1ENSETR,      2),
170         CFG_GATE_SETCLR(GATE_TIM5,      RCC_MP_APB1ENSETR,      3),
171         CFG_GATE_SETCLR(GATE_TIM6,      RCC_MP_APB1ENSETR,      4),
172         CFG_GATE_SETCLR(GATE_TIM7,      RCC_MP_APB1ENSETR,      5),
173         CFG_GATE_SETCLR(GATE_LPTIM1,    RCC_MP_APB1ENSETR,      9),
174         CFG_GATE_SETCLR(GATE_SPI2,      RCC_MP_APB1ENSETR,      11),
175         CFG_GATE_SETCLR(GATE_SPI3,      RCC_MP_APB1ENSETR,      12),
176         CFG_GATE_SETCLR(GATE_USART3,    RCC_MP_APB1ENSETR,      15),
177         CFG_GATE_SETCLR(GATE_UART4,     RCC_MP_APB1ENSETR,      16),
178         CFG_GATE_SETCLR(GATE_UART5,     RCC_MP_APB1ENSETR,      17),
179         CFG_GATE_SETCLR(GATE_UART7,     RCC_MP_APB1ENSETR,      18),
180         CFG_GATE_SETCLR(GATE_UART8,     RCC_MP_APB1ENSETR,      19),
181         CFG_GATE_SETCLR(GATE_I2C1,      RCC_MP_APB1ENSETR,      21),
182         CFG_GATE_SETCLR(GATE_I2C2,      RCC_MP_APB1ENSETR,      22),
183         CFG_GATE_SETCLR(GATE_SPDIF,     RCC_MP_APB1ENSETR,      26),
184         CFG_GATE_SETCLR(GATE_TIM1,      RCC_MP_APB2ENSETR,      0),
185         CFG_GATE_SETCLR(GATE_TIM8,      RCC_MP_APB2ENSETR,      1),
186         CFG_GATE_SETCLR(GATE_SPI1,      RCC_MP_APB2ENSETR,      8),
187         CFG_GATE_SETCLR(GATE_USART6,    RCC_MP_APB2ENSETR,      13),
188         CFG_GATE_SETCLR(GATE_SAI1,      RCC_MP_APB2ENSETR,      16),
189         CFG_GATE_SETCLR(GATE_SAI2,      RCC_MP_APB2ENSETR,      17),
190         CFG_GATE_SETCLR(GATE_DFSDM,     RCC_MP_APB2ENSETR,      20),
191         CFG_GATE_SETCLR(GATE_ADFSDM,    RCC_MP_APB2ENSETR,      21),
192         CFG_GATE_SETCLR(GATE_FDCAN,     RCC_MP_APB2ENSETR,      24),
193         CFG_GATE_SETCLR(GATE_LPTIM2,    RCC_MP_APB3ENSETR,      0),
194         CFG_GATE_SETCLR(GATE_LPTIM3,    RCC_MP_APB3ENSETR,      1),
195         CFG_GATE_SETCLR(GATE_LPTIM4,    RCC_MP_APB3ENSETR,      2),
196         CFG_GATE_SETCLR(GATE_LPTIM5,    RCC_MP_APB3ENSETR,      3),
197         CFG_GATE_SETCLR(GATE_VREF,      RCC_MP_APB3ENSETR,      13),
198         CFG_GATE_SETCLR(GATE_DTS,       RCC_MP_APB3ENSETR,      16),
199         CFG_GATE_SETCLR(GATE_PMBCTRL,   RCC_MP_APB3ENSETR,      17),
200         CFG_GATE_SETCLR(GATE_HDP,       RCC_MP_APB3ENSETR,      20),
201         CFG_GATE_SETCLR(GATE_SYSCFG,    RCC_MP_NS_APB3ENSETR,   0),
202         CFG_GATE_SETCLR(GATE_DCMIPP,    RCC_MP_APB4ENSETR,      1),
203         CFG_GATE_SETCLR(GATE_DDRPERFM,  RCC_MP_APB4ENSETR,      8),
204         CFG_GATE_SETCLR(GATE_IWDG2APB,  RCC_MP_APB4ENSETR,      15),
205         CFG_GATE_SETCLR(GATE_USBPHY,    RCC_MP_APB4ENSETR,      16),
206         CFG_GATE_SETCLR(GATE_STGENRO,   RCC_MP_APB4ENSETR,      20),
207         CFG_GATE_SETCLR(GATE_LTDC,      RCC_MP_NS_APB4ENSETR,   0),
208         CFG_GATE_SETCLR(GATE_RTCAPB,    RCC_MP_APB5ENSETR,      8),
209         CFG_GATE_SETCLR(GATE_TZC,       RCC_MP_APB5ENSETR,      11),
210         CFG_GATE_SETCLR(GATE_ETZPC,     RCC_MP_APB5ENSETR,      13),
211         CFG_GATE_SETCLR(GATE_IWDG1APB,  RCC_MP_APB5ENSETR,      15),
212         CFG_GATE_SETCLR(GATE_BSEC,      RCC_MP_APB5ENSETR,      16),
213         CFG_GATE_SETCLR(GATE_STGENC,    RCC_MP_APB5ENSETR,      20),
214         CFG_GATE_SETCLR(GATE_USART1,    RCC_MP_APB6ENSETR,      0),
215         CFG_GATE_SETCLR(GATE_USART2,    RCC_MP_APB6ENSETR,      1),
216         CFG_GATE_SETCLR(GATE_SPI4,      RCC_MP_APB6ENSETR,      2),
217         CFG_GATE_SETCLR(GATE_SPI5,      RCC_MP_APB6ENSETR,      3),
218         CFG_GATE_SETCLR(GATE_I2C3,      RCC_MP_APB6ENSETR,      4),
219         CFG_GATE_SETCLR(GATE_I2C4,      RCC_MP_APB6ENSETR,      5),
220         CFG_GATE_SETCLR(GATE_I2C5,      RCC_MP_APB6ENSETR,      6),
221         CFG_GATE_SETCLR(GATE_TIM12,     RCC_MP_APB6ENSETR,      7),
222         CFG_GATE_SETCLR(GATE_TIM13,     RCC_MP_APB6ENSETR,      8),
223         CFG_GATE_SETCLR(GATE_TIM14,     RCC_MP_APB6ENSETR,      9),
224         CFG_GATE_SETCLR(GATE_TIM15,     RCC_MP_APB6ENSETR,      10),
225         CFG_GATE_SETCLR(GATE_TIM16,     RCC_MP_APB6ENSETR,      11),
226         CFG_GATE_SETCLR(GATE_TIM17,     RCC_MP_APB6ENSETR,      12),
227         CFG_GATE_SETCLR(GATE_DMA1,      RCC_MP_AHB2ENSETR,      0),
228         CFG_GATE_SETCLR(GATE_DMA2,      RCC_MP_AHB2ENSETR,      1),
229         CFG_GATE_SETCLR(GATE_DMAMUX1,   RCC_MP_AHB2ENSETR,      2),
230         CFG_GATE_SETCLR(GATE_DMA3,      RCC_MP_AHB2ENSETR,      3),
231         CFG_GATE_SETCLR(GATE_DMAMUX2,   RCC_MP_AHB2ENSETR,      4),
232         CFG_GATE_SETCLR(GATE_ADC1,      RCC_MP_AHB2ENSETR,      5),
233         CFG_GATE_SETCLR(GATE_ADC2,      RCC_MP_AHB2ENSETR,      6),
234         CFG_GATE_SETCLR(GATE_USBO,      RCC_MP_AHB2ENSETR,      8),
235         CFG_GATE_SETCLR(GATE_TSC,       RCC_MP_AHB4ENSETR,      15),
236         CFG_GATE_SETCLR(GATE_GPIOA,     RCC_MP_NS_AHB4ENSETR,   0),
237         CFG_GATE_SETCLR(GATE_GPIOB,     RCC_MP_NS_AHB4ENSETR,   1),
238         CFG_GATE_SETCLR(GATE_GPIOC,     RCC_MP_NS_AHB4ENSETR,   2),
239         CFG_GATE_SETCLR(GATE_GPIOD,     RCC_MP_NS_AHB4ENSETR,   3),
240         CFG_GATE_SETCLR(GATE_GPIOE,     RCC_MP_NS_AHB4ENSETR,   4),
241         CFG_GATE_SETCLR(GATE_GPIOF,     RCC_MP_NS_AHB4ENSETR,   5),
242         CFG_GATE_SETCLR(GATE_GPIOG,     RCC_MP_NS_AHB4ENSETR,   6),
243         CFG_GATE_SETCLR(GATE_GPIOH,     RCC_MP_NS_AHB4ENSETR,   7),
244         CFG_GATE_SETCLR(GATE_GPIOI,     RCC_MP_NS_AHB4ENSETR,   8),
245         CFG_GATE_SETCLR(GATE_PKA,       RCC_MP_AHB5ENSETR,      2),
246         CFG_GATE_SETCLR(GATE_SAES,      RCC_MP_AHB5ENSETR,      3),
247         CFG_GATE_SETCLR(GATE_CRYP1,     RCC_MP_AHB5ENSETR,      4),
248         CFG_GATE_SETCLR(GATE_HASH1,     RCC_MP_AHB5ENSETR,      5),
249         CFG_GATE_SETCLR(GATE_RNG1,      RCC_MP_AHB5ENSETR,      6),
250         CFG_GATE_SETCLR(GATE_BKPSRAM,   RCC_MP_AHB5ENSETR,      8),
251         CFG_GATE_SETCLR(GATE_AXIMC,     RCC_MP_AHB5ENSETR,      16),
252         CFG_GATE_SETCLR(GATE_MCE,       RCC_MP_AHB6ENSETR,      1),
253         CFG_GATE_SETCLR(GATE_ETH1CK,    RCC_MP_AHB6ENSETR,      7),
254         CFG_GATE_SETCLR(GATE_ETH1TX,    RCC_MP_AHB6ENSETR,      8),
255         CFG_GATE_SETCLR(GATE_ETH1RX,    RCC_MP_AHB6ENSETR,      9),
256         CFG_GATE_SETCLR(GATE_ETH1MAC,   RCC_MP_AHB6ENSETR,      10),
257         CFG_GATE_SETCLR(GATE_FMC,       RCC_MP_AHB6ENSETR,      12),
258         CFG_GATE_SETCLR(GATE_QSPI,      RCC_MP_AHB6ENSETR,      14),
259         CFG_GATE_SETCLR(GATE_SDMMC1,    RCC_MP_AHB6ENSETR,      16),
260         CFG_GATE_SETCLR(GATE_SDMMC2,    RCC_MP_AHB6ENSETR,      17),
261         CFG_GATE_SETCLR(GATE_CRC1,      RCC_MP_AHB6ENSETR,      20),
262         CFG_GATE_SETCLR(GATE_USBH,      RCC_MP_AHB6ENSETR,      24),
263         CFG_GATE_SETCLR(GATE_ETH2CK,    RCC_MP_AHB6ENSETR,      27),
264         CFG_GATE_SETCLR(GATE_ETH2TX,    RCC_MP_AHB6ENSETR,      28),
265         CFG_GATE_SETCLR(GATE_ETH2RX,    RCC_MP_AHB6ENSETR,      29),
266         CFG_GATE_SETCLR(GATE_ETH2MAC,   RCC_MP_AHB6ENSETR,      30),
267         CFG_GATE_SETCLR(GATE_ETH1STP,   RCC_MP_AHB6LPENSETR,    11),
268         CFG_GATE_SETCLR(GATE_ETH2STP,   RCC_MP_AHB6LPENSETR,    31),
269         CFG_GATE_SETCLR(GATE_MDMA,      RCC_MP_NS_AHB6ENSETR,   0),
270 };
271
272 /* STM32 Divivers definition */
273 enum enum_div_cfg {
274         DIV_RTC,
275         DIV_HSI,
276         DIV_MCO1,
277         DIV_MCO2,
278         DIV_TRACE,
279         DIV_ETH1PTP,
280         DIV_ETH2PTP,
281         DIV_NB
282 };
283
284 static const struct clk_div_table ck_trace_div_table[] = {
285         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
286         { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
287         { 0 },
288 };
289
290 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\
291         [(_id)] = {\
292                 .offset = (_offset),\
293                 .shift  = (_shift),\
294                 .width  = (_width),\
295                 .flags  = (_flags),\
296                 .table  = (_table),\
297                 .ready  = (_ready),\
298         }
299
300 static const struct stm32_div_cfg stm32mp13_dividers[DIV_NB] = {
301         CFG_DIV(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY),
302         CFG_DIV(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_RDY),
303         CFG_DIV(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_RDY),
304         CFG_DIV(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table, DIV_NO_RDY),
305         CFG_DIV(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_RDY),
306         CFG_DIV(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_RDY),
307 };
308
309 /* STM32 Muxes definition */
310 enum enum_mux_cfg {
311         MUX_ADC1,
312         MUX_ADC2,
313         MUX_DCMIPP,
314         MUX_ETH1,
315         MUX_ETH2,
316         MUX_FDCAN,
317         MUX_FMC,
318         MUX_I2C12,
319         MUX_I2C3,
320         MUX_I2C4,
321         MUX_I2C5,
322         MUX_LPTIM1,
323         MUX_LPTIM2,
324         MUX_LPTIM3,
325         MUX_LPTIM45,
326         MUX_MCO1,
327         MUX_MCO2,
328         MUX_QSPI,
329         MUX_RNG1,
330         MUX_SAES,
331         MUX_SAI1,
332         MUX_SAI2,
333         MUX_SDMMC1,
334         MUX_SDMMC2,
335         MUX_SPDIF,
336         MUX_SPI1,
337         MUX_SPI23,
338         MUX_SPI4,
339         MUX_SPI5,
340         MUX_STGEN,
341         MUX_UART1,
342         MUX_UART2,
343         MUX_UART4,
344         MUX_UART6,
345         MUX_UART35,
346         MUX_UART78,
347         MUX_USBO,
348         MUX_USBPHY,
349         MUX_NB
350 };
351
352 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\
353         [_id] = {\
354                 .offset         = (_offset),\
355                 .shift          = (_shift),\
356                 .width          = (_witdh),\
357                 .ready          = (_ready),\
358                 .flags          = (_flags),\
359         }
360
361 #define CFG_MUX(_id, _offset, _shift, _witdh)\
362         _CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, 0)
363
364 #define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\
365         _CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, MUX_SAFE)
366
367 static const struct stm32_mux_cfg stm32mp13_muxes[] = {
368         CFG_MUX(MUX_I2C12,      RCC_I2C12CKSELR,        0, 3),
369         CFG_MUX(MUX_LPTIM45,    RCC_LPTIM45CKSELR,      0, 3),
370         CFG_MUX(MUX_SPI23,      RCC_SPI2S23CKSELR,      0, 3),
371         CFG_MUX(MUX_UART35,     RCC_UART35CKSELR,       0, 3),
372         CFG_MUX(MUX_UART78,     RCC_UART78CKSELR,       0, 3),
373         CFG_MUX(MUX_ADC1,       RCC_ADC12CKSELR,        0, 2),
374         CFG_MUX(MUX_ADC2,       RCC_ADC12CKSELR,        2, 2),
375         CFG_MUX(MUX_DCMIPP,     RCC_DCMIPPCKSELR,       0, 2),
376         CFG_MUX(MUX_ETH1,       RCC_ETH12CKSELR,        0, 2),
377         CFG_MUX(MUX_ETH2,       RCC_ETH12CKSELR,        8, 2),
378         CFG_MUX(MUX_FDCAN,      RCC_FDCANCKSELR,        0, 2),
379         CFG_MUX(MUX_I2C3,       RCC_I2C345CKSELR,       0, 3),
380         CFG_MUX(MUX_I2C4,       RCC_I2C345CKSELR,       3, 3),
381         CFG_MUX(MUX_I2C5,       RCC_I2C345CKSELR,       6, 3),
382         CFG_MUX(MUX_LPTIM1,     RCC_LPTIM1CKSELR,       0, 3),
383         CFG_MUX(MUX_LPTIM2,     RCC_LPTIM23CKSELR,      0, 3),
384         CFG_MUX(MUX_LPTIM3,     RCC_LPTIM23CKSELR,      3, 3),
385         CFG_MUX(MUX_MCO1,       RCC_MCO1CFGR,           0, 3),
386         CFG_MUX(MUX_MCO2,       RCC_MCO2CFGR,           0, 3),
387         CFG_MUX(MUX_RNG1,       RCC_RNG1CKSELR,         0, 2),
388         CFG_MUX(MUX_SAES,       RCC_SAESCKSELR,         0, 2),
389         CFG_MUX(MUX_SAI1,       RCC_SAI1CKSELR,         0, 3),
390         CFG_MUX(MUX_SAI2,       RCC_SAI2CKSELR,         0, 3),
391         CFG_MUX(MUX_SPDIF,      RCC_SPDIFCKSELR,        0, 2),
392         CFG_MUX(MUX_SPI1,       RCC_SPI2S1CKSELR,       0, 3),
393         CFG_MUX(MUX_SPI4,       RCC_SPI45CKSELR,        0, 3),
394         CFG_MUX(MUX_SPI5,       RCC_SPI45CKSELR,        3, 3),
395         CFG_MUX(MUX_STGEN,      RCC_STGENCKSELR,        0, 2),
396         CFG_MUX(MUX_UART1,      RCC_UART12CKSELR,       0, 3),
397         CFG_MUX(MUX_UART2,      RCC_UART12CKSELR,       3, 3),
398         CFG_MUX(MUX_UART4,      RCC_UART4CKSELR,        0, 3),
399         CFG_MUX(MUX_UART6,      RCC_UART6CKSELR,        0, 3),
400         CFG_MUX(MUX_USBO,       RCC_USBCKSELR,          4, 1),
401         CFG_MUX(MUX_USBPHY,     RCC_USBCKSELR,          0, 2),
402         CFG_MUX_SAFE(MUX_FMC,   RCC_FMCCKSELR,          0, 2),
403         CFG_MUX_SAFE(MUX_QSPI,  RCC_QSPICKSELR,         0, 2),
404         CFG_MUX_SAFE(MUX_SDMMC1, RCC_SDMMC12CKSELR,     0, 3),
405         CFG_MUX_SAFE(MUX_SDMMC2, RCC_SDMMC12CKSELR,     3, 3),
406 };
407
408 struct clk_stm32_securiy {
409         u32     offset;
410         u8      bit_idx;
411         unsigned long scmi_id;
412 };
413
414 enum security_clk {
415         SECF_NONE,
416         SECF_LPTIM2,
417         SECF_LPTIM3,
418         SECF_VREF,
419         SECF_DCMIPP,
420         SECF_USBPHY,
421         SECF_TZC,
422         SECF_ETZPC,
423         SECF_IWDG1,
424         SECF_BSEC,
425         SECF_STGENC,
426         SECF_STGENRO,
427         SECF_USART1,
428         SECF_USART2,
429         SECF_SPI4,
430         SECF_SPI5,
431         SECF_I2C3,
432         SECF_I2C4,
433         SECF_I2C5,
434         SECF_TIM12,
435         SECF_TIM13,
436         SECF_TIM14,
437         SECF_TIM15,
438         SECF_TIM16,
439         SECF_TIM17,
440         SECF_DMA3,
441         SECF_DMAMUX2,
442         SECF_ADC1,
443         SECF_ADC2,
444         SECF_USBO,
445         SECF_TSC,
446         SECF_PKA,
447         SECF_SAES,
448         SECF_CRYP1,
449         SECF_HASH1,
450         SECF_RNG1,
451         SECF_BKPSRAM,
452         SECF_MCE,
453         SECF_FMC,
454         SECF_QSPI,
455         SECF_SDMMC1,
456         SECF_SDMMC2,
457         SECF_ETH1CK,
458         SECF_ETH1TX,
459         SECF_ETH1RX,
460         SECF_ETH1MAC,
461         SECF_ETH1STP,
462         SECF_ETH2CK,
463         SECF_ETH2TX,
464         SECF_ETH2RX,
465         SECF_ETH2MAC,
466         SECF_ETH2STP,
467         SECF_MCO1,
468         SECF_MCO2
469 };
470
471 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\
472         .offset = _offset,\
473         .bit_idx        = _bit_idx,\
474         .scmi_id        = -1,\
475 }
476
477 static const struct clk_stm32_securiy stm32mp13_security[] = {
478         SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF),
479         SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF),
480         SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF),
481         SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF),
482         SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF),
483         SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF),
484         SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF),
485         SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF),
486         SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF),
487         SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF),
488         SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF),
489         SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF),
490         SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF),
491         SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF),
492         SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF),
493         SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF),
494         SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF),
495         SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF),
496         SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF),
497         SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF),
498         SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF),
499         SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF),
500         SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF),
501         SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF),
502         SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF),
503         SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF),
504         SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF),
505         SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF),
506         SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF),
507         SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF),
508         SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF),
509         SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF),
510         SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF),
511         SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF),
512         SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF),
513         SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF),
514         SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF),
515         SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF),
516         SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF),
517         SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF),
518         SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF),
519         SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF),
520         SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF),
521         SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF),
522         SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF),
523         SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF),
524         SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF),
525         SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF),
526         SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF),
527         SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF),
528         SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF),
529         SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SEC),
530         SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SEC),
531 };
532
533 static const char * const adc12_src[] = {
534         "pll4_r", "ck_per", "pll3_q"
535 };
536
537 static const char * const dcmipp_src[] = {
538         "ck_axi", "pll2_q", "pll4_p", "ck_per",
539 };
540
541 static const char * const eth12_src[] = {
542         "pll4_p", "pll3_q"
543 };
544
545 static const char * const fdcan_src[] = {
546         "ck_hse", "pll3_q", "pll4_q", "pll4_r"
547 };
548
549 static const char * const fmc_src[] = {
550         "ck_axi", "pll3_r", "pll4_p", "ck_per"
551 };
552
553 static const char * const i2c12_src[] = {
554         "pclk1", "pll4_r", "ck_hsi", "ck_csi"
555 };
556
557 static const char * const i2c345_src[] = {
558         "pclk6", "pll4_r", "ck_hsi", "ck_csi"
559 };
560
561 static const char * const lptim1_src[] = {
562         "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
563 };
564
565 static const char * const lptim23_src[] = {
566         "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
567 };
568
569 static const char * const lptim45_src[] = {
570         "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
571 };
572
573 static const char * const mco1_src[] = {
574         "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
575 };
576
577 static const char * const mco2_src[] = {
578         "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
579 };
580
581 static const char * const qspi_src[] = {
582         "ck_axi", "pll3_r", "pll4_p", "ck_per"
583 };
584
585 static const char * const rng1_src[] = {
586         "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
587 };
588
589 static const char * const saes_src[] = {
590         "ck_axi", "ck_per", "pll4_r", "ck_lsi"
591 };
592
593 static const char * const sai1_src[] = {
594         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
595 };
596
597 static const char * const sai2_src[] = {
598         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
599 };
600
601 static const char * const sdmmc12_src[] = {
602         "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
603 };
604
605 static const char * const spdif_src[] = {
606         "pll4_p", "pll3_q", "ck_hsi"
607 };
608
609 static const char * const spi123_src[] = {
610         "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
611 };
612
613 static const char * const spi4_src[] = {
614         "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "i2s_ckin"
615 };
616
617 static const char * const spi5_src[] = {
618         "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
619 };
620
621 static const char * const stgen_src[] = {
622         "ck_hsi", "ck_hse"
623 };
624
625 static const char * const usart12_src[] = {
626         "pclk6", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
627 };
628
629 static const char * const usart34578_src[] = {
630         "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
631 };
632
633 static const char * const usart6_src[] = {
634         "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
635 };
636
637 static const char * const usbo_src[] = {
638         "pll4_r", "ck_usbo_48m"
639 };
640
641 static const char * const usbphy_src[] = {
642         "ck_hse", "pll4_r", "clk-hse-div2"
643 };
644
645 /* Timer clocks */
646 static struct clk_stm32_gate tim2_k = {
647         .gate_id = GATE_TIM2,
648         .hw.init = CLK_HW_INIT("tim2_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
649 };
650
651 static struct clk_stm32_gate tim3_k = {
652         .gate_id = GATE_TIM3,
653         .hw.init = CLK_HW_INIT("tim3_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
654 };
655
656 static struct clk_stm32_gate tim4_k = {
657         .gate_id = GATE_TIM4,
658         .hw.init = CLK_HW_INIT("tim4_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
659 };
660
661 static struct clk_stm32_gate tim5_k = {
662         .gate_id = GATE_TIM5,
663         .hw.init = CLK_HW_INIT("tim5_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
664 };
665
666 static struct clk_stm32_gate tim6_k = {
667         .gate_id = GATE_TIM6,
668         .hw.init = CLK_HW_INIT("tim6_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
669 };
670
671 static struct clk_stm32_gate tim7_k = {
672         .gate_id = GATE_TIM7,
673         .hw.init = CLK_HW_INIT("tim7_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
674 };
675
676 static struct clk_stm32_gate tim1_k = {
677         .gate_id = GATE_TIM1,
678         .hw.init = CLK_HW_INIT("tim1_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
679 };
680
681 static struct clk_stm32_gate tim8_k = {
682         .gate_id = GATE_TIM8,
683         .hw.init = CLK_HW_INIT("tim8_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
684 };
685
686 static struct clk_stm32_gate tim12_k = {
687         .gate_id = GATE_TIM12,
688         .hw.init = CLK_HW_INIT("tim12_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
689 };
690
691 static struct clk_stm32_gate tim13_k = {
692         .gate_id = GATE_TIM13,
693         .hw.init = CLK_HW_INIT("tim13_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
694 };
695
696 static struct clk_stm32_gate tim14_k = {
697         .gate_id = GATE_TIM14,
698         .hw.init = CLK_HW_INIT("tim14_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
699 };
700
701 static struct clk_stm32_gate tim15_k = {
702         .gate_id = GATE_TIM15,
703         .hw.init = CLK_HW_INIT("tim15_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
704 };
705
706 static struct clk_stm32_gate tim16_k = {
707         .gate_id = GATE_TIM16,
708         .hw.init = CLK_HW_INIT("tim16_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
709 };
710
711 static struct clk_stm32_gate tim17_k = {
712         .gate_id = GATE_TIM17,
713         .hw.init = CLK_HW_INIT("tim17_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
714 };
715
716 /* Peripheral clocks */
717 static struct clk_stm32_gate sai1 = {
718         .gate_id = GATE_SAI1,
719         .hw.init = CLK_HW_INIT("sai1", "pclk2", &clk_stm32_gate_ops, 0),
720 };
721
722 static struct clk_stm32_gate sai2 = {
723         .gate_id = GATE_SAI2,
724         .hw.init = CLK_HW_INIT("sai2", "pclk2", &clk_stm32_gate_ops, 0),
725 };
726
727 static struct clk_stm32_gate syscfg = {
728         .gate_id = GATE_SYSCFG,
729         .hw.init = CLK_HW_INIT("syscfg", "pclk3", &clk_stm32_gate_ops, 0),
730 };
731
732 static struct clk_stm32_gate vref = {
733         .gate_id = GATE_VREF,
734         .hw.init = CLK_HW_INIT("vref", "pclk3", &clk_stm32_gate_ops, 0),
735 };
736
737 static struct clk_stm32_gate dts = {
738         .gate_id = GATE_DTS,
739         .hw.init = CLK_HW_INIT("dts", "pclk3", &clk_stm32_gate_ops, 0),
740 };
741
742 static struct clk_stm32_gate pmbctrl = {
743         .gate_id = GATE_PMBCTRL,
744         .hw.init = CLK_HW_INIT("pmbctrl", "pclk3", &clk_stm32_gate_ops, 0),
745 };
746
747 static struct clk_stm32_gate hdp = {
748         .gate_id = GATE_HDP,
749         .hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0),
750 };
751
752 static struct clk_stm32_gate iwdg2 = {
753         .gate_id = GATE_IWDG2APB,
754         .hw.init = CLK_HW_INIT("iwdg2", "pclk4", &clk_stm32_gate_ops, 0),
755 };
756
757 static struct clk_stm32_gate stgenro = {
758         .gate_id = GATE_STGENRO,
759         .hw.init = CLK_HW_INIT("stgenro", "pclk4", &clk_stm32_gate_ops, 0),
760 };
761
762 static struct clk_stm32_gate gpioa = {
763         .gate_id = GATE_GPIOA,
764         .hw.init = CLK_HW_INIT("gpioa", "pclk4", &clk_stm32_gate_ops, 0),
765 };
766
767 static struct clk_stm32_gate gpiob = {
768         .gate_id = GATE_GPIOB,
769         .hw.init = CLK_HW_INIT("gpiob", "pclk4", &clk_stm32_gate_ops, 0),
770 };
771
772 static struct clk_stm32_gate gpioc = {
773         .gate_id = GATE_GPIOC,
774         .hw.init = CLK_HW_INIT("gpioc", "pclk4", &clk_stm32_gate_ops, 0),
775 };
776
777 static struct clk_stm32_gate gpiod = {
778         .gate_id = GATE_GPIOD,
779         .hw.init = CLK_HW_INIT("gpiod", "pclk4", &clk_stm32_gate_ops, 0),
780 };
781
782 static struct clk_stm32_gate gpioe = {
783         .gate_id = GATE_GPIOE,
784         .hw.init = CLK_HW_INIT("gpioe", "pclk4", &clk_stm32_gate_ops, 0),
785 };
786
787 static struct clk_stm32_gate gpiof = {
788         .gate_id = GATE_GPIOF,
789         .hw.init = CLK_HW_INIT("gpiof", "pclk4", &clk_stm32_gate_ops, 0),
790 };
791
792 static struct clk_stm32_gate gpiog = {
793         .gate_id = GATE_GPIOG,
794         .hw.init = CLK_HW_INIT("gpiog", "pclk4", &clk_stm32_gate_ops, 0),
795 };
796
797 static struct clk_stm32_gate gpioh = {
798         .gate_id = GATE_GPIOH,
799         .hw.init = CLK_HW_INIT("gpioh", "pclk4", &clk_stm32_gate_ops, 0),
800 };
801
802 static struct clk_stm32_gate gpioi = {
803         .gate_id = GATE_GPIOI,
804         .hw.init = CLK_HW_INIT("gpioi", "pclk4", &clk_stm32_gate_ops, 0),
805 };
806
807 static struct clk_stm32_gate tsc = {
808         .gate_id = GATE_TSC,
809         .hw.init = CLK_HW_INIT("tsc", "pclk4", &clk_stm32_gate_ops, 0),
810 };
811
812 static struct clk_stm32_gate ddrperfm = {
813         .gate_id = GATE_DDRPERFM,
814         .hw.init = CLK_HW_INIT("ddrperfm", "pclk4", &clk_stm32_gate_ops, 0),
815 };
816
817 static struct clk_stm32_gate tzpc = {
818         .gate_id = GATE_TZC,
819         .hw.init = CLK_HW_INIT("tzpc", "pclk5", &clk_stm32_gate_ops, 0),
820 };
821
822 static struct clk_stm32_gate iwdg1 = {
823         .gate_id = GATE_IWDG1APB,
824         .hw.init = CLK_HW_INIT("iwdg1", "pclk5", &clk_stm32_gate_ops, 0),
825 };
826
827 static struct clk_stm32_gate bsec = {
828         .gate_id = GATE_BSEC,
829         .hw.init = CLK_HW_INIT("bsec", "pclk5", &clk_stm32_gate_ops, 0),
830 };
831
832 static struct clk_stm32_gate dma1 = {
833         .gate_id = GATE_DMA1,
834         .hw.init = CLK_HW_INIT("dma1", "ck_mlahb", &clk_stm32_gate_ops, 0),
835 };
836
837 static struct clk_stm32_gate dma2 = {
838         .gate_id = GATE_DMA2,
839         .hw.init = CLK_HW_INIT("dma2", "ck_mlahb", &clk_stm32_gate_ops, 0),
840 };
841
842 static struct clk_stm32_gate dmamux1 = {
843         .gate_id = GATE_DMAMUX1,
844         .hw.init = CLK_HW_INIT("dmamux1", "ck_mlahb", &clk_stm32_gate_ops, 0),
845 };
846
847 static struct clk_stm32_gate dma3 = {
848         .gate_id = GATE_DMA3,
849         .hw.init = CLK_HW_INIT("dma3", "ck_mlahb", &clk_stm32_gate_ops, 0),
850 };
851
852 static struct clk_stm32_gate dmamux2 = {
853         .gate_id = GATE_DMAMUX2,
854         .hw.init = CLK_HW_INIT("dmamux2", "ck_mlahb", &clk_stm32_gate_ops, 0),
855 };
856
857 static struct clk_stm32_gate adc1 = {
858         .gate_id = GATE_ADC1,
859         .hw.init = CLK_HW_INIT("adc1", "ck_mlahb", &clk_stm32_gate_ops, 0),
860 };
861
862 static struct clk_stm32_gate adc2 = {
863         .gate_id = GATE_ADC2,
864         .hw.init = CLK_HW_INIT("adc2", "ck_mlahb", &clk_stm32_gate_ops, 0),
865 };
866
867 static struct clk_stm32_gate pka = {
868         .gate_id = GATE_PKA,
869         .hw.init = CLK_HW_INIT("pka", "ck_axi", &clk_stm32_gate_ops, 0),
870 };
871
872 static struct clk_stm32_gate cryp1 = {
873         .gate_id = GATE_CRYP1,
874         .hw.init = CLK_HW_INIT("cryp1", "ck_axi", &clk_stm32_gate_ops, 0),
875 };
876
877 static struct clk_stm32_gate hash1 = {
878         .gate_id = GATE_HASH1,
879         .hw.init = CLK_HW_INIT("hash1", "ck_axi", &clk_stm32_gate_ops, 0),
880 };
881
882 static struct clk_stm32_gate bkpsram = {
883         .gate_id = GATE_BKPSRAM,
884         .hw.init = CLK_HW_INIT("bkpsram", "ck_axi", &clk_stm32_gate_ops, 0),
885 };
886
887 static struct clk_stm32_gate mdma = {
888         .gate_id = GATE_MDMA,
889         .hw.init = CLK_HW_INIT("mdma", "ck_axi", &clk_stm32_gate_ops, 0),
890 };
891
892 static struct clk_stm32_gate eth1tx = {
893         .gate_id = GATE_ETH1TX,
894         .hw.init = CLK_HW_INIT("eth1tx", "ck_axi", &clk_stm32_gate_ops, 0),
895 };
896
897 static struct clk_stm32_gate eth1rx = {
898         .gate_id = GATE_ETH1RX,
899         .hw.init = CLK_HW_INIT("eth1rx", "ck_axi", &clk_stm32_gate_ops, 0),
900 };
901
902 static struct clk_stm32_gate eth1mac = {
903         .gate_id = GATE_ETH1MAC,
904         .hw.init = CLK_HW_INIT("eth1mac", "ck_axi", &clk_stm32_gate_ops, 0),
905 };
906
907 static struct clk_stm32_gate eth2tx = {
908         .gate_id = GATE_ETH2TX,
909         .hw.init = CLK_HW_INIT("eth2tx", "ck_axi", &clk_stm32_gate_ops, 0),
910 };
911
912 static struct clk_stm32_gate eth2rx = {
913         .gate_id = GATE_ETH2RX,
914         .hw.init = CLK_HW_INIT("eth2rx", "ck_axi", &clk_stm32_gate_ops, 0),
915 };
916
917 static struct clk_stm32_gate eth2mac = {
918         .gate_id = GATE_ETH2MAC,
919         .hw.init = CLK_HW_INIT("eth2mac", "ck_axi", &clk_stm32_gate_ops, 0),
920 };
921
922 static struct clk_stm32_gate crc1 = {
923         .gate_id = GATE_CRC1,
924         .hw.init = CLK_HW_INIT("crc1", "ck_axi", &clk_stm32_gate_ops, 0),
925 };
926
927 static struct clk_stm32_gate usbh = {
928         .gate_id = GATE_USBH,
929         .hw.init = CLK_HW_INIT("usbh", "ck_axi", &clk_stm32_gate_ops, 0),
930 };
931
932 static struct clk_stm32_gate eth1stp = {
933         .gate_id = GATE_ETH1STP,
934         .hw.init = CLK_HW_INIT("eth1stp", "ck_axi", &clk_stm32_gate_ops, 0),
935 };
936
937 static struct clk_stm32_gate eth2stp = {
938         .gate_id = GATE_ETH2STP,
939         .hw.init = CLK_HW_INIT("eth2stp", "ck_axi", &clk_stm32_gate_ops, 0),
940 };
941
942 /* Kernel clocks */
943 static struct clk_stm32_composite sdmmc1_k = {
944         .gate_id = GATE_SDMMC1,
945         .mux_id = MUX_SDMMC1,
946         .div_id = NO_STM32_DIV,
947         .hw.init = CLK_HW_INIT_PARENTS("sdmmc1_k", sdmmc12_src, &clk_stm32_composite_ops,
948                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
949 };
950
951 static struct clk_stm32_composite sdmmc2_k = {
952         .gate_id = GATE_SDMMC2,
953         .mux_id = MUX_SDMMC2,
954         .div_id = NO_STM32_DIV,
955         .hw.init = CLK_HW_INIT_PARENTS("sdmmc2_k", sdmmc12_src, &clk_stm32_composite_ops,
956                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
957 };
958
959 static struct clk_stm32_composite fmc_k = {
960         .gate_id = GATE_FMC,
961         .mux_id = MUX_FMC,
962         .div_id = NO_STM32_DIV,
963         .hw.init = CLK_HW_INIT_PARENTS("fmc_k", fmc_src, &clk_stm32_composite_ops,
964                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
965 };
966
967 static struct clk_stm32_composite qspi_k = {
968         .gate_id = GATE_QSPI,
969         .mux_id = MUX_QSPI,
970         .div_id = NO_STM32_DIV,
971         .hw.init = CLK_HW_INIT_PARENTS("qspi_k", qspi_src, &clk_stm32_composite_ops,
972                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
973 };
974
975 static struct clk_stm32_composite spi2_k = {
976         .gate_id = GATE_SPI2,
977         .mux_id = MUX_SPI23,
978         .div_id = NO_STM32_DIV,
979         .hw.init = CLK_HW_INIT_PARENTS("spi2_k", spi123_src, &clk_stm32_composite_ops,
980                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
981 };
982
983 static struct clk_stm32_composite spi3_k = {
984         .gate_id = GATE_SPI3,
985         .mux_id = MUX_SPI23,
986         .div_id = NO_STM32_DIV,
987         .hw.init = CLK_HW_INIT_PARENTS("spi3_k", spi123_src, &clk_stm32_composite_ops,
988                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
989 };
990
991 static struct clk_stm32_composite i2c1_k = {
992         .gate_id = GATE_I2C1,
993         .mux_id = MUX_I2C12,
994         .div_id = NO_STM32_DIV,
995         .hw.init = CLK_HW_INIT_PARENTS("i2c1_k", i2c12_src, &clk_stm32_composite_ops,
996                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
997 };
998
999 static struct clk_stm32_composite i2c2_k = {
1000         .gate_id = GATE_I2C2,
1001         .mux_id = MUX_I2C12,
1002         .div_id = NO_STM32_DIV,
1003         .hw.init = CLK_HW_INIT_PARENTS("i2c2_k", i2c12_src, &clk_stm32_composite_ops,
1004                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1005 };
1006
1007 static struct clk_stm32_composite lptim4_k = {
1008         .gate_id = GATE_LPTIM4,
1009         .mux_id = MUX_LPTIM45,
1010         .div_id = NO_STM32_DIV,
1011         .hw.init = CLK_HW_INIT_PARENTS("lptim4_k", lptim45_src, &clk_stm32_composite_ops,
1012                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1013 };
1014
1015 static struct clk_stm32_composite lptim5_k = {
1016         .gate_id = GATE_LPTIM5,
1017         .mux_id = MUX_LPTIM45,
1018         .div_id = NO_STM32_DIV,
1019         .hw.init = CLK_HW_INIT_PARENTS("lptim5_k", lptim45_src, &clk_stm32_composite_ops,
1020                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1021 };
1022
1023 static struct clk_stm32_composite usart3_k = {
1024         .gate_id = GATE_USART3,
1025         .mux_id = MUX_UART35,
1026         .div_id = NO_STM32_DIV,
1027         .hw.init = CLK_HW_INIT_PARENTS("usart3_k", usart34578_src, &clk_stm32_composite_ops,
1028                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1029 };
1030
1031 static struct clk_stm32_composite uart5_k = {
1032         .gate_id = GATE_UART5,
1033         .mux_id = MUX_UART35,
1034         .div_id = NO_STM32_DIV,
1035         .hw.init = CLK_HW_INIT_PARENTS("uart5_k", usart34578_src, &clk_stm32_composite_ops,
1036                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1037 };
1038
1039 static struct clk_stm32_composite uart7_k = {
1040         .gate_id = GATE_UART7,
1041         .mux_id = MUX_UART78,
1042         .div_id = NO_STM32_DIV,
1043         .hw.init = CLK_HW_INIT_PARENTS("uart7_k", usart34578_src, &clk_stm32_composite_ops,
1044                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1045 };
1046
1047 static struct clk_stm32_composite uart8_k = {
1048         .gate_id = GATE_UART8,
1049         .mux_id = MUX_UART78,
1050         .div_id = NO_STM32_DIV,
1051         .hw.init = CLK_HW_INIT_PARENTS("uart8_k", usart34578_src, &clk_stm32_composite_ops,
1052                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1053 };
1054
1055 static struct clk_stm32_composite sai1_k = {
1056         .gate_id = GATE_SAI1,
1057         .mux_id = MUX_SAI1,
1058         .div_id = NO_STM32_DIV,
1059         .hw.init = CLK_HW_INIT_PARENTS("sai1_k", sai1_src, &clk_stm32_composite_ops,
1060                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1061 };
1062
1063 static struct clk_stm32_composite adfsdm_k = {
1064         .gate_id = GATE_ADFSDM,
1065         .mux_id = MUX_SAI1,
1066         .div_id = NO_STM32_DIV,
1067         .hw.init = CLK_HW_INIT_PARENTS("adfsdm_k", sai1_src, &clk_stm32_composite_ops,
1068                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1069 };
1070
1071 static struct clk_stm32_composite sai2_k = {
1072         .gate_id = GATE_SAI2,
1073         .mux_id = MUX_SAI2,
1074         .div_id = NO_STM32_DIV,
1075         .hw.init = CLK_HW_INIT_PARENTS("sai2_k", sai2_src, &clk_stm32_composite_ops,
1076                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1077 };
1078
1079 static struct clk_stm32_composite adc1_k = {
1080         .gate_id = GATE_ADC1,
1081         .mux_id = MUX_ADC1,
1082         .div_id = NO_STM32_DIV,
1083         .hw.init = CLK_HW_INIT_PARENTS("adc1_k", adc12_src, &clk_stm32_composite_ops,
1084                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1085 };
1086
1087 static struct clk_stm32_composite adc2_k = {
1088         .gate_id = GATE_ADC2,
1089         .mux_id = MUX_ADC2,
1090         .div_id = NO_STM32_DIV,
1091         .hw.init = CLK_HW_INIT_PARENTS("adc2_k", adc12_src, &clk_stm32_composite_ops,
1092                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1093 };
1094
1095 static struct clk_stm32_composite rng1_k = {
1096         .gate_id = GATE_RNG1,
1097         .mux_id = MUX_RNG1,
1098         .div_id = NO_STM32_DIV,
1099         .hw.init = CLK_HW_INIT_PARENTS("rng1_k", rng1_src, &clk_stm32_composite_ops,
1100                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1101 };
1102
1103 static struct clk_stm32_composite usbphy_k = {
1104         .gate_id = GATE_USBPHY,
1105         .mux_id = MUX_USBPHY,
1106         .div_id = NO_STM32_DIV,
1107         .hw.init = CLK_HW_INIT_PARENTS("usbphy_k", usbphy_src, &clk_stm32_composite_ops,
1108                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1109 };
1110
1111 static struct clk_stm32_composite stgen_k = {
1112         .gate_id = GATE_STGENC,
1113         .mux_id = MUX_STGEN,
1114         .div_id = NO_STM32_DIV,
1115         .hw.init = CLK_HW_INIT_PARENTS("stgen_k", stgen_src, &clk_stm32_composite_ops,
1116                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1117 };
1118
1119 static struct clk_stm32_composite spdif_k = {
1120         .gate_id = GATE_SPDIF,
1121         .mux_id = MUX_SPDIF,
1122         .div_id = NO_STM32_DIV,
1123         .hw.init = CLK_HW_INIT_PARENTS("spdif_k", spdif_src, &clk_stm32_composite_ops,
1124                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1125 };
1126
1127 static struct clk_stm32_composite spi1_k = {
1128         .gate_id = GATE_SPI1,
1129         .mux_id = MUX_SPI1,
1130         .div_id = NO_STM32_DIV,
1131         .hw.init = CLK_HW_INIT_PARENTS("spi1_k", spi123_src, &clk_stm32_composite_ops,
1132                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1133 };
1134
1135 static struct clk_stm32_composite spi4_k = {
1136         .gate_id = GATE_SPI4,
1137         .mux_id = MUX_SPI4,
1138         .div_id = NO_STM32_DIV,
1139         .hw.init = CLK_HW_INIT_PARENTS("spi4_k", spi4_src, &clk_stm32_composite_ops,
1140                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1141 };
1142
1143 static struct clk_stm32_composite spi5_k = {
1144         .gate_id = GATE_SPI5,
1145         .mux_id = MUX_SPI5,
1146         .div_id = NO_STM32_DIV,
1147         .hw.init = CLK_HW_INIT_PARENTS("spi5_k", spi5_src, &clk_stm32_composite_ops,
1148                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1149 };
1150
1151 static struct clk_stm32_composite i2c3_k = {
1152         .gate_id = GATE_I2C3,
1153         .mux_id = MUX_I2C3,
1154         .div_id = NO_STM32_DIV,
1155         .hw.init = CLK_HW_INIT_PARENTS("i2c3_k", i2c345_src, &clk_stm32_composite_ops,
1156                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1157 };
1158
1159 static struct clk_stm32_composite i2c4_k = {
1160         .gate_id = GATE_I2C4,
1161         .mux_id = MUX_I2C4,
1162         .div_id = NO_STM32_DIV,
1163         .hw.init = CLK_HW_INIT_PARENTS("i2c4_k", i2c345_src, &clk_stm32_composite_ops,
1164                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1165 };
1166
1167 static struct clk_stm32_composite i2c5_k = {
1168         .gate_id = GATE_I2C5,
1169         .mux_id = MUX_I2C5,
1170         .div_id = NO_STM32_DIV,
1171         .hw.init = CLK_HW_INIT_PARENTS("i2c5_k", i2c345_src, &clk_stm32_composite_ops,
1172                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1173 };
1174
1175 static struct clk_stm32_composite lptim1_k = {
1176         .gate_id = GATE_LPTIM1,
1177         .mux_id = MUX_LPTIM1,
1178         .div_id = NO_STM32_DIV,
1179         .hw.init = CLK_HW_INIT_PARENTS("lptim1_k", lptim1_src, &clk_stm32_composite_ops,
1180                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1181 };
1182
1183 static struct clk_stm32_composite lptim2_k = {
1184         .gate_id = GATE_LPTIM2,
1185         .mux_id = MUX_LPTIM2,
1186         .div_id = NO_STM32_DIV,
1187         .hw.init = CLK_HW_INIT_PARENTS("lptim2_k", lptim23_src, &clk_stm32_composite_ops,
1188                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1189 };
1190
1191 static struct clk_stm32_composite lptim3_k = {
1192         .gate_id = GATE_LPTIM3,
1193         .mux_id = MUX_LPTIM3,
1194         .div_id = NO_STM32_DIV,
1195         .hw.init = CLK_HW_INIT_PARENTS("lptim3_k", lptim23_src, &clk_stm32_composite_ops,
1196                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1197 };
1198
1199 static struct clk_stm32_composite usart1_k = {
1200         .gate_id = GATE_USART1,
1201         .mux_id = MUX_UART1,
1202         .div_id = NO_STM32_DIV,
1203         .hw.init = CLK_HW_INIT_PARENTS("usart1_k", usart12_src, &clk_stm32_composite_ops,
1204                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1205 };
1206
1207 static struct clk_stm32_composite usart2_k = {
1208         .gate_id = GATE_USART2,
1209         .mux_id = MUX_UART2,
1210         .div_id = NO_STM32_DIV,
1211         .hw.init = CLK_HW_INIT_PARENTS("usart2_k", usart12_src, &clk_stm32_composite_ops,
1212                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1213 };
1214
1215 static struct clk_stm32_composite uart4_k = {
1216         .gate_id = GATE_UART4,
1217         .mux_id = MUX_UART4,
1218         .div_id = NO_STM32_DIV,
1219         .hw.init = CLK_HW_INIT_PARENTS("uart4_k", usart34578_src, &clk_stm32_composite_ops,
1220                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1221 };
1222
1223 static struct clk_stm32_composite uart6_k = {
1224         .gate_id = GATE_USART6,
1225         .mux_id = MUX_UART6,
1226         .div_id = NO_STM32_DIV,
1227         .hw.init = CLK_HW_INIT_PARENTS("uart6_k", usart6_src, &clk_stm32_composite_ops,
1228                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1229 };
1230
1231 static struct clk_stm32_composite fdcan_k = {
1232         .gate_id = GATE_FDCAN,
1233         .mux_id = MUX_FDCAN,
1234         .div_id = NO_STM32_DIV,
1235         .hw.init = CLK_HW_INIT_PARENTS("fdcan_k", fdcan_src, &clk_stm32_composite_ops,
1236                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1237 };
1238
1239 static struct clk_stm32_composite dcmipp_k = {
1240         .gate_id = GATE_DCMIPP,
1241         .mux_id = MUX_DCMIPP,
1242         .div_id = NO_STM32_DIV,
1243         .hw.init = CLK_HW_INIT_PARENTS("dcmipp_k", dcmipp_src, &clk_stm32_composite_ops,
1244                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1245 };
1246
1247 static struct clk_stm32_composite usbo_k = {
1248         .gate_id = GATE_USBO,
1249         .mux_id = MUX_USBO,
1250         .div_id = NO_STM32_DIV,
1251         .hw.init = CLK_HW_INIT_PARENTS("usbo_k", usbo_src, &clk_stm32_composite_ops,
1252                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1253 };
1254
1255 static struct clk_stm32_composite saes_k = {
1256         .gate_id = GATE_SAES,
1257         .mux_id = MUX_SAES,
1258         .div_id = NO_STM32_DIV,
1259         .hw.init = CLK_HW_INIT_PARENTS("saes_k", saes_src, &clk_stm32_composite_ops,
1260                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1261 };
1262
1263 static struct clk_stm32_gate dfsdm_k = {
1264         .gate_id = GATE_DFSDM,
1265         .hw.init = CLK_HW_INIT("dfsdm_k", "ck_mlahb", &clk_stm32_gate_ops, 0),
1266 };
1267
1268 static struct clk_stm32_gate ltdc_px = {
1269         .gate_id = GATE_LTDC,
1270         .hw.init = CLK_HW_INIT("ltdc_px", "pll4_q", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
1271 };
1272
1273 static struct clk_stm32_mux ck_ker_eth1 = {
1274         .mux_id = MUX_ETH1,
1275         .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
1276                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1277 };
1278
1279 static struct clk_stm32_gate eth1ck_k = {
1280         .gate_id = GATE_ETH1CK,
1281         .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0),
1282 };
1283
1284 static struct clk_stm32_div eth1ptp_k = {
1285         .div_id = DIV_ETH1PTP,
1286         .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops,
1287                                   CLK_SET_RATE_NO_REPARENT),
1288 };
1289
1290 static struct clk_stm32_mux ck_ker_eth2 = {
1291         .mux_id = MUX_ETH2,
1292         .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth2", eth12_src, &clk_stm32_mux_ops,
1293                                             CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1294 };
1295
1296 static struct clk_stm32_gate eth2ck_k = {
1297         .gate_id = GATE_ETH2CK,
1298         .hw.init = CLK_HW_INIT_HW("eth2ck_k", &ck_ker_eth2.hw, &clk_stm32_gate_ops, 0),
1299 };
1300
1301 static struct clk_stm32_div eth2ptp_k = {
1302         .div_id = DIV_ETH2PTP,
1303         .hw.init = CLK_HW_INIT_HW("eth2ptp_k", &ck_ker_eth2.hw, &clk_stm32_divider_ops,
1304                                   CLK_SET_RATE_NO_REPARENT),
1305 };
1306
1307 static struct clk_stm32_composite ck_mco1 = {
1308         .gate_id = GATE_MCO1,
1309         .mux_id = MUX_MCO1,
1310         .div_id = DIV_MCO1,
1311         .hw.init = CLK_HW_INIT_PARENTS("ck_mco1", mco1_src, &clk_stm32_composite_ops,
1312                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
1313                                        CLK_IGNORE_UNUSED),
1314 };
1315
1316 static struct clk_stm32_composite ck_mco2 = {
1317         .gate_id = GATE_MCO2,
1318         .mux_id = MUX_MCO2,
1319         .div_id = DIV_MCO2,
1320         .hw.init = CLK_HW_INIT_PARENTS("ck_mco2", mco2_src, &clk_stm32_composite_ops,
1321                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
1322                                        CLK_IGNORE_UNUSED),
1323 };
1324
1325 /* Debug clocks */
1326 static struct clk_stm32_gate ck_sys_dbg = {
1327         .gate_id = GATE_DBGCK,
1328         .hw.init = CLK_HW_INIT("ck_sys_dbg", "ck_axi", &clk_stm32_gate_ops, CLK_IS_CRITICAL),
1329 };
1330
1331 static struct clk_stm32_composite ck_trace = {
1332         .gate_id = GATE_TRACECK,
1333         .mux_id = NO_STM32_MUX,
1334         .div_id = DIV_TRACE,
1335         .hw.init = CLK_HW_INIT("ck_trace", "ck_axi", &clk_stm32_composite_ops, CLK_IGNORE_UNUSED),
1336 };
1337
1338 static const struct clock_config stm32mp13_clock_cfg[] = {
1339         /* Timer clocks */
1340         STM32_GATE_CFG(TIM2_K, tim2_k, SECF_NONE),
1341         STM32_GATE_CFG(TIM3_K, tim3_k, SECF_NONE),
1342         STM32_GATE_CFG(TIM4_K, tim4_k, SECF_NONE),
1343         STM32_GATE_CFG(TIM5_K, tim5_k, SECF_NONE),
1344         STM32_GATE_CFG(TIM6_K, tim6_k, SECF_NONE),
1345         STM32_GATE_CFG(TIM7_K, tim7_k, SECF_NONE),
1346         STM32_GATE_CFG(TIM1_K, tim1_k, SECF_NONE),
1347         STM32_GATE_CFG(TIM8_K, tim8_k, SECF_NONE),
1348         STM32_GATE_CFG(TIM12_K, tim12_k, SECF_TIM12),
1349         STM32_GATE_CFG(TIM13_K, tim13_k, SECF_TIM13),
1350         STM32_GATE_CFG(TIM14_K, tim14_k, SECF_TIM14),
1351         STM32_GATE_CFG(TIM15_K, tim15_k, SECF_TIM15),
1352         STM32_GATE_CFG(TIM16_K, tim16_k, SECF_TIM16),
1353         STM32_GATE_CFG(TIM17_K, tim17_k, SECF_TIM17),
1354
1355         /* Peripheral clocks */
1356         STM32_GATE_CFG(SAI1, sai1, SECF_NONE),
1357         STM32_GATE_CFG(SAI2, sai2, SECF_NONE),
1358         STM32_GATE_CFG(SYSCFG, syscfg, SECF_NONE),
1359         STM32_GATE_CFG(VREF, vref, SECF_VREF),
1360         STM32_GATE_CFG(DTS, dts, SECF_NONE),
1361         STM32_GATE_CFG(PMBCTRL, pmbctrl, SECF_NONE),
1362         STM32_GATE_CFG(HDP, hdp, SECF_NONE),
1363         STM32_GATE_CFG(IWDG2, iwdg2, SECF_NONE),
1364         STM32_GATE_CFG(STGENRO, stgenro, SECF_STGENRO),
1365         STM32_GATE_CFG(TZPC, tzpc, SECF_TZC),
1366         STM32_GATE_CFG(IWDG1, iwdg1, SECF_IWDG1),
1367         STM32_GATE_CFG(BSEC, bsec, SECF_BSEC),
1368         STM32_GATE_CFG(DMA1, dma1, SECF_NONE),
1369         STM32_GATE_CFG(DMA2, dma2, SECF_NONE),
1370         STM32_GATE_CFG(DMAMUX1, dmamux1, SECF_NONE),
1371         STM32_GATE_CFG(DMA3, dma3, SECF_DMA3),
1372         STM32_GATE_CFG(DMAMUX2, dmamux2, SECF_DMAMUX2),
1373         STM32_GATE_CFG(ADC1, adc1, SECF_ADC1),
1374         STM32_GATE_CFG(ADC2, adc2, SECF_ADC2),
1375         STM32_GATE_CFG(GPIOA, gpioa, SECF_NONE),
1376         STM32_GATE_CFG(GPIOB, gpiob, SECF_NONE),
1377         STM32_GATE_CFG(GPIOC, gpioc, SECF_NONE),
1378         STM32_GATE_CFG(GPIOD, gpiod, SECF_NONE),
1379         STM32_GATE_CFG(GPIOE, gpioe, SECF_NONE),
1380         STM32_GATE_CFG(GPIOF, gpiof, SECF_NONE),
1381         STM32_GATE_CFG(GPIOG, gpiog, SECF_NONE),
1382         STM32_GATE_CFG(GPIOH, gpioh, SECF_NONE),
1383         STM32_GATE_CFG(GPIOI, gpioi, SECF_NONE),
1384         STM32_GATE_CFG(TSC, tsc, SECF_TZC),
1385         STM32_GATE_CFG(PKA, pka, SECF_PKA),
1386         STM32_GATE_CFG(CRYP1, cryp1, SECF_CRYP1),
1387         STM32_GATE_CFG(HASH1, hash1, SECF_HASH1),
1388         STM32_GATE_CFG(BKPSRAM, bkpsram, SECF_BKPSRAM),
1389         STM32_GATE_CFG(MDMA, mdma, SECF_NONE),
1390         STM32_GATE_CFG(ETH1TX, eth1tx, SECF_ETH1TX),
1391         STM32_GATE_CFG(ETH1RX, eth1rx, SECF_ETH1RX),
1392         STM32_GATE_CFG(ETH1MAC, eth1mac, SECF_ETH1MAC),
1393         STM32_GATE_CFG(ETH2TX, eth2tx, SECF_ETH2TX),
1394         STM32_GATE_CFG(ETH2RX, eth2rx, SECF_ETH2RX),
1395         STM32_GATE_CFG(ETH2MAC, eth2mac, SECF_ETH2MAC),
1396         STM32_GATE_CFG(CRC1, crc1, SECF_NONE),
1397         STM32_GATE_CFG(USBH, usbh, SECF_NONE),
1398         STM32_GATE_CFG(DDRPERFM, ddrperfm, SECF_NONE),
1399         STM32_GATE_CFG(ETH1STP, eth1stp, SECF_ETH1STP),
1400         STM32_GATE_CFG(ETH2STP, eth2stp, SECF_ETH2STP),
1401
1402         /* Kernel clocks */
1403         STM32_COMPOSITE_CFG(SDMMC1_K, sdmmc1_k, SECF_SDMMC1),
1404         STM32_COMPOSITE_CFG(SDMMC2_K, sdmmc2_k, SECF_SDMMC2),
1405         STM32_COMPOSITE_CFG(FMC_K, fmc_k, SECF_FMC),
1406         STM32_COMPOSITE_CFG(QSPI_K, qspi_k, SECF_QSPI),
1407         STM32_COMPOSITE_CFG(SPI2_K, spi2_k, SECF_NONE),
1408         STM32_COMPOSITE_CFG(SPI3_K, spi3_k, SECF_NONE),
1409         STM32_COMPOSITE_CFG(I2C1_K, i2c1_k, SECF_NONE),
1410         STM32_COMPOSITE_CFG(I2C2_K, i2c2_k, SECF_NONE),
1411         STM32_COMPOSITE_CFG(LPTIM4_K, lptim4_k, SECF_NONE),
1412         STM32_COMPOSITE_CFG(LPTIM5_K, lptim5_k, SECF_NONE),
1413         STM32_COMPOSITE_CFG(USART3_K, usart3_k, SECF_NONE),
1414         STM32_COMPOSITE_CFG(UART5_K, uart5_k, SECF_NONE),
1415         STM32_COMPOSITE_CFG(UART7_K, uart7_k, SECF_NONE),
1416         STM32_COMPOSITE_CFG(UART8_K, uart8_k, SECF_NONE),
1417         STM32_COMPOSITE_CFG(SAI1_K, sai1_k, SECF_NONE),
1418         STM32_COMPOSITE_CFG(SAI2_K, sai2_k, SECF_NONE),
1419         STM32_COMPOSITE_CFG(ADFSDM_K, adfsdm_k, SECF_NONE),
1420         STM32_COMPOSITE_CFG(ADC1_K, adc1_k, SECF_ADC1),
1421         STM32_COMPOSITE_CFG(ADC2_K, adc2_k, SECF_ADC2),
1422         STM32_COMPOSITE_CFG(RNG1_K, rng1_k, SECF_RNG1),
1423         STM32_COMPOSITE_CFG(USBPHY_K, usbphy_k, SECF_USBPHY),
1424         STM32_COMPOSITE_CFG(STGEN_K, stgen_k, SECF_STGENC),
1425         STM32_COMPOSITE_CFG(SPDIF_K, spdif_k, SECF_NONE),
1426         STM32_COMPOSITE_CFG(SPI1_K, spi1_k, SECF_NONE),
1427         STM32_COMPOSITE_CFG(SPI4_K, spi4_k, SECF_SPI4),
1428         STM32_COMPOSITE_CFG(SPI5_K, spi5_k, SECF_SPI5),
1429         STM32_COMPOSITE_CFG(I2C3_K, i2c3_k, SECF_I2C3),
1430         STM32_COMPOSITE_CFG(I2C4_K, i2c4_k, SECF_I2C4),
1431         STM32_COMPOSITE_CFG(I2C5_K, i2c5_k, SECF_I2C5),
1432         STM32_COMPOSITE_CFG(LPTIM1_K, lptim1_k, SECF_NONE),
1433         STM32_COMPOSITE_CFG(LPTIM2_K, lptim2_k, SECF_LPTIM2),
1434         STM32_COMPOSITE_CFG(LPTIM3_K, lptim3_k, SECF_LPTIM3),
1435         STM32_COMPOSITE_CFG(USART1_K, usart1_k, SECF_USART1),
1436         STM32_COMPOSITE_CFG(USART2_K, usart2_k, SECF_USART2),
1437         STM32_COMPOSITE_CFG(UART4_K, uart4_k, SECF_NONE),
1438         STM32_COMPOSITE_CFG(USART6_K, uart6_k, SECF_NONE),
1439         STM32_COMPOSITE_CFG(FDCAN_K, fdcan_k, SECF_NONE),
1440         STM32_COMPOSITE_CFG(DCMIPP_K, dcmipp_k, SECF_DCMIPP),
1441         STM32_COMPOSITE_CFG(USBO_K, usbo_k, SECF_USBO),
1442         STM32_COMPOSITE_CFG(SAES_K, saes_k, SECF_SAES),
1443         STM32_GATE_CFG(DFSDM_K, dfsdm_k, SECF_NONE),
1444         STM32_GATE_CFG(LTDC_PX, ltdc_px, SECF_NONE),
1445
1446         STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK),
1447         STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK),
1448         STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK),
1449
1450         STM32_MUX_CFG(NO_ID, ck_ker_eth2, SECF_ETH2CK),
1451         STM32_GATE_CFG(ETH2CK_K, eth2ck_k, SECF_ETH2CK),
1452         STM32_DIV_CFG(ETH2PTP_K, eth2ptp_k, SECF_ETH2CK),
1453
1454         STM32_GATE_CFG(CK_DBG, ck_sys_dbg, SECF_NONE),
1455         STM32_COMPOSITE_CFG(CK_TRACE, ck_trace, SECF_NONE),
1456
1457         STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, SECF_MCO1),
1458         STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, SECF_MCO2),
1459 };
1460
1461 static int stm32mp13_clock_is_provided_by_secure(struct device_node *np, void __iomem *base,
1462                                                  const struct clock_config *cfg)
1463 {
1464         int sec_id = cfg->sec_id;
1465
1466         if (sec_id != SECF_NONE) {
1467                 const struct clk_stm32_securiy *secf;
1468
1469                 secf = &stm32mp13_security[sec_id];
1470
1471                 return !!(readl(base + secf->offset) & BIT(secf->bit_idx));
1472         }
1473
1474         return 0;
1475 }
1476
1477 struct multi_mux {
1478         struct clk_hw *hw1;
1479         struct clk_hw *hw2;
1480 };
1481
1482 static struct multi_mux *stm32_mp13_multi_mux[MUX_NB] = {
1483         [MUX_SPI23]     = &(struct multi_mux){ &spi2_k.hw,      &spi3_k.hw },
1484         [MUX_I2C12]     = &(struct multi_mux){ &i2c1_k.hw,      &i2c2_k.hw },
1485         [MUX_LPTIM45]   = &(struct multi_mux){ &lptim4_k.hw,    &lptim5_k.hw },
1486         [MUX_UART35]    = &(struct multi_mux){ &usart3_k.hw,    &uart5_k.hw },
1487         [MUX_UART78]    = &(struct multi_mux){ &uart7_k.hw,     &uart8_k.hw },
1488         [MUX_SAI1]      = &(struct multi_mux){ &sai1_k.hw,      &adfsdm_k.hw },
1489 };
1490
1491 static struct clk_hw *stm32mp13_is_multi_mux(struct clk_hw *hw)
1492 {
1493         struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
1494         struct multi_mux *mmux = stm32_mp13_multi_mux[composite->mux_id];
1495
1496         if (mmux) {
1497                 if (!(mmux->hw1 == hw))
1498                         return mmux->hw1;
1499                 else
1500                         return mmux->hw2;
1501         }
1502
1503         return NULL;
1504 }
1505
1506 static u16 stm32mp13_cpt_gate[GATE_NB];
1507
1508 static struct clk_stm32_clock_data stm32mp13_clock_data = {
1509         .gate_cpt       = stm32mp13_cpt_gate,
1510         .gates          = stm32mp13_gates,
1511         .muxes          = stm32mp13_muxes,
1512         .dividers       = stm32mp13_dividers,
1513         .is_multi_mux   = stm32mp13_is_multi_mux,
1514 };
1515
1516 static struct clk_stm32_reset_data stm32mp13_reset_data = {
1517         .nr_lines       = STM32MP1_RESET_ID_MASK,
1518         .clear_offset   = RCC_CLR_OFFSET,
1519 };
1520
1521 static const struct stm32_rcc_match_data stm32mp13_data = {
1522         .tab_clocks     = stm32mp13_clock_cfg,
1523         .num_clocks     = ARRAY_SIZE(stm32mp13_clock_cfg),
1524         .clock_data     = &stm32mp13_clock_data,
1525         .check_security = &stm32mp13_clock_is_provided_by_secure,
1526         .maxbinding     = STM32MP1_LAST_CLK,
1527         .reset_data     = &stm32mp13_reset_data,
1528 };
1529
1530 static const struct of_device_id stm32mp13_match_data[] = {
1531         {
1532                 .compatible = "st,stm32mp13-rcc",
1533                 .data = &stm32mp13_data,
1534         },
1535         { }
1536 };
1537 MODULE_DEVICE_TABLE(of, stm32mp13_match_data);
1538
1539 static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
1540 {
1541         struct device *dev = &pdev->dev;
1542         void __iomem *base;
1543
1544         base = devm_platform_ioremap_resource(pdev, 0);
1545         if (WARN_ON(IS_ERR(base)))
1546                 return PTR_ERR(base);
1547
1548         return stm32_rcc_init(dev, stm32mp13_match_data, base);
1549 }
1550
1551 static struct platform_driver stm32mp13_rcc_clocks_driver = {
1552         .driver = {
1553                 .name = "stm32mp13_rcc",
1554                 .of_match_table = stm32mp13_match_data,
1555         },
1556         .probe = stm32mp1_rcc_clocks_probe,
1557 };
1558
1559 static int __init stm32mp13_clocks_init(void)
1560 {
1561         return platform_driver_register(&stm32mp13_rcc_clocks_driver);
1562 }
1563 core_initcall(stm32mp13_clocks_init);
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