drivers/clk/stm32/clk-stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  * Author: Olivier Bideau <[email protected]> for STMicroelectronics.
   5  * Author: Gabriel Fernandez <[email protected]> for STMicroelectronics.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/reset-controller.h>
  18 #include <linux/slab.h>
  19 #include <linux/spinlock.h>
  20
  21 #include <dt-bindings/clock/stm32mp1-clks.h>
  22
  23 #include "reset-stm32.h"
  24
  25 #define STM32MP1_RESET_ID_MASK GENMASK(15, 0)
  26
  27 static DEFINE_SPINLOCK(rlock);
  28
  29 #define RCC_OCENSETR            0x0C
  30 #define RCC_HSICFGR             0x18
  31 #define RCC_RDLSICR             0x144
  32 #define RCC_PLL1CR              0x80
  33 #define RCC_PLL1CFGR1           0x84
  34 #define RCC_PLL1CFGR2           0x88
  35 #define RCC_PLL2CR              0x94
  36 #define RCC_PLL2CFGR1           0x98
  37 #define RCC_PLL2CFGR2           0x9C
  38 #define RCC_PLL3CR              0x880
  39 #define RCC_PLL3CFGR1           0x884
  40 #define RCC_PLL3CFGR2           0x888
  41 #define RCC_PLL4CR              0x894
  42 #define RCC_PLL4CFGR1           0x898
  43 #define RCC_PLL4CFGR2           0x89C
  44 #define RCC_APB1ENSETR          0xA00
  45 #define RCC_APB2ENSETR          0xA08
  46 #define RCC_APB3ENSETR          0xA10
  47 #define RCC_APB4ENSETR          0x200
  48 #define RCC_APB5ENSETR          0x208
  49 #define RCC_AHB2ENSETR          0xA18
  50 #define RCC_AHB3ENSETR          0xA20
  51 #define RCC_AHB4ENSETR          0xA28
  52 #define RCC_AHB5ENSETR          0x210
  53 #define RCC_AHB6ENSETR          0x218
  54 #define RCC_AHB6LPENSETR        0x318
  55 #define RCC_RCK12SELR           0x28
  56 #define RCC_RCK3SELR            0x820
  57 #define RCC_RCK4SELR            0x824
  58 #define RCC_MPCKSELR            0x20
  59 #define RCC_ASSCKSELR           0x24
  60 #define RCC_MSSCKSELR           0x48
  61 #define RCC_SPI6CKSELR          0xC4
  62 #define RCC_SDMMC12CKSELR       0x8F4
  63 #define RCC_SDMMC3CKSELR        0x8F8
  64 #define RCC_FMCCKSELR           0x904
  65 #define RCC_I2C46CKSELR         0xC0
  66 #define RCC_I2C12CKSELR         0x8C0
  67 #define RCC_I2C35CKSELR         0x8C4
  68 #define RCC_UART1CKSELR         0xC8
  69 #define RCC_QSPICKSELR          0x900
  70 #define RCC_ETHCKSELR           0x8FC
  71 #define RCC_RNG1CKSELR          0xCC
  72 #define RCC_RNG2CKSELR          0x920
  73 #define RCC_GPUCKSELR           0x938
  74 #define RCC_USBCKSELR           0x91C
  75 #define RCC_STGENCKSELR         0xD4
  76 #define RCC_SPDIFCKSELR         0x914
  77 #define RCC_SPI2S1CKSELR        0x8D8
  78 #define RCC_SPI2S23CKSELR       0x8DC
  79 #define RCC_SPI2S45CKSELR       0x8E0
  80 #define RCC_CECCKSELR           0x918
  81 #define RCC_LPTIM1CKSELR        0x934
  82 #define RCC_LPTIM23CKSELR       0x930
  83 #define RCC_LPTIM45CKSELR       0x92C
  84 #define RCC_UART24CKSELR        0x8E8
  85 #define RCC_UART35CKSELR        0x8EC
  86 #define RCC_UART6CKSELR         0x8E4
  87 #define RCC_UART78CKSELR        0x8F0
  88 #define RCC_FDCANCKSELR         0x90C
  89 #define RCC_SAI1CKSELR          0x8C8
  90 #define RCC_SAI2CKSELR          0x8CC
  91 #define RCC_SAI3CKSELR          0x8D0
  92 #define RCC_SAI4CKSELR          0x8D4
  93 #define RCC_ADCCKSELR           0x928
  94 #define RCC_MPCKDIVR            0x2C
  95 #define RCC_DSICKSELR           0x924
  96 #define RCC_CPERCKSELR          0xD0
  97 #define RCC_MCO1CFGR            0x800
  98 #define RCC_MCO2CFGR            0x804
  99 #define RCC_BDCR                0x140
 100 #define RCC_AXIDIVR             0x30
 101 #define RCC_MCUDIVR             0x830
 102 #define RCC_APB1DIVR            0x834
 103 #define RCC_APB2DIVR            0x838
 104 #define RCC_APB3DIVR            0x83C
 105 #define RCC_APB4DIVR            0x3C
 106 #define RCC_APB5DIVR            0x40
 107 #define RCC_TIMG1PRER           0x828
 108 #define RCC_TIMG2PRER           0x82C
 109 #define RCC_RTCDIVR             0x44
 110 #define RCC_DBGCFGR             0x80C
 111
 112 #define RCC_CLR 0x4
 113
 114 static const char * const ref12_parents[] = {
 115         "ck_hsi", "ck_hse"
 116 };
 117
 118 static const char * const ref3_parents[] = {
 119         "ck_hsi", "ck_hse", "ck_csi"
 120 };
 121
 122 static const char * const ref4_parents[] = {
 123         "ck_hsi", "ck_hse", "ck_csi"
 124 };
 125
 126 static const char * const cpu_src[] = {
 127         "ck_hsi", "ck_hse", "pll1_p"
 128 };
 129
 130 static const char * const axi_src[] = {
 131         "ck_hsi", "ck_hse", "pll2_p"
 132 };
 133
 134 static const char * const per_src[] = {
 135         "ck_hsi", "ck_csi", "ck_hse"
 136 };
 137
 138 static const char * const mcu_src[] = {
 139         "ck_hsi", "ck_hse", "ck_csi", "pll3_p"
 140 };
 141
 142 static const char * const sdmmc12_src[] = {
 143         "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
 144 };
 145
 146 static const char * const sdmmc3_src[] = {
 147         "ck_mcu", "pll3_r", "pll4_p", "ck_hsi"
 148 };
 149
 150 static const char * const fmc_src[] = {
 151         "ck_axi", "pll3_r", "pll4_p", "ck_per"
 152 };
 153
 154 static const char * const qspi_src[] = {
 155         "ck_axi", "pll3_r", "pll4_p", "ck_per"
 156 };
 157
 158 static const char * const eth_src[] = {
 159         "pll4_p", "pll3_q"
 160 };
 161
 162 static const struct clk_parent_data ethrx_src[] = {
 163         { .name = "ethck_k", .fw_name = "ETH_RX_CLK/ETH_REF_CLK" },
 164 };
 165
 166 static const char * const rng_src[] = {
 167         "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
 168 };
 169
 170 static const char * const usbphy_src[] = {
 171         "ck_hse", "pll4_r", "clk-hse-div2"
 172 };
 173
 174 static const char * const usbo_src[] = {
 175         "pll4_r", "ck_usbo_48m"
 176 };
 177
 178 static const char * const stgen_src[] = {
 179         "ck_hsi", "ck_hse"
 180 };
 181
 182 static const char * const spdif_src[] = {
 183         "pll4_p", "pll3_q", "ck_hsi"
 184 };
 185
 186 static const char * const spi123_src[] = {
 187         "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 188 };
 189
 190 static const char * const spi45_src[] = {
 191         "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 192 };
 193
 194 static const char * const spi6_src[] = {
 195         "pclk5", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "pll3_q"
 196 };
 197
 198 static const char * const cec_src[] = {
 199         "ck_lse", "ck_lsi", "ck_csi"
 200 };
 201
 202 static const char * const i2c12_src[] = {
 203         "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 204 };
 205
 206 static const char * const i2c35_src[] = {
 207         "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 208 };
 209
 210 static const char * const i2c46_src[] = {
 211         "pclk5", "pll3_q", "ck_hsi", "ck_csi"
 212 };
 213
 214 static const char * const lptim1_src[] = {
 215         "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 216 };
 217
 218 static const char * const lptim23_src[] = {
 219         "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
 220 };
 221
 222 static const char * const lptim45_src[] = {
 223         "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 224 };
 225
 226 static const char * const usart1_src[] = {
 227         "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 228 };
 229
 230 static const char * const usart234578_src[] = {
 231         "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 232 };
 233
 234 static const char * const usart6_src[] = {
 235         "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 236 };
 237
 238 static const char * const fdcan_src[] = {
 239         "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 240 };
 241
 242 static const char * const sai_src[] = {
 243         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 244 };
 245
 246 static const char * const sai2_src[] = {
 247         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 248 };
 249
 250 static const char * const adc12_src[] = {
 251         "pll4_r", "ck_per", "pll3_q"
 252 };
 253
 254 static const char * const dsi_src[] = {
 255         "ck_dsi_phy", "pll4_p"
 256 };
 257
 258 static const char * const rtc_src[] = {
 259         "off", "ck_lse", "ck_lsi", "ck_hse"
 260 };
 261
 262 static const char * const mco1_src[] = {
 263         "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
 264 };
 265
 266 static const char * const mco2_src[] = {
 267         "ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
 268 };
 269
 270 static const char * const ck_trace_src[] = {
 271         "ck_axi"
 272 };
 273
 274 static const struct clk_div_table axi_div_table[] = {
 275         { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
 276         { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
 277         { 0 },
 278 };
 279
 280 static const struct clk_div_table mcu_div_table[] = {
 281         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 282         { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
 283         { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
 284         { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
 285         { 0 },
 286 };
 287
 288 static const struct clk_div_table apb_div_table[] = {
 289         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 290         { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 291         { 0 },
 292 };
 293
 294 static const struct clk_div_table ck_trace_div_table[] = {
 295         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 296         { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 297         { 0 },
 298 };
 299
 300 #define MAX_MUX_CLK 2
 301
 302 struct stm32_mmux {
 303         u8 nbr_clk;
 304         struct clk_hw *hws[MAX_MUX_CLK];
 305 };
 306
 307 struct stm32_clk_mmux {
 308         struct clk_mux mux;
 309         struct stm32_mmux *mmux;
 310 };
 311
 312 struct stm32_mgate {
 313         u8 nbr_clk;
 314         u32 flag;
 315 };
 316
 317 struct stm32_clk_mgate {
 318         struct clk_gate gate;
 319         struct stm32_mgate *mgate;
 320         u32 mask;
 321 };
 322
 323 struct clock_config {
 324         u32 id;
 325         const char *name;
 326         const char *parent_name;
 327         const char * const *parent_names;
 328         const struct clk_parent_data *parent_data;
 329         int num_parents;
 330         unsigned long flags;
 331         void *cfg;
 332         struct clk_hw * (*func)(struct device *dev,
 333                                 struct clk_hw_onecell_data *clk_data,
 334                                 void __iomem *base, spinlock_t *lock,
 335                                 const struct clock_config *cfg);
 336 };
 337
 338 #define NO_ID ~0
 339
 340 struct gate_cfg {
 341         u32 reg_off;
 342         u8 bit_idx;
 343         u8 gate_flags;
 344 };
 345
 346 struct fixed_factor_cfg {
 347         unsigned int mult;
 348         unsigned int div;
 349 };
 350
 351 struct div_cfg {
 352         u32 reg_off;
 353         u8 shift;
 354         u8 width;
 355         u8 div_flags;
 356         const struct clk_div_table *table;
 357 };
 358
 359 struct mux_cfg {
 360         u32 reg_off;
 361         u8 shift;
 362         u8 width;
 363         u8 mux_flags;
 364         u32 *table;
 365 };
 366
 367 struct stm32_gate_cfg {
 368         struct gate_cfg         *gate;
 369         struct stm32_mgate      *mgate;
 370         const struct clk_ops    *ops;
 371 };
 372
 373 struct stm32_div_cfg {
 374         struct div_cfg          *div;
 375         const struct clk_ops    *ops;
 376 };
 377
 378 struct stm32_mux_cfg {
 379         struct mux_cfg          *mux;
 380         struct stm32_mmux       *mmux;
 381         const struct clk_ops    *ops;
 382 };
 383
 384 /* STM32 Composite clock */
 385 struct stm32_composite_cfg {
 386         const struct stm32_gate_cfg     *gate;
 387         const struct stm32_div_cfg      *div;
 388         const struct stm32_mux_cfg      *mux;
 389 };
 390
 391 static struct clk_hw *
 392 _clk_hw_register_gate(struct device *dev,
 393                       struct clk_hw_onecell_data *clk_data,
 394                       void __iomem *base, spinlock_t *lock,
 395                       const struct clock_config *cfg)
 396 {
 397         struct gate_cfg *gate_cfg = cfg->cfg;
 398
 399         return clk_hw_register_gate(dev,
 400                                     cfg->name,
 401                                     cfg->parent_name,
 402                                     cfg->flags,
 403                                     gate_cfg->reg_off + base,
 404                                     gate_cfg->bit_idx,
 405                                     gate_cfg->gate_flags,
 406                                     lock);
 407 }
 408
 409 static struct clk_hw *
 410 _clk_hw_register_fixed_factor(struct device *dev,
 411                               struct clk_hw_onecell_data *clk_data,
 412                               void __iomem *base, spinlock_t *lock,
 413                               const struct clock_config *cfg)
 414 {
 415         struct fixed_factor_cfg *ff_cfg = cfg->cfg;
 416
 417         return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
 418                                             cfg->flags, ff_cfg->mult,
 419                                             ff_cfg->div);
 420 }
 421
 422 static struct clk_hw *
 423 _clk_hw_register_divider_table(struct device *dev,
 424                                struct clk_hw_onecell_data *clk_data,
 425                                void __iomem *base, spinlock_t *lock,
 426                                const struct clock_config *cfg)
 427 {
 428         struct div_cfg *div_cfg = cfg->cfg;
 429
 430         return clk_hw_register_divider_table(dev,
 431                                              cfg->name,
 432                                              cfg->parent_name,
 433                                              cfg->flags,
 434                                              div_cfg->reg_off + base,
 435                                              div_cfg->shift,
 436                                              div_cfg->width,
 437                                              div_cfg->div_flags,
 438                                              div_cfg->table,
 439                                              lock);
 440 }
 441
 442 static struct clk_hw *
 443 _clk_hw_register_mux(struct device *dev,
 444                      struct clk_hw_onecell_data *clk_data,
 445                      void __iomem *base, spinlock_t *lock,
 446                      const struct clock_config *cfg)
 447 {
 448         struct mux_cfg *mux_cfg = cfg->cfg;
 449
 450         return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
 451                                    cfg->num_parents, cfg->flags,
 452                                    mux_cfg->reg_off + base, mux_cfg->shift,
 453                                    mux_cfg->width, mux_cfg->mux_flags, lock);
 454 }
 455
 456 /* MP1 Gate clock with set & clear registers */
 457
 458 static int mp1_gate_clk_enable(struct clk_hw *hw)
 459 {
 460         if (!clk_gate_ops.is_enabled(hw))
 461                 clk_gate_ops.enable(hw);
 462
 463         return 0;
 464 }
 465
 466 static void mp1_gate_clk_disable(struct clk_hw *hw)
 467 {
 468         struct clk_gate *gate = to_clk_gate(hw);
 469         unsigned long flags = 0;
 470
 471         if (clk_gate_ops.is_enabled(hw)) {
 472                 spin_lock_irqsave(gate->lock, flags);
 473                 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
 474                 spin_unlock_irqrestore(gate->lock, flags);
 475         }
 476 }
 477
 478 static const struct clk_ops mp1_gate_clk_ops = {
 479         .enable         = mp1_gate_clk_enable,
 480         .disable        = mp1_gate_clk_disable,
 481         .is_enabled     = clk_gate_is_enabled,
 482 };
 483
 484 static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
 485                                      const struct stm32_mux_cfg *cfg,
 486                                      spinlock_t *lock)
 487 {
 488         struct stm32_clk_mmux *mmux;
 489         struct clk_mux *mux;
 490         struct clk_hw *mux_hw;
 491
 492         if (cfg->mmux) {
 493                 mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL);
 494                 if (!mmux)
 495                         return ERR_PTR(-ENOMEM);
 496
 497                 mmux->mux.reg = cfg->mux->reg_off + base;
 498                 mmux->mux.shift = cfg->mux->shift;
 499                 mmux->mux.mask = (1 << cfg->mux->width) - 1;
 500                 mmux->mux.flags = cfg->mux->mux_flags;
 501                 mmux->mux.table = cfg->mux->table;
 502                 mmux->mux.lock = lock;
 503                 mmux->mmux = cfg->mmux;
 504                 mux_hw = &mmux->mux.hw;
 505                 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
 506
 507         } else {
 508                 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 509                 if (!mux)
 510                         return ERR_PTR(-ENOMEM);
 511
 512                 mux->reg = cfg->mux->reg_off + base;
 513                 mux->shift = cfg->mux->shift;
 514                 mux->mask = (1 << cfg->mux->width) - 1;
 515                 mux->flags = cfg->mux->mux_flags;
 516                 mux->table = cfg->mux->table;
 517                 mux->lock = lock;
 518                 mux_hw = &mux->hw;
 519         }
 520
 521         return mux_hw;
 522 }
 523
 524 static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base,
 525                                      const struct stm32_div_cfg *cfg,
 526                                      spinlock_t *lock)
 527 {
 528         struct clk_divider *div;
 529
 530         div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 531
 532         if (!div)
 533                 return ERR_PTR(-ENOMEM);
 534
 535         div->reg = cfg->div->reg_off + base;
 536         div->shift = cfg->div->shift;
 537         div->width = cfg->div->width;
 538         div->flags = cfg->div->div_flags;
 539         div->table = cfg->div->table;
 540         div->lock = lock;
 541
 542         return &div->hw;
 543 }
 544
 545 static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base,
 546                                       const struct stm32_gate_cfg *cfg,
 547                                       spinlock_t *lock)
 548 {
 549         struct stm32_clk_mgate *mgate;
 550         struct clk_gate *gate;
 551         struct clk_hw *gate_hw;
 552
 553         if (cfg->mgate) {
 554                 mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL);
 555                 if (!mgate)
 556                         return ERR_PTR(-ENOMEM);
 557
 558                 mgate->gate.reg = cfg->gate->reg_off + base;
 559                 mgate->gate.bit_idx = cfg->gate->bit_idx;
 560                 mgate->gate.flags = cfg->gate->gate_flags;
 561                 mgate->gate.lock = lock;
 562                 mgate->mask = BIT(cfg->mgate->nbr_clk++);
 563
 564                 mgate->mgate = cfg->mgate;
 565
 566                 gate_hw = &mgate->gate.hw;
 567
 568         } else {
 569                 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
 570                 if (!gate)
 571                         return ERR_PTR(-ENOMEM);
 572
 573                 gate->reg = cfg->gate->reg_off + base;
 574                 gate->bit_idx = cfg->gate->bit_idx;
 575                 gate->flags = cfg->gate->gate_flags;
 576                 gate->lock = lock;
 577
 578                 gate_hw = &gate->hw;
 579         }
 580
 581         return gate_hw;
 582 }
 583
 584 static struct clk_hw *
 585 clk_stm32_register_gate_ops(struct device *dev,
 586                             const char *name,
 587                             const char *parent_name,
 588                             const struct clk_parent_data *parent_data,
 589                             unsigned long flags,
 590                             void __iomem *base,
 591                             const struct stm32_gate_cfg *cfg,
 592                             spinlock_t *lock)
 593 {
 594         struct clk_init_data init = { NULL };
 595         struct clk_hw *hw;
 596         int ret;
 597
 598         init.name = name;
 599         if (parent_name)
 600                 init.parent_names = &parent_name;
 601         if (parent_data)
 602                 init.parent_data = parent_data;
 603         init.num_parents = 1;
 604         init.flags = flags;
 605
 606         init.ops = &clk_gate_ops;
 607
 608         if (cfg->ops)
 609                 init.ops = cfg->ops;
 610
 611         hw = _get_stm32_gate(dev, base, cfg, lock);
 612         if (IS_ERR(hw))
 613                 return ERR_PTR(-ENOMEM);
 614
 615         hw->init = &init;
 616
 617         ret = clk_hw_register(dev, hw);
 618         if (ret)
 619                 hw = ERR_PTR(ret);
 620
 621         return hw;
 622 }
 623
 624 static struct clk_hw *
 625 clk_stm32_register_composite(struct device *dev,
 626                              const char *name, const char * const *parent_names,
 627                              const struct clk_parent_data *parent_data,
 628                              int num_parents, void __iomem *base,
 629                              const struct stm32_composite_cfg *cfg,
 630                              unsigned long flags, spinlock_t *lock)
 631 {
 632         const struct clk_ops *mux_ops, *div_ops, *gate_ops;
 633         struct clk_hw *mux_hw, *div_hw, *gate_hw;
 634
 635         mux_hw = NULL;
 636         div_hw = NULL;
 637         gate_hw = NULL;
 638         mux_ops = NULL;
 639         div_ops = NULL;
 640         gate_ops = NULL;
 641
 642         if (cfg->mux) {
 643                 mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
 644
 645                 if (!IS_ERR(mux_hw)) {
 646                         mux_ops = &clk_mux_ops;
 647
 648                         if (cfg->mux->ops)
 649                                 mux_ops = cfg->mux->ops;
 650                 }
 651         }
 652
 653         if (cfg->div) {
 654                 div_hw = _get_stm32_div(dev, base, cfg->div, lock);
 655
 656                 if (!IS_ERR(div_hw)) {
 657                         div_ops = &clk_divider_ops;
 658
 659                         if (cfg->div->ops)
 660                                 div_ops = cfg->div->ops;
 661                 }
 662         }
 663
 664         if (cfg->gate) {
 665                 gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
 666
 667                 if (!IS_ERR(gate_hw)) {
 668                         gate_ops = &clk_gate_ops;
 669
 670                         if (cfg->gate->ops)
 671                                 gate_ops = cfg->gate->ops;
 672                 }
 673         }
 674
 675         return clk_hw_register_composite(dev, name, parent_names, num_parents,
 676                                        mux_hw, mux_ops, div_hw, div_ops,
 677                                        gate_hw, gate_ops, flags);
 678 }
 679
 680 #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate)
 681
 682 static int mp1_mgate_clk_enable(struct clk_hw *hw)
 683 {
 684         struct clk_gate *gate = to_clk_gate(hw);
 685         struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
 686
 687         clk_mgate->mgate->flag |= clk_mgate->mask;
 688
 689         mp1_gate_clk_enable(hw);
 690
 691         return  0;
 692 }
 693
 694 static void mp1_mgate_clk_disable(struct clk_hw *hw)
 695 {
 696         struct clk_gate *gate = to_clk_gate(hw);
 697         struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
 698
 699         clk_mgate->mgate->flag &= ~clk_mgate->mask;
 700
 701         if (clk_mgate->mgate->flag == 0)
 702                 mp1_gate_clk_disable(hw);
 703 }
 704
 705 static const struct clk_ops mp1_mgate_clk_ops = {
 706         .enable         = mp1_mgate_clk_enable,
 707         .disable        = mp1_mgate_clk_disable,
 708         .is_enabled     = clk_gate_is_enabled,
 709
 710 };
 711
 712 #define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux)
 713
 714 static u8 clk_mmux_get_parent(struct clk_hw *hw)
 715 {
 716         return clk_mux_ops.get_parent(hw);
 717 }
 718
 719 static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
 720 {
 721         struct clk_mux *mux = to_clk_mux(hw);
 722         struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux);
 723         struct clk_hw *hwp;
 724         int ret, n;
 725
 726         ret = clk_mux_ops.set_parent(hw, index);
 727         if (ret)
 728                 return ret;
 729
 730         hwp = clk_hw_get_parent(hw);
 731
 732         for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)
 733                 if (clk_mmux->mmux->hws[n] != hw)
 734                         clk_hw_reparent(clk_mmux->mmux->hws[n], hwp);
 735
 736         return 0;
 737 }
 738
 739 static const struct clk_ops clk_mmux_ops = {
 740         .get_parent     = clk_mmux_get_parent,
 741         .set_parent     = clk_mmux_set_parent,
 742         .determine_rate = __clk_mux_determine_rate,
 743 };
 744
 745 /* STM32 PLL */
 746 struct stm32_pll_obj {
 747         /* lock pll enable/disable registers */
 748         spinlock_t *lock;
 749         void __iomem *reg;
 750         struct clk_hw hw;
 751         struct clk_mux mux;
 752 };
 753
 754 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
 755
 756 #define PLL_ON          BIT(0)
 757 #define PLL_RDY         BIT(1)
 758 #define DIVN_MASK       0x1FF
 759 #define DIVM_MASK       0x3F
 760 #define DIVM_SHIFT      16
 761 #define DIVN_SHIFT      0
 762 #define FRAC_OFFSET     0xC
 763 #define FRAC_MASK       0x1FFF
 764 #define FRAC_SHIFT      3
 765 #define FRACLE          BIT(16)
 766 #define PLL_MUX_SHIFT   0
 767 #define PLL_MUX_MASK    3
 768
 769 static int __pll_is_enabled(struct clk_hw *hw)
 770 {
 771         struct stm32_pll_obj *clk_elem = to_pll(hw);
 772
 773         return readl_relaxed(clk_elem->reg) & PLL_ON;
 774 }
 775
 776 #define TIMEOUT 5
 777
 778 static int pll_enable(struct clk_hw *hw)
 779 {
 780         struct stm32_pll_obj *clk_elem = to_pll(hw);
 781         u32 reg;
 782         unsigned long flags = 0;
 783         unsigned int timeout = TIMEOUT;
 784         int bit_status = 0;
 785
 786         spin_lock_irqsave(clk_elem->lock, flags);
 787
 788         if (__pll_is_enabled(hw))
 789                 goto unlock;
 790
 791         reg = readl_relaxed(clk_elem->reg);
 792         reg |= PLL_ON;
 793         writel_relaxed(reg, clk_elem->reg);
 794
 795         /* We can't use readl_poll_timeout() because we can be blocked if
 796          * someone enables this clock before clocksource changes.
 797          * Only jiffies counter is available. Jiffies are incremented by
 798          * interruptions and enable op does not allow to be interrupted.
 799          */
 800         do {
 801                 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY);
 802
 803                 if (bit_status)
 804                         udelay(120);
 805
 806         } while (bit_status && --timeout);
 807
 808 unlock:
 809         spin_unlock_irqrestore(clk_elem->lock, flags);
 810
 811         return bit_status;
 812 }
 813
 814 static void pll_disable(struct clk_hw *hw)
 815 {
 816         struct stm32_pll_obj *clk_elem = to_pll(hw);
 817         u32 reg;
 818         unsigned long flags = 0;
 819
 820         spin_lock_irqsave(clk_elem->lock, flags);
 821
 822         reg = readl_relaxed(clk_elem->reg);
 823         reg &= ~PLL_ON;
 824         writel_relaxed(reg, clk_elem->reg);
 825
 826         spin_unlock_irqrestore(clk_elem->lock, flags);
 827 }
 828
 829 static u32 pll_frac_val(struct clk_hw *hw)
 830 {
 831         struct stm32_pll_obj *clk_elem = to_pll(hw);
 832         u32 reg, frac = 0;
 833
 834         reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET);
 835         if (reg & FRACLE)
 836                 frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
 837
 838         return frac;
 839 }
 840
 841 static unsigned long pll_recalc_rate(struct clk_hw *hw,
 842                                      unsigned long parent_rate)
 843 {
 844         struct stm32_pll_obj *clk_elem = to_pll(hw);
 845         u32 reg;
 846         u32 frac, divm, divn;
 847         u64 rate, rate_frac = 0;
 848
 849         reg = readl_relaxed(clk_elem->reg + 4);
 850
 851         divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1;
 852         divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1;
 853         rate = (u64)parent_rate * divn;
 854
 855         do_div(rate, divm);
 856
 857         frac = pll_frac_val(hw);
 858         if (frac) {
 859                 rate_frac = (u64)parent_rate * (u64)frac;
 860                 do_div(rate_frac, (divm * 8192));
 861         }
 862
 863         return rate + rate_frac;
 864 }
 865
 866 static int pll_is_enabled(struct clk_hw *hw)
 867 {
 868         struct stm32_pll_obj *clk_elem = to_pll(hw);
 869         unsigned long flags = 0;
 870         int ret;
 871
 872         spin_lock_irqsave(clk_elem->lock, flags);
 873         ret = __pll_is_enabled(hw);
 874         spin_unlock_irqrestore(clk_elem->lock, flags);
 875
 876         return ret;
 877 }
 878
 879 static u8 pll_get_parent(struct clk_hw *hw)
 880 {
 881         struct stm32_pll_obj *clk_elem = to_pll(hw);
 882         struct clk_hw *mux_hw = &clk_elem->mux.hw;
 883
 884         __clk_hw_set_clk(mux_hw, hw);
 885
 886         return clk_mux_ops.get_parent(mux_hw);
 887 }
 888
 889 static const struct clk_ops pll_ops = {
 890         .enable         = pll_enable,
 891         .disable        = pll_disable,
 892         .recalc_rate    = pll_recalc_rate,
 893         .is_enabled     = pll_is_enabled,
 894         .get_parent     = pll_get_parent,
 895 };
 896
 897 static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
 898                                        const char * const *parent_names,
 899                                        int num_parents,
 900                                        void __iomem *reg,
 901                                        void __iomem *mux_reg,
 902                                        unsigned long flags,
 903                                        spinlock_t *lock)
 904 {
 905         struct stm32_pll_obj *element;
 906         struct clk_init_data init;
 907         struct clk_hw *hw;
 908         int err;
 909
 910         element = devm_kzalloc(dev, sizeof(*element), GFP_KERNEL);
 911         if (!element)
 912                 return ERR_PTR(-ENOMEM);
 913
 914         init.name = name;
 915         init.ops = &pll_ops;
 916         init.flags = flags;
 917         init.parent_names = parent_names;
 918         init.num_parents = num_parents;
 919
 920         element->mux.lock = lock;
 921         element->mux.reg =  mux_reg;
 922         element->mux.shift = PLL_MUX_SHIFT;
 923         element->mux.mask =  PLL_MUX_MASK;
 924         element->mux.flags =  CLK_MUX_READ_ONLY;
 925         element->mux.reg =  mux_reg;
 926
 927         element->hw.init = &init;
 928         element->reg = reg;
 929         element->lock = lock;
 930
 931         hw = &element->hw;
 932         err = clk_hw_register(dev, hw);
 933
 934         if (err)
 935                 return ERR_PTR(err);
 936
 937         return hw;
 938 }
 939
 940 /* Kernel Timer */
 941 struct timer_cker {
 942         /* lock the kernel output divider register */
 943         spinlock_t *lock;
 944         void __iomem *apbdiv;
 945         void __iomem *timpre;
 946         struct clk_hw hw;
 947 };
 948
 949 #define to_timer_cker(_hw) container_of(_hw, struct timer_cker, hw)
 950
 951 #define APB_DIV_MASK 0x07
 952 #define TIM_PRE_MASK 0x01
 953
 954 static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
 955                                 unsigned long parent_rate)
 956 {
 957         struct timer_cker *tim_ker = to_timer_cker(hw);
 958         u32 prescaler;
 959         unsigned int mult = 0;
 960
 961         prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
 962         if (prescaler < 2)
 963                 return 1;
 964
 965         mult = 2;
 966
 967         if (rate / parent_rate >= 4)
 968                 mult = 4;
 969
 970         return mult;
 971 }
 972
 973 static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate,
 974                                  unsigned long *parent_rate)
 975 {
 976         unsigned long factor = __bestmult(hw, rate, *parent_rate);
 977
 978         return *parent_rate * factor;
 979 }
 980
 981 static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate,
 982                               unsigned long parent_rate)
 983 {
 984         struct timer_cker *tim_ker = to_timer_cker(hw);
 985         unsigned long flags = 0;
 986         unsigned long factor = __bestmult(hw, rate, parent_rate);
 987         int ret = 0;
 988
 989         spin_lock_irqsave(tim_ker->lock, flags);
 990
 991         switch (factor) {
 992         case 1:
 993                 break;
 994         case 2:
 995                 writel_relaxed(0, tim_ker->timpre);
 996                 break;
 997         case 4:
 998                 writel_relaxed(1, tim_ker->timpre);
 999                 break;
1000         default:
1001                 ret = -EINVAL;
1002         }
1003         spin_unlock_irqrestore(tim_ker->lock, flags);
1004
1005         return ret;
1006 }
1007
1008 static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
1009                                            unsigned long parent_rate)
1010 {
1011         struct timer_cker *tim_ker = to_timer_cker(hw);
1012         u32 prescaler, timpre;
1013         u32 mul;
1014
1015         prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
1016
1017         timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK;
1018
1019         if (!prescaler)
1020                 return parent_rate;
1021
1022         mul = (timpre + 1) * 2;
1023
1024         return parent_rate * mul;
1025 }
1026
1027 static const struct clk_ops timer_ker_ops = {
1028         .recalc_rate    = timer_ker_recalc_rate,
1029         .round_rate     = timer_ker_round_rate,
1030         .set_rate       = timer_ker_set_rate,
1031
1032 };
1033
1034 static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
1035                                          const char *parent_name,
1036                                          unsigned long flags,
1037                                          void __iomem *apbdiv,
1038                                          void __iomem *timpre,
1039                                          spinlock_t *lock)
1040 {
1041         struct timer_cker *tim_ker;
1042         struct clk_init_data init;
1043         struct clk_hw *hw;
1044         int err;
1045
1046         tim_ker = devm_kzalloc(dev, sizeof(*tim_ker), GFP_KERNEL);
1047         if (!tim_ker)
1048                 return ERR_PTR(-ENOMEM);
1049
1050         init.name = name;
1051         init.ops = &timer_ker_ops;
1052         init.flags = flags;
1053         init.parent_names = &parent_name;
1054         init.num_parents = 1;
1055
1056         tim_ker->hw.init = &init;
1057         tim_ker->lock = lock;
1058         tim_ker->apbdiv = apbdiv;
1059         tim_ker->timpre = timpre;
1060
1061         hw = &tim_ker->hw;
1062         err = clk_hw_register(dev, hw);
1063
1064         if (err)
1065                 return ERR_PTR(err);
1066
1067         return hw;
1068 }
1069
1070 /* The divider of RTC clock concerns only ck_hse clock */
1071 #define HSE_RTC 3
1072
1073 static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
1074                                                  unsigned long parent_rate)
1075 {
1076         if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
1077                 return clk_divider_ops.recalc_rate(hw, parent_rate);
1078
1079         return parent_rate;
1080 }
1081
1082 static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
1083                                     unsigned long parent_rate)
1084 {
1085         if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
1086                 return clk_divider_ops.set_rate(hw, rate, parent_rate);
1087
1088         return parent_rate;
1089 }
1090
1091 static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
1092 {
1093         if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC))
1094                 return clk_divider_ops.determine_rate(hw, req);
1095
1096         req->rate = req->best_parent_rate;
1097
1098         return 0;
1099 }
1100
1101 static const struct clk_ops rtc_div_clk_ops = {
1102         .recalc_rate    = clk_divider_rtc_recalc_rate,
1103         .set_rate       = clk_divider_rtc_set_rate,
1104         .determine_rate = clk_divider_rtc_determine_rate
1105 };
1106
1107 struct stm32_pll_cfg {
1108         u32 offset;
1109         u32 muxoff;
1110 };
1111
1112 static struct clk_hw *_clk_register_pll(struct device *dev,
1113                                         struct clk_hw_onecell_data *clk_data,
1114                                         void __iomem *base, spinlock_t *lock,
1115                                         const struct clock_config *cfg)
1116 {
1117         struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1118
1119         return clk_register_pll(dev, cfg->name, cfg->parent_names,
1120                                 cfg->num_parents,
1121                                 base + stm_pll_cfg->offset,
1122                                 base + stm_pll_cfg->muxoff,
1123                                 cfg->flags, lock);
1124 }
1125
1126 struct stm32_cktim_cfg {
1127         u32 offset_apbdiv;
1128         u32 offset_timpre;
1129 };
1130
1131 static struct clk_hw *_clk_register_cktim(struct device *dev,
1132                                           struct clk_hw_onecell_data *clk_data,
1133                                           void __iomem *base, spinlock_t *lock,
1134                                           const struct clock_config *cfg)
1135 {
1136         struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
1137
1138         return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
1139                                   cktim_cfg->offset_apbdiv + base,
1140                                   cktim_cfg->offset_timpre + base, lock);
1141 }
1142
1143 static struct clk_hw *
1144 _clk_stm32_register_gate(struct device *dev,
1145                          struct clk_hw_onecell_data *clk_data,
1146                          void __iomem *base, spinlock_t *lock,
1147                          const struct clock_config *cfg)
1148 {
1149         return clk_stm32_register_gate_ops(dev,
1150                                     cfg->name,
1151                                     cfg->parent_name,
1152                                     cfg->parent_data,
1153                                     cfg->flags,
1154                                     base,
1155                                     cfg->cfg,
1156                                     lock);
1157 }
1158
1159 static struct clk_hw *
1160 _clk_stm32_register_composite(struct device *dev,
1161                               struct clk_hw_onecell_data *clk_data,
1162                               void __iomem *base, spinlock_t *lock,
1163                               const struct clock_config *cfg)
1164 {
1165         return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
1166                                             cfg->parent_data, cfg->num_parents,
1167                                             base, cfg->cfg, cfg->flags, lock);
1168 }
1169
1170 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1171 {\
1172         .id             = _id,\
1173         .name           = _name,\
1174         .parent_name    = _parent,\
1175         .flags          = _flags,\
1176         .cfg            =  &(struct gate_cfg) {\
1177                 .reg_off        = _offset,\
1178                 .bit_idx        = _bit_idx,\
1179                 .gate_flags     = _gate_flags,\
1180         },\
1181         .func           = _clk_hw_register_gate,\
1182 }
1183
1184 #define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
1185 {\
1186         .id             = _id,\
1187         .name           = _name,\
1188         .parent_name    = _parent,\
1189         .flags          = _flags,\
1190         .cfg            =  &(struct fixed_factor_cfg) {\
1191                 .mult = _mult,\
1192                 .div = _div,\
1193         },\
1194         .func           = _clk_hw_register_fixed_factor,\
1195 }
1196
1197 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1198                   _div_flags, _div_table)\
1199 {\
1200         .id             = _id,\
1201         .name           = _name,\
1202         .parent_name    = _parent,\
1203         .flags          = _flags,\
1204         .cfg            =  &(struct div_cfg) {\
1205                 .reg_off        = _offset,\
1206                 .shift          = _shift,\
1207                 .width          = _width,\
1208                 .div_flags      = _div_flags,\
1209                 .table          = _div_table,\
1210         },\
1211         .func           = _clk_hw_register_divider_table,\
1212 }
1213
1214 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
1215         DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1216                   _div_flags, NULL)
1217
1218 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
1219 {\
1220         .id             = _id,\
1221         .name           = _name,\
1222         .parent_names   = _parents,\
1223         .num_parents    = ARRAY_SIZE(_parents),\
1224         .flags          = _flags,\
1225         .cfg            =  &(struct mux_cfg) {\
1226                 .reg_off        = _offset,\
1227                 .shift          = _shift,\
1228                 .width          = _width,\
1229                 .mux_flags      = _mux_flags,\
1230         },\
1231         .func           = _clk_hw_register_mux,\
1232 }
1233
1234 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
1235 {\
1236         .id             = _id,\
1237         .name           = _name,\
1238         .parent_names   = _parents,\
1239         .num_parents    = ARRAY_SIZE(_parents),\
1240         .flags          = CLK_IGNORE_UNUSED | (_flags),\
1241         .cfg            =  &(struct stm32_pll_cfg) {\
1242                 .offset = _offset_p,\
1243                 .muxoff = _offset_mux,\
1244         },\
1245         .func           = _clk_register_pll,\
1246 }
1247
1248 #define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\
1249 {\
1250         .id             = NO_ID,\
1251         .name           = _name,\
1252         .parent_name    = _parent,\
1253         .flags          = _flags,\
1254         .cfg            =  &(struct stm32_cktim_cfg) {\
1255                 .offset_apbdiv = _offset_apbdiv,\
1256                 .offset_timpre = _offset_timpre,\
1257         },\
1258         .func           = _clk_register_cktim,\
1259 }
1260
1261 #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
1262                   GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
1263                            _offset_set, _bit_idx, 0)
1264
1265 /* STM32 GATE */
1266 #define STM32_GATE(_id, _name, _parent, _flags, _gate)\
1267 {\
1268         .id             = _id,\
1269         .name           = _name,\
1270         .parent_name    = _parent,\
1271         .flags          = _flags,\
1272         .cfg            = (struct stm32_gate_cfg *) {_gate},\
1273         .func           = _clk_stm32_register_gate,\
1274 }
1275
1276 #define STM32_GATE_PDATA(_id, _name, _parent, _flags, _gate)\
1277 {\
1278         .id             = _id,\
1279         .name           = _name,\
1280         .parent_data    = _parent,\
1281         .flags          = _flags,\
1282         .cfg            = (struct stm32_gate_cfg *) {_gate},\
1283         .func           = _clk_stm32_register_gate,\
1284 }
1285
1286 #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\
1287         (&(struct stm32_gate_cfg) {\
1288                 &(struct gate_cfg) {\
1289                         .reg_off        = _gate_offset,\
1290                         .bit_idx        = _gate_bit_idx,\
1291                         .gate_flags     = _gate_flags,\
1292                 },\
1293                 .mgate          = _mgate,\
1294                 .ops            = _ops,\
1295         })
1296
1297 #define _STM32_MGATE(_mgate)\
1298         (&per_gate_cfg[_mgate])
1299
1300 #define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
1301         _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1302                     NULL, NULL)\
1303
1304 #define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
1305         _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1306                     NULL, &mp1_gate_clk_ops)\
1307
1308 #define _MGATE_MP1(_mgate)\
1309         .gate = &per_gate_cfg[_mgate]
1310
1311 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1312         STM32_GATE(_id, _name, _parent, _flags,\
1313                    _GATE_MP1(_offset, _bit_idx, _gate_flags))
1314
1315 #define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
1316         STM32_GATE(_id, _name, _parent, _flags,\
1317                    _STM32_MGATE(_mgate))
1318
1319 #define MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate)\
1320         STM32_GATE_PDATA(_id, _name, _parent, _flags,\
1321                    _STM32_MGATE(_mgate))
1322
1323 #define _STM32_DIV(_div_offset, _div_shift, _div_width,\
1324                    _div_flags, _div_table, _ops)\
1325         .div = &(struct stm32_div_cfg) {\
1326                 &(struct div_cfg) {\
1327                         .reg_off        = _div_offset,\
1328                         .shift          = _div_shift,\
1329                         .width          = _div_width,\
1330                         .div_flags      = _div_flags,\
1331                         .table          = _div_table,\
1332                 },\
1333                 .ops            = _ops,\
1334         }
1335
1336 #define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1337         _STM32_DIV(_div_offset, _div_shift, _div_width,\
1338                    _div_flags, _div_table, NULL)\
1339
1340 #define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1341         _STM32_DIV(_div_offset, _div_shift, _div_width,\
1342                    _div_flags, _div_table, &rtc_div_clk_ops)
1343
1344 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
1345         .mux = &(struct stm32_mux_cfg) {\
1346                 &(struct mux_cfg) {\
1347                         .reg_off        = _offset,\
1348                         .shift          = _shift,\
1349                         .width          = _width,\
1350                         .mux_flags      = _mux_flags,\
1351                         .table          = NULL,\
1352                 },\
1353                 .mmux           = _mmux,\
1354                 .ops            = _ops,\
1355         }
1356
1357 #define _MUX(_offset, _shift, _width, _mux_flags)\
1358         _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
1359
1360 #define _MMUX(_mmux) .mux = &ker_mux_cfg[_mmux]
1361
1362 #define PARENT(_parent) ((const char *[]) { _parent})
1363
1364 #define _NO_MUX .mux = NULL
1365 #define _NO_DIV .div = NULL
1366 #define _NO_GATE .gate = NULL
1367
1368 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
1369 {\
1370         .id             = _id,\
1371         .name           = _name,\
1372         .parent_names   = _parents,\
1373         .num_parents    = ARRAY_SIZE(_parents),\
1374         .flags          = _flags,\
1375         .cfg            = &(struct stm32_composite_cfg) {\
1376                 _gate,\
1377                 _mux,\
1378                 _div,\
1379         },\
1380         .func           = _clk_stm32_register_composite,\
1381 }
1382
1383 #define PCLK(_id, _name, _parent, _flags, _mgate)\
1384         MGATE_MP1(_id, _name, _parent, _flags, _mgate)
1385
1386 #define PCLK_PDATA(_id, _name, _parent, _flags, _mgate)\
1387         MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate)
1388
1389 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
1390              COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
1391                        CLK_SET_RATE_NO_REPARENT | _flags,\
1392                        _MGATE_MP1(_mgate),\
1393                        _MMUX(_mmux),\
1394                        _NO_DIV)
1395
1396 enum {
1397         G_SAI1,
1398         G_SAI2,
1399         G_SAI3,
1400         G_SAI4,
1401         G_SPI1,
1402         G_SPI2,
1403         G_SPI3,
1404         G_SPI4,
1405         G_SPI5,
1406         G_SPI6,
1407         G_SPDIF,
1408         G_I2C1,
1409         G_I2C2,
1410         G_I2C3,
1411         G_I2C4,
1412         G_I2C5,
1413         G_I2C6,
1414         G_USART2,
1415         G_UART4,
1416         G_USART3,
1417         G_UART5,
1418         G_USART1,
1419         G_USART6,
1420         G_UART7,
1421         G_UART8,
1422         G_LPTIM1,
1423         G_LPTIM2,
1424         G_LPTIM3,
1425         G_LPTIM4,
1426         G_LPTIM5,
1427         G_LTDC,
1428         G_DSI,
1429         G_QSPI,
1430         G_FMC,
1431         G_SDMMC1,
1432         G_SDMMC2,
1433         G_SDMMC3,
1434         G_USBO,
1435         G_USBPHY,
1436         G_RNG1,
1437         G_RNG2,
1438         G_FDCAN,
1439         G_DAC12,
1440         G_CEC,
1441         G_ADC12,
1442         G_GPU,
1443         G_STGEN,
1444         G_DFSDM,
1445         G_ADFSDM,
1446         G_TIM2,
1447         G_TIM3,
1448         G_TIM4,
1449         G_TIM5,
1450         G_TIM6,
1451         G_TIM7,
1452         G_TIM12,
1453         G_TIM13,
1454         G_TIM14,
1455         G_MDIO,
1456         G_TIM1,
1457         G_TIM8,
1458         G_TIM15,
1459         G_TIM16,
1460         G_TIM17,
1461         G_SYSCFG,
1462         G_VREF,
1463         G_TMPSENS,
1464         G_PMBCTRL,
1465         G_HDP,
1466         G_IWDG2,
1467         G_STGENRO,
1468         G_DMA1,
1469         G_DMA2,
1470         G_DMAMUX,
1471         G_DCMI,
1472         G_CRYP2,
1473         G_HASH2,
1474         G_CRC2,
1475         G_HSEM,
1476         G_IPCC,
1477         G_GPIOA,
1478         G_GPIOB,
1479         G_GPIOC,
1480         G_GPIOD,
1481         G_GPIOE,
1482         G_GPIOF,
1483         G_GPIOG,
1484         G_GPIOH,
1485         G_GPIOI,
1486         G_GPIOJ,
1487         G_GPIOK,
1488         G_MDMA,
1489         G_ETHCK,
1490         G_ETHTX,
1491         G_ETHRX,
1492         G_ETHMAC,
1493         G_CRC1,
1494         G_USBH,
1495         G_ETHSTP,
1496         G_RTCAPB,
1497         G_TZC1,
1498         G_TZC2,
1499         G_TZPC,
1500         G_IWDG1,
1501         G_BSEC,
1502         G_GPIOZ,
1503         G_CRYP1,
1504         G_HASH1,
1505         G_BKPSRAM,
1506         G_DDRPERFM,
1507
1508         G_LAST
1509 };
1510
1511 static struct stm32_mgate mp1_mgate[G_LAST];
1512
1513 #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1514                _mgate, _ops)\
1515         [_id] = {\
1516                 &(struct gate_cfg) {\
1517                         .reg_off        = _gate_offset,\
1518                         .bit_idx        = _gate_bit_idx,\
1519                         .gate_flags     = _gate_flags,\
1520                 },\
1521                 .mgate          = _mgate,\
1522                 .ops            = _ops,\
1523         }
1524
1525 #define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1526         _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1527                NULL, &mp1_gate_clk_ops)
1528
1529 #define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1530         _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1531                &mp1_mgate[_id], &mp1_mgate_clk_ops)
1532
1533 /* Peripheral gates */
1534 static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1535         /* Multi gates */
1536         K_GATE(G_MDIO,          RCC_APB1ENSETR, 31, 0),
1537         K_MGATE(G_DAC12,        RCC_APB1ENSETR, 29, 0),
1538         K_MGATE(G_CEC,          RCC_APB1ENSETR, 27, 0),
1539         K_MGATE(G_SPDIF,        RCC_APB1ENSETR, 26, 0),
1540         K_MGATE(G_I2C5,         RCC_APB1ENSETR, 24, 0),
1541         K_MGATE(G_I2C3,         RCC_APB1ENSETR, 23, 0),
1542         K_MGATE(G_I2C2,         RCC_APB1ENSETR, 22, 0),
1543         K_MGATE(G_I2C1,         RCC_APB1ENSETR, 21, 0),
1544         K_MGATE(G_UART8,        RCC_APB1ENSETR, 19, 0),
1545         K_MGATE(G_UART7,        RCC_APB1ENSETR, 18, 0),
1546         K_MGATE(G_UART5,        RCC_APB1ENSETR, 17, 0),
1547         K_MGATE(G_UART4,        RCC_APB1ENSETR, 16, 0),
1548         K_MGATE(G_USART3,       RCC_APB1ENSETR, 15, 0),
1549         K_MGATE(G_USART2,       RCC_APB1ENSETR, 14, 0),
1550         K_MGATE(G_SPI3,         RCC_APB1ENSETR, 12, 0),
1551         K_MGATE(G_SPI2,         RCC_APB1ENSETR, 11, 0),
1552         K_MGATE(G_LPTIM1,       RCC_APB1ENSETR, 9, 0),
1553         K_GATE(G_TIM14,         RCC_APB1ENSETR, 8, 0),
1554         K_GATE(G_TIM13,         RCC_APB1ENSETR, 7, 0),
1555         K_GATE(G_TIM12,         RCC_APB1ENSETR, 6, 0),
1556         K_GATE(G_TIM7,          RCC_APB1ENSETR, 5, 0),
1557         K_GATE(G_TIM6,          RCC_APB1ENSETR, 4, 0),
1558         K_GATE(G_TIM5,          RCC_APB1ENSETR, 3, 0),
1559         K_GATE(G_TIM4,          RCC_APB1ENSETR, 2, 0),
1560         K_GATE(G_TIM3,          RCC_APB1ENSETR, 1, 0),
1561         K_GATE(G_TIM2,          RCC_APB1ENSETR, 0, 0),
1562
1563         K_MGATE(G_FDCAN,        RCC_APB2ENSETR, 24, 0),
1564         K_GATE(G_ADFSDM,        RCC_APB2ENSETR, 21, 0),
1565         K_GATE(G_DFSDM,         RCC_APB2ENSETR, 20, 0),
1566         K_MGATE(G_SAI3,         RCC_APB2ENSETR, 18, 0),
1567         K_MGATE(G_SAI2,         RCC_APB2ENSETR, 17, 0),
1568         K_MGATE(G_SAI1,         RCC_APB2ENSETR, 16, 0),
1569         K_MGATE(G_USART6,       RCC_APB2ENSETR, 13, 0),
1570         K_MGATE(G_SPI5,         RCC_APB2ENSETR, 10, 0),
1571         K_MGATE(G_SPI4,         RCC_APB2ENSETR, 9, 0),
1572         K_MGATE(G_SPI1,         RCC_APB2ENSETR, 8, 0),
1573         K_GATE(G_TIM17,         RCC_APB2ENSETR, 4, 0),
1574         K_GATE(G_TIM16,         RCC_APB2ENSETR, 3, 0),
1575         K_GATE(G_TIM15,         RCC_APB2ENSETR, 2, 0),
1576         K_GATE(G_TIM8,          RCC_APB2ENSETR, 1, 0),
1577         K_GATE(G_TIM1,          RCC_APB2ENSETR, 0, 0),
1578
1579         K_GATE(G_HDP,           RCC_APB3ENSETR, 20, 0),
1580         K_GATE(G_PMBCTRL,       RCC_APB3ENSETR, 17, 0),
1581         K_GATE(G_TMPSENS,       RCC_APB3ENSETR, 16, 0),
1582         K_GATE(G_VREF,          RCC_APB3ENSETR, 13, 0),
1583         K_GATE(G_SYSCFG,        RCC_APB3ENSETR, 11, 0),
1584         K_MGATE(G_SAI4,         RCC_APB3ENSETR, 8, 0),
1585         K_MGATE(G_LPTIM5,       RCC_APB3ENSETR, 3, 0),
1586         K_MGATE(G_LPTIM4,       RCC_APB3ENSETR, 2, 0),
1587         K_MGATE(G_LPTIM3,       RCC_APB3ENSETR, 1, 0),
1588         K_MGATE(G_LPTIM2,       RCC_APB3ENSETR, 0, 0),
1589
1590         K_GATE(G_STGENRO,       RCC_APB4ENSETR, 20, 0),
1591         K_MGATE(G_USBPHY,       RCC_APB4ENSETR, 16, 0),
1592         K_GATE(G_IWDG2,         RCC_APB4ENSETR, 15, 0),
1593         K_GATE(G_DDRPERFM,      RCC_APB4ENSETR, 8, 0),
1594         K_MGATE(G_DSI,          RCC_APB4ENSETR, 4, 0),
1595         K_MGATE(G_LTDC,         RCC_APB4ENSETR, 0, 0),
1596
1597         K_GATE(G_STGEN,         RCC_APB5ENSETR, 20, 0),
1598         K_GATE(G_BSEC,          RCC_APB5ENSETR, 16, 0),
1599         K_GATE(G_IWDG1,         RCC_APB5ENSETR, 15, 0),
1600         K_GATE(G_TZPC,          RCC_APB5ENSETR, 13, 0),
1601         K_GATE(G_TZC2,          RCC_APB5ENSETR, 12, 0),
1602         K_GATE(G_TZC1,          RCC_APB5ENSETR, 11, 0),
1603         K_GATE(G_RTCAPB,        RCC_APB5ENSETR, 8, 0),
1604         K_MGATE(G_USART1,       RCC_APB5ENSETR, 4, 0),
1605         K_MGATE(G_I2C6,         RCC_APB5ENSETR, 3, 0),
1606         K_MGATE(G_I2C4,         RCC_APB5ENSETR, 2, 0),
1607         K_MGATE(G_SPI6,         RCC_APB5ENSETR, 0, 0),
1608
1609         K_MGATE(G_SDMMC3,       RCC_AHB2ENSETR, 16, 0),
1610         K_MGATE(G_USBO,         RCC_AHB2ENSETR, 8, 0),
1611         K_MGATE(G_ADC12,        RCC_AHB2ENSETR, 5, 0),
1612         K_GATE(G_DMAMUX,        RCC_AHB2ENSETR, 2, 0),
1613         K_GATE(G_DMA2,          RCC_AHB2ENSETR, 1, 0),
1614         K_GATE(G_DMA1,          RCC_AHB2ENSETR, 0, 0),
1615
1616         K_GATE(G_IPCC,          RCC_AHB3ENSETR, 12, 0),
1617         K_GATE(G_HSEM,          RCC_AHB3ENSETR, 11, 0),
1618         K_GATE(G_CRC2,          RCC_AHB3ENSETR, 7, 0),
1619         K_MGATE(G_RNG2,         RCC_AHB3ENSETR, 6, 0),
1620         K_GATE(G_HASH2,         RCC_AHB3ENSETR, 5, 0),
1621         K_GATE(G_CRYP2,         RCC_AHB3ENSETR, 4, 0),
1622         K_GATE(G_DCMI,          RCC_AHB3ENSETR, 0, 0),
1623
1624         K_GATE(G_GPIOK,         RCC_AHB4ENSETR, 10, 0),
1625         K_GATE(G_GPIOJ,         RCC_AHB4ENSETR, 9, 0),
1626         K_GATE(G_GPIOI,         RCC_AHB4ENSETR, 8, 0),
1627         K_GATE(G_GPIOH,         RCC_AHB4ENSETR, 7, 0),
1628         K_GATE(G_GPIOG,         RCC_AHB4ENSETR, 6, 0),
1629         K_GATE(G_GPIOF,         RCC_AHB4ENSETR, 5, 0),
1630         K_GATE(G_GPIOE,         RCC_AHB4ENSETR, 4, 0),
1631         K_GATE(G_GPIOD,         RCC_AHB4ENSETR, 3, 0),
1632         K_GATE(G_GPIOC,         RCC_AHB4ENSETR, 2, 0),
1633         K_GATE(G_GPIOB,         RCC_AHB4ENSETR, 1, 0),
1634         K_GATE(G_GPIOA,         RCC_AHB4ENSETR, 0, 0),
1635
1636         K_GATE(G_BKPSRAM,       RCC_AHB5ENSETR, 8, 0),
1637         K_MGATE(G_RNG1,         RCC_AHB5ENSETR, 6, 0),
1638         K_GATE(G_HASH1,         RCC_AHB5ENSETR, 5, 0),
1639         K_GATE(G_CRYP1,         RCC_AHB5ENSETR, 4, 0),
1640         K_GATE(G_GPIOZ,         RCC_AHB5ENSETR, 0, 0),
1641
1642         K_GATE(G_USBH,          RCC_AHB6ENSETR, 24, 0),
1643         K_GATE(G_CRC1,          RCC_AHB6ENSETR, 20, 0),
1644         K_MGATE(G_SDMMC2,       RCC_AHB6ENSETR, 17, 0),
1645         K_MGATE(G_SDMMC1,       RCC_AHB6ENSETR, 16, 0),
1646         K_MGATE(G_QSPI,         RCC_AHB6ENSETR, 14, 0),
1647         K_MGATE(G_FMC,          RCC_AHB6ENSETR, 12, 0),
1648         K_GATE(G_ETHMAC,        RCC_AHB6ENSETR, 10, 0),
1649         K_GATE(G_ETHRX,         RCC_AHB6ENSETR, 9, 0),
1650         K_GATE(G_ETHTX,         RCC_AHB6ENSETR, 8, 0),
1651         K_GATE(G_ETHCK,         RCC_AHB6ENSETR, 7, 0),
1652         K_MGATE(G_GPU,          RCC_AHB6ENSETR, 5, 0),
1653         K_GATE(G_MDMA,          RCC_AHB6ENSETR, 0, 0),
1654         K_GATE(G_ETHSTP,        RCC_AHB6LPENSETR, 11, 0),
1655 };
1656
1657 enum {
1658         M_SDMMC12,
1659         M_SDMMC3,
1660         M_FMC,
1661         M_QSPI,
1662         M_RNG1,
1663         M_RNG2,
1664         M_USBPHY,
1665         M_USBO,
1666         M_STGEN,
1667         M_SPDIF,
1668         M_SPI1,
1669         M_SPI23,
1670         M_SPI45,
1671         M_SPI6,
1672         M_CEC,
1673         M_I2C12,
1674         M_I2C35,
1675         M_I2C46,
1676         M_LPTIM1,
1677         M_LPTIM23,
1678         M_LPTIM45,
1679         M_USART1,
1680         M_UART24,
1681         M_UART35,
1682         M_USART6,
1683         M_UART78,
1684         M_SAI1,
1685         M_SAI2,
1686         M_SAI3,
1687         M_SAI4,
1688         M_DSI,
1689         M_FDCAN,
1690         M_ADC12,
1691         M_ETHCK,
1692         M_CKPER,
1693         M_LAST
1694 };
1695
1696 static struct stm32_mmux ker_mux[M_LAST];
1697
1698 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
1699         [_id] = {\
1700                 &(struct mux_cfg) {\
1701                         .reg_off        = _offset,\
1702                         .shift          = _shift,\
1703                         .width          = _width,\
1704                         .mux_flags      = _mux_flags,\
1705                         .table          = NULL,\
1706                 },\
1707                 .mmux           = _mmux,\
1708                 .ops            = _ops,\
1709         }
1710
1711 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
1712         _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1713                         NULL, NULL)
1714
1715 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
1716         _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1717                         &ker_mux[_id], &clk_mmux_ops)
1718
1719 static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1720         /* Kernel multi mux */
1721         K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1722         K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
1723         K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
1724         K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
1725         K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
1726         K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
1727         K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
1728         K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
1729         K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
1730         K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
1731         K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
1732         K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
1733         K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
1734
1735         /*  Kernel simple mux */
1736         K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
1737         K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
1738         K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
1739         K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
1740         K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
1741         K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
1742         K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
1743         K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
1744         K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
1745         K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
1746         K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
1747         K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
1748         K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
1749         K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
1750         K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
1751         K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
1752         K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
1753         K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
1754         K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
1755         K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
1756         K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
1757         K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
1758 };
1759
1760 static const struct clock_config stm32mp1_clock_cfg[] = {
1761         /*  External / Internal Oscillators */
1762         GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1763         /* ck_csi is used by IO compensation and should be critical */
1764         GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1765                  RCC_OCENSETR, 4, 0),
1766         COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
1767                   _GATE_MP1(RCC_OCENSETR, 0, 0),
1768                   _NO_MUX,
1769                   _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
1770                        CLK_DIVIDER_READ_ONLY, NULL)),
1771         GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1772         GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1773
1774         FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1775
1776         /* PLLs */
1777         PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
1778         PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
1779         PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
1780         PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
1781
1782         /* ODF */
1783         COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
1784                   _GATE(RCC_PLL1CR, 4, 0),
1785                   _NO_MUX,
1786                   _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
1787
1788         COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
1789                   _GATE(RCC_PLL2CR, 4, 0),
1790                   _NO_MUX,
1791                   _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
1792
1793         COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
1794                   _GATE(RCC_PLL2CR, 5, 0),
1795                   _NO_MUX,
1796                   _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
1797
1798         COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
1799                   _GATE(RCC_PLL2CR, 6, 0),
1800                   _NO_MUX,
1801                   _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
1802
1803         COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
1804                   _GATE(RCC_PLL3CR, 4, 0),
1805                   _NO_MUX,
1806                   _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
1807
1808         COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
1809                   _GATE(RCC_PLL3CR, 5, 0),
1810                   _NO_MUX,
1811                   _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
1812
1813         COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
1814                   _GATE(RCC_PLL3CR, 6, 0),
1815                   _NO_MUX,
1816                   _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
1817
1818         COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
1819                   _GATE(RCC_PLL4CR, 4, 0),
1820                   _NO_MUX,
1821                   _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
1822
1823         COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
1824                   _GATE(RCC_PLL4CR, 5, 0),
1825                   _NO_MUX,
1826                   _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
1827
1828         COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
1829                   _GATE(RCC_PLL4CR, 6, 0),
1830                   _NO_MUX,
1831                   _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
1832
1833         /* MUX system clocks */
1834         MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1835             RCC_CPERCKSELR, 0, 2, 0),
1836
1837         MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1838              CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
1839
1840         COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
1841                    CLK_OPS_PARENT_ENABLE,
1842                    _NO_GATE,
1843                    _MUX(RCC_ASSCKSELR, 0, 2, 0),
1844                    _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
1845
1846         COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
1847                    CLK_OPS_PARENT_ENABLE,
1848                    _NO_GATE,
1849                    _MUX(RCC_MSSCKSELR, 0, 2, 0),
1850                    _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
1851
1852         DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
1853                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1854
1855         DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
1856                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1857
1858         DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
1859                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1860
1861         DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
1862                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1863
1864         DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
1865                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1866
1867         /* Kernel Timers */
1868         STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1869         STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1870
1871         STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
1872         STM32_TIM(TIM3_K, "tim3_k", "ck1_tim", RCC_APB1ENSETR, 1),
1873         STM32_TIM(TIM4_K, "tim4_k", "ck1_tim", RCC_APB1ENSETR, 2),
1874         STM32_TIM(TIM5_K, "tim5_k", "ck1_tim", RCC_APB1ENSETR, 3),
1875         STM32_TIM(TIM6_K, "tim6_k", "ck1_tim", RCC_APB1ENSETR, 4),
1876         STM32_TIM(TIM7_K, "tim7_k", "ck1_tim", RCC_APB1ENSETR, 5),
1877         STM32_TIM(TIM12_K, "tim12_k", "ck1_tim", RCC_APB1ENSETR, 6),
1878         STM32_TIM(TIM13_K, "tim13_k", "ck1_tim", RCC_APB1ENSETR, 7),
1879         STM32_TIM(TIM14_K, "tim14_k", "ck1_tim", RCC_APB1ENSETR, 8),
1880         STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
1881         STM32_TIM(TIM8_K, "tim8_k", "ck2_tim", RCC_APB2ENSETR, 1),
1882         STM32_TIM(TIM15_K, "tim15_k", "ck2_tim", RCC_APB2ENSETR, 2),
1883         STM32_TIM(TIM16_K, "tim16_k", "ck2_tim", RCC_APB2ENSETR, 3),
1884         STM32_TIM(TIM17_K, "tim17_k", "ck2_tim", RCC_APB2ENSETR, 4),
1885
1886         /* Peripheral clocks */
1887         PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1888         PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1889         PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1890         PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1891         PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1892         PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1893         PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1894         PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1895         PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
1896         PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
1897         PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
1898         PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
1899         PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
1900         PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
1901         PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
1902         PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
1903         PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
1904         PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
1905         PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
1906         PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
1907         PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
1908         PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
1909         PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
1910         PCLK(CEC, "cec", "pclk1", 0, G_CEC),
1911         PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
1912         PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
1913         PCLK(TIM1, "tim1", "pclk2", CLK_IGNORE_UNUSED, G_TIM1),
1914         PCLK(TIM8, "tim8", "pclk2", CLK_IGNORE_UNUSED, G_TIM8),
1915         PCLK(TIM15, "tim15", "pclk2", CLK_IGNORE_UNUSED, G_TIM15),
1916         PCLK(TIM16, "tim16", "pclk2", CLK_IGNORE_UNUSED, G_TIM16),
1917         PCLK(TIM17, "tim17", "pclk2", CLK_IGNORE_UNUSED, G_TIM17),
1918         PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
1919         PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
1920         PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
1921         PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
1922         PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
1923         PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
1924         PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
1925         PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
1926         PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
1927         PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
1928         PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
1929         PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
1930         PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
1931         PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
1932         PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
1933         PCLK(VREF, "vref", "pclk3", 13, G_VREF),
1934         PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
1935         PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
1936         PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
1937         PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
1938         PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
1939         PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
1940         PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
1941         PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
1942         PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
1943         PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
1944         PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
1945         PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1946         PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
1947              CLK_IS_CRITICAL, G_RTCAPB),
1948         PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
1949         PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
1950         PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
1951         PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1952         PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
1953         PCLK(STGEN, "stgen", "pclk5", CLK_IGNORE_UNUSED, G_STGEN),
1954         PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
1955         PCLK(DMA2, "dma2", "ck_mcu",  0, G_DMA2),
1956         PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
1957         PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
1958         PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
1959         PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
1960         PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
1961         PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
1962         PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
1963         PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
1964         PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
1965         PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
1966         PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
1967         PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
1968         PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
1969         PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
1970         PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
1971         PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
1972         PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
1973         PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
1974         PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
1975         PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
1976         PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
1977         PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
1978         PCLK(GPIOZ, "gpioz", "ck_axi", CLK_IGNORE_UNUSED, G_GPIOZ),
1979         PCLK(CRYP1, "cryp1", "ck_axi", CLK_IGNORE_UNUSED, G_CRYP1),
1980         PCLK(HASH1, "hash1", "ck_axi", CLK_IGNORE_UNUSED, G_HASH1),
1981         PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
1982         PCLK(BKPSRAM, "bkpsram", "ck_axi", CLK_IGNORE_UNUSED, G_BKPSRAM),
1983         PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
1984         PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
1985         PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
1986         PCLK_PDATA(ETHRX, "ethrx", ethrx_src, 0, G_ETHRX),
1987         PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
1988         PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC),
1989         PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI),
1990         PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
1991         PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
1992         PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
1993         PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
1994         PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
1995         PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
1996
1997         /* Kernel clocks */
1998         KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
1999         KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
2000         KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
2001         KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
2002         KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
2003         KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
2004         KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
2005         KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
2006         KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
2007         KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
2008         KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
2009         KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
2010         KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
2011         KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
2012         KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
2013         KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
2014         KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
2015         KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
2016         KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
2017         KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
2018         KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
2019         KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
2020         KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
2021         KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
2022         KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
2023         KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
2024         KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
2025         KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
2026         KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
2027         KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
2028         KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
2029         KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
2030         KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
2031         KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
2032         KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
2033         KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
2034         KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
2035         KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
2036         KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
2037         KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
2038         KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
2039         KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
2040         KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
2041         KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
2042         KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
2043
2044         /* Particulary Kernel Clocks (no mux or no gate) */
2045         MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
2046         MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
2047         MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),
2048         MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
2049         MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
2050
2051         COMPOSITE(NO_ID, "ck_ker_eth", eth_src, CLK_OPS_PARENT_ENABLE |
2052                   CLK_SET_RATE_NO_REPARENT,
2053                   _NO_GATE,
2054                   _MMUX(M_ETHCK),
2055                   _NO_DIV),
2056
2057         MGATE_MP1(ETHCK_K, "ethck_k", "ck_ker_eth", 0, G_ETHCK),
2058
2059         DIV(ETHPTP_K, "ethptp_k", "ck_ker_eth", CLK_OPS_PARENT_ENABLE |
2060             CLK_SET_RATE_NO_REPARENT, RCC_ETHCKSELR, 4, 4, 0),
2061
2062         /* RTC clock */
2063         COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
2064                   _GATE(RCC_BDCR, 20, 0),
2065                   _MUX(RCC_BDCR, 16, 2, 0),
2066                   _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
2067
2068         /* MCO clocks */
2069         COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
2070                   CLK_SET_RATE_NO_REPARENT,
2071                   _GATE(RCC_MCO1CFGR, 12, 0),
2072                   _MUX(RCC_MCO1CFGR, 0, 3, 0),
2073                   _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
2074
2075         COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
2076                   CLK_SET_RATE_NO_REPARENT,
2077                   _GATE(RCC_MCO2CFGR, 12, 0),
2078                   _MUX(RCC_MCO2CFGR, 0, 3, 0),
2079                   _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
2080
2081         /* Debug clocks */
2082         GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
2083              RCC_DBGCFGR, 8, 0),
2084
2085         COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
2086                   _GATE(RCC_DBGCFGR, 9, 0),
2087                   _NO_MUX,
2088                   _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
2089 };
2090
2091 static const u32 stm32mp1_clock_secured[] = {
2092         CK_HSE,
2093         CK_HSI,
2094         CK_CSI,
2095         CK_LSI,
2096         CK_LSE,
2097         PLL1,
2098         PLL2,
2099         PLL1_P,
2100         PLL2_P,
2101         PLL2_Q,
2102         PLL2_R,
2103         CK_MPU,
2104         CK_AXI,
2105         SPI6,
2106         I2C4,
2107         I2C6,
2108         USART1,
2109         RTCAPB,
2110         TZC1,
2111         TZC2,
2112         TZPC,
2113         IWDG1,
2114         BSEC,
2115         STGEN,
2116         GPIOZ,
2117         CRYP1,
2118         HASH1,
2119         RNG1,
2120         BKPSRAM,
2121         RNG1_K,
2122         STGEN_K,
2123         SPI6_K,
2124         I2C4_K,
2125         I2C6_K,
2126         USART1_K,
2127         RTC,
2128 };
2129
2130 static bool stm32_check_security(const struct clock_config *cfg)
2131 {
2132         int i;
2133
2134         for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
2135                 if (cfg->id == stm32mp1_clock_secured[i])
2136                         return true;
2137         return false;
2138 }
2139
2140 struct stm32_rcc_match_data {
2141         const struct clock_config *cfg;
2142         unsigned int num;
2143         unsigned int maxbinding;
2144         struct clk_stm32_reset_data *reset_data;
2145         bool (*check_security)(const struct clock_config *cfg);
2146 };
2147
2148 static struct clk_stm32_reset_data stm32mp1_reset_data = {
2149         .nr_lines       = STM32MP1_RESET_ID_MASK,
2150         .clear_offset   = RCC_CLR,
2151 };
2152
2153 static struct stm32_rcc_match_data stm32mp1_data = {
2154         .cfg            = stm32mp1_clock_cfg,
2155         .num            = ARRAY_SIZE(stm32mp1_clock_cfg),
2156         .maxbinding     = STM32MP1_LAST_CLK,
2157         .reset_data     = &stm32mp1_reset_data,
2158 };
2159
2160 static struct stm32_rcc_match_data stm32mp1_data_secure = {
2161         .cfg            = stm32mp1_clock_cfg,
2162         .num            = ARRAY_SIZE(stm32mp1_clock_cfg),
2163         .maxbinding     = STM32MP1_LAST_CLK,
2164         .reset_data     = &stm32mp1_reset_data,
2165         .check_security = &stm32_check_security
2166 };
2167
2168 static const struct of_device_id stm32mp1_match_data[] = {
2169         {
2170                 .compatible = "st,stm32mp1-rcc",
2171                 .data = &stm32mp1_data,
2172         },
2173         {
2174                 .compatible = "st,stm32mp1-rcc-secure",
2175                 .data = &stm32mp1_data_secure,
2176         },
2177         { }
2178 };
2179 MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
2180
2181 static int stm32_register_hw_clk(struct device *dev,
2182                                  struct clk_hw_onecell_data *clk_data,
2183                                  void __iomem *base, spinlock_t *lock,
2184                                  const struct clock_config *cfg)
2185 {
2186         struct clk_hw **hws;
2187         struct clk_hw *hw = ERR_PTR(-ENOENT);
2188
2189         hws = clk_data->hws;
2190
2191         if (cfg->func)
2192                 hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
2193
2194         if (IS_ERR(hw)) {
2195                 pr_err("Unable to register %s\n", cfg->name);
2196                 return  PTR_ERR(hw);
2197         }
2198
2199         if (cfg->id != NO_ID)
2200                 hws[cfg->id] = hw;
2201
2202         return 0;
2203 }
2204
2205 static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,
2206                                 const struct of_device_id *match)
2207 {
2208         const struct stm32_rcc_match_data *data = match->data;
2209         struct clk_hw_onecell_data *clk_data;
2210         struct clk_hw **hws;
2211         int err, n, max_binding;
2212
2213         max_binding =  data->maxbinding;
2214
2215         clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding),
2216                                 GFP_KERNEL);
2217         if (!clk_data)
2218                 return -ENOMEM;
2219
2220         clk_data->num = max_binding;
2221
2222         hws = clk_data->hws;
2223
2224         for (n = 0; n < max_binding; n++)
2225                 hws[n] = ERR_PTR(-ENOENT);
2226
2227         for (n = 0; n < data->num; n++) {
2228                 if (data->check_security && data->check_security(&data->cfg[n]))
2229                         continue;
2230
2231                 err = stm32_register_hw_clk(dev, clk_data, base, &rlock,
2232                                             &data->cfg[n]);
2233                 if (err) {
2234                         dev_err(dev, "Can't register clk %s: %d\n",
2235                                 data->cfg[n].name, err);
2236
2237                         return err;
2238                 }
2239         }
2240
2241         return of_clk_add_hw_provider(dev_of_node(dev), of_clk_hw_onecell_get, clk_data);
2242 }
2243
2244 static int stm32_rcc_init(struct device *dev, void __iomem *base,
2245                           const struct of_device_id *match_data)
2246 {
2247         const struct stm32_rcc_match_data *rcc_match_data;
2248         const struct of_device_id *match;
2249         int err;
2250
2251         match = of_match_node(match_data, dev_of_node(dev));
2252         if (!match) {
2253                 dev_err(dev, "match data not found\n");
2254                 return -ENODEV;
2255         }
2256
2257         rcc_match_data = match->data;
2258
2259         /* RCC Reset Configuration */
2260         err = stm32_rcc_reset_init(dev, rcc_match_data->reset_data, base);
2261         if (err) {
2262                 pr_err("stm32mp1 reset failed to initialize\n");
2263                 return err;
2264         }
2265
2266         /* RCC Clock Configuration */
2267         err = stm32_rcc_clock_init(dev, base, match);
2268         if (err) {
2269                 pr_err("stm32mp1 clock failed to initialize\n");
2270                 return err;
2271         }
2272
2273         return 0;
2274 }
2275
2276 static int stm32mp1_rcc_init(struct device *dev)
2277 {
2278         void __iomem *base;
2279         int ret;
2280
2281         base = of_iomap(dev_of_node(dev), 0);
2282         if (!base) {
2283                 pr_err("%pOFn: unable to map resource", dev_of_node(dev));
2284                 ret = -ENOMEM;
2285                 goto out;
2286         }
2287
2288         ret = stm32_rcc_init(dev, base, stm32mp1_match_data);
2289
2290 out:
2291         if (ret) {
2292                 if (base)
2293                         iounmap(base);
2294
2295                 of_node_put(dev_of_node(dev));
2296         }
2297
2298         return ret;
2299 }
2300
2301 static int get_clock_deps(struct device *dev)
2302 {
2303         static const char * const clock_deps_name[] = {
2304                 "hsi", "hse", "csi", "lsi", "lse",
2305         };
2306         size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
2307         struct clk **clk_deps;
2308         int i;
2309
2310         clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
2311         if (!clk_deps)
2312                 return -ENOMEM;
2313
2314         for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
2315                 struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
2316                                                      clock_deps_name[i]);
2317
2318                 if (IS_ERR(clk)) {
2319                         if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
2320                                 return PTR_ERR(clk);
2321                 } else {
2322                         /* Device gets a reference count on the clock */
2323                         clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
2324                         clk_put(clk);
2325                 }
2326         }
2327
2328         return 0;
2329 }
2330
2331 static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
2332 {
2333         struct device *dev = &pdev->dev;
2334         int ret = get_clock_deps(dev);
2335
2336         if (!ret)
2337                 ret = stm32mp1_rcc_init(dev);
2338
2339         return ret;
2340 }
2341
2342 static void stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
2343 {
2344         struct device *dev = &pdev->dev;
2345         struct device_node *child, *np = dev_of_node(dev);
2346
2347         for_each_available_child_of_node(np, child)
2348                 of_clk_del_provider(child);
2349 }
2350
2351 static struct platform_driver stm32mp1_rcc_clocks_driver = {
2352         .driver = {
2353                 .name = "stm32mp1_rcc",
2354                 .of_match_table = stm32mp1_match_data,
2355         },
2356         .probe = stm32mp1_rcc_clocks_probe,
2357         .remove = stm32mp1_rcc_clocks_remove,
2358 };
2359
2360 static int __init stm32mp1_clocks_init(void)
2361 {
2362         return platform_driver_register(&stm32mp1_rcc_clocks_driver);
2363 }
2364 core_initcall(stm32mp1_clocks_init);