drivers/clk/samsung/clk-fsd.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
   4  *             https://www.samsung.com
   5  * Copyright (c) 2017-2022 Tesla, Inc.
   6  *             https://www.tesla.com
   7  *
   8  * Common Clock Framework support for FSD SoC.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17
  18 #include <dt-bindings/clock/fsd-clk.h>
  19
  20 #include "clk.h"
  21 #include "clk-exynos-arm64.h"
  22
  23 /* Register Offset definitions for CMU_CMU (0x11c10000) */
  24 #define PLL_LOCKTIME_PLL_SHARED0                        0x0
  25 #define PLL_LOCKTIME_PLL_SHARED1                        0x4
  26 #define PLL_LOCKTIME_PLL_SHARED2                        0x8
  27 #define PLL_LOCKTIME_PLL_SHARED3                        0xc
  28 #define PLL_CON0_PLL_SHARED0                            0x100
  29 #define PLL_CON0_PLL_SHARED1                            0x120
  30 #define PLL_CON0_PLL_SHARED2                            0x140
  31 #define PLL_CON0_PLL_SHARED3                            0x160
  32 #define MUX_CMU_CIS0_CLKMUX                             0x1000
  33 #define MUX_CMU_CIS1_CLKMUX                             0x1004
  34 #define MUX_CMU_CIS2_CLKMUX                             0x1008
  35 #define MUX_CMU_CPUCL_SWITCHMUX                         0x100c
  36 #define MUX_CMU_FSYS1_ACLK_MUX                          0x1014
  37 #define MUX_PLL_SHARED0_MUX                             0x1020
  38 #define MUX_PLL_SHARED1_MUX                             0x1024
  39 #define DIV_CMU_CIS0_CLK                                0x1800
  40 #define DIV_CMU_CIS1_CLK                                0x1804
  41 #define DIV_CMU_CIS2_CLK                                0x1808
  42 #define DIV_CMU_CMU_ACLK                                0x180c
  43 #define DIV_CMU_CPUCL_SWITCH                            0x1810
  44 #define DIV_CMU_FSYS0_SHARED0DIV4                       0x181c
  45 #define DIV_CMU_FSYS0_SHARED1DIV3                       0x1820
  46 #define DIV_CMU_FSYS0_SHARED1DIV4                       0x1824
  47 #define DIV_CMU_FSYS1_SHARED0DIV4                       0x1828
  48 #define DIV_CMU_FSYS1_SHARED0DIV8                       0x182c
  49 #define DIV_CMU_IMEM_ACLK                               0x1834
  50 #define DIV_CMU_IMEM_DMACLK                             0x1838
  51 #define DIV_CMU_IMEM_TCUCLK                             0x183c
  52 #define DIV_CMU_PERIC_SHARED0DIV20                      0x1844
  53 #define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK                0x1848
  54 #define DIV_CMU_PERIC_SHARED1DIV36                      0x184c
  55 #define DIV_CMU_PERIC_SHARED1DIV4_DMACLK                0x1850
  56 #define DIV_PLL_SHARED0_DIV2                            0x1858
  57 #define DIV_PLL_SHARED0_DIV3                            0x185c
  58 #define DIV_PLL_SHARED0_DIV4                            0x1860
  59 #define DIV_PLL_SHARED0_DIV6                            0x1864
  60 #define DIV_PLL_SHARED1_DIV3                            0x1868
  61 #define DIV_PLL_SHARED1_DIV36                           0x186c
  62 #define DIV_PLL_SHARED1_DIV4                            0x1870
  63 #define DIV_PLL_SHARED1_DIV9                            0x1874
  64 #define GAT_CMU_CIS0_CLKGATE                            0x2000
  65 #define GAT_CMU_CIS1_CLKGATE                            0x2004
  66 #define GAT_CMU_CIS2_CLKGATE                            0x2008
  67 #define GAT_CMU_CPUCL_SWITCH_GATE                       0x200c
  68 #define GAT_CMU_FSYS0_SHARED0DIV4_GATE                  0x2018
  69 #define GAT_CMU_FSYS0_SHARED1DIV4_CLK                   0x201c
  70 #define GAT_CMU_FSYS0_SHARED1DIV4_GATE                  0x2020
  71 #define GAT_CMU_FSYS1_SHARED0DIV4_GATE                  0x2024
  72 #define GAT_CMU_FSYS1_SHARED1DIV4_GATE                  0x2028
  73 #define GAT_CMU_IMEM_ACLK_GATE                          0x2030
  74 #define GAT_CMU_IMEM_DMACLK_GATE                        0x2034
  75 #define GAT_CMU_IMEM_TCUCLK_GATE                        0x2038
  76 #define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE          0x2040
  77 #define GAT_CMU_PERIC_SHARED0DIVE4_GATE                 0x2044
  78 #define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE           0x2048
  79 #define GAT_CMU_PERIC_SHARED1DIVE4_GATE                 0x204c
  80 #define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK                  0x2054
  81 #define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK              0x2058
  82 #define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU    0x205c
  83 #define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK               0x2060
  84
  85 /* NOTE: Must be equal to the last clock ID increased by one */
  86 #define CLKS_NR_CMU             (GAT_CMU_FSYS0_SHARED0DIV4 + 1)
  87 #define CLKS_NR_PERIC           (PERIC_DOUT_RGMII_CLK + 1)
  88 #define CLKS_NR_FSYS0           (FSYS0_DOUT_FSYS0_PERIBUS_GRP + 1)
  89 #define CLKS_NR_FSYS1           (PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1)
  90 #define CLKS_NR_IMEM            (IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1)
  91 #define CLKS_NR_MFC             (MFC_MFC_IPCLKPORT_ACLK + 1)
  92 #define CLKS_NR_CAM_CSI         (CAM_CSI2_3_IPCLKPORT_I_ACLK + 1)
  93
  94 static const unsigned long cmu_clk_regs[] __initconst = {
  95         PLL_LOCKTIME_PLL_SHARED0,
  96         PLL_LOCKTIME_PLL_SHARED1,
  97         PLL_LOCKTIME_PLL_SHARED2,
  98         PLL_LOCKTIME_PLL_SHARED3,
  99         PLL_CON0_PLL_SHARED0,
 100         PLL_CON0_PLL_SHARED1,
 101         PLL_CON0_PLL_SHARED2,
 102         PLL_CON0_PLL_SHARED3,
 103         MUX_CMU_CIS0_CLKMUX,
 104         MUX_CMU_CIS1_CLKMUX,
 105         MUX_CMU_CIS2_CLKMUX,
 106         MUX_CMU_CPUCL_SWITCHMUX,
 107         MUX_CMU_FSYS1_ACLK_MUX,
 108         MUX_PLL_SHARED0_MUX,
 109         MUX_PLL_SHARED1_MUX,
 110         DIV_CMU_CIS0_CLK,
 111         DIV_CMU_CIS1_CLK,
 112         DIV_CMU_CIS2_CLK,
 113         DIV_CMU_CMU_ACLK,
 114         DIV_CMU_CPUCL_SWITCH,
 115         DIV_CMU_FSYS0_SHARED0DIV4,
 116         DIV_CMU_FSYS0_SHARED1DIV3,
 117         DIV_CMU_FSYS0_SHARED1DIV4,
 118         DIV_CMU_FSYS1_SHARED0DIV4,
 119         DIV_CMU_FSYS1_SHARED0DIV8,
 120         DIV_CMU_IMEM_ACLK,
 121         DIV_CMU_IMEM_DMACLK,
 122         DIV_CMU_IMEM_TCUCLK,
 123         DIV_CMU_PERIC_SHARED0DIV20,
 124         DIV_CMU_PERIC_SHARED0DIV3_TBUCLK,
 125         DIV_CMU_PERIC_SHARED1DIV36,
 126         DIV_CMU_PERIC_SHARED1DIV4_DMACLK,
 127         DIV_PLL_SHARED0_DIV2,
 128         DIV_PLL_SHARED0_DIV3,
 129         DIV_PLL_SHARED0_DIV4,
 130         DIV_PLL_SHARED0_DIV6,
 131         DIV_PLL_SHARED1_DIV3,
 132         DIV_PLL_SHARED1_DIV36,
 133         DIV_PLL_SHARED1_DIV4,
 134         DIV_PLL_SHARED1_DIV9,
 135         GAT_CMU_CIS0_CLKGATE,
 136         GAT_CMU_CIS1_CLKGATE,
 137         GAT_CMU_CIS2_CLKGATE,
 138         GAT_CMU_CPUCL_SWITCH_GATE,
 139         GAT_CMU_FSYS0_SHARED0DIV4_GATE,
 140         GAT_CMU_FSYS0_SHARED1DIV4_CLK,
 141         GAT_CMU_FSYS0_SHARED1DIV4_GATE,
 142         GAT_CMU_FSYS1_SHARED0DIV4_GATE,
 143         GAT_CMU_FSYS1_SHARED1DIV4_GATE,
 144         GAT_CMU_IMEM_ACLK_GATE,
 145         GAT_CMU_IMEM_DMACLK_GATE,
 146         GAT_CMU_IMEM_TCUCLK_GATE,
 147         GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE,
 148         GAT_CMU_PERIC_SHARED0DIVE4_GATE,
 149         GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE,
 150         GAT_CMU_PERIC_SHARED1DIVE4_GATE,
 151         GAT_CMU_CMU_CMU_IPCLKPORT_PCLK,
 152         GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK,
 153         GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU,
 154         GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK,
 155 };
 156
 157 static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = {
 158         PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0),
 159 };
 160
 161 static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = {
 162         PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
 163 };
 164
 165 static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = {
 166         PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
 167 };
 168
 169 static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = {
 170         PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0),
 171 };
 172
 173 static const struct samsung_pll_clock cmu_pll_clks[] __initconst = {
 174         PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
 175             PLL_CON0_PLL_SHARED0, pll_shared0_rate_table),
 176         PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
 177             PLL_CON0_PLL_SHARED1, pll_shared1_rate_table),
 178         PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
 179             PLL_CON0_PLL_SHARED2, pll_shared2_rate_table),
 180         PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
 181             PLL_CON0_PLL_SHARED3, pll_shared3_rate_table),
 182 };
 183
 184 /* List of parent clocks for Muxes in CMU_CMU */
 185 PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
 186 PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
 187 PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
 188 PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
 189 PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
 190 PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
 191 PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
 192 PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" };
 193 PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" };
 194 PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" };
 195 PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" };
 196
 197 static const struct samsung_mux_clock cmu_mux_clks[] __initconst = {
 198         MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1),
 199         MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1),
 200         MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1),
 201         MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1),
 202         MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1),
 203         MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1),
 204         MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1),
 205         MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
 206             MUX_CMU_CPUCL_SWITCHMUX, 0, 1),
 207         MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1),
 208         MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1),
 209         MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1),
 210 };
 211
 212 static const struct samsung_div_clock cmu_div_clks[] __initconst = {
 213         DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4),
 214         DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4),
 215         DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4),
 216         DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4),
 217         DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4),
 218         DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate",
 219             DIV_CMU_FSYS0_SHARED0DIV4, 0, 4),
 220         DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk",
 221             DIV_CMU_FSYS0_SHARED1DIV3, 0, 4),
 222         DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate",
 223             DIV_CMU_FSYS0_SHARED1DIV4, 0, 4),
 224         DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate",
 225             DIV_CMU_FSYS1_SHARED0DIV4, 0, 4),
 226         DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate",
 227             DIV_CMU_FSYS1_SHARED0DIV8, 0, 4),
 228         DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate",
 229             DIV_CMU_IMEM_ACLK, 0, 4),
 230         DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate",
 231             DIV_CMU_IMEM_DMACLK, 0, 4),
 232         DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate",
 233             DIV_CMU_IMEM_TCUCLK, 0, 4),
 234         DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20",
 235             "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4),
 236         DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk",
 237             "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4),
 238         DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36",
 239             "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4),
 240         DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk",
 241             "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4),
 242         DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux",
 243             DIV_PLL_SHARED0_DIV2, 0, 4),
 244         DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux",
 245             DIV_PLL_SHARED0_DIV3, 0, 4),
 246         DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2",
 247             DIV_PLL_SHARED0_DIV4, 0, 4),
 248         DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3",
 249             DIV_PLL_SHARED0_DIV6, 0, 4),
 250         DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux",
 251             DIV_PLL_SHARED1_DIV3, 0, 4),
 252         DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9",
 253             DIV_PLL_SHARED1_DIV36, 0, 4),
 254         DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux",
 255             DIV_PLL_SHARED1_DIV4, 0, 4),
 256         DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3",
 257             DIV_PLL_SHARED1_DIV9, 0, 4),
 258 };
 259
 260 static const struct samsung_gate_clock cmu_gate_clks[] __initconst = {
 261         GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
 262              CLK_IGNORE_UNUSED, 0),
 263         GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
 264              CLK_IGNORE_UNUSED, 0),
 265         GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
 266              CLK_IGNORE_UNUSED, 0),
 267         GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux",
 268              GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0),
 269         GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4",
 270              GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
 271         GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
 272              GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0),
 273         GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
 274              GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
 275         GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
 276              GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
 277         GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
 278              GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
 279         GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
 280              CLK_IGNORE_UNUSED, 0),
 281         GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21,
 282              CLK_IGNORE_UNUSED, 0),
 283         GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21,
 284              CLK_IGNORE_UNUSED, 0),
 285         GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3",
 286              GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
 287         GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4",
 288              GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
 289         GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4",
 290              GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
 291         GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36",
 292              GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
 293         GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
 294              GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 295         GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk",
 296              GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 297         GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk",
 298              GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0),
 299         GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
 300              GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 301 };
 302
 303 static const struct samsung_cmu_info cmu_cmu_info __initconst = {
 304         .pll_clks               = cmu_pll_clks,
 305         .nr_pll_clks            = ARRAY_SIZE(cmu_pll_clks),
 306         .mux_clks               = cmu_mux_clks,
 307         .nr_mux_clks            = ARRAY_SIZE(cmu_mux_clks),
 308         .div_clks               = cmu_div_clks,
 309         .nr_div_clks            = ARRAY_SIZE(cmu_div_clks),
 310         .gate_clks              = cmu_gate_clks,
 311         .nr_gate_clks           = ARRAY_SIZE(cmu_gate_clks),
 312         .nr_clk_ids             = CLKS_NR_CMU,
 313         .clk_regs               = cmu_clk_regs,
 314         .nr_clk_regs            = ARRAY_SIZE(cmu_clk_regs),
 315 };
 316
 317 static void __init fsd_clk_cmu_init(struct device_node *np)
 318 {
 319         samsung_cmu_register_one(np, &cmu_cmu_info);
 320 }
 321
 322 CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
 323
 324 /* Register Offset definitions for CMU_PERIC (0x14010000) */
 325 #define PLL_CON0_PERIC_DMACLK_MUX               0x100
 326 #define PLL_CON0_PERIC_EQOS_BUSCLK_MUX          0x120
 327 #define PLL_CON0_PERIC_PCLK_MUX                 0x140
 328 #define PLL_CON0_PERIC_TBUCLK_MUX               0x160
 329 #define PLL_CON0_SPI_CLK                        0x180
 330 #define PLL_CON0_SPI_PCLK                       0x1a0
 331 #define PLL_CON0_UART_CLK                       0x1c0
 332 #define PLL_CON0_UART_PCLK                      0x1e0
 333 #define MUX_PERIC_EQOS_PHYRXCLK                 0x1000
 334 #define DIV_EQOS_BUSCLK                         0x1800
 335 #define DIV_PERIC_MCAN_CLK                      0x1804
 336 #define DIV_RGMII_CLK                           0x1808
 337 #define DIV_RII_CLK                             0x180c
 338 #define DIV_RMII_CLK                            0x1810
 339 #define DIV_SPI_CLK                             0x1814
 340 #define DIV_UART_CLK                            0x1818
 341 #define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I    0x2000
 342 #define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK         0x2004
 343 #define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK       0x2008
 344 #define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK      0x200c
 345 #define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK       0x2010
 346 #define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK       0x2014
 347 #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM      0x2018
 348 #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS      0x201c
 349 #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM      0x2020
 350 #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS      0x2024
 351 #define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK       0x2028
 352 #define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK       0x202c
 353 #define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK       0x2030
 354 #define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK        0x2034
 355 #define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK       0x2038
 356 #define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK       0x203c
 357 #define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK       0x2040
 358 #define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK       0x2044
 359 #define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK       0x2048
 360 #define GAT_EQOS_TOP_IPCLKPORT_ACLK_I           0x204c
 361 #define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I         0x2050
 362 #define GAT_EQOS_TOP_IPCLKPORT_HCLK_I           0x2054
 363 #define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I      0x2058
 364 #define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I        0x205c
 365 #define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I       0x2060
 366 #define GAT_GPIO_PERIC_IPCLKPORT_PCLK           0x2064
 367 #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D        0x2068
 368 #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P        0x206c
 369 #define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0        0x2070
 370 #define GAT_PERIC_DMA0_IPCLKPORT_ACLK           0x2074
 371 #define GAT_PERIC_DMA1_IPCLKPORT_ACLK           0x2078
 372 #define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK         0x207c
 373 #define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK         0x2080
 374 #define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK         0x2084
 375 #define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK         0x2088
 376 #define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK         0x208c
 377 #define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK         0x2090
 378 #define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK         0x2094
 379 #define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK         0x2098
 380 #define GAT_PERIC_MCAN0_IPCLKPORT_CCLK          0x209c
 381 #define GAT_PERIC_MCAN0_IPCLKPORT_PCLK          0x20a0
 382 #define GAT_PERIC_MCAN1_IPCLKPORT_CCLK          0x20a4
 383 #define GAT_PERIC_MCAN1_IPCLKPORT_PCLK          0x20a8
 384 #define GAT_PERIC_MCAN2_IPCLKPORT_CCLK          0x20ac
 385 #define GAT_PERIC_MCAN2_IPCLKPORT_PCLK          0x20b0
 386 #define GAT_PERIC_MCAN3_IPCLKPORT_CCLK          0x20b4
 387 #define GAT_PERIC_MCAN3_IPCLKPORT_PCLK          0x20b8
 388 #define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0      0x20bc
 389 #define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0      0x20c0
 390 #define GAT_PERIC_SMMU_IPCLKPORT_CCLK           0x20c4
 391 #define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK     0x20c8
 392 #define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK         0x20cc
 393 #define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI     0x20d0
 394 #define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK         0x20d4
 395 #define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI     0x20d8
 396 #define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK         0x20dc
 397 #define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI     0x20e0
 398 #define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M         0x20e4
 399 #define GAT_PERIC_TDM0_IPCLKPORT_PCLK           0x20e8
 400 #define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M         0x20ec
 401 #define GAT_PERIC_TDM1_IPCLKPORT_PCLK           0x20f0
 402 #define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART   0x20f4
 403 #define GAT_PERIC_UART0_IPCLKPORT_PCLK          0x20f8
 404 #define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART   0x20fc
 405 #define GAT_PERIC_UART1_IPCLKPORT_PCLK          0x2100
 406 #define GAT_SYSREG_PERI_IPCLKPORT_PCLK          0x2104
 407
 408 static const unsigned long peric_clk_regs[] __initconst = {
 409         PLL_CON0_PERIC_DMACLK_MUX,
 410         PLL_CON0_PERIC_EQOS_BUSCLK_MUX,
 411         PLL_CON0_PERIC_PCLK_MUX,
 412         PLL_CON0_PERIC_TBUCLK_MUX,
 413         PLL_CON0_SPI_CLK,
 414         PLL_CON0_SPI_PCLK,
 415         PLL_CON0_UART_CLK,
 416         PLL_CON0_UART_PCLK,
 417         MUX_PERIC_EQOS_PHYRXCLK,
 418         DIV_EQOS_BUSCLK,
 419         DIV_PERIC_MCAN_CLK,
 420         DIV_RGMII_CLK,
 421         DIV_RII_CLK,
 422         DIV_RMII_CLK,
 423         DIV_SPI_CLK,
 424         DIV_UART_CLK,
 425         GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I,
 426         GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
 427         GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK,
 428         GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK,
 429         GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK,
 430         GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK,
 431         GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM,
 432         GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS,
 433         GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM,
 434         GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS,
 435         GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK,
 436         GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK,
 437         GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK,
 438         GAT_BUS_D_PERIC_IPCLKPORT_DMACLK,
 439         GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK,
 440         GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK,
 441         GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK,
 442         GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK,
 443         GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK,
 444         GAT_EQOS_TOP_IPCLKPORT_ACLK_I,
 445         GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I,
 446         GAT_EQOS_TOP_IPCLKPORT_HCLK_I,
 447         GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I,
 448         GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I,
 449         GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I,
 450         GAT_GPIO_PERIC_IPCLKPORT_PCLK,
 451         GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D,
 452         GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P,
 453         GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0,
 454         GAT_PERIC_DMA0_IPCLKPORT_ACLK,
 455         GAT_PERIC_DMA1_IPCLKPORT_ACLK,
 456         GAT_PERIC_I2C0_IPCLKPORT_I_PCLK,
 457         GAT_PERIC_I2C1_IPCLKPORT_I_PCLK,
 458         GAT_PERIC_I2C2_IPCLKPORT_I_PCLK,
 459         GAT_PERIC_I2C3_IPCLKPORT_I_PCLK,
 460         GAT_PERIC_I2C4_IPCLKPORT_I_PCLK,
 461         GAT_PERIC_I2C5_IPCLKPORT_I_PCLK,
 462         GAT_PERIC_I2C6_IPCLKPORT_I_PCLK,
 463         GAT_PERIC_I2C7_IPCLKPORT_I_PCLK,
 464         GAT_PERIC_MCAN0_IPCLKPORT_CCLK,
 465         GAT_PERIC_MCAN0_IPCLKPORT_PCLK,
 466         GAT_PERIC_MCAN1_IPCLKPORT_CCLK,
 467         GAT_PERIC_MCAN1_IPCLKPORT_PCLK,
 468         GAT_PERIC_MCAN2_IPCLKPORT_CCLK,
 469         GAT_PERIC_MCAN2_IPCLKPORT_PCLK,
 470         GAT_PERIC_MCAN3_IPCLKPORT_CCLK,
 471         GAT_PERIC_MCAN3_IPCLKPORT_PCLK,
 472         GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0,
 473         GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0,
 474         GAT_PERIC_SMMU_IPCLKPORT_CCLK,
 475         GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK,
 476         GAT_PERIC_SPI0_IPCLKPORT_I_PCLK,
 477         GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI,
 478         GAT_PERIC_SPI1_IPCLKPORT_I_PCLK,
 479         GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI,
 480         GAT_PERIC_SPI2_IPCLKPORT_I_PCLK,
 481         GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI,
 482         GAT_PERIC_TDM0_IPCLKPORT_HCLK_M,
 483         GAT_PERIC_TDM0_IPCLKPORT_PCLK,
 484         GAT_PERIC_TDM1_IPCLKPORT_HCLK_M,
 485         GAT_PERIC_TDM1_IPCLKPORT_PCLK,
 486         GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART,
 487         GAT_PERIC_UART0_IPCLKPORT_PCLK,
 488         GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART,
 489         GAT_PERIC_UART1_IPCLKPORT_PCLK,
 490         GAT_SYSREG_PERI_IPCLKPORT_PCLK,
 491 };
 492
 493 static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = {
 494         FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000),
 495 };
 496
 497 /* List of parent clocks for Muxes in CMU_PERIC */
 498 PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" };
 499 PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
 500 PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
 501 PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" };
 502 PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" };
 503 PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
 504 PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" };
 505 PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
 506 PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" };
 507
 508 static const struct samsung_mux_clock peric_mux_clks[] __initconst = {
 509         MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1),
 510         MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p,
 511             PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1),
 512         MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1),
 513         MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1),
 514         MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1),
 515         MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1),
 516         MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1),
 517         MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1),
 518         MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p,
 519                 MUX_PERIC_EQOS_PHYRXCLK, 0, 1),
 520 };
 521
 522 static const struct samsung_div_clock peric_div_clks[] __initconst = {
 523         DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4),
 524         DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4),
 525         DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk",
 526                 DIV_RGMII_CLK, 0, 4),
 527         DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4),
 528         DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4),
 529         DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6),
 530         DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6),
 531 };
 532
 533 static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
 534         GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i",
 535              "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
 536         GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
 537              21, CLK_IGNORE_UNUSED, 0),
 538         GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll",
 539              GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
 540         GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk",
 541              GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 542         GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21,
 543              CLK_IGNORE_UNUSED, 0),
 544         GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21,
 545              CLK_IGNORE_UNUSED, 0),
 546         GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk",
 547              GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
 548         GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk",
 549              GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
 550         GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk",
 551              GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
 552         GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk",
 553              GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
 554         GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk",
 555              GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 556         GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk",
 557              GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 558         GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk",
 559              GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 560         GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk",
 561              GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0),
 562         GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk",
 563              "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
 564         GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk",
 565              GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
 566         GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk",
 567              "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
 568         GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk",
 569              GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
 570         GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk",
 571              GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0),
 572         GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i",
 573              "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0),
 574         GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i",
 575              "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0),
 576         GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i",
 577              "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0),
 578         GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i",
 579              "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
 580         GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk",
 581              GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
 582         GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk",
 583              GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
 584         GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk",
 585              GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 586         GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk",
 587              GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0),
 588         GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk",
 589              GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0),
 590         GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk",
 591              GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
 592         GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk",
 593              GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 594         GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk",
 595              GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 596         GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk",
 597              GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 598         GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk",
 599              GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 600         GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk",
 601              GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 602         GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk",
 603              GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 604         GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk",
 605              GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 606         GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk",
 607              GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 608         GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk",
 609              GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 610         GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk",
 611              GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 612         GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk",
 613              GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
 614         GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk",
 615              GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 616         GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk",
 617              GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
 618         GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk",
 619              GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 620         GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk",
 621              GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
 622         GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk",
 623              GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 624         GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk",
 625              GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
 626         GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk",
 627              GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 628         GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk",
 629              GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
 630         GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk",
 631              GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
 632         GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk",
 633              GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
 634         GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk",
 635              GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0),
 636         GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk",
 637              GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 638         GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
 639              GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
 640         GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk",
 641              GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 642         GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
 643              GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
 644         GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk",
 645              GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 646         GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
 647              GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
 648         GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk",
 649              GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
 650         GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk",
 651              GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 652         GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk",
 653              GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
 654         GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk",
 655              GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 656         GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
 657              GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
 658         GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk",
 659              GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 660         GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
 661              GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
 662         GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk",
 663              GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 664         GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk",
 665              GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 666 };
 667
 668 static const struct samsung_cmu_info peric_cmu_info __initconst = {
 669         .mux_clks               = peric_mux_clks,
 670         .nr_mux_clks            = ARRAY_SIZE(peric_mux_clks),
 671         .div_clks               = peric_div_clks,
 672         .nr_div_clks            = ARRAY_SIZE(peric_div_clks),
 673         .gate_clks              = peric_gate_clks,
 674         .nr_gate_clks           = ARRAY_SIZE(peric_gate_clks),
 675         .fixed_clks             = peric_fixed_clks,
 676         .nr_fixed_clks          = ARRAY_SIZE(peric_fixed_clks),
 677         .nr_clk_ids             = CLKS_NR_PERIC,
 678         .clk_regs               = peric_clk_regs,
 679         .nr_clk_regs            = ARRAY_SIZE(peric_clk_regs),
 680         .clk_name               = "dout_cmu_pll_shared0_div4",
 681 };
 682
 683 /* Register Offset definitions for CMU_FSYS0 (0x15010000) */
 684 #define PLL_CON0_CLKCMU_FSYS0_UNIPRO            0x100
 685 #define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK          0x140
 686 #define PLL_CON0_EQOS_RGMII_125_MUX1            0x160
 687 #define DIV_CLK_UNIPRO                          0x1800
 688 #define DIV_EQS_RGMII_CLK_125                   0x1804
 689 #define DIV_PERIBUS_GRP                         0x1808
 690 #define DIV_EQOS_RII_CLK2O5                     0x180c
 691 #define DIV_EQOS_RMIICLK_25                     0x1810
 692 #define DIV_PCIE_PHY_OSCCLK                     0x1814
 693 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I     0x2004
 694 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I  0x2008
 695 #define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK        0x200c
 696 #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK   0x2010
 697 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO    0x2014
 698 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK     0x2018
 699 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC       0x201c
 700 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24      0x2020
 701 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26      0x2024
 702 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24      0x2028
 703 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26      0x202c
 704 #define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK    0x2038
 705 #define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK  0x203c
 706 #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040
 707 #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044
 708 #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048
 709 #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK  0x204c
 710 #define GAT_FSYS0_CPE425_IPCLKPORT_ACLK         0x2050
 711 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I    0x2054
 712 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I    0x2058
 713 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I       0x205c
 714 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060
 715 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I        0x2064
 716 #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK     0x2068
 717 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D  0x206c
 718 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070
 719 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P  0x2074
 720 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S  0x2078
 721 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK    0x207c
 722 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL        0x2080
 723 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0       0x2084
 724 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC      0x2088
 725 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK  0x208c
 726 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC     0x2090
 727 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC      0x2094
 728 #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK     0x2098
 729 #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK       0x209c
 730 #define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK   0x20a0
 731 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS   0x20a4
 732 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK     0x20a8
 733 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO       0x20ac
 734 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK  0x20b0
 735 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS   0x20b4
 736 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK     0x20b8
 737 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO       0x20bc
 738 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK  0x20c0
 739 #define GAT_FSYS0_RII_CLK_DIVGATE                       0x20d4
 740
 741 static const unsigned long fsys0_clk_regs[] __initconst = {
 742         PLL_CON0_CLKCMU_FSYS0_UNIPRO,
 743         PLL_CON0_CLK_FSYS0_SLAVEBUSCLK,
 744         PLL_CON0_EQOS_RGMII_125_MUX1,
 745         DIV_CLK_UNIPRO,
 746         DIV_EQS_RGMII_CLK_125,
 747         DIV_PERIBUS_GRP,
 748         DIV_EQOS_RII_CLK2O5,
 749         DIV_EQOS_RMIICLK_25,
 750         DIV_PCIE_PHY_OSCCLK,
 751         GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I,
 752         GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I,
 753         GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
 754         GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK,
 755         GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO,
 756         GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK,
 757         GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC,
 758         GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
 759         GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
 760         GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
 761         GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
 762         GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK,
 763         GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK,
 764         GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK,
 765         GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK,
 766         GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK,
 767         GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK,
 768         GAT_FSYS0_CPE425_IPCLKPORT_ACLK,
 769         GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I,
 770         GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I,
 771         GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I,
 772         GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I,
 773         GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I,
 774         GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK,
 775         GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D,
 776         GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1,
 777         GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P,
 778         GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S,
 779         GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK,
 780         GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
 781         GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0,
 782         GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC,
 783         GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
 784         GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC,
 785         GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC,
 786         GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK,
 787         GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK,
 788         GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK,
 789         GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS,
 790         GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK,
 791         GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO,
 792         GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK,
 793         GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS,
 794         GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK,
 795         GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO,
 796         GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK,
 797         GAT_FSYS0_RII_CLK_DIVGATE,
 798 };
 799
 800 static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = {
 801         FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000),
 802         FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000),
 803         FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000),
 804 };
 805
 806 /* List of parent clocks for Muxes in CMU_FSYS0 */
 807 PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" };
 808 PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" };
 809 PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" };
 810
 811 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
 812         MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p,
 813             PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1),
 814         MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p,
 815             PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1),
 816         MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p,
 817             PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1),
 818 };
 819
 820 static const struct samsung_div_clock fsys0_div_clks[] __initconst = {
 821         DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4),
 822         DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1",
 823             DIV_EQS_RGMII_CLK_125, 0, 4),
 824         DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp",
 825             "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4),
 826         DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4),
 827         DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1",
 828             DIV_EQOS_RMIICLK_25, 0, 5),
 829         DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1",
 830             DIV_PCIE_PHY_OSCCLK, 0, 4),
 831 };
 832
 833 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
 834         GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i",
 835              "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21,
 836              CLK_IGNORE_UNUSED, 0),
 837         GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC,
 838              "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll",
 839              GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21,
 840              CLK_IGNORE_UNUSED, 0),
 841         GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
 842              GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 843         GATE(0,
 844              "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo",
 845              "xtal_clk_pcie_phy",
 846              GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21,
 847              CLK_IGNORE_UNUSED, 0),
 848         GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24",
 849              "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
 850              CLK_IGNORE_UNUSED, 0),
 851         GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26",
 852              "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
 853              CLK_IGNORE_UNUSED, 0),
 854         GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24",
 855              "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
 856              CLK_IGNORE_UNUSED, 0),
 857         GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26",
 858              "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
 859              CLK_IGNORE_UNUSED, 0),
 860         GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp",
 861              GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0),
 862         GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp",
 863              GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 864         GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk",
 865              GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
 866         GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp",
 867              GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
 868         GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp",
 869              GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
 870         GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1",
 871              GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
 872         GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk",
 873              GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 874         GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i",
 875              "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21,
 876              CLK_IGNORE_UNUSED, 0),
 877         GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i",
 878              "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21,
 879              CLK_IGNORE_UNUSED, 0),
 880         GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i",
 881               "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21,
 882               CLK_IGNORE_UNUSED, 0),
 883         GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5",
 884              GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
 885         GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25",
 886              GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
 887         GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
 888              GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 889         GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll",
 890              GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
 891         GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d",
 892              "mout_fsys0_clk_fsys0_slavebusclk",
 893              GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21,
 894              CLK_IGNORE_UNUSED, 0),
 895         GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1",
 896              "mout_fsys0_eqos_rgmii_125_mux1",
 897              GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21,
 898              CLK_IGNORE_UNUSED, 0),
 899         GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p",
 900              "dout_fsys0_peribus_grp",
 901              GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21,
 902              CLK_IGNORE_UNUSED, 0),
 903         GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s",
 904              "mout_fsys0_clk_fsys0_slavebusclk",
 905              GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21,
 906              CLK_IGNORE_UNUSED, 0),
 907         GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk",
 908              "dout_fsys0_peribus_grp",
 909              GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21,
 910              CLK_IGNORE_UNUSED, 0),
 911         GATE(0,
 912              "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll",
 913              "dout_fsys0_pcie_phy_oscclk",
 914              GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
 915              21, CLK_IGNORE_UNUSED, 0),
 916         GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp",
 917              GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0),
 918         GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll",
 919              GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0),
 920         GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC,
 921              "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc",
 922              "dout_fsys0_peribus_grp",
 923              GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21,
 924              CLK_IGNORE_UNUSED, 0),
 925         GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk",
 926              "dout_fsys0_peribus_grp",
 927              GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21,
 928              CLK_IGNORE_UNUSED, 0),
 929         GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC,
 930              "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc",
 931              "mout_fsys0_clk_fsys0_slavebusclk",
 932              GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21,
 933              CLK_IGNORE_UNUSED, 0),
 934         GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC,
 935              "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc",
 936              "mout_fsys0_clk_fsys0_slavebusclk",
 937              GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21,
 938              CLK_IGNORE_UNUSED, 0),
 939         GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1",
 940              GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
 941         GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk",
 942              GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0),
 943         GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
 944              GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 945         GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
 946              GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
 947         GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
 948              GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 949         GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
 950              GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
 951         GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
 952              GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
 953         GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
 954              GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
 955         GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
 956              GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
 957         GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
 958              GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
 959         GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
 960              GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
 961         GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE,
 962              21, CLK_IGNORE_UNUSED, 0),
 963         GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i",
 964              "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
 965 };
 966
 967 static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
 968         .mux_clks               = fsys0_mux_clks,
 969         .nr_mux_clks            = ARRAY_SIZE(fsys0_mux_clks),
 970         .div_clks               = fsys0_div_clks,
 971         .nr_div_clks            = ARRAY_SIZE(fsys0_div_clks),
 972         .gate_clks              = fsys0_gate_clks,
 973         .nr_gate_clks           = ARRAY_SIZE(fsys0_gate_clks),
 974         .fixed_clks             = fsys0_fixed_clks,
 975         .nr_fixed_clks          = ARRAY_SIZE(fsys0_fixed_clks),
 976         .nr_clk_ids             = CLKS_NR_FSYS0,
 977         .clk_regs               = fsys0_clk_regs,
 978         .nr_clk_regs            = ARRAY_SIZE(fsys0_clk_regs),
 979         .clk_name               = "dout_cmu_fsys0_shared1div4",
 980 };
 981
 982 /* Register Offset definitions for CMU_FSYS1 (0x16810000) */
 983 #define PLL_CON0_ACLK_FSYS1_BUSP_MUX                    0x100
 984 #define PLL_CON0_PCLKL_FSYS1_BUSP_MUX                   0x180
 985 #define DIV_CLK_FSYS1_PHY0_OSCCLK                       0x1800
 986 #define DIV_CLK_FSYS1_PHY1_OSCCLK                       0x1804
 987 #define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK      0x2000
 988 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK           0x2004
 989 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK    0x2008
 990 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK           0x200c
 991 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL        0x202c
 992 #define GAT_FSYS1_PHY0_OSCCLLK                          0x2034
 993 #define GAT_FSYS1_PHY1_OSCCLK                           0x2038
 994 #define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK          0x203c
 995 #define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK        0x2040
 996 #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK        0x2048
 997 #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK        0x204c
 998 #define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK         0x2054
 999 #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c
1000 #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064
1001 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK         0x206c
1002 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK        0x2070
1003 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074
1004 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK        0x2078
1005 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK         0x207c
1006 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK         0x2080
1007 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084
1008 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK        0x2088
1009 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK         0x208c
1010 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK         0x20a4
1011 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL     0x20a8
1012 #define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK           0x20b4
1013 #define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK             0x20b8
1014
1015 static const unsigned long fsys1_clk_regs[] __initconst = {
1016         PLL_CON0_ACLK_FSYS1_BUSP_MUX,
1017         PLL_CON0_PCLKL_FSYS1_BUSP_MUX,
1018         DIV_CLK_FSYS1_PHY0_OSCCLK,
1019         DIV_CLK_FSYS1_PHY1_OSCCLK,
1020         GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
1021         GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK,
1022         GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK,
1023         GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK,
1024         GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL,
1025         GAT_FSYS1_PHY0_OSCCLLK,
1026         GAT_FSYS1_PHY1_OSCCLK,
1027         GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK,
1028         GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK,
1029         GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK,
1030         GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK,
1031         GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK,
1032         GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0,
1033         GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0,
1034         GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK,
1035         GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK,
1036         GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK,
1037         GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK,
1038         GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK,
1039         GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK,
1040         GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK,
1041         GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK,
1042         GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK,
1043         GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK,
1044         GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL,
1045         GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK,
1046         GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK,
1047 };
1048
1049 static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = {
1050         FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000),
1051         FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000),
1052 };
1053
1054 /* List of parent clocks for Muxes in CMU_FSYS1 */
1055 PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" };
1056 PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" };
1057
1058 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
1059         MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p,
1060             PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1),
1061         MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p,
1062             PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1),
1063 };
1064
1065 static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
1066         DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk",
1067             DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4),
1068         DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk",
1069             DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4),
1070 };
1071
1072 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
1073         GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
1074              GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1075         GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref",
1076              GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0),
1077         GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux",
1078              GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0),
1079         GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux",
1080              GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
1081         GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux",
1082              GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1083         GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
1084              GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
1085         GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1086              GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0),
1087         GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
1088              GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
1089         GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
1090              GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1091         GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0",
1092              "mout_fsys1_aclk_fsys1_busp_mux",
1093              GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21,
1094              CLK_IGNORE_UNUSED, 0),
1095         GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0",
1096              "mout_fsys1_aclk_fsys1_busp_mux",
1097              GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21,
1098              CLK_IGNORE_UNUSED, 0),
1099         GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk",
1100              "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21,
1101              CLK_IGNORE_UNUSED, 0),
1102         GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1103              GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
1104         GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll",
1105              GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0),
1106         GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1107              GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
1108         GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk",
1109              "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21,
1110              CLK_IGNORE_UNUSED, 0),
1111         GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk",
1112              "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21,
1113              CLK_IGNORE_UNUSED, 0),
1114         GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk",
1115              "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21,
1116              CLK_IGNORE_UNUSED, 0),
1117         GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1118              GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
1119         GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk",
1120              "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21,
1121              CLK_IGNORE_UNUSED, 0),
1122         GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk",
1123              "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21,
1124              CLK_IGNORE_UNUSED, 0),
1125         GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1126              GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
1127         GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll",
1128              GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
1129         GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll",
1130              GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
1131         GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk",
1132              GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0),
1133         GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
1134              GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1135         GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
1136              GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1137 };
1138
1139 static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
1140         .mux_clks               = fsys1_mux_clks,
1141         .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
1142         .div_clks               = fsys1_div_clks,
1143         .nr_div_clks            = ARRAY_SIZE(fsys1_div_clks),
1144         .gate_clks              = fsys1_gate_clks,
1145         .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
1146         .fixed_clks             = fsys1_fixed_clks,
1147         .nr_fixed_clks          = ARRAY_SIZE(fsys1_fixed_clks),
1148         .nr_clk_ids             = CLKS_NR_FSYS1,
1149         .clk_regs               = fsys1_clk_regs,
1150         .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
1151         .clk_name               = "dout_cmu_fsys1_shared0div4",
1152 };
1153
1154 /* Register Offset definitions for CMU_IMEM (0x10010000) */
1155 #define PLL_CON0_CLK_IMEM_ACLK                          0x100
1156 #define PLL_CON0_CLK_IMEM_INTMEMCLK                     0x120
1157 #define PLL_CON0_CLK_IMEM_TCUCLK                        0x140
1158 #define DIV_OSCCLK_IMEM_TMUTSCLK                        0x1800
1159 #define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK           0x2000
1160 #define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO              0x2004
1161 #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK         0x2008
1162 #define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK          0x200c
1163 #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK               0x2010
1164 #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS            0x2014
1165 #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK               0x2018
1166 #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS            0x201c
1167 #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK                0x2020
1168 #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS             0x2024
1169 #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK                 0x2028
1170 #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS              0x202c
1171 #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK                0x2030
1172 #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS             0x2034
1173 #define GAT_IMEM_WDT0_IPCLKPORT_CLK                     0x2038
1174 #define GAT_IMEM_WDT1_IPCLKPORT_CLK                     0x203c
1175 #define GAT_IMEM_WDT2_IPCLKPORT_CLK                     0x2040
1176 #define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM     0x2044
1177 #define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM     0x2048
1178 #define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM     0x204c
1179 #define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS     0x2050
1180 #define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS     0x2054
1181 #define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS     0x2058
1182 #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM             0x205c
1183 #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS             0x2060
1184 #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM             0x2064
1185 #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS             0x2068
1186 #define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK          0x206c
1187 #define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK          0x2070
1188 #define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK           0x2074
1189 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK           0x2078
1190 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK           0x207c
1191 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK            0x2080
1192 #define GAT_IMEM_DMA0_IPCLKPORT_ACLK                    0x2084
1193 #define GAT_IMEM_DMA1_IPCLKPORT_ACLK                    0x2088
1194 #define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK        0x208c
1195 #define GAT_IMEM_GIC_IPCLKPORT_CLK                      0x2090
1196 #define GAT_IMEM_INTMEM_IPCLKPORT_ACLK                  0x2094
1197 #define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK        0x2098
1198 #define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK        0x209c
1199 #define GAT_IMEM_MCT_IPCLKPORT_PCLK                     0x20a0
1200 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D      0x20a4
1201 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU    0x20a8
1202 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P      0x20ac
1203 #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK             0x20b0
1204 #define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK            0x20b4
1205 #define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK       0x20b8
1206 #define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK          0x20bc
1207 #define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK         0x20c0
1208 #define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK         0x20c4
1209 #define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK             0x20c8
1210 #define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK                0x20cc
1211 #define GAT_IMEM_TCU_IPCLKPORT_ACLK                     0x20d0
1212 #define GAT_IMEM_WDT0_IPCLKPORT_PCLK                    0x20d4
1213 #define GAT_IMEM_WDT1_IPCLKPORT_PCLK                    0x20d8
1214 #define GAT_IMEM_WDT2_IPCLKPORT_PCLK                    0x20dc
1215
1216 static const unsigned long imem_clk_regs[] __initconst = {
1217         PLL_CON0_CLK_IMEM_ACLK,
1218         PLL_CON0_CLK_IMEM_INTMEMCLK,
1219         PLL_CON0_CLK_IMEM_TCUCLK,
1220         DIV_OSCCLK_IMEM_TMUTSCLK,
1221         GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK,
1222         GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO,
1223         GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
1224         GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK,
1225         GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK,
1226         GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS,
1227         GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK,
1228         GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS,
1229         GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK,
1230         GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS,
1231         GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK,
1232         GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS,
1233         GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK,
1234         GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS,
1235         GAT_IMEM_WDT0_IPCLKPORT_CLK,
1236         GAT_IMEM_WDT1_IPCLKPORT_CLK,
1237         GAT_IMEM_WDT2_IPCLKPORT_CLK,
1238         GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM,
1239         GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM,
1240         GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM,
1241         GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS,
1242         GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS,
1243         GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS,
1244         GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM,
1245         GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS,
1246         GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM,
1247         GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS,
1248         GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK,
1249         GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK,
1250         GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK,
1251         GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK,
1252         GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK,
1253         GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK,
1254         GAT_IMEM_DMA0_IPCLKPORT_ACLK,
1255         GAT_IMEM_DMA1_IPCLKPORT_ACLK,
1256         GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK,
1257         GAT_IMEM_GIC_IPCLKPORT_CLK,
1258         GAT_IMEM_INTMEM_IPCLKPORT_ACLK,
1259         GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK,
1260         GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK,
1261         GAT_IMEM_MCT_IPCLKPORT_PCLK,
1262         GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D,
1263         GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU,
1264         GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P,
1265         GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK,
1266         GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK,
1267         GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK,
1268         GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK,
1269         GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK,
1270         GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK,
1271         GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK,
1272         GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK,
1273         GAT_IMEM_TCU_IPCLKPORT_ACLK,
1274         GAT_IMEM_WDT0_IPCLKPORT_PCLK,
1275         GAT_IMEM_WDT1_IPCLKPORT_PCLK,
1276         GAT_IMEM_WDT2_IPCLKPORT_PCLK,
1277 };
1278
1279 PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" };
1280 PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" };
1281 PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" };
1282
1283 static const struct samsung_mux_clock imem_mux_clks[] __initconst = {
1284         MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,
1285             PLL_CON0_CLK_IMEM_TCUCLK, 4, 1),
1286         MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1),
1287         MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,
1288             PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1),
1289 };
1290
1291 static const struct samsung_div_clock imem_div_clks[] __initconst = {
1292         DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),
1293 };
1294
1295 static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
1296         GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1297              GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1298         GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",
1299              GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
1300         GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",
1301              GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1302         GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
1303              GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1304         GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",
1305              GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1306         GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",
1307              GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1308         GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",
1309              GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0),
1310         GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
1311              GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1312         GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
1313              GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1314         GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
1315              GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1316         GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts",
1317              "dout_imem_oscclk_imem_tmutsclk",
1318              GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1319         GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts",
1320              "dout_imem_oscclk_imem_tmutsclk",
1321              GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1322         GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts",
1323              "dout_imem_oscclk_imem_tmutsclk",
1324              GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1325         GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts",
1326              "dout_imem_oscclk_imem_tmutsclk",
1327              GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1328         GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts",
1329              "dout_imem_oscclk_imem_tmutsclk",
1330              GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1331         GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
1332              GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
1333         GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
1334              GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
1335         GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
1336              GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
1337         GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
1338              GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
1339         GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
1340              GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
1341         GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
1342              GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
1343         GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
1344              GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
1345         GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk",
1346              GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
1347         GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
1348              GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
1349         GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk",
1350              GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
1351         GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk",
1352              GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1353         GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk",
1354              GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1355         GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk",
1356              GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
1357         GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk",
1358              GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
1359         GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk",
1360              GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
1361         GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk",
1362              GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
1363         GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
1364              GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
1365         GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
1366              GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
1367         GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk",
1368              GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1369         GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk",
1370              GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1371         GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk",
1372              GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1373         GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1374              GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1375         GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1376              GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1377         GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1378              GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1379         GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d",
1380              "mout_imem_clk_imem_tcuclk",
1381              GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0),
1382         GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu",
1383              "mout_imem_clk_imem_tcuclk",
1384              GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21,
1385              CLK_IGNORE_UNUSED, 0),
1386         GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk",
1387              GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0),
1388         GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1389              GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1390         GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk",
1391              GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1392         GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",
1393              GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1394         GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk",
1395              GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1396         GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk",
1397              GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1398         GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1399              GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1400         GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1401              GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1402         GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",
1403              GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1404         GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1405              GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1406         GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
1407              GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1408         GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
1409              GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1410         GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1411              GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1412         GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1413              GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1414         GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1415              GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1416 };
1417
1418 static const struct samsung_cmu_info imem_cmu_info __initconst = {
1419         .mux_clks               = imem_mux_clks,
1420         .nr_mux_clks            = ARRAY_SIZE(imem_mux_clks),
1421         .div_clks               = imem_div_clks,
1422         .nr_div_clks            = ARRAY_SIZE(imem_div_clks),
1423         .gate_clks              = imem_gate_clks,
1424         .nr_gate_clks           = ARRAY_SIZE(imem_gate_clks),
1425         .nr_clk_ids             = CLKS_NR_IMEM,
1426         .clk_regs               = imem_clk_regs,
1427         .nr_clk_regs            = ARRAY_SIZE(imem_clk_regs),
1428 };
1429
1430 static void __init fsd_clk_imem_init(struct device_node *np)
1431 {
1432         samsung_cmu_register_one(np, &imem_cmu_info);
1433 }
1434
1435 CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
1436
1437 /* Register Offset definitions for CMU_MFC (0x12810000) */
1438 #define PLL_LOCKTIME_PLL_MFC                                    0x0
1439 #define PLL_CON0_PLL_MFC                                        0x100
1440 #define MUX_MFC_BUSD                                            0x1000
1441 #define MUX_MFC_BUSP                                            0x1008
1442 #define DIV_MFC_BUSD_DIV4                                       0x1800
1443 #define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK                          0x2000
1444 #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM                        0x2004
1445 #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS                        0x2008
1446 #define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK                      0x200c
1447 #define GAT_MFC_MFC_IPCLKPORT_ACLK                              0x2010
1448 #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D      0x2018
1449 #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P      0x201c
1450 #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK                       0x2028
1451 #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK                       0x202c
1452 #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK                       0x2030
1453 #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK                       0x2034
1454 #define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK                       0x2038
1455 #define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK                         0x203c
1456 #define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK                         0x2040
1457 #define GAT_MFC_BUSD_DIV4_GATE                                  0x2044
1458 #define GAT_MFC_BUSD_GATE                                       0x2048
1459
1460 static const unsigned long mfc_clk_regs[] __initconst = {
1461         PLL_LOCKTIME_PLL_MFC,
1462         PLL_CON0_PLL_MFC,
1463         MUX_MFC_BUSD,
1464         MUX_MFC_BUSP,
1465         DIV_MFC_BUSD_DIV4,
1466         GAT_MFC_CMU_MFC_IPCLKPORT_PCLK,
1467         GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM,
1468         GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS,
1469         GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK,
1470         GAT_MFC_MFC_IPCLKPORT_ACLK,
1471         GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D,
1472         GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P,
1473         GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK,
1474         GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK,
1475         GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK,
1476         GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK,
1477         GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK,
1478         GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK,
1479         GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK,
1480         GAT_MFC_BUSD_DIV4_GATE,
1481         GAT_MFC_BUSD_GATE,
1482 };
1483
1484 static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = {
1485         PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0),
1486 };
1487
1488 static const struct samsung_pll_clock mfc_pll_clks[] __initconst = {
1489         PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
1490             PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table),
1491 };
1492
1493 PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" };
1494 PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" };
1495 PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" };
1496
1497 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
1498         MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1),
1499         MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1),
1500         MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1),
1501 };
1502
1503 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
1504         DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4),
1505 };
1506
1507 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
1508         GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp",
1509              GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1510         GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd",
1511              GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
1512         GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp",
1513              GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
1514         GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp",
1515              GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1516         GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd",
1517              GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1518         GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd",
1519              GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0),
1520         GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp",
1521              GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0),
1522         GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd",
1523              GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1524         GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp",
1525              GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1526         GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd",
1527              GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1528         GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp",
1529              GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1530         GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp",
1531              GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1532         GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd",
1533              GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1534         GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd",
1535              GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1536         GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll",
1537              GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
1538         GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0),
1539 };
1540
1541 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
1542         .pll_clks               = mfc_pll_clks,
1543         .nr_pll_clks            = ARRAY_SIZE(mfc_pll_clks),
1544         .mux_clks               = mfc_mux_clks,
1545         .nr_mux_clks            = ARRAY_SIZE(mfc_mux_clks),
1546         .div_clks               = mfc_div_clks,
1547         .nr_div_clks            = ARRAY_SIZE(mfc_div_clks),
1548         .gate_clks              = mfc_gate_clks,
1549         .nr_gate_clks           = ARRAY_SIZE(mfc_gate_clks),
1550         .nr_clk_ids             = CLKS_NR_MFC,
1551         .clk_regs               = mfc_clk_regs,
1552         .nr_clk_regs            = ARRAY_SIZE(mfc_clk_regs),
1553 };
1554
1555 /* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
1556 #define PLL_LOCKTIME_PLL_CAM_CSI                0x0
1557 #define PLL_CON0_PLL_CAM_CSI                    0x100
1558 #define DIV_CAM_CSI0_ACLK                       0x1800
1559 #define DIV_CAM_CSI1_ACLK                       0x1804
1560 #define DIV_CAM_CSI2_ACLK                       0x1808
1561 #define DIV_CAM_CSI_BUSD                        0x180c
1562 #define DIV_CAM_CSI_BUSP                        0x1810
1563 #define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK  0x2000
1564 #define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK  0x2004
1565 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0       0x2008
1566 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1       0x200c
1567 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2       0x2010
1568 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC    0x2014
1569 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC            0x2018
1570 #define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK         0x201c
1571 #define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK         0x2020
1572 #define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK         0x2024
1573 #define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK         0x2028
1574 #define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK         0x202c
1575 #define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK         0x2030
1576 #define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK         0x2034
1577 #define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK         0x2038
1578 #define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK         0x203c
1579 #define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK         0x2040
1580 #define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK         0x2044
1581 #define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK         0x2048
1582 #define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK         0x204c
1583 #define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK         0x2050
1584 #define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK         0x2054
1585 #define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK         0x2058
1586 #define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK         0x205c
1587 #define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK         0x2060
1588 #define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK         0x2064
1589 #define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK         0x2068
1590 #define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK         0x206c
1591 #define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK         0x2070
1592 #define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK         0x2074
1593 #define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK         0x2078
1594 #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D      0x207c
1595 #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P      0x2080
1596 #define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK   0x2084
1597 #define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK      0x2088
1598
1599 static const unsigned long cam_csi_clk_regs[] __initconst = {
1600         PLL_LOCKTIME_PLL_CAM_CSI,
1601         PLL_CON0_PLL_CAM_CSI,
1602         DIV_CAM_CSI0_ACLK,
1603         DIV_CAM_CSI1_ACLK,
1604         DIV_CAM_CSI2_ACLK,
1605         DIV_CAM_CSI_BUSD,
1606         DIV_CAM_CSI_BUSP,
1607         GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
1608         GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
1609         GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
1610         GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
1611         GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
1612         GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
1613         GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
1614         GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
1615         GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
1616         GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
1617         GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
1618         GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
1619         GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
1620         GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
1621         GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
1622         GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
1623         GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
1624         GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
1625         GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
1626         GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
1627         GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
1628         GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
1629         GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
1630         GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
1631         GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
1632         GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
1633         GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
1634         GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
1635         GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
1636         GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
1637         GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
1638         GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
1639         GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
1640         GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
1641         GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
1642 };
1643
1644 static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
1645         PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0),
1646 };
1647
1648 static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
1649         PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
1650             PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
1651 };
1652
1653 PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
1654
1655 static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
1656         MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
1657 };
1658
1659 static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
1660         DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
1661         DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
1662         DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
1663         DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
1664         DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
1665 };
1666
1667 static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
1668         GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
1669              GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1670         GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
1671              GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1672         GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
1673              GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
1674         GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
1675              GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
1676         GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
1677              GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
1678         GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
1679              GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
1680              CLK_IGNORE_UNUSED, 0),
1681         GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
1682              GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
1683         GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
1684              GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1685         GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1686              GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1687         GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
1688              GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1689         GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1690              GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1691         GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
1692              GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1693         GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1694              GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1695         GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
1696              GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1697         GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1698              GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1699         GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
1700              GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1701         GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1702              GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1703         GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
1704              GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1705         GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1706              GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1707         GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
1708              GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1709         GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1710              GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1711         GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
1712              GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1713         GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1714              GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1715         GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
1716              GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1717         GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1718              GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1719         GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
1720              GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1721         GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1722              GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1723         GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
1724              GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1725         GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1726              GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1727         GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
1728              GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1729         GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1730              GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1731         GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
1732              "dout_cam_csi_busd",
1733              GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
1734              CLK_IGNORE_UNUSED, 0),
1735         GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
1736              "dout_cam_csi_busp",
1737              GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
1738              CLK_IGNORE_UNUSED, 0),
1739         GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
1740              GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1741         GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
1742              GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1743 };
1744
1745 static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
1746         .pll_clks               = cam_csi_pll_clks,
1747         .nr_pll_clks            = ARRAY_SIZE(cam_csi_pll_clks),
1748         .mux_clks               = cam_csi_mux_clks,
1749         .nr_mux_clks            = ARRAY_SIZE(cam_csi_mux_clks),
1750         .div_clks               = cam_csi_div_clks,
1751         .nr_div_clks            = ARRAY_SIZE(cam_csi_div_clks),
1752         .gate_clks              = cam_csi_gate_clks,
1753         .nr_gate_clks           = ARRAY_SIZE(cam_csi_gate_clks),
1754         .nr_clk_ids             = CLKS_NR_CAM_CSI,
1755         .clk_regs               = cam_csi_clk_regs,
1756         .nr_clk_regs            = ARRAY_SIZE(cam_csi_clk_regs),
1757 };
1758
1759 /**
1760  * fsd_cmu_probe - Probe function for FSD platform clocks
1761  * @pdev: Pointer to platform device
1762  *
1763  * Configure clock hierarchy for clock domains of FSD platform
1764  */
1765 static int __init fsd_cmu_probe(struct platform_device *pdev)
1766 {
1767         const struct samsung_cmu_info *info;
1768         struct device *dev = &pdev->dev;
1769
1770         info = of_device_get_match_data(dev);
1771         exynos_arm64_register_cmu(dev, dev->of_node, info);
1772
1773         return 0;
1774 }
1775
1776 /* CMUs which belong to Power Domains and need runtime PM to be implemented */
1777 static const struct of_device_id fsd_cmu_of_match[] = {
1778         {
1779                 .compatible = "tesla,fsd-clock-peric",
1780                 .data = &peric_cmu_info,
1781         }, {
1782                 .compatible = "tesla,fsd-clock-fsys0",
1783                 .data = &fsys0_cmu_info,
1784         }, {
1785                 .compatible = "tesla,fsd-clock-fsys1",
1786                 .data = &fsys1_cmu_info,
1787         }, {
1788                 .compatible = "tesla,fsd-clock-mfc",
1789                 .data = &mfc_cmu_info,
1790         }, {
1791                 .compatible = "tesla,fsd-clock-cam_csi",
1792                 .data = &cam_csi_cmu_info,
1793         }, {
1794         },
1795 };
1796
1797 static struct platform_driver fsd_cmu_driver __refdata = {
1798         .driver = {
1799                 .name = "fsd-cmu",
1800                 .of_match_table = fsd_cmu_of_match,
1801                 .suppress_bind_attrs = true,
1802         },
1803         .probe = fsd_cmu_probe,
1804 };
1805
1806 static int __init fsd_cmu_init(void)
1807 {
1808         return platform_driver_register(&fsd_cmu_driver);
1809 }
1810 core_initcall(fsd_cmu_init);