drivers/clk/qcom/mmcc-msm8974.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset-controller.h>
  15
  16 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
  17 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-pll.h"
  22 #include "clk-rcg.h"
  23 #include "clk-branch.h"
  24 #include "reset.h"
  25 #include "gdsc.h"
  26
  27 enum {
  28         P_XO,
  29         P_MMPLL0,
  30         P_EDPLINK,
  31         P_MMPLL1,
  32         P_HDMIPLL,
  33         P_GPLL0,
  34         P_EDPVCO,
  35         P_GPLL1,
  36         P_DSI0PLL,
  37         P_DSI0PLL_BYTE,
  38         P_MMPLL2,
  39         P_MMPLL3,
  40         P_DSI1PLL,
  41         P_DSI1PLL_BYTE,
  42 };
  43
  44 static struct clk_pll mmpll0 = {
  45         .l_reg = 0x0004,
  46         .m_reg = 0x0008,
  47         .n_reg = 0x000c,
  48         .config_reg = 0x0014,
  49         .mode_reg = 0x0000,
  50         .status_reg = 0x001c,
  51         .status_bit = 17,
  52         .clkr.hw.init = &(struct clk_init_data){
  53                 .name = "mmpll0",
  54                 .parent_data = (const struct clk_parent_data[]){
  55                         { .fw_name = "xo", .name = "xo_board" },
  56                 },
  57                 .num_parents = 1,
  58                 .ops = &clk_pll_ops,
  59         },
  60 };
  61
  62 static struct clk_regmap mmpll0_vote = {
  63         .enable_reg = 0x0100,
  64         .enable_mask = BIT(0),
  65         .hw.init = &(struct clk_init_data){
  66                 .name = "mmpll0_vote",
  67                 .parent_hws = (const struct clk_hw*[]){
  68                         &mmpll0.clkr.hw
  69                 },
  70                 .num_parents = 1,
  71                 .ops = &clk_pll_vote_ops,
  72         },
  73 };
  74
  75 static struct clk_pll mmpll1 = {
  76         .l_reg = 0x0044,
  77         .m_reg = 0x0048,
  78         .n_reg = 0x004c,
  79         .config_reg = 0x0050,
  80         .mode_reg = 0x0040,
  81         .status_reg = 0x005c,
  82         .status_bit = 17,
  83         .clkr.hw.init = &(struct clk_init_data){
  84                 .name = "mmpll1",
  85                 .parent_data = (const struct clk_parent_data[]){
  86                         { .fw_name = "xo", .name = "xo_board" },
  87                 },
  88                 .num_parents = 1,
  89                 .ops = &clk_pll_ops,
  90         },
  91 };
  92
  93 static struct clk_regmap mmpll1_vote = {
  94         .enable_reg = 0x0100,
  95         .enable_mask = BIT(1),
  96         .hw.init = &(struct clk_init_data){
  97                 .name = "mmpll1_vote",
  98                 .parent_hws = (const struct clk_hw*[]){
  99                         &mmpll1.clkr.hw
 100                 },
 101                 .num_parents = 1,
 102                 .ops = &clk_pll_vote_ops,
 103         },
 104 };
 105
 106 static struct clk_pll mmpll2 = {
 107         .l_reg = 0x4104,
 108         .m_reg = 0x4108,
 109         .n_reg = 0x410c,
 110         .config_reg = 0x4110,
 111         .mode_reg = 0x4100,
 112         .status_reg = 0x411c,
 113         .clkr.hw.init = &(struct clk_init_data){
 114                 .name = "mmpll2",
 115                 .parent_data = (const struct clk_parent_data[]){
 116                         { .fw_name = "xo", .name = "xo_board" },
 117                 },
 118                 .num_parents = 1,
 119                 .ops = &clk_pll_ops,
 120         },
 121 };
 122
 123 static struct clk_pll mmpll3 = {
 124         .l_reg = 0x0084,
 125         .m_reg = 0x0088,
 126         .n_reg = 0x008c,
 127         .config_reg = 0x0090,
 128         .mode_reg = 0x0080,
 129         .status_reg = 0x009c,
 130         .status_bit = 17,
 131         .clkr.hw.init = &(struct clk_init_data){
 132                 .name = "mmpll3",
 133                 .parent_data = (const struct clk_parent_data[]){
 134                         { .fw_name = "xo", .name = "xo_board" },
 135                 },
 136                 .num_parents = 1,
 137                 .ops = &clk_pll_ops,
 138         },
 139 };
 140
 141 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
 142         { P_XO, 0 },
 143         { P_MMPLL0, 1 },
 144         { P_MMPLL1, 2 },
 145         { P_GPLL0, 5 }
 146 };
 147
 148 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
 149         { .fw_name = "xo", .name = "xo_board" },
 150         { .hw = &mmpll0_vote.hw },
 151         { .hw = &mmpll1_vote.hw },
 152         { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
 153 };
 154
 155 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
 156         { P_XO, 0 },
 157         { P_MMPLL0, 1 },
 158         { P_HDMIPLL, 4 },
 159         { P_GPLL0, 5 },
 160         { P_DSI0PLL, 2 },
 161         { P_DSI1PLL, 3 }
 162 };
 163
 164 static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
 165         { .fw_name = "xo", .name = "xo_board" },
 166         { .hw = &mmpll0_vote.hw },
 167         { .fw_name = "hdmipll", .name = "hdmipll" },
 168         { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
 169         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 170         { .fw_name = "dsi1pll", .name = "dsi1pll" },
 171 };
 172
 173 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
 174         { P_XO, 0 },
 175         { P_MMPLL0, 1 },
 176         { P_MMPLL1, 2 },
 177         { P_GPLL0, 5 },
 178         { P_MMPLL3, 3 }
 179 };
 180
 181 static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
 182         { .fw_name = "xo", .name = "xo_board" },
 183         { .hw = &mmpll0_vote.hw },
 184         { .hw = &mmpll1_vote.hw },
 185         { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
 186         { .hw = &mmpll3.clkr.hw },
 187 };
 188
 189 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
 190         { P_XO, 0 },
 191         { P_MMPLL0, 1 },
 192         { P_MMPLL1, 2 },
 193         { P_GPLL0, 5 },
 194         { P_GPLL1, 4 }
 195 };
 196
 197 static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
 198         { .fw_name = "xo", .name = "xo_board" },
 199         { .hw = &mmpll0_vote.hw },
 200         { .hw = &mmpll1_vote.hw },
 201         { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
 202         { .fw_name = "gpll1_vote", .name = "gpll1_vote" },
 203 };
 204
 205 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
 206         { P_XO, 0 },
 207         { P_EDPLINK, 4 },
 208         { P_HDMIPLL, 3 },
 209         { P_EDPVCO, 5 },
 210         { P_DSI0PLL, 1 },
 211         { P_DSI1PLL, 2 }
 212 };
 213
 214 static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
 215         { .fw_name = "xo", .name = "xo_board" },
 216         { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
 217         { .fw_name = "hdmipll", .name = "hdmipll" },
 218         { .fw_name = "edp_vco_div", .name = "edp_vco_div" },
 219         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 220         { .fw_name = "dsi1pll", .name = "dsi1pll" },
 221 };
 222
 223 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
 224         { P_XO, 0 },
 225         { P_EDPLINK, 4 },
 226         { P_HDMIPLL, 3 },
 227         { P_GPLL0, 5 },
 228         { P_DSI0PLL, 1 },
 229         { P_DSI1PLL, 2 }
 230 };
 231
 232 static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
 233         { .fw_name = "xo", .name = "xo_board" },
 234         { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
 235         { .fw_name = "hdmipll", .name = "hdmipll" },
 236         { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
 237         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 238         { .fw_name = "dsi1pll", .name = "dsi1pll" },
 239 };
 240
 241 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
 242         { P_XO, 0 },
 243         { P_EDPLINK, 4 },
 244         { P_HDMIPLL, 3 },
 245         { P_GPLL0, 5 },
 246         { P_DSI0PLL_BYTE, 1 },
 247         { P_DSI1PLL_BYTE, 2 }
 248 };
 249
 250 static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
 251         { .fw_name = "xo", .name = "xo_board" },
 252         { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
 253         { .fw_name = "hdmipll", .name = "hdmipll" },
 254         { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
 255         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 256         { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
 257 };
 258
 259 static struct clk_rcg2 mmss_ahb_clk_src = {
 260         .cmd_rcgr = 0x5000,
 261         .hid_width = 5,
 262         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 263         .clkr.hw.init = &(struct clk_init_data){
 264                 .name = "mmss_ahb_clk_src",
 265                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 266                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 267                 .ops = &clk_rcg2_ops,
 268         },
 269 };
 270
 271 static const struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
 272         F(19200000, P_XO, 1, 0, 0),
 273         F(37500000, P_GPLL0, 16, 0, 0),
 274         F(50000000, P_GPLL0, 12, 0, 0),
 275         F(75000000, P_GPLL0, 8, 0, 0),
 276         F(100000000, P_GPLL0, 6, 0, 0),
 277         F(150000000, P_GPLL0, 4, 0, 0),
 278         F(200000000, P_MMPLL0, 4, 0, 0),
 279         F(266666666, P_MMPLL0, 3, 0, 0),
 280         { }
 281 };
 282
 283 static const struct freq_tbl ftbl_mmss_axi_clk[] = {
 284         F( 19200000, P_XO, 1, 0, 0),
 285         F( 37500000, P_GPLL0, 16, 0, 0),
 286         F( 50000000, P_GPLL0, 12, 0, 0),
 287         F( 75000000, P_GPLL0, 8, 0, 0),
 288         F(100000000, P_GPLL0, 6, 0, 0),
 289         F(150000000, P_GPLL0, 4, 0, 0),
 290         F(291750000, P_MMPLL1, 4, 0, 0),
 291         F(400000000, P_MMPLL0, 2, 0, 0),
 292         F(466800000, P_MMPLL1, 2.5, 0, 0),
 293         { }
 294 };
 295
 296 static struct clk_rcg2 mmss_axi_clk_src = {
 297         .cmd_rcgr = 0x5040,
 298         .hid_width = 5,
 299         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 300         .freq_tbl = ftbl_mmss_axi_clk,
 301         .clkr.hw.init = &(struct clk_init_data){
 302                 .name = "mmss_axi_clk_src",
 303                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 304                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 305                 .ops = &clk_rcg2_ops,
 306         },
 307 };
 308
 309 static const struct freq_tbl ftbl_ocmemnoc_clk[] = {
 310         F( 19200000, P_XO, 1, 0, 0),
 311         F( 37500000, P_GPLL0, 16, 0, 0),
 312         F( 50000000, P_GPLL0, 12, 0, 0),
 313         F( 75000000, P_GPLL0, 8, 0, 0),
 314         F(100000000, P_GPLL0, 6, 0, 0),
 315         F(150000000, P_GPLL0, 4, 0, 0),
 316         F(291750000, P_MMPLL1, 4, 0, 0),
 317         F(400000000, P_MMPLL0, 2, 0, 0),
 318         { }
 319 };
 320
 321 static struct clk_rcg2 ocmemnoc_clk_src = {
 322         .cmd_rcgr = 0x5090,
 323         .hid_width = 5,
 324         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 325         .freq_tbl = ftbl_ocmemnoc_clk,
 326         .clkr.hw.init = &(struct clk_init_data){
 327                 .name = "ocmemnoc_clk_src",
 328                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 329                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 330                 .ops = &clk_rcg2_ops,
 331         },
 332 };
 333
 334 static const struct freq_tbl ftbl_camss_csi0_3_clk[] = {
 335         F(100000000, P_GPLL0, 6, 0, 0),
 336         F(200000000, P_MMPLL0, 4, 0, 0),
 337         { }
 338 };
 339
 340 static struct clk_rcg2 csi0_clk_src = {
 341         .cmd_rcgr = 0x3090,
 342         .hid_width = 5,
 343         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 344         .freq_tbl = ftbl_camss_csi0_3_clk,
 345         .clkr.hw.init = &(struct clk_init_data){
 346                 .name = "csi0_clk_src",
 347                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 348                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 349                 .ops = &clk_rcg2_ops,
 350         },
 351 };
 352
 353 static struct clk_rcg2 csi1_clk_src = {
 354         .cmd_rcgr = 0x3100,
 355         .hid_width = 5,
 356         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 357         .freq_tbl = ftbl_camss_csi0_3_clk,
 358         .clkr.hw.init = &(struct clk_init_data){
 359                 .name = "csi1_clk_src",
 360                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 361                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 362                 .ops = &clk_rcg2_ops,
 363         },
 364 };
 365
 366 static struct clk_rcg2 csi2_clk_src = {
 367         .cmd_rcgr = 0x3160,
 368         .hid_width = 5,
 369         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 370         .freq_tbl = ftbl_camss_csi0_3_clk,
 371         .clkr.hw.init = &(struct clk_init_data){
 372                 .name = "csi2_clk_src",
 373                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 374                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 375                 .ops = &clk_rcg2_ops,
 376         },
 377 };
 378
 379 static struct clk_rcg2 csi3_clk_src = {
 380         .cmd_rcgr = 0x31c0,
 381         .hid_width = 5,
 382         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 383         .freq_tbl = ftbl_camss_csi0_3_clk,
 384         .clkr.hw.init = &(struct clk_init_data){
 385                 .name = "csi3_clk_src",
 386                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 387                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 388                 .ops = &clk_rcg2_ops,
 389         },
 390 };
 391
 392 static const struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
 393         F(37500000, P_GPLL0, 16, 0, 0),
 394         F(50000000, P_GPLL0, 12, 0, 0),
 395         F(60000000, P_GPLL0, 10, 0, 0),
 396         F(80000000, P_GPLL0, 7.5, 0, 0),
 397         F(100000000, P_GPLL0, 6, 0, 0),
 398         F(109090000, P_GPLL0, 5.5, 0, 0),
 399         F(133330000, P_GPLL0, 4.5, 0, 0),
 400         F(150000000, P_GPLL0, 4, 0, 0),
 401         F(200000000, P_GPLL0, 3, 0, 0),
 402         F(228570000, P_MMPLL0, 3.5, 0, 0),
 403         F(266670000, P_MMPLL0, 3, 0, 0),
 404         F(320000000, P_MMPLL0, 2.5, 0, 0),
 405         F(400000000, P_MMPLL0, 2, 0, 0),
 406         { }
 407 };
 408
 409 static const struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
 410         F(37500000, P_GPLL0, 16, 0, 0),
 411         F(50000000, P_GPLL0, 12, 0, 0),
 412         F(60000000, P_GPLL0, 10, 0, 0),
 413         F(80000000, P_GPLL0, 7.5, 0, 0),
 414         F(100000000, P_GPLL0, 6, 0, 0),
 415         F(109090000, P_GPLL0, 5.5, 0, 0),
 416         F(133330000, P_GPLL0, 4.5, 0, 0),
 417         F(200000000, P_GPLL0, 3, 0, 0),
 418         F(228570000, P_MMPLL0, 3.5, 0, 0),
 419         F(266670000, P_MMPLL0, 3, 0, 0),
 420         F(320000000, P_MMPLL0, 2.5, 0, 0),
 421         F(400000000, P_MMPLL0, 2, 0, 0),
 422         F(465000000, P_MMPLL3, 2, 0, 0),
 423         { }
 424 };
 425
 426 static struct clk_rcg2 vfe0_clk_src = {
 427         .cmd_rcgr = 0x3600,
 428         .hid_width = 5,
 429         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 430         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 431         .clkr.hw.init = &(struct clk_init_data){
 432                 .name = "vfe0_clk_src",
 433                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 434                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 435                 .ops = &clk_rcg2_ops,
 436         },
 437 };
 438
 439 static struct clk_rcg2 vfe1_clk_src = {
 440         .cmd_rcgr = 0x3620,
 441         .hid_width = 5,
 442         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 443         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 444         .clkr.hw.init = &(struct clk_init_data){
 445                 .name = "vfe1_clk_src",
 446                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 447                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 448                 .ops = &clk_rcg2_ops,
 449         },
 450 };
 451
 452 static const struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
 453         F(37500000, P_GPLL0, 16, 0, 0),
 454         F(60000000, P_GPLL0, 10, 0, 0),
 455         F(75000000, P_GPLL0, 8, 0, 0),
 456         F(92310000, P_GPLL0, 6.5, 0, 0),
 457         F(100000000, P_GPLL0, 6, 0, 0),
 458         F(133330000, P_MMPLL0, 6, 0, 0),
 459         F(177780000, P_MMPLL0, 4.5, 0, 0),
 460         F(200000000, P_MMPLL0, 4, 0, 0),
 461         { }
 462 };
 463
 464 static const struct freq_tbl ftbl_mdss_mdp_clk[] = {
 465         F(37500000, P_GPLL0, 16, 0, 0),
 466         F(60000000, P_GPLL0, 10, 0, 0),
 467         F(75000000, P_GPLL0, 8, 0, 0),
 468         F(85710000, P_GPLL0, 7, 0, 0),
 469         F(100000000, P_GPLL0, 6, 0, 0),
 470         F(133330000, P_MMPLL0, 6, 0, 0),
 471         F(160000000, P_MMPLL0, 5, 0, 0),
 472         F(200000000, P_MMPLL0, 4, 0, 0),
 473         F(228570000, P_MMPLL0, 3.5, 0, 0),
 474         F(240000000, P_GPLL0, 2.5, 0, 0),
 475         F(266670000, P_MMPLL0, 3, 0, 0),
 476         F(320000000, P_MMPLL0, 2.5, 0, 0),
 477         { }
 478 };
 479
 480 static struct clk_rcg2 mdp_clk_src = {
 481         .cmd_rcgr = 0x2040,
 482         .hid_width = 5,
 483         .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
 484         .freq_tbl = ftbl_mdss_mdp_clk,
 485         .clkr.hw.init = &(struct clk_init_data){
 486                 .name = "mdp_clk_src",
 487                 .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
 488                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
 489                 .ops = &clk_rcg2_shared_ops,
 490         },
 491 };
 492
 493 static const struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
 494         F(75000000, P_GPLL0, 8, 0, 0),
 495         F(133330000, P_GPLL0, 4.5, 0, 0),
 496         F(200000000, P_GPLL0, 3, 0, 0),
 497         F(228570000, P_MMPLL0, 3.5, 0, 0),
 498         F(266670000, P_MMPLL0, 3, 0, 0),
 499         F(320000000, P_MMPLL0, 2.5, 0, 0),
 500         { }
 501 };
 502
 503 static struct clk_rcg2 jpeg0_clk_src = {
 504         .cmd_rcgr = 0x3500,
 505         .hid_width = 5,
 506         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 507         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 508         .clkr.hw.init = &(struct clk_init_data){
 509                 .name = "jpeg0_clk_src",
 510                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 511                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 512                 .ops = &clk_rcg2_ops,
 513         },
 514 };
 515
 516 static struct clk_rcg2 jpeg1_clk_src = {
 517         .cmd_rcgr = 0x3520,
 518         .hid_width = 5,
 519         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 520         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 521         .clkr.hw.init = &(struct clk_init_data){
 522                 .name = "jpeg1_clk_src",
 523                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 524                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 525                 .ops = &clk_rcg2_ops,
 526         },
 527 };
 528
 529 static struct clk_rcg2 jpeg2_clk_src = {
 530         .cmd_rcgr = 0x3540,
 531         .hid_width = 5,
 532         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 533         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 534         .clkr.hw.init = &(struct clk_init_data){
 535                 .name = "jpeg2_clk_src",
 536                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 537                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 538                 .ops = &clk_rcg2_ops,
 539         },
 540 };
 541
 542 static struct clk_rcg2 pclk0_clk_src = {
 543         .cmd_rcgr = 0x2000,
 544         .mnd_width = 8,
 545         .hid_width = 5,
 546         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 547         .clkr.hw.init = &(struct clk_init_data){
 548                 .name = "pclk0_clk_src",
 549                 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
 550                 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 551                 .ops = &clk_pixel_ops,
 552                 .flags = CLK_SET_RATE_PARENT,
 553         },
 554 };
 555
 556 static struct clk_rcg2 pclk1_clk_src = {
 557         .cmd_rcgr = 0x2020,
 558         .mnd_width = 8,
 559         .hid_width = 5,
 560         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 561         .clkr.hw.init = &(struct clk_init_data){
 562                 .name = "pclk1_clk_src",
 563                 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
 564                 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 565                 .ops = &clk_pixel_ops,
 566                 .flags = CLK_SET_RATE_PARENT,
 567         },
 568 };
 569
 570 static const struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
 571         F(66700000, P_GPLL0, 9, 0, 0),
 572         F(100000000, P_GPLL0, 6, 0, 0),
 573         F(133330000, P_MMPLL0, 6, 0, 0),
 574         F(160000000, P_MMPLL0, 5, 0, 0),
 575         { }
 576 };
 577
 578 static const struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
 579         F(50000000, P_GPLL0, 12, 0, 0),
 580         F(100000000, P_GPLL0, 6, 0, 0),
 581         F(133330000, P_MMPLL0, 6, 0, 0),
 582         F(200000000, P_MMPLL0, 4, 0, 0),
 583         F(266670000, P_MMPLL0, 3, 0, 0),
 584         F(465000000, P_MMPLL3, 2, 0, 0),
 585         { }
 586 };
 587
 588 static struct clk_rcg2 vcodec0_clk_src = {
 589         .cmd_rcgr = 0x1000,
 590         .mnd_width = 8,
 591         .hid_width = 5,
 592         .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
 593         .freq_tbl = ftbl_venus0_vcodec0_clk,
 594         .clkr.hw.init = &(struct clk_init_data){
 595                 .name = "vcodec0_clk_src",
 596                 .parent_data = mmcc_xo_mmpll0_1_3_gpll0,
 597                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
 598                 .ops = &clk_rcg2_ops,
 599         },
 600 };
 601
 602 static const struct freq_tbl ftbl_camss_cci_cci_clk[] = {
 603         F(19200000, P_XO, 1, 0, 0),
 604         { }
 605 };
 606
 607 static struct clk_rcg2 cci_clk_src = {
 608         .cmd_rcgr = 0x3300,
 609         .hid_width = 5,
 610         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 611         .freq_tbl = ftbl_camss_cci_cci_clk,
 612         .clkr.hw.init = &(struct clk_init_data){
 613                 .name = "cci_clk_src",
 614                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 615                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 616                 .ops = &clk_rcg2_ops,
 617         },
 618 };
 619
 620 static const struct freq_tbl ftbl_camss_gp0_1_clk[] = {
 621         F(10000, P_XO, 16, 1, 120),
 622         F(24000, P_XO, 16, 1, 50),
 623         F(6000000, P_GPLL0, 10, 1, 10),
 624         F(12000000, P_GPLL0, 10, 1, 5),
 625         F(13000000, P_GPLL0, 4, 13, 150),
 626         F(24000000, P_GPLL0, 5, 1, 5),
 627         { }
 628 };
 629
 630 static struct clk_rcg2 camss_gp0_clk_src = {
 631         .cmd_rcgr = 0x3420,
 632         .mnd_width = 8,
 633         .hid_width = 5,
 634         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 635         .freq_tbl = ftbl_camss_gp0_1_clk,
 636         .clkr.hw.init = &(struct clk_init_data){
 637                 .name = "camss_gp0_clk_src",
 638                 .parent_data = mmcc_xo_mmpll0_1_gpll1_0,
 639                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
 640                 .ops = &clk_rcg2_ops,
 641         },
 642 };
 643
 644 static struct clk_rcg2 camss_gp1_clk_src = {
 645         .cmd_rcgr = 0x3450,
 646         .mnd_width = 8,
 647         .hid_width = 5,
 648         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 649         .freq_tbl = ftbl_camss_gp0_1_clk,
 650         .clkr.hw.init = &(struct clk_init_data){
 651                 .name = "camss_gp1_clk_src",
 652                 .parent_data = mmcc_xo_mmpll0_1_gpll1_0,
 653                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
 654                 .ops = &clk_rcg2_ops,
 655         },
 656 };
 657
 658 static const struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
 659         F(19200000, P_XO, 1, 0, 0),
 660         F(24000000, P_GPLL0, 5, 1, 5),
 661         F(66670000, P_GPLL0, 9, 0, 0),
 662         { }
 663 };
 664
 665 static const struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
 666         F(4800000, P_XO, 4, 0, 0),
 667         F(6000000, P_GPLL0, 10, 1, 10),
 668         F(8000000, P_GPLL0, 15, 1, 5),
 669         F(9600000, P_XO, 2, 0, 0),
 670         F(16000000, P_GPLL0, 12.5, 1, 3),
 671         F(19200000, P_XO, 1, 0, 0),
 672         F(24000000, P_GPLL0, 5, 1, 5),
 673         F(32000000, P_MMPLL0, 5, 1, 5),
 674         F(48000000, P_GPLL0, 12.5, 0, 0),
 675         F(64000000, P_MMPLL0, 12.5, 0, 0),
 676         F(66670000, P_GPLL0, 9, 0, 0),
 677         { }
 678 };
 679
 680 static struct clk_rcg2 mclk0_clk_src = {
 681         .cmd_rcgr = 0x3360,
 682         .hid_width = 5,
 683         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 684         .freq_tbl = ftbl_camss_mclk0_3_clk,
 685         .clkr.hw.init = &(struct clk_init_data){
 686                 .name = "mclk0_clk_src",
 687                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 688                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 689                 .ops = &clk_rcg2_ops,
 690         },
 691 };
 692
 693 static struct clk_rcg2 mclk1_clk_src = {
 694         .cmd_rcgr = 0x3390,
 695         .hid_width = 5,
 696         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 697         .freq_tbl = ftbl_camss_mclk0_3_clk,
 698         .clkr.hw.init = &(struct clk_init_data){
 699                 .name = "mclk1_clk_src",
 700                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 701                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 702                 .ops = &clk_rcg2_ops,
 703         },
 704 };
 705
 706 static struct clk_rcg2 mclk2_clk_src = {
 707         .cmd_rcgr = 0x33c0,
 708         .hid_width = 5,
 709         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 710         .freq_tbl = ftbl_camss_mclk0_3_clk,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "mclk2_clk_src",
 713                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 714                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 715                 .ops = &clk_rcg2_ops,
 716         },
 717 };
 718
 719 static struct clk_rcg2 mclk3_clk_src = {
 720         .cmd_rcgr = 0x33f0,
 721         .hid_width = 5,
 722         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 723         .freq_tbl = ftbl_camss_mclk0_3_clk,
 724         .clkr.hw.init = &(struct clk_init_data){
 725                 .name = "mclk3_clk_src",
 726                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 727                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 728                 .ops = &clk_rcg2_ops,
 729         },
 730 };
 731
 732 static const struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
 733         F(100000000, P_GPLL0, 6, 0, 0),
 734         F(200000000, P_MMPLL0, 4, 0, 0),
 735         { }
 736 };
 737
 738 static struct clk_rcg2 csi0phytimer_clk_src = {
 739         .cmd_rcgr = 0x3000,
 740         .hid_width = 5,
 741         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 742         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 743         .clkr.hw.init = &(struct clk_init_data){
 744                 .name = "csi0phytimer_clk_src",
 745                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 746                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 747                 .ops = &clk_rcg2_ops,
 748         },
 749 };
 750
 751 static struct clk_rcg2 csi1phytimer_clk_src = {
 752         .cmd_rcgr = 0x3030,
 753         .hid_width = 5,
 754         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 755         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 756         .clkr.hw.init = &(struct clk_init_data){
 757                 .name = "csi1phytimer_clk_src",
 758                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 759                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 760                 .ops = &clk_rcg2_ops,
 761         },
 762 };
 763
 764 static struct clk_rcg2 csi2phytimer_clk_src = {
 765         .cmd_rcgr = 0x3060,
 766         .hid_width = 5,
 767         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 768         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 769         .clkr.hw.init = &(struct clk_init_data){
 770                 .name = "csi2phytimer_clk_src",
 771                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 772                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 773                 .ops = &clk_rcg2_ops,
 774         },
 775 };
 776
 777 static const struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
 778         F(133330000, P_GPLL0, 4.5, 0, 0),
 779         F(150000000, P_GPLL0, 4, 0, 0),
 780         F(266670000, P_MMPLL0, 3, 0, 0),
 781         F(320000000, P_MMPLL0, 2.5, 0, 0),
 782         F(400000000, P_MMPLL0, 2, 0, 0),
 783         { }
 784 };
 785
 786 static const struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
 787         F(133330000, P_GPLL0, 4.5, 0, 0),
 788         F(266670000, P_MMPLL0, 3, 0, 0),
 789         F(320000000, P_MMPLL0, 2.5, 0, 0),
 790         F(400000000, P_MMPLL0, 2, 0, 0),
 791         F(465000000, P_MMPLL3, 2, 0, 0),
 792         { }
 793 };
 794
 795 static struct clk_rcg2 cpp_clk_src = {
 796         .cmd_rcgr = 0x3640,
 797         .hid_width = 5,
 798         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 799         .freq_tbl = ftbl_camss_vfe_cpp_clk,
 800         .clkr.hw.init = &(struct clk_init_data){
 801                 .name = "cpp_clk_src",
 802                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 803                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 804                 .ops = &clk_rcg2_ops,
 805         },
 806 };
 807
 808 static const struct freq_tbl byte_freq_tbl[] = {
 809         { .src = P_DSI0PLL_BYTE },
 810         { }
 811 };
 812
 813 static struct clk_rcg2 byte0_clk_src = {
 814         .cmd_rcgr = 0x2120,
 815         .hid_width = 5,
 816         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 817         .freq_tbl = byte_freq_tbl,
 818         .clkr.hw.init = &(struct clk_init_data){
 819                 .name = "byte0_clk_src",
 820                 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 821                 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 822                 .ops = &clk_byte2_ops,
 823                 .flags = CLK_SET_RATE_PARENT,
 824         },
 825 };
 826
 827 static struct clk_rcg2 byte1_clk_src = {
 828         .cmd_rcgr = 0x2140,
 829         .hid_width = 5,
 830         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 831         .freq_tbl = byte_freq_tbl,
 832         .clkr.hw.init = &(struct clk_init_data){
 833                 .name = "byte1_clk_src",
 834                 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 835                 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 836                 .ops = &clk_byte2_ops,
 837                 .flags = CLK_SET_RATE_PARENT,
 838         },
 839 };
 840
 841 static const struct freq_tbl ftbl_mdss_edpaux_clk[] = {
 842         F(19200000, P_XO, 1, 0, 0),
 843         { }
 844 };
 845
 846 static struct clk_rcg2 edpaux_clk_src = {
 847         .cmd_rcgr = 0x20e0,
 848         .hid_width = 5,
 849         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 850         .freq_tbl = ftbl_mdss_edpaux_clk,
 851         .clkr.hw.init = &(struct clk_init_data){
 852                 .name = "edpaux_clk_src",
 853                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 854                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 855                 .ops = &clk_rcg2_ops,
 856         },
 857 };
 858
 859 static const struct freq_tbl ftbl_mdss_edplink_clk[] = {
 860         F(135000000, P_EDPLINK, 2, 0, 0),
 861         F(270000000, P_EDPLINK, 11, 0, 0),
 862         { }
 863 };
 864
 865 static struct clk_rcg2 edplink_clk_src = {
 866         .cmd_rcgr = 0x20c0,
 867         .hid_width = 5,
 868         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 869         .freq_tbl = ftbl_mdss_edplink_clk,
 870         .clkr.hw.init = &(struct clk_init_data){
 871                 .name = "edplink_clk_src",
 872                 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
 873                 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 874                 .ops = &clk_rcg2_ops,
 875                 .flags = CLK_SET_RATE_PARENT,
 876         },
 877 };
 878
 879 static const struct freq_tbl edp_pixel_freq_tbl[] = {
 880         { .src = P_EDPVCO },
 881         { }
 882 };
 883
 884 static struct clk_rcg2 edppixel_clk_src = {
 885         .cmd_rcgr = 0x20a0,
 886         .mnd_width = 8,
 887         .hid_width = 5,
 888         .parent_map = mmcc_xo_dsi_hdmi_edp_map,
 889         .freq_tbl = edp_pixel_freq_tbl,
 890         .clkr.hw.init = &(struct clk_init_data){
 891                 .name = "edppixel_clk_src",
 892                 .parent_data = mmcc_xo_dsi_hdmi_edp,
 893                 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
 894                 .ops = &clk_edp_pixel_ops,
 895         },
 896 };
 897
 898 static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 899         F(19200000, P_XO, 1, 0, 0),
 900         { }
 901 };
 902
 903 static struct clk_rcg2 esc0_clk_src = {
 904         .cmd_rcgr = 0x2160,
 905         .hid_width = 5,
 906         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 907         .freq_tbl = ftbl_mdss_esc0_1_clk,
 908         .clkr.hw.init = &(struct clk_init_data){
 909                 .name = "esc0_clk_src",
 910                 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 911                 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 912                 .ops = &clk_rcg2_ops,
 913         },
 914 };
 915
 916 static struct clk_rcg2 esc1_clk_src = {
 917         .cmd_rcgr = 0x2180,
 918         .hid_width = 5,
 919         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 920         .freq_tbl = ftbl_mdss_esc0_1_clk,
 921         .clkr.hw.init = &(struct clk_init_data){
 922                 .name = "esc1_clk_src",
 923                 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 924                 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
 925                 .ops = &clk_rcg2_ops,
 926         },
 927 };
 928
 929 static const struct freq_tbl extpclk_freq_tbl[] = {
 930         { .src = P_HDMIPLL },
 931         { }
 932 };
 933
 934 static struct clk_rcg2 extpclk_clk_src = {
 935         .cmd_rcgr = 0x2060,
 936         .hid_width = 5,
 937         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 938         .freq_tbl = extpclk_freq_tbl,
 939         .clkr.hw.init = &(struct clk_init_data){
 940                 .name = "extpclk_clk_src",
 941                 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
 942                 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
 943                 .ops = &clk_byte_ops,
 944                 .flags = CLK_SET_RATE_PARENT,
 945         },
 946 };
 947
 948 static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 949         F(19200000, P_XO, 1, 0, 0),
 950         { }
 951 };
 952
 953 static struct clk_rcg2 hdmi_clk_src = {
 954         .cmd_rcgr = 0x2100,
 955         .hid_width = 5,
 956         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 957         .freq_tbl = ftbl_mdss_hdmi_clk,
 958         .clkr.hw.init = &(struct clk_init_data){
 959                 .name = "hdmi_clk_src",
 960                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 961                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 962                 .ops = &clk_rcg2_ops,
 963         },
 964 };
 965
 966 static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
 967         F(19200000, P_XO, 1, 0, 0),
 968         { }
 969 };
 970
 971 static struct clk_rcg2 vsync_clk_src = {
 972         .cmd_rcgr = 0x2080,
 973         .hid_width = 5,
 974         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 975         .freq_tbl = ftbl_mdss_vsync_clk,
 976         .clkr.hw.init = &(struct clk_init_data){
 977                 .name = "vsync_clk_src",
 978                 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
 979                 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
 980                 .ops = &clk_rcg2_ops,
 981         },
 982 };
 983
 984 static struct clk_branch camss_cci_cci_ahb_clk = {
 985         .halt_reg = 0x3348,
 986         .clkr = {
 987                 .enable_reg = 0x3348,
 988                 .enable_mask = BIT(0),
 989                 .hw.init = &(struct clk_init_data){
 990                         .name = "camss_cci_cci_ahb_clk",
 991                         .parent_hws = (const struct clk_hw*[]){
 992                                 &mmss_ahb_clk_src.clkr.hw
 993                         },
 994                         .num_parents = 1,
 995                         .ops = &clk_branch2_ops,
 996                 },
 997         },
 998 };
 999
1000 static struct clk_branch camss_cci_cci_clk = {
1001         .halt_reg = 0x3344,
1002         .clkr = {
1003                 .enable_reg = 0x3344,
1004                 .enable_mask = BIT(0),
1005                 .hw.init = &(struct clk_init_data){
1006                         .name = "camss_cci_cci_clk",
1007                         .parent_hws = (const struct clk_hw*[]){
1008                                 &cci_clk_src.clkr.hw
1009                         },
1010                         .num_parents = 1,
1011                         .flags = CLK_SET_RATE_PARENT,
1012                         .ops = &clk_branch2_ops,
1013                 },
1014         },
1015 };
1016
1017 static struct clk_branch camss_csi0_ahb_clk = {
1018         .halt_reg = 0x30bc,
1019         .clkr = {
1020                 .enable_reg = 0x30bc,
1021                 .enable_mask = BIT(0),
1022                 .hw.init = &(struct clk_init_data){
1023                         .name = "camss_csi0_ahb_clk",
1024                         .parent_hws = (const struct clk_hw*[]){
1025                                 &mmss_ahb_clk_src.clkr.hw
1026                         },
1027                         .num_parents = 1,
1028                         .ops = &clk_branch2_ops,
1029                 },
1030         },
1031 };
1032
1033 static struct clk_branch camss_csi0_clk = {
1034         .halt_reg = 0x30b4,
1035         .clkr = {
1036                 .enable_reg = 0x30b4,
1037                 .enable_mask = BIT(0),
1038                 .hw.init = &(struct clk_init_data){
1039                         .name = "camss_csi0_clk",
1040                         .parent_hws = (const struct clk_hw*[]){
1041                                 &csi0_clk_src.clkr.hw
1042                         },
1043                         .num_parents = 1,
1044                         .flags = CLK_SET_RATE_PARENT,
1045                         .ops = &clk_branch2_ops,
1046                 },
1047         },
1048 };
1049
1050 static struct clk_branch camss_csi0phy_clk = {
1051         .halt_reg = 0x30c4,
1052         .clkr = {
1053                 .enable_reg = 0x30c4,
1054                 .enable_mask = BIT(0),
1055                 .hw.init = &(struct clk_init_data){
1056                         .name = "camss_csi0phy_clk",
1057                         .parent_hws = (const struct clk_hw*[]){
1058                                 &csi0_clk_src.clkr.hw
1059                         },
1060                         .num_parents = 1,
1061                         .flags = CLK_SET_RATE_PARENT,
1062                         .ops = &clk_branch2_ops,
1063                 },
1064         },
1065 };
1066
1067 static struct clk_branch camss_csi0pix_clk = {
1068         .halt_reg = 0x30e4,
1069         .clkr = {
1070                 .enable_reg = 0x30e4,
1071                 .enable_mask = BIT(0),
1072                 .hw.init = &(struct clk_init_data){
1073                         .name = "camss_csi0pix_clk",
1074                         .parent_hws = (const struct clk_hw*[]){
1075                                 &csi0_clk_src.clkr.hw
1076                         },
1077                         .num_parents = 1,
1078                         .flags = CLK_SET_RATE_PARENT,
1079                         .ops = &clk_branch2_ops,
1080                 },
1081         },
1082 };
1083
1084 static struct clk_branch camss_csi0rdi_clk = {
1085         .halt_reg = 0x30d4,
1086         .clkr = {
1087                 .enable_reg = 0x30d4,
1088                 .enable_mask = BIT(0),
1089                 .hw.init = &(struct clk_init_data){
1090                         .name = "camss_csi0rdi_clk",
1091                         .parent_hws = (const struct clk_hw*[]){
1092                                 &csi0_clk_src.clkr.hw
1093                         },
1094                         .num_parents = 1,
1095                         .flags = CLK_SET_RATE_PARENT,
1096                         .ops = &clk_branch2_ops,
1097                 },
1098         },
1099 };
1100
1101 static struct clk_branch camss_csi1_ahb_clk = {
1102         .halt_reg = 0x3128,
1103         .clkr = {
1104                 .enable_reg = 0x3128,
1105                 .enable_mask = BIT(0),
1106                 .hw.init = &(struct clk_init_data){
1107                         .name = "camss_csi1_ahb_clk",
1108                         .parent_hws = (const struct clk_hw*[]){
1109                                 &mmss_ahb_clk_src.clkr.hw
1110                         },
1111                         .num_parents = 1,
1112                         .ops = &clk_branch2_ops,
1113                 },
1114         },
1115 };
1116
1117 static struct clk_branch camss_csi1_clk = {
1118         .halt_reg = 0x3124,
1119         .clkr = {
1120                 .enable_reg = 0x3124,
1121                 .enable_mask = BIT(0),
1122                 .hw.init = &(struct clk_init_data){
1123                         .name = "camss_csi1_clk",
1124                         .parent_hws = (const struct clk_hw*[]){
1125                                 &csi1_clk_src.clkr.hw
1126                         },
1127                         .num_parents = 1,
1128                         .flags = CLK_SET_RATE_PARENT,
1129                         .ops = &clk_branch2_ops,
1130                 },
1131         },
1132 };
1133
1134 static struct clk_branch camss_csi1phy_clk = {
1135         .halt_reg = 0x3134,
1136         .clkr = {
1137                 .enable_reg = 0x3134,
1138                 .enable_mask = BIT(0),
1139                 .hw.init = &(struct clk_init_data){
1140                         .name = "camss_csi1phy_clk",
1141                         .parent_hws = (const struct clk_hw*[]){
1142                                 &csi1_clk_src.clkr.hw
1143                         },
1144                         .num_parents = 1,
1145                         .flags = CLK_SET_RATE_PARENT,
1146                         .ops = &clk_branch2_ops,
1147                 },
1148         },
1149 };
1150
1151 static struct clk_branch camss_csi1pix_clk = {
1152         .halt_reg = 0x3154,
1153         .clkr = {
1154                 .enable_reg = 0x3154,
1155                 .enable_mask = BIT(0),
1156                 .hw.init = &(struct clk_init_data){
1157                         .name = "camss_csi1pix_clk",
1158                         .parent_hws = (const struct clk_hw*[]){
1159                                 &csi1_clk_src.clkr.hw
1160                         },
1161                         .num_parents = 1,
1162                         .flags = CLK_SET_RATE_PARENT,
1163                         .ops = &clk_branch2_ops,
1164                 },
1165         },
1166 };
1167
1168 static struct clk_branch camss_csi1rdi_clk = {
1169         .halt_reg = 0x3144,
1170         .clkr = {
1171                 .enable_reg = 0x3144,
1172                 .enable_mask = BIT(0),
1173                 .hw.init = &(struct clk_init_data){
1174                         .name = "camss_csi1rdi_clk",
1175                         .parent_hws = (const struct clk_hw*[]){
1176                                 &csi1_clk_src.clkr.hw
1177                         },
1178                         .num_parents = 1,
1179                         .flags = CLK_SET_RATE_PARENT,
1180                         .ops = &clk_branch2_ops,
1181                 },
1182         },
1183 };
1184
1185 static struct clk_branch camss_csi2_ahb_clk = {
1186         .halt_reg = 0x3188,
1187         .clkr = {
1188                 .enable_reg = 0x3188,
1189                 .enable_mask = BIT(0),
1190                 .hw.init = &(struct clk_init_data){
1191                         .name = "camss_csi2_ahb_clk",
1192                         .parent_hws = (const struct clk_hw*[]){
1193                                 &mmss_ahb_clk_src.clkr.hw
1194                         },
1195                         .num_parents = 1,
1196                         .ops = &clk_branch2_ops,
1197                 },
1198         },
1199 };
1200
1201 static struct clk_branch camss_csi2_clk = {
1202         .halt_reg = 0x3184,
1203         .clkr = {
1204                 .enable_reg = 0x3184,
1205                 .enable_mask = BIT(0),
1206                 .hw.init = &(struct clk_init_data){
1207                         .name = "camss_csi2_clk",
1208                         .parent_hws = (const struct clk_hw*[]){
1209                                 &csi2_clk_src.clkr.hw
1210                         },
1211                         .num_parents = 1,
1212                         .flags = CLK_SET_RATE_PARENT,
1213                         .ops = &clk_branch2_ops,
1214                 },
1215         },
1216 };
1217
1218 static struct clk_branch camss_csi2phy_clk = {
1219         .halt_reg = 0x3194,
1220         .clkr = {
1221                 .enable_reg = 0x3194,
1222                 .enable_mask = BIT(0),
1223                 .hw.init = &(struct clk_init_data){
1224                         .name = "camss_csi2phy_clk",
1225                         .parent_hws = (const struct clk_hw*[]){
1226                                 &csi2_clk_src.clkr.hw
1227                         },
1228                         .num_parents = 1,
1229                         .flags = CLK_SET_RATE_PARENT,
1230                         .ops = &clk_branch2_ops,
1231                 },
1232         },
1233 };
1234
1235 static struct clk_branch camss_csi2pix_clk = {
1236         .halt_reg = 0x31b4,
1237         .clkr = {
1238                 .enable_reg = 0x31b4,
1239                 .enable_mask = BIT(0),
1240                 .hw.init = &(struct clk_init_data){
1241                         .name = "camss_csi2pix_clk",
1242                         .parent_hws = (const struct clk_hw*[]){
1243                                 &csi2_clk_src.clkr.hw
1244                         },
1245                         .num_parents = 1,
1246                         .flags = CLK_SET_RATE_PARENT,
1247                         .ops = &clk_branch2_ops,
1248                 },
1249         },
1250 };
1251
1252 static struct clk_branch camss_csi2rdi_clk = {
1253         .halt_reg = 0x31a4,
1254         .clkr = {
1255                 .enable_reg = 0x31a4,
1256                 .enable_mask = BIT(0),
1257                 .hw.init = &(struct clk_init_data){
1258                         .name = "camss_csi2rdi_clk",
1259                         .parent_hws = (const struct clk_hw*[]){
1260                                 &csi2_clk_src.clkr.hw
1261                         },
1262                         .num_parents = 1,
1263                         .flags = CLK_SET_RATE_PARENT,
1264                         .ops = &clk_branch2_ops,
1265                 },
1266         },
1267 };
1268
1269 static struct clk_branch camss_csi3_ahb_clk = {
1270         .halt_reg = 0x31e8,
1271         .clkr = {
1272                 .enable_reg = 0x31e8,
1273                 .enable_mask = BIT(0),
1274                 .hw.init = &(struct clk_init_data){
1275                         .name = "camss_csi3_ahb_clk",
1276                         .parent_hws = (const struct clk_hw*[]){
1277                                 &mmss_ahb_clk_src.clkr.hw
1278                         },
1279                         .num_parents = 1,
1280                         .ops = &clk_branch2_ops,
1281                 },
1282         },
1283 };
1284
1285 static struct clk_branch camss_csi3_clk = {
1286         .halt_reg = 0x31e4,
1287         .clkr = {
1288                 .enable_reg = 0x31e4,
1289                 .enable_mask = BIT(0),
1290                 .hw.init = &(struct clk_init_data){
1291                         .name = "camss_csi3_clk",
1292                         .parent_hws = (const struct clk_hw*[]){
1293                                 &csi3_clk_src.clkr.hw
1294                         },
1295                         .num_parents = 1,
1296                         .flags = CLK_SET_RATE_PARENT,
1297                         .ops = &clk_branch2_ops,
1298                 },
1299         },
1300 };
1301
1302 static struct clk_branch camss_csi3phy_clk = {
1303         .halt_reg = 0x31f4,
1304         .clkr = {
1305                 .enable_reg = 0x31f4,
1306                 .enable_mask = BIT(0),
1307                 .hw.init = &(struct clk_init_data){
1308                         .name = "camss_csi3phy_clk",
1309                         .parent_hws = (const struct clk_hw*[]){
1310                                 &csi3_clk_src.clkr.hw
1311                         },
1312                         .num_parents = 1,
1313                         .flags = CLK_SET_RATE_PARENT,
1314                         .ops = &clk_branch2_ops,
1315                 },
1316         },
1317 };
1318
1319 static struct clk_branch camss_csi3pix_clk = {
1320         .halt_reg = 0x3214,
1321         .clkr = {
1322                 .enable_reg = 0x3214,
1323                 .enable_mask = BIT(0),
1324                 .hw.init = &(struct clk_init_data){
1325                         .name = "camss_csi3pix_clk",
1326                         .parent_hws = (const struct clk_hw*[]){
1327                                 &csi3_clk_src.clkr.hw
1328                         },
1329                         .num_parents = 1,
1330                         .flags = CLK_SET_RATE_PARENT,
1331                         .ops = &clk_branch2_ops,
1332                 },
1333         },
1334 };
1335
1336 static struct clk_branch camss_csi3rdi_clk = {
1337         .halt_reg = 0x3204,
1338         .clkr = {
1339                 .enable_reg = 0x3204,
1340                 .enable_mask = BIT(0),
1341                 .hw.init = &(struct clk_init_data){
1342                         .name = "camss_csi3rdi_clk",
1343                         .parent_hws = (const struct clk_hw*[]){
1344                                 &csi3_clk_src.clkr.hw
1345                         },
1346                         .num_parents = 1,
1347                         .flags = CLK_SET_RATE_PARENT,
1348                         .ops = &clk_branch2_ops,
1349                 },
1350         },
1351 };
1352
1353 static struct clk_branch camss_csi_vfe0_clk = {
1354         .halt_reg = 0x3704,
1355         .clkr = {
1356                 .enable_reg = 0x3704,
1357                 .enable_mask = BIT(0),
1358                 .hw.init = &(struct clk_init_data){
1359                         .name = "camss_csi_vfe0_clk",
1360                         .parent_hws = (const struct clk_hw*[]){
1361                                 &vfe0_clk_src.clkr.hw
1362                         },
1363                         .num_parents = 1,
1364                         .flags = CLK_SET_RATE_PARENT,
1365                         .ops = &clk_branch2_ops,
1366                 },
1367         },
1368 };
1369
1370 static struct clk_branch camss_csi_vfe1_clk = {
1371         .halt_reg = 0x3714,
1372         .clkr = {
1373                 .enable_reg = 0x3714,
1374                 .enable_mask = BIT(0),
1375                 .hw.init = &(struct clk_init_data){
1376                         .name = "camss_csi_vfe1_clk",
1377                         .parent_hws = (const struct clk_hw*[]){
1378                                 &vfe1_clk_src.clkr.hw
1379                         },
1380                         .num_parents = 1,
1381                         .flags = CLK_SET_RATE_PARENT,
1382                         .ops = &clk_branch2_ops,
1383                 },
1384         },
1385 };
1386
1387 static struct clk_branch camss_gp0_clk = {
1388         .halt_reg = 0x3444,
1389         .clkr = {
1390                 .enable_reg = 0x3444,
1391                 .enable_mask = BIT(0),
1392                 .hw.init = &(struct clk_init_data){
1393                         .name = "camss_gp0_clk",
1394                         .parent_hws = (const struct clk_hw*[]){
1395                                 &camss_gp0_clk_src.clkr.hw
1396                         },
1397                         .num_parents = 1,
1398                         .flags = CLK_SET_RATE_PARENT,
1399                         .ops = &clk_branch2_ops,
1400                 },
1401         },
1402 };
1403
1404 static struct clk_branch camss_gp1_clk = {
1405         .halt_reg = 0x3474,
1406         .clkr = {
1407                 .enable_reg = 0x3474,
1408                 .enable_mask = BIT(0),
1409                 .hw.init = &(struct clk_init_data){
1410                         .name = "camss_gp1_clk",
1411                         .parent_hws = (const struct clk_hw*[]){
1412                                 &camss_gp1_clk_src.clkr.hw
1413                         },
1414                         .num_parents = 1,
1415                         .flags = CLK_SET_RATE_PARENT,
1416                         .ops = &clk_branch2_ops,
1417                 },
1418         },
1419 };
1420
1421 static struct clk_branch camss_ispif_ahb_clk = {
1422         .halt_reg = 0x3224,
1423         .clkr = {
1424                 .enable_reg = 0x3224,
1425                 .enable_mask = BIT(0),
1426                 .hw.init = &(struct clk_init_data){
1427                         .name = "camss_ispif_ahb_clk",
1428                         .parent_hws = (const struct clk_hw*[]){
1429                                 &mmss_ahb_clk_src.clkr.hw
1430                         },
1431                         .num_parents = 1,
1432                         .ops = &clk_branch2_ops,
1433                 },
1434         },
1435 };
1436
1437 static struct clk_branch camss_jpeg_jpeg0_clk = {
1438         .halt_reg = 0x35a8,
1439         .clkr = {
1440                 .enable_reg = 0x35a8,
1441                 .enable_mask = BIT(0),
1442                 .hw.init = &(struct clk_init_data){
1443                         .name = "camss_jpeg_jpeg0_clk",
1444                         .parent_hws = (const struct clk_hw*[]){
1445                                 &jpeg0_clk_src.clkr.hw
1446                         },
1447                         .num_parents = 1,
1448                         .flags = CLK_SET_RATE_PARENT,
1449                         .ops = &clk_branch2_ops,
1450                 },
1451         },
1452 };
1453
1454 static struct clk_branch camss_jpeg_jpeg1_clk = {
1455         .halt_reg = 0x35ac,
1456         .clkr = {
1457                 .enable_reg = 0x35ac,
1458                 .enable_mask = BIT(0),
1459                 .hw.init = &(struct clk_init_data){
1460                         .name = "camss_jpeg_jpeg1_clk",
1461                         .parent_hws = (const struct clk_hw*[]){
1462                                 &jpeg1_clk_src.clkr.hw
1463                         },
1464                         .num_parents = 1,
1465                         .flags = CLK_SET_RATE_PARENT,
1466                         .ops = &clk_branch2_ops,
1467                 },
1468         },
1469 };
1470
1471 static struct clk_branch camss_jpeg_jpeg2_clk = {
1472         .halt_reg = 0x35b0,
1473         .clkr = {
1474                 .enable_reg = 0x35b0,
1475                 .enable_mask = BIT(0),
1476                 .hw.init = &(struct clk_init_data){
1477                         .name = "camss_jpeg_jpeg2_clk",
1478                         .parent_hws = (const struct clk_hw*[]){
1479                                 &jpeg2_clk_src.clkr.hw
1480                         },
1481                         .num_parents = 1,
1482                         .flags = CLK_SET_RATE_PARENT,
1483                         .ops = &clk_branch2_ops,
1484                 },
1485         },
1486 };
1487
1488 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1489         .halt_reg = 0x35b4,
1490         .clkr = {
1491                 .enable_reg = 0x35b4,
1492                 .enable_mask = BIT(0),
1493                 .hw.init = &(struct clk_init_data){
1494                         .name = "camss_jpeg_jpeg_ahb_clk",
1495                         .parent_hws = (const struct clk_hw*[]){
1496                                 &mmss_ahb_clk_src.clkr.hw
1497                         },
1498                         .num_parents = 1,
1499                         .ops = &clk_branch2_ops,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1505         .halt_reg = 0x35b8,
1506         .clkr = {
1507                 .enable_reg = 0x35b8,
1508                 .enable_mask = BIT(0),
1509                 .hw.init = &(struct clk_init_data){
1510                         .name = "camss_jpeg_jpeg_axi_clk",
1511                         .parent_hws = (const struct clk_hw*[]){
1512                                 &mmss_axi_clk_src.clkr.hw
1513                         },
1514                         .num_parents = 1,
1515                         .ops = &clk_branch2_ops,
1516                 },
1517         },
1518 };
1519
1520 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1521         .halt_reg = 0x35bc,
1522         .clkr = {
1523                 .enable_reg = 0x35bc,
1524                 .enable_mask = BIT(0),
1525                 .hw.init = &(struct clk_init_data){
1526                         .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1527                         .parent_hws = (const struct clk_hw*[]){
1528                                 &ocmemnoc_clk_src.clkr.hw
1529                         },
1530                         .num_parents = 1,
1531                         .flags = CLK_SET_RATE_PARENT,
1532                         .ops = &clk_branch2_ops,
1533                 },
1534         },
1535 };
1536
1537 static struct clk_branch camss_mclk0_clk = {
1538         .halt_reg = 0x3384,
1539         .clkr = {
1540                 .enable_reg = 0x3384,
1541                 .enable_mask = BIT(0),
1542                 .hw.init = &(struct clk_init_data){
1543                         .name = "camss_mclk0_clk",
1544                         .parent_hws = (const struct clk_hw*[]){
1545                                 &mclk0_clk_src.clkr.hw
1546                         },
1547                         .num_parents = 1,
1548                         .flags = CLK_SET_RATE_PARENT,
1549                         .ops = &clk_branch2_ops,
1550                 },
1551         },
1552 };
1553
1554 static struct clk_branch camss_mclk1_clk = {
1555         .halt_reg = 0x33b4,
1556         .clkr = {
1557                 .enable_reg = 0x33b4,
1558                 .enable_mask = BIT(0),
1559                 .hw.init = &(struct clk_init_data){
1560                         .name = "camss_mclk1_clk",
1561                         .parent_hws = (const struct clk_hw*[]){
1562                                 &mclk1_clk_src.clkr.hw
1563                         },
1564                         .num_parents = 1,
1565                         .flags = CLK_SET_RATE_PARENT,
1566                         .ops = &clk_branch2_ops,
1567                 },
1568         },
1569 };
1570
1571 static struct clk_branch camss_mclk2_clk = {
1572         .halt_reg = 0x33e4,
1573         .clkr = {
1574                 .enable_reg = 0x33e4,
1575                 .enable_mask = BIT(0),
1576                 .hw.init = &(struct clk_init_data){
1577                         .name = "camss_mclk2_clk",
1578                         .parent_hws = (const struct clk_hw*[]){
1579                                 &mclk2_clk_src.clkr.hw
1580                         },
1581                         .num_parents = 1,
1582                         .flags = CLK_SET_RATE_PARENT,
1583                         .ops = &clk_branch2_ops,
1584                 },
1585         },
1586 };
1587
1588 static struct clk_branch camss_mclk3_clk = {
1589         .halt_reg = 0x3414,
1590         .clkr = {
1591                 .enable_reg = 0x3414,
1592                 .enable_mask = BIT(0),
1593                 .hw.init = &(struct clk_init_data){
1594                         .name = "camss_mclk3_clk",
1595                         .parent_hws = (const struct clk_hw*[]){
1596                                 &mclk3_clk_src.clkr.hw
1597                         },
1598                         .num_parents = 1,
1599                         .flags = CLK_SET_RATE_PARENT,
1600                         .ops = &clk_branch2_ops,
1601                 },
1602         },
1603 };
1604
1605 static struct clk_branch camss_micro_ahb_clk = {
1606         .halt_reg = 0x3494,
1607         .clkr = {
1608                 .enable_reg = 0x3494,
1609                 .enable_mask = BIT(0),
1610                 .hw.init = &(struct clk_init_data){
1611                         .name = "camss_micro_ahb_clk",
1612                         .parent_hws = (const struct clk_hw*[]){
1613                                 &mmss_ahb_clk_src.clkr.hw
1614                         },
1615                         .num_parents = 1,
1616                         .ops = &clk_branch2_ops,
1617                 },
1618         },
1619 };
1620
1621 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1622         .halt_reg = 0x3024,
1623         .clkr = {
1624                 .enable_reg = 0x3024,
1625                 .enable_mask = BIT(0),
1626                 .hw.init = &(struct clk_init_data){
1627                         .name = "camss_phy0_csi0phytimer_clk",
1628                         .parent_hws = (const struct clk_hw*[]){
1629                                 &csi0phytimer_clk_src.clkr.hw
1630                         },
1631                         .num_parents = 1,
1632                         .flags = CLK_SET_RATE_PARENT,
1633                         .ops = &clk_branch2_ops,
1634                 },
1635         },
1636 };
1637
1638 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1639         .halt_reg = 0x3054,
1640         .clkr = {
1641                 .enable_reg = 0x3054,
1642                 .enable_mask = BIT(0),
1643                 .hw.init = &(struct clk_init_data){
1644                         .name = "camss_phy1_csi1phytimer_clk",
1645                         .parent_hws = (const struct clk_hw*[]){
1646                                 &csi1phytimer_clk_src.clkr.hw
1647                         },
1648                         .num_parents = 1,
1649                         .flags = CLK_SET_RATE_PARENT,
1650                         .ops = &clk_branch2_ops,
1651                 },
1652         },
1653 };
1654
1655 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1656         .halt_reg = 0x3084,
1657         .clkr = {
1658                 .enable_reg = 0x3084,
1659                 .enable_mask = BIT(0),
1660                 .hw.init = &(struct clk_init_data){
1661                         .name = "camss_phy2_csi2phytimer_clk",
1662                         .parent_hws = (const struct clk_hw*[]){
1663                                 &csi2phytimer_clk_src.clkr.hw
1664                         },
1665                         .num_parents = 1,
1666                         .flags = CLK_SET_RATE_PARENT,
1667                         .ops = &clk_branch2_ops,
1668                 },
1669         },
1670 };
1671
1672 static struct clk_branch camss_top_ahb_clk = {
1673         .halt_reg = 0x3484,
1674         .clkr = {
1675                 .enable_reg = 0x3484,
1676                 .enable_mask = BIT(0),
1677                 .hw.init = &(struct clk_init_data){
1678                         .name = "camss_top_ahb_clk",
1679                         .parent_hws = (const struct clk_hw*[]){
1680                                 &mmss_ahb_clk_src.clkr.hw
1681                         },
1682                         .num_parents = 1,
1683                         .ops = &clk_branch2_ops,
1684                 },
1685         },
1686 };
1687
1688 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1689         .halt_reg = 0x36b4,
1690         .clkr = {
1691                 .enable_reg = 0x36b4,
1692                 .enable_mask = BIT(0),
1693                 .hw.init = &(struct clk_init_data){
1694                         .name = "camss_vfe_cpp_ahb_clk",
1695                         .parent_hws = (const struct clk_hw*[]){
1696                                 &mmss_ahb_clk_src.clkr.hw
1697                         },
1698                         .num_parents = 1,
1699                         .ops = &clk_branch2_ops,
1700                 },
1701         },
1702 };
1703
1704 static struct clk_branch camss_vfe_cpp_clk = {
1705         .halt_reg = 0x36b0,
1706         .clkr = {
1707                 .enable_reg = 0x36b0,
1708                 .enable_mask = BIT(0),
1709                 .hw.init = &(struct clk_init_data){
1710                         .name = "camss_vfe_cpp_clk",
1711                         .parent_hws = (const struct clk_hw*[]){
1712                                 &cpp_clk_src.clkr.hw
1713                         },
1714                         .num_parents = 1,
1715                         .flags = CLK_SET_RATE_PARENT,
1716                         .ops = &clk_branch2_ops,
1717                 },
1718         },
1719 };
1720
1721 static struct clk_branch camss_vfe_vfe0_clk = {
1722         .halt_reg = 0x36a8,
1723         .clkr = {
1724                 .enable_reg = 0x36a8,
1725                 .enable_mask = BIT(0),
1726                 .hw.init = &(struct clk_init_data){
1727                         .name = "camss_vfe_vfe0_clk",
1728                         .parent_hws = (const struct clk_hw*[]){
1729                                 &vfe0_clk_src.clkr.hw
1730                         },
1731                         .num_parents = 1,
1732                         .flags = CLK_SET_RATE_PARENT,
1733                         .ops = &clk_branch2_ops,
1734                 },
1735         },
1736 };
1737
1738 static struct clk_branch camss_vfe_vfe1_clk = {
1739         .halt_reg = 0x36ac,
1740         .clkr = {
1741                 .enable_reg = 0x36ac,
1742                 .enable_mask = BIT(0),
1743                 .hw.init = &(struct clk_init_data){
1744                         .name = "camss_vfe_vfe1_clk",
1745                         .parent_hws = (const struct clk_hw*[]){
1746                                 &vfe1_clk_src.clkr.hw
1747                         },
1748                         .num_parents = 1,
1749                         .flags = CLK_SET_RATE_PARENT,
1750                         .ops = &clk_branch2_ops,
1751                 },
1752         },
1753 };
1754
1755 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1756         .halt_reg = 0x36b8,
1757         .clkr = {
1758                 .enable_reg = 0x36b8,
1759                 .enable_mask = BIT(0),
1760                 .hw.init = &(struct clk_init_data){
1761                         .name = "camss_vfe_vfe_ahb_clk",
1762                         .parent_hws = (const struct clk_hw*[]){
1763                                 &mmss_ahb_clk_src.clkr.hw
1764                         },
1765                         .num_parents = 1,
1766                         .ops = &clk_branch2_ops,
1767                 },
1768         },
1769 };
1770
1771 static struct clk_branch camss_vfe_vfe_axi_clk = {
1772         .halt_reg = 0x36bc,
1773         .clkr = {
1774                 .enable_reg = 0x36bc,
1775                 .enable_mask = BIT(0),
1776                 .hw.init = &(struct clk_init_data){
1777                         .name = "camss_vfe_vfe_axi_clk",
1778                         .parent_hws = (const struct clk_hw*[]){
1779                                 &mmss_axi_clk_src.clkr.hw
1780                         },
1781                         .num_parents = 1,
1782                         .ops = &clk_branch2_ops,
1783                 },
1784         },
1785 };
1786
1787 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1788         .halt_reg = 0x36c0,
1789         .clkr = {
1790                 .enable_reg = 0x36c0,
1791                 .enable_mask = BIT(0),
1792                 .hw.init = &(struct clk_init_data){
1793                         .name = "camss_vfe_vfe_ocmemnoc_clk",
1794                         .parent_hws = (const struct clk_hw*[]){
1795                                 &ocmemnoc_clk_src.clkr.hw
1796                         },
1797                         .num_parents = 1,
1798                         .flags = CLK_SET_RATE_PARENT,
1799                         .ops = &clk_branch2_ops,
1800                 },
1801         },
1802 };
1803
1804 static struct clk_branch mdss_ahb_clk = {
1805         .halt_reg = 0x2308,
1806         .clkr = {
1807                 .enable_reg = 0x2308,
1808                 .enable_mask = BIT(0),
1809                 .hw.init = &(struct clk_init_data){
1810                         .name = "mdss_ahb_clk",
1811                         .parent_hws = (const struct clk_hw*[]){
1812                                 &mmss_ahb_clk_src.clkr.hw
1813                         },
1814                         .num_parents = 1,
1815                         .ops = &clk_branch2_ops,
1816                 },
1817         },
1818 };
1819
1820 static struct clk_branch mdss_axi_clk = {
1821         .halt_reg = 0x2310,
1822         .clkr = {
1823                 .enable_reg = 0x2310,
1824                 .enable_mask = BIT(0),
1825                 .hw.init = &(struct clk_init_data){
1826                         .name = "mdss_axi_clk",
1827                         .parent_hws = (const struct clk_hw*[]){
1828                                 &mmss_axi_clk_src.clkr.hw
1829                         },
1830                         .num_parents = 1,
1831                         .flags = CLK_SET_RATE_PARENT,
1832                         .ops = &clk_branch2_ops,
1833                 },
1834         },
1835 };
1836
1837 static struct clk_branch mdss_byte0_clk = {
1838         .halt_reg = 0x233c,
1839         .clkr = {
1840                 .enable_reg = 0x233c,
1841                 .enable_mask = BIT(0),
1842                 .hw.init = &(struct clk_init_data){
1843                         .name = "mdss_byte0_clk",
1844                         .parent_hws = (const struct clk_hw*[]){
1845                                 &byte0_clk_src.clkr.hw
1846                         },
1847                         .num_parents = 1,
1848                         .flags = CLK_SET_RATE_PARENT,
1849                         .ops = &clk_branch2_ops,
1850                 },
1851         },
1852 };
1853
1854 static struct clk_branch mdss_byte1_clk = {
1855         .halt_reg = 0x2340,
1856         .clkr = {
1857                 .enable_reg = 0x2340,
1858                 .enable_mask = BIT(0),
1859                 .hw.init = &(struct clk_init_data){
1860                         .name = "mdss_byte1_clk",
1861                         .parent_hws = (const struct clk_hw*[]){
1862                                 &byte1_clk_src.clkr.hw
1863                         },
1864                         .num_parents = 1,
1865                         .flags = CLK_SET_RATE_PARENT,
1866                         .ops = &clk_branch2_ops,
1867                 },
1868         },
1869 };
1870
1871 static struct clk_branch mdss_edpaux_clk = {
1872         .halt_reg = 0x2334,
1873         .clkr = {
1874                 .enable_reg = 0x2334,
1875                 .enable_mask = BIT(0),
1876                 .hw.init = &(struct clk_init_data){
1877                         .name = "mdss_edpaux_clk",
1878                         .parent_hws = (const struct clk_hw*[]){
1879                                 &edpaux_clk_src.clkr.hw
1880                         },
1881                         .num_parents = 1,
1882                         .flags = CLK_SET_RATE_PARENT,
1883                         .ops = &clk_branch2_ops,
1884                 },
1885         },
1886 };
1887
1888 static struct clk_branch mdss_edplink_clk = {
1889         .halt_reg = 0x2330,
1890         .clkr = {
1891                 .enable_reg = 0x2330,
1892                 .enable_mask = BIT(0),
1893                 .hw.init = &(struct clk_init_data){
1894                         .name = "mdss_edplink_clk",
1895                         .parent_hws = (const struct clk_hw*[]){
1896                                 &edplink_clk_src.clkr.hw
1897                         },
1898                         .num_parents = 1,
1899                         .flags = CLK_SET_RATE_PARENT,
1900                         .ops = &clk_branch2_ops,
1901                 },
1902         },
1903 };
1904
1905 static struct clk_branch mdss_edppixel_clk = {
1906         .halt_reg = 0x232c,
1907         .clkr = {
1908                 .enable_reg = 0x232c,
1909                 .enable_mask = BIT(0),
1910                 .hw.init = &(struct clk_init_data){
1911                         .name = "mdss_edppixel_clk",
1912                         .parent_hws = (const struct clk_hw*[]){
1913                                 &edppixel_clk_src.clkr.hw
1914                         },
1915                         .num_parents = 1,
1916                         .flags = CLK_SET_RATE_PARENT,
1917                         .ops = &clk_branch2_ops,
1918                 },
1919         },
1920 };
1921
1922 static struct clk_branch mdss_esc0_clk = {
1923         .halt_reg = 0x2344,
1924         .clkr = {
1925                 .enable_reg = 0x2344,
1926                 .enable_mask = BIT(0),
1927                 .hw.init = &(struct clk_init_data){
1928                         .name = "mdss_esc0_clk",
1929                         .parent_hws = (const struct clk_hw*[]){
1930                                 &esc0_clk_src.clkr.hw
1931                         },
1932                         .num_parents = 1,
1933                         .flags = CLK_SET_RATE_PARENT,
1934                         .ops = &clk_branch2_ops,
1935                 },
1936         },
1937 };
1938
1939 static struct clk_branch mdss_esc1_clk = {
1940         .halt_reg = 0x2348,
1941         .clkr = {
1942                 .enable_reg = 0x2348,
1943                 .enable_mask = BIT(0),
1944                 .hw.init = &(struct clk_init_data){
1945                         .name = "mdss_esc1_clk",
1946                         .parent_hws = (const struct clk_hw*[]){
1947                                 &esc1_clk_src.clkr.hw
1948                         },
1949                         .num_parents = 1,
1950                         .flags = CLK_SET_RATE_PARENT,
1951                         .ops = &clk_branch2_ops,
1952                 },
1953         },
1954 };
1955
1956 static struct clk_branch mdss_extpclk_clk = {
1957         .halt_reg = 0x2324,
1958         .clkr = {
1959                 .enable_reg = 0x2324,
1960                 .enable_mask = BIT(0),
1961                 .hw.init = &(struct clk_init_data){
1962                         .name = "mdss_extpclk_clk",
1963                         .parent_hws = (const struct clk_hw*[]){
1964                                 &extpclk_clk_src.clkr.hw
1965                         },
1966                         .num_parents = 1,
1967                         .flags = CLK_SET_RATE_PARENT,
1968                         .ops = &clk_branch2_ops,
1969                 },
1970         },
1971 };
1972
1973 static struct clk_branch mdss_hdmi_ahb_clk = {
1974         .halt_reg = 0x230c,
1975         .clkr = {
1976                 .enable_reg = 0x230c,
1977                 .enable_mask = BIT(0),
1978                 .hw.init = &(struct clk_init_data){
1979                         .name = "mdss_hdmi_ahb_clk",
1980                         .parent_hws = (const struct clk_hw*[]){
1981                                 &mmss_ahb_clk_src.clkr.hw
1982                         },
1983                         .num_parents = 1,
1984                         .ops = &clk_branch2_ops,
1985                 },
1986         },
1987 };
1988
1989 static struct clk_branch mdss_hdmi_clk = {
1990         .halt_reg = 0x2338,
1991         .clkr = {
1992                 .enable_reg = 0x2338,
1993                 .enable_mask = BIT(0),
1994                 .hw.init = &(struct clk_init_data){
1995                         .name = "mdss_hdmi_clk",
1996                         .parent_hws = (const struct clk_hw*[]){
1997                                 &hdmi_clk_src.clkr.hw
1998                         },
1999                         .num_parents = 1,
2000                         .flags = CLK_SET_RATE_PARENT,
2001                         .ops = &clk_branch2_ops,
2002                 },
2003         },
2004 };
2005
2006 static struct clk_branch mdss_mdp_clk = {
2007         .halt_reg = 0x231c,
2008         .clkr = {
2009                 .enable_reg = 0x231c,
2010                 .enable_mask = BIT(0),
2011                 .hw.init = &(struct clk_init_data){
2012                         .name = "mdss_mdp_clk",
2013                         .parent_hws = (const struct clk_hw*[]){
2014                                 &mdp_clk_src.clkr.hw
2015                         },
2016                         .num_parents = 1,
2017                         .flags = CLK_SET_RATE_PARENT,
2018                         .ops = &clk_branch2_ops,
2019                 },
2020         },
2021 };
2022
2023 static struct clk_branch mdss_mdp_lut_clk = {
2024         .halt_reg = 0x2320,
2025         .clkr = {
2026                 .enable_reg = 0x2320,
2027                 .enable_mask = BIT(0),
2028                 .hw.init = &(struct clk_init_data){
2029                         .name = "mdss_mdp_lut_clk",
2030                         .parent_hws = (const struct clk_hw*[]){
2031                                 &mdp_clk_src.clkr.hw
2032                         },
2033                         .num_parents = 1,
2034                         .flags = CLK_SET_RATE_PARENT,
2035                         .ops = &clk_branch2_ops,
2036                 },
2037         },
2038 };
2039
2040 static struct clk_branch mdss_pclk0_clk = {
2041         .halt_reg = 0x2314,
2042         .clkr = {
2043                 .enable_reg = 0x2314,
2044                 .enable_mask = BIT(0),
2045                 .hw.init = &(struct clk_init_data){
2046                         .name = "mdss_pclk0_clk",
2047                         .parent_hws = (const struct clk_hw*[]){
2048                                 &pclk0_clk_src.clkr.hw
2049                         },
2050                         .num_parents = 1,
2051                         .flags = CLK_SET_RATE_PARENT,
2052                         .ops = &clk_branch2_ops,
2053                 },
2054         },
2055 };
2056
2057 static struct clk_branch mdss_pclk1_clk = {
2058         .halt_reg = 0x2318,
2059         .clkr = {
2060                 .enable_reg = 0x2318,
2061                 .enable_mask = BIT(0),
2062                 .hw.init = &(struct clk_init_data){
2063                         .name = "mdss_pclk1_clk",
2064                         .parent_hws = (const struct clk_hw*[]){
2065                                 &pclk1_clk_src.clkr.hw
2066                         },
2067                         .num_parents = 1,
2068                         .flags = CLK_SET_RATE_PARENT,
2069                         .ops = &clk_branch2_ops,
2070                 },
2071         },
2072 };
2073
2074 static struct clk_branch mdss_vsync_clk = {
2075         .halt_reg = 0x2328,
2076         .clkr = {
2077                 .enable_reg = 0x2328,
2078                 .enable_mask = BIT(0),
2079                 .hw.init = &(struct clk_init_data){
2080                         .name = "mdss_vsync_clk",
2081                         .parent_hws = (const struct clk_hw*[]){
2082                                 &vsync_clk_src.clkr.hw
2083                         },
2084                         .num_parents = 1,
2085                         .flags = CLK_SET_RATE_PARENT,
2086                         .ops = &clk_branch2_ops,
2087                 },
2088         },
2089 };
2090
2091 static struct clk_branch mmss_misc_ahb_clk = {
2092         .halt_reg = 0x502c,
2093         .clkr = {
2094                 .enable_reg = 0x502c,
2095                 .enable_mask = BIT(0),
2096                 .hw.init = &(struct clk_init_data){
2097                         .name = "mmss_misc_ahb_clk",
2098                         .parent_hws = (const struct clk_hw*[]){
2099                                 &mmss_ahb_clk_src.clkr.hw
2100                         },
2101                         .num_parents = 1,
2102                         .ops = &clk_branch2_ops,
2103                 },
2104         },
2105 };
2106
2107 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2108         .halt_reg = 0x5024,
2109         .clkr = {
2110                 .enable_reg = 0x5024,
2111                 .enable_mask = BIT(0),
2112                 .hw.init = &(struct clk_init_data){
2113                         .name = "mmss_mmssnoc_ahb_clk",
2114                         .parent_hws = (const struct clk_hw*[]){
2115                                 &mmss_ahb_clk_src.clkr.hw
2116                         },
2117                         .num_parents = 1,
2118                         .ops = &clk_branch2_ops,
2119                         .flags = CLK_IGNORE_UNUSED,
2120                 },
2121         },
2122 };
2123
2124 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2125         .halt_reg = 0x5028,
2126         .clkr = {
2127                 .enable_reg = 0x5028,
2128                 .enable_mask = BIT(0),
2129                 .hw.init = &(struct clk_init_data){
2130                         .name = "mmss_mmssnoc_bto_ahb_clk",
2131                         .parent_hws = (const struct clk_hw*[]){
2132                                 &mmss_ahb_clk_src.clkr.hw
2133                         },
2134                         .num_parents = 1,
2135                         .ops = &clk_branch2_ops,
2136                         .flags = CLK_IGNORE_UNUSED,
2137                 },
2138         },
2139 };
2140
2141 static struct clk_branch mmss_mmssnoc_axi_clk = {
2142         .halt_reg = 0x506c,
2143         .clkr = {
2144                 .enable_reg = 0x506c,
2145                 .enable_mask = BIT(0),
2146                 .hw.init = &(struct clk_init_data){
2147                         .name = "mmss_mmssnoc_axi_clk",
2148                         .parent_hws = (const struct clk_hw*[]){
2149                                 &mmss_axi_clk_src.clkr.hw
2150                         },
2151                         .num_parents = 1,
2152                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2153                         .ops = &clk_branch2_ops,
2154                 },
2155         },
2156 };
2157
2158 static struct clk_branch mmss_s0_axi_clk = {
2159         .halt_reg = 0x5064,
2160         .clkr = {
2161                 .enable_reg = 0x5064,
2162                 .enable_mask = BIT(0),
2163                 .hw.init = &(struct clk_init_data){
2164                         .name = "mmss_s0_axi_clk",
2165                         .parent_hws = (const struct clk_hw*[]){
2166                                 &mmss_axi_clk_src.clkr.hw
2167                         },
2168                         .num_parents = 1,
2169                         .ops = &clk_branch2_ops,
2170                         .flags = CLK_IGNORE_UNUSED,
2171                 },
2172         },
2173 };
2174
2175 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2176         .halt_reg = 0x4058,
2177         .clkr = {
2178                 .enable_reg = 0x4058,
2179                 .enable_mask = BIT(0),
2180                 .hw.init = &(struct clk_init_data){
2181                         .name = "ocmemcx_ocmemnoc_clk",
2182                         .parent_hws = (const struct clk_hw*[]){
2183                                 &ocmemnoc_clk_src.clkr.hw
2184                         },
2185                         .num_parents = 1,
2186                         .flags = CLK_SET_RATE_PARENT,
2187                         .ops = &clk_branch2_ops,
2188                 },
2189         },
2190 };
2191
2192 static struct clk_branch ocmemnoc_clk = {
2193         .halt_reg = 0x50b4,
2194         .clkr = {
2195                 .enable_reg = 0x50b4,
2196                 .enable_mask = BIT(0),
2197                 .hw.init = &(struct clk_init_data){
2198                         .name = "ocmemnoc_clk",
2199                         .parent_hws = (const struct clk_hw*[]){
2200                                 &ocmemnoc_clk_src.clkr.hw
2201                         },
2202                         .num_parents = 1,
2203                         .flags = CLK_SET_RATE_PARENT,
2204                         .ops = &clk_branch2_ops,
2205                 },
2206         },
2207 };
2208
2209 static struct clk_branch oxili_gfx3d_clk = {
2210         .halt_reg = 0x4028,
2211         .clkr = {
2212                 .enable_reg = 0x4028,
2213                 .enable_mask = BIT(0),
2214                 .hw.init = &(struct clk_init_data){
2215                         .name = "oxili_gfx3d_clk",
2216                         .parent_data = (const struct clk_parent_data[]){
2217                                 { .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
2218                         },
2219                         .num_parents = 1,
2220                         .flags = CLK_SET_RATE_PARENT,
2221                         .ops = &clk_branch2_ops,
2222                 },
2223         },
2224 };
2225
2226 static struct clk_branch oxilicx_ahb_clk = {
2227         .halt_reg = 0x403c,
2228         .clkr = {
2229                 .enable_reg = 0x403c,
2230                 .enable_mask = BIT(0),
2231                 .hw.init = &(struct clk_init_data){
2232                         .name = "oxilicx_ahb_clk",
2233                         .parent_hws = (const struct clk_hw*[]){
2234                                 &mmss_ahb_clk_src.clkr.hw
2235                         },
2236                         .num_parents = 1,
2237                         .ops = &clk_branch2_ops,
2238                 },
2239         },
2240 };
2241
2242 static struct clk_branch oxilicx_axi_clk = {
2243         .halt_reg = 0x4038,
2244         .clkr = {
2245                 .enable_reg = 0x4038,
2246                 .enable_mask = BIT(0),
2247                 .hw.init = &(struct clk_init_data){
2248                         .name = "oxilicx_axi_clk",
2249                         .parent_hws = (const struct clk_hw*[]){
2250                                 &mmss_axi_clk_src.clkr.hw
2251                         },
2252                         .num_parents = 1,
2253                         .ops = &clk_branch2_ops,
2254                 },
2255         },
2256 };
2257
2258 static struct clk_branch venus0_ahb_clk = {
2259         .halt_reg = 0x1030,
2260         .clkr = {
2261                 .enable_reg = 0x1030,
2262                 .enable_mask = BIT(0),
2263                 .hw.init = &(struct clk_init_data){
2264                         .name = "venus0_ahb_clk",
2265                         .parent_hws = (const struct clk_hw*[]){
2266                                 &mmss_ahb_clk_src.clkr.hw
2267                         },
2268                         .num_parents = 1,
2269                         .ops = &clk_branch2_ops,
2270                 },
2271         },
2272 };
2273
2274 static struct clk_branch venus0_axi_clk = {
2275         .halt_reg = 0x1034,
2276         .clkr = {
2277                 .enable_reg = 0x1034,
2278                 .enable_mask = BIT(0),
2279                 .hw.init = &(struct clk_init_data){
2280                         .name = "venus0_axi_clk",
2281                         .parent_hws = (const struct clk_hw*[]){
2282                                 &mmss_axi_clk_src.clkr.hw
2283                         },
2284                         .num_parents = 1,
2285                         .ops = &clk_branch2_ops,
2286                 },
2287         },
2288 };
2289
2290 static struct clk_branch venus0_ocmemnoc_clk = {
2291         .halt_reg = 0x1038,
2292         .clkr = {
2293                 .enable_reg = 0x1038,
2294                 .enable_mask = BIT(0),
2295                 .hw.init = &(struct clk_init_data){
2296                         .name = "venus0_ocmemnoc_clk",
2297                         .parent_hws = (const struct clk_hw*[]){
2298                                 &ocmemnoc_clk_src.clkr.hw
2299                         },
2300                         .num_parents = 1,
2301                         .flags = CLK_SET_RATE_PARENT,
2302                         .ops = &clk_branch2_ops,
2303                 },
2304         },
2305 };
2306
2307 static struct clk_branch venus0_vcodec0_clk = {
2308         .halt_reg = 0x1028,
2309         .clkr = {
2310                 .enable_reg = 0x1028,
2311                 .enable_mask = BIT(0),
2312                 .hw.init = &(struct clk_init_data){
2313                         .name = "venus0_vcodec0_clk",
2314                         .parent_hws = (const struct clk_hw*[]){
2315                                 &vcodec0_clk_src.clkr.hw
2316                         },
2317                         .num_parents = 1,
2318                         .flags = CLK_SET_RATE_PARENT,
2319                         .ops = &clk_branch2_ops,
2320                 },
2321         },
2322 };
2323
2324 static const struct pll_config mmpll1_config = {
2325         .l = 60,
2326         .m = 25,
2327         .n = 32,
2328         .vco_val = 0x0,
2329         .vco_mask = 0x3 << 20,
2330         .pre_div_val = 0x0,
2331         .pre_div_mask = 0x7 << 12,
2332         .post_div_val = 0x0,
2333         .post_div_mask = 0x3 << 8,
2334         .mn_ena_mask = BIT(24),
2335         .main_output_mask = BIT(0),
2336 };
2337
2338 static struct pll_config mmpll3_config = {
2339         .l = 48,
2340         .m = 7,
2341         .n = 16,
2342         .vco_val = 0x0,
2343         .vco_mask = 0x3 << 20,
2344         .pre_div_val = 0x0,
2345         .pre_div_mask = 0x7 << 12,
2346         .post_div_val = 0x0,
2347         .post_div_mask = 0x3 << 8,
2348         .mn_ena_mask = BIT(24),
2349         .main_output_mask = BIT(0),
2350         .aux_output_mask = BIT(1),
2351 };
2352
2353 static struct gdsc venus0_gdsc = {
2354         .gdscr = 0x1024,
2355         .cxcs = (unsigned int []){ 0x1028 },
2356         .cxc_count = 1,
2357         .resets = (unsigned int []){ VENUS0_RESET },
2358         .reset_count = 1,
2359         .pd = {
2360                 .name = "venus0",
2361         },
2362         .pwrsts = PWRSTS_ON,
2363 };
2364
2365 static struct gdsc mdss_gdsc = {
2366         .gdscr = 0x2304,
2367         .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2368         .cxc_count = 2,
2369         .pd = {
2370                 .name = "mdss",
2371         },
2372         .pwrsts = PWRSTS_OFF_ON,
2373 };
2374
2375 static struct gdsc camss_jpeg_gdsc = {
2376         .gdscr = 0x35a4,
2377         .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2378         .cxc_count = 3,
2379         .pd = {
2380                 .name = "camss_jpeg",
2381         },
2382         .pwrsts = PWRSTS_OFF_ON,
2383 };
2384
2385 static struct gdsc camss_vfe_gdsc = {
2386         .gdscr = 0x36a4,
2387         .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2388         .cxc_count = 5,
2389         .pd = {
2390                 .name = "camss_vfe",
2391         },
2392         .pwrsts = PWRSTS_OFF_ON,
2393 };
2394
2395 static struct gdsc oxili_gdsc = {
2396         .gdscr = 0x4024,
2397         .cxcs = (unsigned int []){ 0x4028 },
2398         .cxc_count = 1,
2399         .pd = {
2400                 .name = "oxili",
2401         },
2402         .pwrsts = PWRSTS_OFF_ON,
2403 };
2404
2405 static struct gdsc oxilicx_gdsc = {
2406         .gdscr = 0x4034,
2407         .pd = {
2408                 .name = "oxilicx",
2409         },
2410         .parent = &oxili_gdsc.pd,
2411         .pwrsts = PWRSTS_OFF_ON,
2412 };
2413
2414 static struct gdsc oxili_cx_gdsc_msm8226 = {
2415         .gdscr = 0x4034,
2416         .cxcs = (unsigned int []){ 0x4028 },
2417         .cxc_count = 1,
2418         .pd = {
2419                 .name = "oxili_cx",
2420         },
2421         .pwrsts = PWRSTS_OFF_ON,
2422 };
2423
2424 static struct clk_regmap *mmcc_msm8226_clocks[] = {
2425         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2426         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2427         [MMPLL0] = &mmpll0.clkr,
2428         [MMPLL0_VOTE] = &mmpll0_vote,
2429         [MMPLL1] = &mmpll1.clkr,
2430         [MMPLL1_VOTE] = &mmpll1_vote,
2431         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2432         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2433         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2434         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2435         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2436         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2437         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2438         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2439         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2440         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2441         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2442         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2443         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2444         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2445         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2446         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2447         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2448         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2449         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2450         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2451         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2452         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2453         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2454         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2455         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2456         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2457         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2458         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2459         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2460         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2461         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2462         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2463         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2464         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2465         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2466         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2467         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2468         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2469         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2470         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2471         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2472         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2473         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2474         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2475         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2476         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2477         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2478         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2479         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2480         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2481         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2482         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2483         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2484         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2485         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2486         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2487         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2488         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2489         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2490         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2491         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2492         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2493         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2494         [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2495         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2496         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2497         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2498 };
2499
2500 static const struct qcom_reset_map mmcc_msm8226_resets[] = {
2501         [SPDM_RESET] = { 0x0200 },
2502         [SPDM_RM_RESET] = { 0x0300 },
2503         [VENUS0_RESET] = { 0x1020 },
2504         [MDSS_RESET] = { 0x2300 },
2505 };
2506
2507 static struct gdsc *mmcc_msm8226_gdscs[] = {
2508         [VENUS0_GDSC] = &venus0_gdsc,
2509         [MDSS_GDSC] = &mdss_gdsc,
2510         [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2511         [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2512         [OXILICX_GDSC] = &oxili_cx_gdsc_msm8226,
2513 };
2514
2515 static const struct regmap_config mmcc_msm8226_regmap_config = {
2516         .reg_bits       = 32,
2517         .reg_stride     = 4,
2518         .val_bits       = 32,
2519         .max_register   = 0x5104,
2520         .fast_io        = true,
2521 };
2522
2523 static const struct qcom_cc_desc mmcc_msm8226_desc = {
2524         .config = &mmcc_msm8226_regmap_config,
2525         .clks = mmcc_msm8226_clocks,
2526         .num_clks = ARRAY_SIZE(mmcc_msm8226_clocks),
2527         .resets = mmcc_msm8226_resets,
2528         .num_resets = ARRAY_SIZE(mmcc_msm8226_resets),
2529         .gdscs = mmcc_msm8226_gdscs,
2530         .num_gdscs = ARRAY_SIZE(mmcc_msm8226_gdscs),
2531 };
2532
2533 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2534         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2535         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2536         [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2537         [MMPLL0] = &mmpll0.clkr,
2538         [MMPLL0_VOTE] = &mmpll0_vote,
2539         [MMPLL1] = &mmpll1.clkr,
2540         [MMPLL1_VOTE] = &mmpll1_vote,
2541         [MMPLL2] = &mmpll2.clkr,
2542         [MMPLL3] = &mmpll3.clkr,
2543         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2544         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2545         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2546         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2547         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2548         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2549         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2550         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2551         [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2552         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2553         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2554         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2555         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2556         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2557         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2558         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2559         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2560         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2561         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2562         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2563         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2564         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2565         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2566         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2567         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2568         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2569         [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2570         [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2571         [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2572         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2573         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2574         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2575         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2576         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2577         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2578         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2579         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2580         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2581         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2582         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2583         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2584         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2585         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2586         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2587         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2588         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2589         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2590         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2591         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2592         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2593         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2594         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2595         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2596         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2597         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2598         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2599         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2600         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2601         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2602         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2603         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2604         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2605         [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2606         [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2607         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2608         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2609         [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2610         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2611         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2612         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2613         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2614         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2615         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2616         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2617         [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2618         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2619         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2620         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2621         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2622         [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2623         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2624         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2625         [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2626         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2627         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2628         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2629         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2630         [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2631         [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2632         [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2633         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2634         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2635         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2636         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2637         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2638         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2639         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2640         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2641         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2642         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2643         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2644         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2645         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2646         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2647         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2648         [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2649         [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2650         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2651         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2652         [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2653         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2654         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2655         [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2656         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2657 };
2658
2659 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2660         [SPDM_RESET] = { 0x0200 },
2661         [SPDM_RM_RESET] = { 0x0300 },
2662         [VENUS0_RESET] = { 0x1020 },
2663         [MDSS_RESET] = { 0x2300 },
2664         [CAMSS_PHY0_RESET] = { 0x3020 },
2665         [CAMSS_PHY1_RESET] = { 0x3050 },
2666         [CAMSS_PHY2_RESET] = { 0x3080 },
2667         [CAMSS_CSI0_RESET] = { 0x30b0 },
2668         [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2669         [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2670         [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2671         [CAMSS_CSI1_RESET] = { 0x3120 },
2672         [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2673         [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2674         [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2675         [CAMSS_CSI2_RESET] = { 0x3180 },
2676         [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2677         [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2678         [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2679         [CAMSS_CSI3_RESET] = { 0x31e0 },
2680         [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2681         [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2682         [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2683         [CAMSS_ISPIF_RESET] = { 0x3220 },
2684         [CAMSS_CCI_RESET] = { 0x3340 },
2685         [CAMSS_MCLK0_RESET] = { 0x3380 },
2686         [CAMSS_MCLK1_RESET] = { 0x33b0 },
2687         [CAMSS_MCLK2_RESET] = { 0x33e0 },
2688         [CAMSS_MCLK3_RESET] = { 0x3410 },
2689         [CAMSS_GP0_RESET] = { 0x3440 },
2690         [CAMSS_GP1_RESET] = { 0x3470 },
2691         [CAMSS_TOP_RESET] = { 0x3480 },
2692         [CAMSS_MICRO_RESET] = { 0x3490 },
2693         [CAMSS_JPEG_RESET] = { 0x35a0 },
2694         [CAMSS_VFE_RESET] = { 0x36a0 },
2695         [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2696         [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2697         [OXILI_RESET] = { 0x4020 },
2698         [OXILICX_RESET] = { 0x4030 },
2699         [OCMEMCX_RESET] = { 0x4050 },
2700         [MMSS_RBCRP_RESET] = { 0x4080 },
2701         [MMSSNOCAHB_RESET] = { 0x5020 },
2702         [MMSSNOCAXI_RESET] = { 0x5060 },
2703         [OCMEMNOC_RESET] = { 0x50b0 },
2704 };
2705
2706 static struct gdsc *mmcc_msm8974_gdscs[] = {
2707         [VENUS0_GDSC] = &venus0_gdsc,
2708         [MDSS_GDSC] = &mdss_gdsc,
2709         [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2710         [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2711         [OXILI_GDSC] = &oxili_gdsc,
2712         [OXILICX_GDSC] = &oxilicx_gdsc,
2713 };
2714
2715 static const struct regmap_config mmcc_msm8974_regmap_config = {
2716         .reg_bits       = 32,
2717         .reg_stride     = 4,
2718         .val_bits       = 32,
2719         .max_register   = 0x5104,
2720         .fast_io        = true,
2721 };
2722
2723 static const struct qcom_cc_desc mmcc_msm8974_desc = {
2724         .config = &mmcc_msm8974_regmap_config,
2725         .clks = mmcc_msm8974_clocks,
2726         .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2727         .resets = mmcc_msm8974_resets,
2728         .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2729         .gdscs = mmcc_msm8974_gdscs,
2730         .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2731 };
2732
2733 static const struct of_device_id mmcc_msm8974_match_table[] = {
2734         { .compatible = "qcom,mmcc-msm8226", .data = &mmcc_msm8226_desc },
2735         { .compatible = "qcom,mmcc-msm8974", .data = &mmcc_msm8974_desc },
2736         { }
2737 };
2738 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2739
2740 static void msm8226_clock_override(void)
2741 {
2742         mmss_axi_clk_src.freq_tbl = ftbl_mmss_axi_clk_msm8226;
2743         vfe0_clk_src.freq_tbl = ftbl_camss_vfe_vfe0_clk_msm8226;
2744         mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_msm8226;
2745         vcodec0_clk_src.freq_tbl = ftbl_venus0_vcodec0_clk_msm8226;
2746         mclk0_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
2747         mclk1_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
2748         cpp_clk_src.freq_tbl = ftbl_camss_vfe_cpp_clk_msm8226;
2749 }
2750
2751 static int mmcc_msm8974_probe(struct platform_device *pdev)
2752 {
2753         struct regmap *regmap;
2754         const struct qcom_cc_desc *desc;
2755
2756         desc = of_device_get_match_data(&pdev->dev);
2757         if (!desc)
2758                 return -EINVAL;
2759
2760         regmap = qcom_cc_map(pdev, desc);
2761         if (IS_ERR(regmap))
2762                 return PTR_ERR(regmap);
2763
2764         if (desc == &mmcc_msm8974_desc) {
2765                 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2766                 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2767         } else {
2768                 msm8226_clock_override();
2769         }
2770
2771         return qcom_cc_really_probe(&pdev->dev, desc, regmap);
2772 }
2773
2774 static struct platform_driver mmcc_msm8974_driver = {
2775         .probe          = mmcc_msm8974_probe,
2776         .driver         = {
2777                 .name   = "mmcc-msm8974",
2778                 .of_match_table = mmcc_msm8974_match_table,
2779         },
2780 };
2781 module_platform_driver(mmcc_msm8974_driver);
2782
2783 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2784 MODULE_LICENSE("GPL v2");
2785 MODULE_ALIAS("platform:mmcc-msm8974");