1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 #include <linux/kernel.h>
5 #include <linux/init.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
9 #include <linux/of_device.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/regmap.h>
14 #include "clk-regmap.h"
15 #include "clk-hfpll.h"
17 static const struct hfpll_data qcs404 = {
24 .config_val = 0x430405d,
29 .user_vco_mask = 0x100000,
30 .low_vco_max_rate = 1248000000,
31 .min_rate = 537600000UL,
32 .max_rate = 2900000000UL,
35 static const struct hfpll_data msm8976_a53 = {
42 .config_val = 0x341600,
48 .min_rate = 902400000UL,
49 .max_rate = 1478400000UL,
52 static const struct hfpll_data msm8976_a72 = {
59 .config_val = 0x4e0405d,
65 .min_rate = 940800000UL,
66 .max_rate = 2016000000UL,
69 static const struct hfpll_data msm8976_cci = {
76 .config_val = 0x141400,
82 .min_rate = 556800000UL,
83 .max_rate = 902400000UL,
86 static const struct of_device_id qcom_hfpll_match_table[] = {
87 { .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
88 { .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
89 { .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
90 { .compatible = "qcom,qcs404-hfpll", .data = &qcs404 },
91 /* Deprecated in bindings */
92 { .compatible = "qcom,hfpll", .data = &qcs404 },
95 MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
97 static const struct regmap_config hfpll_regmap_config = {
101 .max_register = 0x30,
105 static int qcom_hfpll_probe(struct platform_device *pdev)
107 struct device *dev = &pdev->dev;
109 struct regmap *regmap;
111 struct clk_init_data init = {
113 .ops = &clk_ops_hfpll,
115 * rather than marking the clock critical and forcing the clock
116 * to be always enabled, we make sure that the clock is not
117 * disabled: the firmware remains responsible of enabling this
118 * clock (for more info check the commit log)
120 .flags = CLK_IGNORE_UNUSED,
123 struct clk_parent_data pdata = { .index = 0 };
125 h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
129 base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
131 return PTR_ERR(base);
133 regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
135 return PTR_ERR(regmap);
137 if (of_property_read_string_index(dev->of_node, "clock-output-names",
141 init.parent_data = &pdata;
143 h->d = of_device_get_match_data(&pdev->dev);
144 h->clkr.hw.init = &init;
145 spin_lock_init(&h->lock);
147 ret = devm_clk_register_regmap(dev, &h->clkr);
149 dev_err(dev, "failed to register regmap clock: %d\n", ret);
153 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
157 static struct platform_driver qcom_hfpll_driver = {
158 .probe = qcom_hfpll_probe,
160 .name = "qcom-hfpll",
161 .of_match_table = qcom_hfpll_match_table,
164 module_platform_driver(qcom_hfpll_driver);
166 MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
167 MODULE_LICENSE("GPL v2");
168 MODULE_ALIAS("platform:qcom-hfpll");