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[J-linux.git] / drivers / clk / qcom / gcc-sar2130p.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2021-2023, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2023, Linaro Limited
5  */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12
13 #include <dt-bindings/clock/qcom,sar2130p-gcc.h>
14
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap.h"
19 #include "clk-regmap-divider.h"
20 #include "clk-regmap-mux.h"
21 #include "clk-regmap-phy-mux.h"
22 #include "gdsc.h"
23 #include "reset.h"
24
25 /* Need to match the order of clocks in DT binding */
26 enum {
27         DT_BI_TCXO,
28         DT_SLEEP_CLK,
29
30         DT_PCIE_0_PIPE,
31         DT_PCIE_1_PIPE,
32
33         DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE,
34 };
35
36 enum {
37         P_BI_TCXO,
38         P_GCC_GPLL0_OUT_EVEN,
39         P_GCC_GPLL0_OUT_MAIN,
40         P_GCC_GPLL1_OUT_EVEN,
41         P_GCC_GPLL1_OUT_MAIN,
42         P_GCC_GPLL4_OUT_MAIN,
43         P_GCC_GPLL5_OUT_MAIN,
44         P_GCC_GPLL7_OUT_MAIN,
45         P_GCC_GPLL9_OUT_EVEN,
46         P_PCIE_0_PIPE_CLK,
47         P_PCIE_1_PIPE_CLK,
48         P_SLEEP_CLK,
49         P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
50 };
51
52 static struct clk_alpha_pll gcc_gpll0 = {
53         .offset = 0x0,
54         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
55         .clkr = {
56                 .enable_reg = 0x62018,
57                 .enable_mask = BIT(0),
58                 .hw.init = &(const struct clk_init_data) {
59                         .name = "gcc_gpll0",
60                         .parent_data = &(const struct clk_parent_data) {
61                                 .index = DT_BI_TCXO,
62                         },
63                         .num_parents = 1,
64                         .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
65                 },
66         },
67 };
68
69 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
70         { 0x1, 2 },
71         { }
72 };
73
74 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
75         .offset = 0x0,
76         .post_div_shift = 10,
77         .post_div_table = post_div_table_gcc_gpll0_out_even,
78         .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
79         .width = 4,
80         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
81         .clkr.hw.init = &(const struct clk_init_data) {
82                 .name = "gcc_gpll0_out_even",
83                 .parent_hws = (const struct clk_hw*[]) {
84                         &gcc_gpll0.clkr.hw,
85                 },
86                 .num_parents = 1,
87                 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
88         },
89 };
90
91 static struct clk_alpha_pll gcc_gpll1 = {
92         .offset = 0x1000,
93         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
94         .clkr = {
95                 .enable_reg = 0x62018,
96                 .enable_mask = BIT(1),
97                 .hw.init = &(const struct clk_init_data) {
98                         .name = "gcc_gpll1",
99                         .parent_data = &(const struct clk_parent_data) {
100                                 .index = DT_BI_TCXO,
101                         },
102                         .num_parents = 1,
103                         .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
104                 },
105         },
106 };
107
108 static struct clk_alpha_pll gcc_gpll4 = {
109         .offset = 0x4000,
110         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
111         .clkr = {
112                 .enable_reg = 0x62018,
113                 .enable_mask = BIT(4),
114                 .hw.init = &(const struct clk_init_data) {
115                         .name = "gcc_gpll4",
116                         .parent_data = &(const struct clk_parent_data) {
117                                 .index = DT_BI_TCXO,
118                         },
119                         .num_parents = 1,
120                         .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
121                 },
122         },
123 };
124
125 static struct clk_alpha_pll gcc_gpll5 = {
126         .offset = 0x5000,
127         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
128         .clkr = {
129                 .enable_reg = 0x62018,
130                 .enable_mask = BIT(5),
131                 .hw.init = &(const struct clk_init_data) {
132                         .name = "gcc_gpll5",
133                         .parent_data = &(const struct clk_parent_data) {
134                                 .index = DT_BI_TCXO,
135                         },
136                         .num_parents = 1,
137                         .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
138                 },
139         },
140 };
141
142 static struct clk_alpha_pll gcc_gpll7 = {
143         .offset = 0x7000,
144         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
145         .clkr = {
146                 .enable_reg = 0x62018,
147                 .enable_mask = BIT(7),
148                 .hw.init = &(const struct clk_init_data) {
149                         .name = "gcc_gpll7",
150                         .parent_data = &(const struct clk_parent_data) {
151                                 .index = DT_BI_TCXO,
152                         },
153                         .num_parents = 1,
154                         .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
155                 },
156         },
157 };
158
159 static struct clk_alpha_pll gcc_gpll9 = {
160         .offset = 0x9000,
161         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
162         .clkr = {
163                 .enable_reg = 0x62018,
164                 .enable_mask = BIT(9),
165                 .hw.init = &(const struct clk_init_data) {
166                         .name = "gcc_gpll9",
167                         .parent_data = &(const struct clk_parent_data) {
168                                 .index = DT_BI_TCXO,
169                         },
170                         .num_parents = 1,
171                         .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
172                 },
173         },
174 };
175
176 static const struct clk_div_table post_div_table_gcc_gpll9_out_even[] = {
177         { 0x1, 2 },
178         { }
179 };
180
181 static struct clk_alpha_pll_postdiv gcc_gpll9_out_even = {
182         .offset = 0x9000,
183         .post_div_shift = 10,
184         .post_div_table = post_div_table_gcc_gpll9_out_even,
185         .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll9_out_even),
186         .width = 4,
187         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
188         .clkr.hw.init = &(const struct clk_init_data) {
189                 .name = "gcc_gpll9_out_even",
190                 .parent_hws = (const struct clk_hw*[]) {
191                         &gcc_gpll9.clkr.hw,
192                 },
193                 .num_parents = 1,
194                 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
195         },
196 };
197
198 static const struct parent_map gcc_parent_map_0[] = {
199         { P_BI_TCXO, 0 },
200         { P_GCC_GPLL0_OUT_MAIN, 1 },
201         { P_GCC_GPLL0_OUT_EVEN, 6 },
202 };
203
204 static const struct clk_parent_data gcc_parent_data_0[] = {
205         { .index = DT_BI_TCXO },
206         { .hw = &gcc_gpll0.clkr.hw },
207         { .hw = &gcc_gpll0_out_even.clkr.hw },
208 };
209
210 static const struct parent_map gcc_parent_map_1[] = {
211         { P_BI_TCXO, 0 },
212         { P_GCC_GPLL0_OUT_MAIN, 1 },
213         { P_SLEEP_CLK, 5 },
214         { P_GCC_GPLL0_OUT_EVEN, 6 },
215 };
216
217 static const struct clk_parent_data gcc_parent_data_1[] = {
218         { .index = DT_BI_TCXO },
219         { .hw = &gcc_gpll0.clkr.hw },
220         { .index = DT_SLEEP_CLK },
221         { .hw = &gcc_gpll0_out_even.clkr.hw },
222 };
223
224 static const struct parent_map gcc_parent_map_2[] = {
225         { P_BI_TCXO, 0 },
226         { P_GCC_GPLL0_OUT_MAIN, 1 },
227         { P_GCC_GPLL7_OUT_MAIN, 2 },
228         { P_GCC_GPLL5_OUT_MAIN, 3 },
229         { P_GCC_GPLL1_OUT_MAIN, 4 },
230         { P_GCC_GPLL4_OUT_MAIN, 5 },
231         { P_GCC_GPLL0_OUT_EVEN, 6 },
232 };
233
234 static const struct clk_parent_data gcc_parent_data_2[] = {
235         { .index = DT_BI_TCXO },
236         { .hw = &gcc_gpll0.clkr.hw },
237         { .hw = &gcc_gpll7.clkr.hw },
238         { .hw = &gcc_gpll5.clkr.hw },
239         { .hw = &gcc_gpll1.clkr.hw },
240         { .hw = &gcc_gpll4.clkr.hw },
241         { .hw = &gcc_gpll0_out_even.clkr.hw },
242 };
243
244 static const struct parent_map gcc_parent_map_3[] = {
245         { P_BI_TCXO, 0 },
246         { P_SLEEP_CLK, 5 },
247 };
248
249 static const struct clk_parent_data gcc_parent_data_3[] = {
250         { .index = DT_BI_TCXO },
251         { .index = DT_SLEEP_CLK },
252 };
253
254 static const struct parent_map gcc_parent_map_6[] = {
255         { P_BI_TCXO, 0 },
256         { P_GCC_GPLL0_OUT_MAIN, 1 },
257         { P_GCC_GPLL9_OUT_EVEN, 2 },
258         { P_GCC_GPLL0_OUT_EVEN, 6 },
259 };
260
261 static const struct clk_parent_data gcc_parent_data_6[] = {
262         { .index = DT_BI_TCXO },
263         { .hw = &gcc_gpll0.clkr.hw },
264         { .hw = &gcc_gpll9_out_even.clkr.hw },
265         { .hw = &gcc_gpll0_out_even.clkr.hw },
266 };
267
268 static const struct parent_map gcc_parent_map_7[] = {
269         { P_BI_TCXO, 0 },
270         { P_GCC_GPLL0_OUT_MAIN, 1 },
271         { P_GCC_GPLL1_OUT_EVEN, 2 },
272         { P_GCC_GPLL0_OUT_EVEN, 6 },
273 };
274
275 static const struct clk_parent_data gcc_parent_data_7[] = {
276         { .index = DT_BI_TCXO },
277         { .hw = &gcc_gpll0.clkr.hw },
278         { .hw = &gcc_gpll1.clkr.hw },
279         { .hw = &gcc_gpll0_out_even.clkr.hw },
280 };
281
282 static const struct parent_map gcc_parent_map_8[] = {
283         { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
284         { P_BI_TCXO, 2 },
285 };
286
287 static const struct clk_parent_data gcc_parent_data_8[] = {
288         { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE },
289         { .index = DT_BI_TCXO },
290 };
291
292 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
293         .reg = 0x7b070,
294         .clkr = {
295                 .hw.init = &(const struct clk_init_data) {
296                         .name = "gcc_pcie_0_pipe_clk_src",
297                         .parent_data = &(const struct clk_parent_data) {
298                                 .index = DT_PCIE_0_PIPE,
299                         },
300                         .num_parents = 1,
301                         .ops = &clk_regmap_phy_mux_ops,
302                 },
303         },
304 };
305
306 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
307         .reg = 0x9d06c,
308         .clkr = {
309                 .hw.init = &(const struct clk_init_data) {
310                         .name = "gcc_pcie_1_pipe_clk_src",
311                         .parent_data = &(const struct clk_parent_data) {
312                                 .index = DT_PCIE_1_PIPE,
313                         },
314                         .num_parents = 1,
315                         .ops = &clk_regmap_phy_mux_ops,
316                 },
317         },
318 };
319
320 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
321         .reg = 0x4906c,
322         .shift = 0,
323         .width = 2,
324         .parent_map = gcc_parent_map_8,
325         .clkr = {
326                 .hw.init = &(const struct clk_init_data) {
327                         .name = "gcc_usb3_prim_phy_pipe_clk_src",
328                         .parent_data = gcc_parent_data_8,
329                         .num_parents = ARRAY_SIZE(gcc_parent_data_8),
330                         .ops = &clk_regmap_mux_closest_ops,
331                 },
332         },
333 };
334
335 static const struct freq_tbl ftbl_gcc_ddrss_spad_clk_src[] = {
336         F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
337         F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
338         F(426400000, P_GCC_GPLL1_OUT_MAIN, 2.5, 0, 0),
339         F(500000000, P_GCC_GPLL7_OUT_MAIN, 1, 0, 0),
340         { }
341 };
342
343 static struct clk_rcg2 gcc_ddrss_spad_clk_src = {
344         .cmd_rcgr = 0x70004,
345         .mnd_width = 0,
346         .hid_width = 5,
347         .parent_map = gcc_parent_map_2,
348         .freq_tbl = ftbl_gcc_ddrss_spad_clk_src,
349         .clkr.hw.init = &(const struct clk_init_data) {
350                 .name = "gcc_ddrss_spad_clk_src",
351                 .parent_data = gcc_parent_data_2,
352                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
353                 .ops = &clk_rcg2_shared_ops,
354         },
355 };
356
357 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
358         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
359         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
360         F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
361         { }
362 };
363
364 static struct clk_rcg2 gcc_gp1_clk_src = {
365         .cmd_rcgr = 0x74004,
366         .mnd_width = 16,
367         .hid_width = 5,
368         .parent_map = gcc_parent_map_1,
369         .freq_tbl = ftbl_gcc_gp1_clk_src,
370         .clkr.hw.init = &(const struct clk_init_data) {
371                 .name = "gcc_gp1_clk_src",
372                 .parent_data = gcc_parent_data_1,
373                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
374                 .ops = &clk_rcg2_shared_ops,
375         },
376 };
377
378 static struct clk_rcg2 gcc_gp2_clk_src = {
379         .cmd_rcgr = 0x75004,
380         .mnd_width = 16,
381         .hid_width = 5,
382         .parent_map = gcc_parent_map_1,
383         .freq_tbl = ftbl_gcc_gp1_clk_src,
384         .clkr.hw.init = &(const struct clk_init_data) {
385                 .name = "gcc_gp2_clk_src",
386                 .parent_data = gcc_parent_data_1,
387                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
388                 .ops = &clk_rcg2_shared_ops,
389         },
390 };
391
392 static struct clk_rcg2 gcc_gp3_clk_src = {
393         .cmd_rcgr = 0x76004,
394         .mnd_width = 16,
395         .hid_width = 5,
396         .parent_map = gcc_parent_map_1,
397         .freq_tbl = ftbl_gcc_gp1_clk_src,
398         .clkr.hw.init = &(const struct clk_init_data) {
399                 .name = "gcc_gp3_clk_src",
400                 .parent_data = gcc_parent_data_1,
401                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
402                 .ops = &clk_rcg2_shared_ops,
403         },
404 };
405
406 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
407         F(19200000, P_BI_TCXO, 1, 0, 0),
408         { }
409 };
410
411 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
412         .cmd_rcgr = 0x7b074,
413         .mnd_width = 16,
414         .hid_width = 5,
415         .parent_map = gcc_parent_map_3,
416         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
417         .clkr.hw.init = &(const struct clk_init_data) {
418                 .name = "gcc_pcie_0_aux_clk_src",
419                 .parent_data = gcc_parent_data_3,
420                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
421                 .ops = &clk_rcg2_shared_ops,
422         },
423 };
424
425 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
426         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
427         { }
428 };
429
430 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
431         .cmd_rcgr = 0x7b058,
432         .mnd_width = 0,
433         .hid_width = 5,
434         .parent_map = gcc_parent_map_0,
435         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
436         .clkr.hw.init = &(const struct clk_init_data) {
437                 .name = "gcc_pcie_0_phy_rchng_clk_src",
438                 .parent_data = gcc_parent_data_0,
439                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
440                 .ops = &clk_rcg2_shared_ops,
441         },
442 };
443
444 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
445         .cmd_rcgr = 0x9d070,
446         .mnd_width = 16,
447         .hid_width = 5,
448         .parent_map = gcc_parent_map_3,
449         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
450         .clkr.hw.init = &(const struct clk_init_data) {
451                 .name = "gcc_pcie_1_aux_clk_src",
452                 .parent_data = gcc_parent_data_3,
453                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
454                 .ops = &clk_rcg2_shared_ops,
455         },
456 };
457
458 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
459         .cmd_rcgr = 0x9d054,
460         .mnd_width = 0,
461         .hid_width = 5,
462         .parent_map = gcc_parent_map_0,
463         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
464         .clkr.hw.init = &(const struct clk_init_data) {
465                 .name = "gcc_pcie_1_phy_rchng_clk_src",
466                 .parent_data = gcc_parent_data_0,
467                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
468                 .ops = &clk_rcg2_shared_ops,
469         },
470 };
471
472 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
473         F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
474         { }
475 };
476
477 static struct clk_rcg2 gcc_pdm2_clk_src = {
478         .cmd_rcgr = 0x43010,
479         .mnd_width = 0,
480         .hid_width = 5,
481         .parent_map = gcc_parent_map_0,
482         .freq_tbl = ftbl_gcc_pdm2_clk_src,
483         .clkr.hw.init = &(const struct clk_init_data) {
484                 .name = "gcc_pdm2_clk_src",
485                 .parent_data = gcc_parent_data_0,
486                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
487                 .ops = &clk_rcg2_shared_ops,
488         },
489 };
490
491 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
492         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
493         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
494         F(19200000, P_BI_TCXO, 1, 0, 0),
495         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
496         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
497         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
498         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
499         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
500         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
501         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
502         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
503         F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
504         F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
505         F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
506         F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
507         { }
508 };
509
510 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
511         .name = "gcc_qupv3_wrap0_s0_clk_src",
512         .parent_data = gcc_parent_data_0,
513         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
514         .ops = &clk_rcg2_shared_ops,
515 };
516
517 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
518         .cmd_rcgr = 0x28018,
519         .mnd_width = 16,
520         .hid_width = 5,
521         .parent_map = gcc_parent_map_0,
522         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
523         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
524 };
525
526 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s1_clk_src[] = {
527         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
528         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
529         F(19200000, P_BI_TCXO, 1, 0, 0),
530         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
531         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
532         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
533         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
534         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
535         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
536         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
537         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
538         { }
539 };
540
541 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
542         .name = "gcc_qupv3_wrap0_s1_clk_src",
543         .parent_data = gcc_parent_data_0,
544         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
545         .ops = &clk_rcg2_shared_ops,
546 };
547
548 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
549         .cmd_rcgr = 0x28150,
550         .mnd_width = 16,
551         .hid_width = 5,
552         .parent_map = gcc_parent_map_0,
553         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
554         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
555 };
556
557 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
558         .name = "gcc_qupv3_wrap0_s2_clk_src",
559         .parent_data = gcc_parent_data_0,
560         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
561         .ops = &clk_rcg2_shared_ops,
562 };
563
564 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
565         .cmd_rcgr = 0x28288,
566         .mnd_width = 16,
567         .hid_width = 5,
568         .parent_map = gcc_parent_map_0,
569         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
570         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
571 };
572
573 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
574         .name = "gcc_qupv3_wrap0_s3_clk_src",
575         .parent_data = gcc_parent_data_0,
576         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
577         .ops = &clk_rcg2_shared_ops,
578 };
579
580 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
581         .cmd_rcgr = 0x283c0,
582         .mnd_width = 16,
583         .hid_width = 5,
584         .parent_map = gcc_parent_map_0,
585         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
586         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
587 };
588
589 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
590         .name = "gcc_qupv3_wrap0_s4_clk_src",
591         .parent_data = gcc_parent_data_0,
592         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
593         .ops = &clk_rcg2_shared_ops,
594 };
595
596 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
597         .cmd_rcgr = 0x284f8,
598         .mnd_width = 16,
599         .hid_width = 5,
600         .parent_map = gcc_parent_map_0,
601         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
602         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
603 };
604
605 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
606         .name = "gcc_qupv3_wrap0_s5_clk_src",
607         .parent_data = gcc_parent_data_0,
608         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
609         .ops = &clk_rcg2_shared_ops,
610 };
611
612 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
613         .cmd_rcgr = 0x28630,
614         .mnd_width = 16,
615         .hid_width = 5,
616         .parent_map = gcc_parent_map_0,
617         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
618         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
619 };
620
621 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
622         .name = "gcc_qupv3_wrap1_s0_clk_src",
623         .parent_data = gcc_parent_data_0,
624         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
625         .ops = &clk_rcg2_shared_ops,
626 };
627
628 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
629         .cmd_rcgr = 0x2e018,
630         .mnd_width = 16,
631         .hid_width = 5,
632         .parent_map = gcc_parent_map_0,
633         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
634         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
635 };
636
637 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
638         .name = "gcc_qupv3_wrap1_s1_clk_src",
639         .parent_data = gcc_parent_data_0,
640         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
641         .ops = &clk_rcg2_shared_ops,
642 };
643
644 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
645         .cmd_rcgr = 0x2e150,
646         .mnd_width = 16,
647         .hid_width = 5,
648         .parent_map = gcc_parent_map_0,
649         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
650         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
651 };
652
653 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
654         .name = "gcc_qupv3_wrap1_s2_clk_src",
655         .parent_data = gcc_parent_data_0,
656         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
657         .ops = &clk_rcg2_shared_ops,
658 };
659
660 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
661         .cmd_rcgr = 0x2e288,
662         .mnd_width = 16,
663         .hid_width = 5,
664         .parent_map = gcc_parent_map_0,
665         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
666         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
667 };
668
669 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
670         .name = "gcc_qupv3_wrap1_s3_clk_src",
671         .parent_data = gcc_parent_data_0,
672         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
673         .ops = &clk_rcg2_shared_ops,
674 };
675
676 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
677         .cmd_rcgr = 0x2e3c0,
678         .mnd_width = 16,
679         .hid_width = 5,
680         .parent_map = gcc_parent_map_0,
681         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
682         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
683 };
684
685 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
686         .name = "gcc_qupv3_wrap1_s4_clk_src",
687         .parent_data = gcc_parent_data_0,
688         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
689         .ops = &clk_rcg2_shared_ops,
690 };
691
692 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
693         .cmd_rcgr = 0x2e4f8,
694         .mnd_width = 16,
695         .hid_width = 5,
696         .parent_map = gcc_parent_map_0,
697         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
698         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
699 };
700
701 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
702         .name = "gcc_qupv3_wrap1_s5_clk_src",
703         .parent_data = gcc_parent_data_0,
704         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
705         .ops = &clk_rcg2_shared_ops,
706 };
707
708 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
709         .cmd_rcgr = 0x2e630,
710         .mnd_width = 16,
711         .hid_width = 5,
712         .parent_map = gcc_parent_map_0,
713         .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,
714         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
715 };
716
717 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
718         F(144000, P_BI_TCXO, 16, 3, 25),
719         F(400000, P_BI_TCXO, 12, 1, 4),
720         F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
721         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
722         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
723         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
724         F(192000000, P_GCC_GPLL9_OUT_EVEN, 2, 0, 0),
725         F(384000000, P_GCC_GPLL9_OUT_EVEN, 1, 0, 0),
726         { }
727 };
728
729 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
730         .cmd_rcgr = 0x26018,
731         .mnd_width = 8,
732         .hid_width = 5,
733         .parent_map = gcc_parent_map_6,
734         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
735         .clkr.hw.init = &(const struct clk_init_data) {
736                 .name = "gcc_sdcc1_apps_clk_src",
737                 .parent_data = gcc_parent_data_6,
738                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
739                 .ops = &clk_rcg2_shared_floor_ops,
740         },
741 };
742
743 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
744         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
745         F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
746         F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
747         { }
748 };
749
750 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
751         .cmd_rcgr = 0x2603c,
752         .mnd_width = 0,
753         .hid_width = 5,
754         .parent_map = gcc_parent_map_7,
755         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
756         .clkr.hw.init = &(const struct clk_init_data) {
757                 .name = "gcc_sdcc1_ice_core_clk_src",
758                 .parent_data = gcc_parent_data_7,
759                 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
760                 .ops = &clk_rcg2_shared_floor_ops,
761         },
762 };
763
764 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
765         F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
766         F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
767         F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
768         { }
769 };
770
771 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
772         .cmd_rcgr = 0x4902c,
773         .mnd_width = 8,
774         .hid_width = 5,
775         .parent_map = gcc_parent_map_0,
776         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
777         .clkr.hw.init = &(const struct clk_init_data) {
778                 .name = "gcc_usb30_prim_master_clk_src",
779                 .parent_data = gcc_parent_data_0,
780                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
781                 .ops = &clk_rcg2_shared_ops,
782         },
783 };
784
785 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
786         .cmd_rcgr = 0x49044,
787         .mnd_width = 0,
788         .hid_width = 5,
789         .parent_map = gcc_parent_map_0,
790         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
791         .clkr.hw.init = &(const struct clk_init_data) {
792                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
793                 .parent_data = gcc_parent_data_0,
794                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
795                 .ops = &clk_rcg2_shared_ops,
796         },
797 };
798
799 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
800         .cmd_rcgr = 0x49070,
801         .mnd_width = 0,
802         .hid_width = 5,
803         .parent_map = gcc_parent_map_3,
804         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
805         .clkr.hw.init = &(const struct clk_init_data) {
806                 .name = "gcc_usb3_prim_phy_aux_clk_src",
807                 .parent_data = gcc_parent_data_3,
808                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
809                 .ops = &clk_rcg2_shared_ops,
810         },
811 };
812
813 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
814         .reg = 0x4905c,
815         .shift = 0,
816         .width = 4,
817         .clkr.hw.init = &(const struct clk_init_data) {
818                 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
819                 .parent_hws = (const struct clk_hw*[]) {
820                         &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
821                 },
822                 .num_parents = 1,
823                 .flags = CLK_SET_RATE_PARENT,
824                 .ops = &clk_regmap_div_ro_ops,
825         },
826 };
827
828 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
829         .halt_reg = 0x7b094,
830         .halt_check = BRANCH_HALT_SKIP,
831         .hwcg_reg = 0x7b094,
832         .hwcg_bit = 1,
833         .clkr = {
834                 .enable_reg = 0x62000,
835                 .enable_mask = BIT(17),
836                 .hw.init = &(const struct clk_init_data) {
837                         .name = "gcc_aggre_noc_pcie_1_axi_clk",
838                         .ops = &clk_branch2_ops,
839                 },
840         },
841 };
842
843 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
844         .halt_reg = 0x4908c,
845         .halt_check = BRANCH_HALT_VOTED,
846         .hwcg_reg = 0x4908c,
847         .hwcg_bit = 1,
848         .clkr = {
849                 .enable_reg = 0x4908c,
850                 .enable_mask = BIT(0),
851                 .hw.init = &(const struct clk_init_data) {
852                         .name = "gcc_aggre_usb3_prim_axi_clk",
853                         .parent_hws = (const struct clk_hw*[]) {
854                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
855                         },
856                         .num_parents = 1,
857                         .flags = CLK_SET_RATE_PARENT,
858                         .ops = &clk_branch2_ops,
859                 },
860         },
861 };
862
863 static struct clk_branch gcc_boot_rom_ahb_clk = {
864         .halt_reg = 0x48004,
865         .halt_check = BRANCH_HALT_VOTED,
866         .hwcg_reg = 0x48004,
867         .hwcg_bit = 1,
868         .clkr = {
869                 .enable_reg = 0x62000,
870                 .enable_mask = BIT(10),
871                 .hw.init = &(const struct clk_init_data) {
872                         .name = "gcc_boot_rom_ahb_clk",
873                         .ops = &clk_branch2_ops,
874                 },
875         },
876 };
877
878 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
879         .halt_reg = 0x20034,
880         .halt_check = BRANCH_HALT_VOTED,
881         .hwcg_reg = 0x20034,
882         .hwcg_bit = 1,
883         .clkr = {
884                 .enable_reg = 0x62000,
885                 .enable_mask = BIT(20),
886                 .hw.init = &(const struct clk_init_data) {
887                         .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
888                         .ops = &clk_branch2_ops,
889                 },
890         },
891 };
892
893 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
894         .halt_reg = 0x49088,
895         .halt_check = BRANCH_HALT_VOTED,
896         .hwcg_reg = 0x49088,
897         .hwcg_bit = 1,
898         .clkr = {
899                 .enable_reg = 0x49088,
900                 .enable_mask = BIT(0),
901                 .hw.init = &(const struct clk_init_data) {
902                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
903                         .parent_hws = (const struct clk_hw*[]) {
904                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
905                         },
906                         .num_parents = 1,
907                         .flags = CLK_SET_RATE_PARENT,
908                         .ops = &clk_branch2_ops,
909                 },
910         },
911 };
912
913 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
914         .halt_reg = 0x81154,
915         .halt_check = BRANCH_HALT_SKIP,
916         .hwcg_reg = 0x81154,
917         .hwcg_bit = 1,
918         .clkr = {
919                 .enable_reg = 0x81154,
920                 .enable_mask = BIT(0),
921                 .hw.init = &(const struct clk_init_data) {
922                         .name = "gcc_ddrss_gpu_axi_clk",
923                         .ops = &clk_branch2_aon_ops,
924                 },
925         },
926 };
927
928 static struct clk_branch gcc_ddrss_pcie_sf_clk = {
929         .halt_reg = 0x9d098,
930         .halt_check = BRANCH_HALT_SKIP,
931         .hwcg_reg = 0x9d098,
932         .hwcg_bit = 1,
933         .clkr = {
934                 .enable_reg = 0x62000,
935                 .enable_mask = BIT(19),
936                 .hw.init = &(const struct clk_init_data) {
937                         .name = "gcc_ddrss_pcie_sf_clk",
938                         .ops = &clk_branch2_ops,
939                 },
940         },
941 };
942
943 static struct clk_branch gcc_ddrss_spad_clk = {
944         .halt_reg = 0x70000,
945         .halt_check = BRANCH_HALT_VOTED,
946         .hwcg_reg = 0x70000,
947         .hwcg_bit = 1,
948         .clkr = {
949                 .enable_reg = 0x70000,
950                 .enable_mask = BIT(0),
951                 .hw.init = &(const struct clk_init_data) {
952                         .name = "gcc_ddrss_spad_clk",
953                         .parent_hws = (const struct clk_hw*[]) {
954                                 &gcc_ddrss_spad_clk_src.clkr.hw,
955                         },
956                         .num_parents = 1,
957                         .flags = CLK_SET_RATE_PARENT,
958                         .ops = &clk_branch2_ops,
959                 },
960         },
961 };
962
963 static struct clk_branch gcc_disp_hf_axi_clk = {
964         .halt_reg = 0x37008,
965         .halt_check = BRANCH_HALT_SKIP,
966         .hwcg_reg = 0x37008,
967         .hwcg_bit = 1,
968         .clkr = {
969                 .enable_reg = 0x37008,
970                 .enable_mask = BIT(0),
971                 .hw.init = &(const struct clk_init_data) {
972                         .name = "gcc_disp_hf_axi_clk",
973                         .ops = &clk_branch2_ops,
974                 },
975         },
976 };
977
978 static struct clk_branch gcc_gp1_clk = {
979         .halt_reg = 0x74000,
980         .halt_check = BRANCH_HALT,
981         .clkr = {
982                 .enable_reg = 0x74000,
983                 .enable_mask = BIT(0),
984                 .hw.init = &(const struct clk_init_data) {
985                         .name = "gcc_gp1_clk",
986                         .parent_hws = (const struct clk_hw*[]) {
987                                 &gcc_gp1_clk_src.clkr.hw,
988                         },
989                         .num_parents = 1,
990                         .flags = CLK_SET_RATE_PARENT,
991                         .ops = &clk_branch2_ops,
992                 },
993         },
994 };
995
996 static struct clk_branch gcc_gp2_clk = {
997         .halt_reg = 0x75000,
998         .halt_check = BRANCH_HALT,
999         .clkr = {
1000                 .enable_reg = 0x75000,
1001                 .enable_mask = BIT(0),
1002                 .hw.init = &(const struct clk_init_data) {
1003                         .name = "gcc_gp2_clk",
1004                         .parent_hws = (const struct clk_hw*[]) {
1005                                 &gcc_gp2_clk_src.clkr.hw,
1006                         },
1007                         .num_parents = 1,
1008                         .flags = CLK_SET_RATE_PARENT,
1009                         .ops = &clk_branch2_ops,
1010                 },
1011         },
1012 };
1013
1014 static struct clk_branch gcc_gp3_clk = {
1015         .halt_reg = 0x76000,
1016         .halt_check = BRANCH_HALT,
1017         .clkr = {
1018                 .enable_reg = 0x76000,
1019                 .enable_mask = BIT(0),
1020                 .hw.init = &(const struct clk_init_data) {
1021                         .name = "gcc_gp3_clk",
1022                         .parent_hws = (const struct clk_hw*[]) {
1023                                 &gcc_gp3_clk_src.clkr.hw,
1024                         },
1025                         .num_parents = 1,
1026                         .flags = CLK_SET_RATE_PARENT,
1027                         .ops = &clk_branch2_ops,
1028                 },
1029         },
1030 };
1031
1032 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1033         .halt_check = BRANCH_HALT_DELAY,
1034         .clkr = {
1035                 .enable_reg = 0x62000,
1036                 .enable_mask = BIT(15),
1037                 .hw.init = &(const struct clk_init_data) {
1038                         .name = "gcc_gpu_gpll0_clk_src",
1039                         .parent_hws = (const struct clk_hw*[]) {
1040                                 &gcc_gpll0.clkr.hw,
1041                         },
1042                         .num_parents = 1,
1043                         .flags = CLK_SET_RATE_PARENT,
1044                         .ops = &clk_branch2_ops,
1045                 },
1046         },
1047 };
1048
1049 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1050         .halt_check = BRANCH_HALT_DELAY,
1051         .clkr = {
1052                 .enable_reg = 0x62000,
1053                 .enable_mask = BIT(16),
1054                 .hw.init = &(const struct clk_init_data) {
1055                         .name = "gcc_gpu_gpll0_div_clk_src",
1056                         .parent_hws = (const struct clk_hw*[]) {
1057                                 &gcc_gpll0_out_even.clkr.hw,
1058                         },
1059                         .num_parents = 1,
1060                         .flags = CLK_SET_RATE_PARENT,
1061                         .ops = &clk_branch2_ops,
1062                 },
1063         },
1064 };
1065
1066 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1067         .halt_reg = 0x9b010,
1068         .halt_check = BRANCH_HALT_VOTED,
1069         .hwcg_reg = 0x9b010,
1070         .hwcg_bit = 1,
1071         .clkr = {
1072                 .enable_reg = 0x9b010,
1073                 .enable_mask = BIT(0),
1074                 .hw.init = &(const struct clk_init_data) {
1075                         .name = "gcc_gpu_memnoc_gfx_clk",
1076                         .ops = &clk_branch2_ops,
1077                 },
1078         },
1079 };
1080
1081 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1082         .halt_reg = 0x9b018,
1083         .halt_check = BRANCH_HALT_DELAY,
1084         .clkr = {
1085                 .enable_reg = 0x9b018,
1086                 .enable_mask = BIT(0),
1087                 .hw.init = &(const struct clk_init_data) {
1088                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1089                         .ops = &clk_branch2_ops,
1090                 },
1091         },
1092 };
1093
1094 static struct clk_branch gcc_iris_ss_hf_axi1_clk = {
1095         .halt_reg = 0x42030,
1096         .halt_check = BRANCH_HALT_SKIP,
1097         .hwcg_reg = 0x42030,
1098         .hwcg_bit = 1,
1099         .clkr = {
1100                 .enable_reg = 0x42030,
1101                 .enable_mask = BIT(0),
1102                 .hw.init = &(const struct clk_init_data) {
1103                         .name = "gcc_iris_ss_hf_axi1_clk",
1104                         .ops = &clk_branch2_ops,
1105                 },
1106         },
1107 };
1108
1109 static struct clk_branch gcc_iris_ss_spd_axi1_clk = {
1110         .halt_reg = 0x70020,
1111         .halt_check = BRANCH_HALT_VOTED,
1112         .hwcg_reg = 0x70020,
1113         .hwcg_bit = 1,
1114         .clkr = {
1115                 .enable_reg = 0x70020,
1116                 .enable_mask = BIT(0),
1117                 .hw.init = &(const struct clk_init_data) {
1118                         .name = "gcc_iris_ss_spd_axi1_clk",
1119                         .parent_hws = (const struct clk_hw*[]) {
1120                                 &gcc_ddrss_spad_clk_src.clkr.hw,
1121                         },
1122                         .num_parents = 1,
1123                         .flags = CLK_SET_RATE_PARENT,
1124                         .ops = &clk_branch2_ops,
1125                 },
1126         },
1127 };
1128
1129 static struct clk_branch gcc_pcie_0_aux_clk = {
1130         .halt_reg = 0x7b03c,
1131         .halt_check = BRANCH_HALT_VOTED,
1132         .clkr = {
1133                 .enable_reg = 0x62008,
1134                 .enable_mask = BIT(3),
1135                 .hw.init = &(const struct clk_init_data) {
1136                         .name = "gcc_pcie_0_aux_clk",
1137                         .parent_hws = (const struct clk_hw*[]) {
1138                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
1139                         },
1140                         .num_parents = 1,
1141                         .flags = CLK_SET_RATE_PARENT,
1142                         .ops = &clk_branch2_ops,
1143                 },
1144         },
1145 };
1146
1147 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1148         .halt_reg = 0x7b038,
1149         .halt_check = BRANCH_HALT_VOTED,
1150         .hwcg_reg = 0x7b038,
1151         .hwcg_bit = 1,
1152         .clkr = {
1153                 .enable_reg = 0x62008,
1154                 .enable_mask = BIT(2),
1155                 .hw.init = &(const struct clk_init_data) {
1156                         .name = "gcc_pcie_0_cfg_ahb_clk",
1157                         .ops = &clk_branch2_ops,
1158                 },
1159         },
1160 };
1161
1162 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1163         .halt_reg = 0x7b02c,
1164         .halt_check = BRANCH_HALT_SKIP,
1165         .hwcg_reg = 0x7b02c,
1166         .hwcg_bit = 1,
1167         .clkr = {
1168                 .enable_reg = 0x62008,
1169                 .enable_mask = BIT(1),
1170                 .hw.init = &(const struct clk_init_data) {
1171                         .name = "gcc_pcie_0_mstr_axi_clk",
1172                         .ops = &clk_branch2_ops,
1173                 },
1174         },
1175 };
1176
1177 static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1178         .halt_reg = 0x7b054,
1179         .halt_check = BRANCH_HALT_VOTED,
1180         .clkr = {
1181                 .enable_reg = 0x62000,
1182                 .enable_mask = BIT(22),
1183                 .hw.init = &(const struct clk_init_data) {
1184                         .name = "gcc_pcie_0_phy_rchng_clk",
1185                         .parent_hws = (const struct clk_hw*[]) {
1186                                 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1187                         },
1188                         .num_parents = 1,
1189                         .flags = CLK_SET_RATE_PARENT,
1190                         .ops = &clk_branch2_ops,
1191                 },
1192         },
1193 };
1194
1195 static struct clk_branch gcc_pcie_0_pipe_clk = {
1196         .halt_reg = 0x7b048,
1197         .halt_check = BRANCH_HALT_SKIP,
1198         .clkr = {
1199                 .enable_reg = 0x62008,
1200                 .enable_mask = BIT(4),
1201                 .hw.init = &(const struct clk_init_data) {
1202                         .name = "gcc_pcie_0_pipe_clk",
1203                         .parent_hws = (const struct clk_hw*[]) {
1204                                 &gcc_pcie_0_pipe_clk_src.clkr.hw,
1205                         },
1206                         .num_parents = 1,
1207                         .flags = CLK_SET_RATE_PARENT,
1208                         .ops = &clk_branch2_ops,
1209                 },
1210         },
1211 };
1212
1213 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1214         .halt_reg = 0x7b020,
1215         .halt_check = BRANCH_HALT_VOTED,
1216         .hwcg_reg = 0x7b020,
1217         .hwcg_bit = 1,
1218         .clkr = {
1219                 .enable_reg = 0x62008,
1220                 .enable_mask = BIT(0),
1221                 .hw.init = &(const struct clk_init_data) {
1222                         .name = "gcc_pcie_0_slv_axi_clk",
1223                         .ops = &clk_branch2_ops,
1224                 },
1225         },
1226 };
1227
1228 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1229         .halt_reg = 0x7b01c,
1230         .halt_check = BRANCH_HALT_VOTED,
1231         .clkr = {
1232                 .enable_reg = 0x62008,
1233                 .enable_mask = BIT(5),
1234                 .hw.init = &(const struct clk_init_data) {
1235                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1236                         .ops = &clk_branch2_ops,
1237                 },
1238         },
1239 };
1240
1241 static struct clk_branch gcc_pcie_1_aux_clk = {
1242         .halt_reg = 0x9d038,
1243         .halt_check = BRANCH_HALT_VOTED,
1244         .clkr = {
1245                 .enable_reg = 0x62000,
1246                 .enable_mask = BIT(29),
1247                 .hw.init = &(const struct clk_init_data) {
1248                         .name = "gcc_pcie_1_aux_clk",
1249                         .parent_hws = (const struct clk_hw*[]) {
1250                                 &gcc_pcie_1_aux_clk_src.clkr.hw,
1251                         },
1252                         .num_parents = 1,
1253                         .flags = CLK_SET_RATE_PARENT,
1254                         .ops = &clk_branch2_ops,
1255                 },
1256         },
1257 };
1258
1259 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1260         .halt_reg = 0x9d034,
1261         .halt_check = BRANCH_HALT_VOTED,
1262         .hwcg_reg = 0x9d034,
1263         .hwcg_bit = 1,
1264         .clkr = {
1265                 .enable_reg = 0x62000,
1266                 .enable_mask = BIT(28),
1267                 .hw.init = &(const struct clk_init_data) {
1268                         .name = "gcc_pcie_1_cfg_ahb_clk",
1269                         .ops = &clk_branch2_ops,
1270                 },
1271         },
1272 };
1273
1274 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1275         .halt_reg = 0x9d028,
1276         .halt_check = BRANCH_HALT_SKIP,
1277         .hwcg_reg = 0x9d028,
1278         .hwcg_bit = 1,
1279         .clkr = {
1280                 .enable_reg = 0x62000,
1281                 .enable_mask = BIT(27),
1282                 .hw.init = &(const struct clk_init_data) {
1283                         .name = "gcc_pcie_1_mstr_axi_clk",
1284                         .ops = &clk_branch2_ops,
1285                 },
1286         },
1287 };
1288
1289 static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1290         .halt_reg = 0x9d050,
1291         .halt_check = BRANCH_HALT_VOTED,
1292         .clkr = {
1293                 .enable_reg = 0x62000,
1294                 .enable_mask = BIT(23),
1295                 .hw.init = &(const struct clk_init_data) {
1296                         .name = "gcc_pcie_1_phy_rchng_clk",
1297                         .parent_hws = (const struct clk_hw*[]) {
1298                                 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1299                         },
1300                         .num_parents = 1,
1301                         .flags = CLK_SET_RATE_PARENT,
1302                         .ops = &clk_branch2_ops,
1303                 },
1304         },
1305 };
1306
1307 static struct clk_branch gcc_pcie_1_pipe_clk = {
1308         .halt_reg = 0x9d044,
1309         .halt_check = BRANCH_HALT_SKIP,
1310         .clkr = {
1311                 .enable_reg = 0x62000,
1312                 .enable_mask = BIT(30),
1313                 .hw.init = &(const struct clk_init_data) {
1314                         .name = "gcc_pcie_1_pipe_clk",
1315                         .parent_hws = (const struct clk_hw*[]) {
1316                                 &gcc_pcie_1_pipe_clk_src.clkr.hw,
1317                         },
1318                         .num_parents = 1,
1319                         .flags = CLK_SET_RATE_PARENT,
1320                         .ops = &clk_branch2_ops,
1321                 },
1322         },
1323 };
1324
1325 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1326         .halt_reg = 0x9d01c,
1327         .halt_check = BRANCH_HALT_VOTED,
1328         .hwcg_reg = 0x9d01c,
1329         .hwcg_bit = 1,
1330         .clkr = {
1331                 .enable_reg = 0x62000,
1332                 .enable_mask = BIT(26),
1333                 .hw.init = &(const struct clk_init_data) {
1334                         .name = "gcc_pcie_1_slv_axi_clk",
1335                         .ops = &clk_branch2_ops,
1336                 },
1337         },
1338 };
1339
1340 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1341         .halt_reg = 0x9d018,
1342         .halt_check = BRANCH_HALT_VOTED,
1343         .clkr = {
1344                 .enable_reg = 0x62000,
1345                 .enable_mask = BIT(25),
1346                 .hw.init = &(const struct clk_init_data) {
1347                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
1348                         .ops = &clk_branch2_ops,
1349                 },
1350         },
1351 };
1352
1353 static struct clk_branch gcc_pdm2_clk = {
1354         .halt_reg = 0x4300c,
1355         .halt_check = BRANCH_HALT,
1356         .clkr = {
1357                 .enable_reg = 0x4300c,
1358                 .enable_mask = BIT(0),
1359                 .hw.init = &(const struct clk_init_data) {
1360                         .name = "gcc_pdm2_clk",
1361                         .parent_hws = (const struct clk_hw*[]) {
1362                                 &gcc_pdm2_clk_src.clkr.hw,
1363                         },
1364                         .num_parents = 1,
1365                         .flags = CLK_SET_RATE_PARENT,
1366                         .ops = &clk_branch2_ops,
1367                 },
1368         },
1369 };
1370
1371 static struct clk_branch gcc_pdm_ahb_clk = {
1372         .halt_reg = 0x43004,
1373         .halt_check = BRANCH_HALT_VOTED,
1374         .hwcg_reg = 0x43004,
1375         .hwcg_bit = 1,
1376         .clkr = {
1377                 .enable_reg = 0x43004,
1378                 .enable_mask = BIT(0),
1379                 .hw.init = &(const struct clk_init_data) {
1380                         .name = "gcc_pdm_ahb_clk",
1381                         .ops = &clk_branch2_ops,
1382                 },
1383         },
1384 };
1385
1386 static struct clk_branch gcc_pdm_xo4_clk = {
1387         .halt_reg = 0x43008,
1388         .halt_check = BRANCH_HALT,
1389         .clkr = {
1390                 .enable_reg = 0x43008,
1391                 .enable_mask = BIT(0),
1392                 .hw.init = &(const struct clk_init_data) {
1393                         .name = "gcc_pdm_xo4_clk",
1394                         .ops = &clk_branch2_ops,
1395                 },
1396         },
1397 };
1398
1399 static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1400         .halt_reg = 0x9b008,
1401         .halt_check = BRANCH_HALT_VOTED,
1402         .hwcg_reg = 0x9b008,
1403         .hwcg_bit = 1,
1404         .clkr = {
1405                 .enable_reg = 0x9b008,
1406                 .enable_mask = BIT(0),
1407                 .hw.init = &(const struct clk_init_data) {
1408                         .name = "gcc_qmip_gpu_ahb_clk",
1409                         .ops = &clk_branch2_ops,
1410                 },
1411         },
1412 };
1413
1414 static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1415         .halt_reg = 0x7b018,
1416         .halt_check = BRANCH_HALT_VOTED,
1417         .hwcg_reg = 0x7b018,
1418         .hwcg_bit = 1,
1419         .clkr = {
1420                 .enable_reg = 0x62000,
1421                 .enable_mask = BIT(11),
1422                 .hw.init = &(const struct clk_init_data) {
1423                         .name = "gcc_qmip_pcie_ahb_clk",
1424                         .ops = &clk_branch2_ops,
1425                 },
1426         },
1427 };
1428
1429 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
1430         .halt_reg = 0x42014,
1431         .halt_check = BRANCH_HALT_VOTED,
1432         .hwcg_reg = 0x42014,
1433         .hwcg_bit = 1,
1434         .clkr = {
1435                 .enable_reg = 0x42014,
1436                 .enable_mask = BIT(0),
1437                 .hw.init = &(const struct clk_init_data) {
1438                         .name = "gcc_qmip_video_cv_cpu_ahb_clk",
1439                         .ops = &clk_branch2_ops,
1440                 },
1441         },
1442 };
1443
1444 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
1445         .halt_reg = 0x42008,
1446         .halt_check = BRANCH_HALT_VOTED,
1447         .hwcg_reg = 0x42008,
1448         .hwcg_bit = 1,
1449         .clkr = {
1450                 .enable_reg = 0x42008,
1451                 .enable_mask = BIT(0),
1452                 .hw.init = &(const struct clk_init_data) {
1453                         .name = "gcc_qmip_video_cvp_ahb_clk",
1454                         .ops = &clk_branch2_ops,
1455                 },
1456         },
1457 };
1458
1459 static struct clk_branch gcc_qmip_video_lsr_ahb_clk = {
1460         .halt_reg = 0x4204c,
1461         .halt_check = BRANCH_HALT_VOTED,
1462         .hwcg_reg = 0x4204c,
1463         .hwcg_bit = 1,
1464         .clkr = {
1465                 .enable_reg = 0x4204c,
1466                 .enable_mask = BIT(0),
1467                 .hw.init = &(const struct clk_init_data) {
1468                         .name = "gcc_qmip_video_lsr_ahb_clk",
1469                         .ops = &clk_branch2_ops,
1470                 },
1471         },
1472 };
1473
1474 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
1475         .halt_reg = 0x42010,
1476         .halt_check = BRANCH_HALT_VOTED,
1477         .hwcg_reg = 0x42010,
1478         .hwcg_bit = 1,
1479         .clkr = {
1480                 .enable_reg = 0x42010,
1481                 .enable_mask = BIT(0),
1482                 .hw.init = &(const struct clk_init_data) {
1483                         .name = "gcc_qmip_video_v_cpu_ahb_clk",
1484                         .ops = &clk_branch2_ops,
1485                 },
1486         },
1487 };
1488
1489 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1490         .halt_reg = 0x4200c,
1491         .halt_check = BRANCH_HALT_VOTED,
1492         .hwcg_reg = 0x4200c,
1493         .hwcg_bit = 1,
1494         .clkr = {
1495                 .enable_reg = 0x4200c,
1496                 .enable_mask = BIT(0),
1497                 .hw.init = &(const struct clk_init_data) {
1498                         .name = "gcc_qmip_video_vcodec_ahb_clk",
1499                         .ops = &clk_branch2_ops,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1505         .halt_reg = 0x33034,
1506         .halt_check = BRANCH_HALT_VOTED,
1507         .clkr = {
1508                 .enable_reg = 0x62008,
1509                 .enable_mask = BIT(18),
1510                 .hw.init = &(const struct clk_init_data) {
1511                         .name = "gcc_qupv3_wrap0_core_2x_clk",
1512                         .ops = &clk_branch2_ops,
1513                 },
1514         },
1515 };
1516
1517 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1518         .halt_reg = 0x33024,
1519         .halt_check = BRANCH_HALT_VOTED,
1520         .clkr = {
1521                 .enable_reg = 0x62008,
1522                 .enable_mask = BIT(19),
1523                 .hw.init = &(const struct clk_init_data) {
1524                         .name = "gcc_qupv3_wrap0_core_clk",
1525                         .ops = &clk_branch2_ops,
1526                 },
1527         },
1528 };
1529
1530 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1531         .halt_reg = 0x2800c,
1532         .halt_check = BRANCH_HALT_VOTED,
1533         .clkr = {
1534                 .enable_reg = 0x62008,
1535                 .enable_mask = BIT(22),
1536                 .hw.init = &(const struct clk_init_data) {
1537                         .name = "gcc_qupv3_wrap0_s0_clk",
1538                         .parent_hws = (const struct clk_hw*[]) {
1539                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1540                         },
1541                         .num_parents = 1,
1542                         .flags = CLK_SET_RATE_PARENT,
1543                         .ops = &clk_branch2_ops,
1544                 },
1545         },
1546 };
1547
1548 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1549         .halt_reg = 0x28144,
1550         .halt_check = BRANCH_HALT_VOTED,
1551         .clkr = {
1552                 .enable_reg = 0x62008,
1553                 .enable_mask = BIT(23),
1554                 .hw.init = &(const struct clk_init_data) {
1555                         .name = "gcc_qupv3_wrap0_s1_clk",
1556                         .parent_hws = (const struct clk_hw*[]) {
1557                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1558                         },
1559                         .num_parents = 1,
1560                         .flags = CLK_SET_RATE_PARENT,
1561                         .ops = &clk_branch2_ops,
1562                 },
1563         },
1564 };
1565
1566 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1567         .halt_reg = 0x2827c,
1568         .halt_check = BRANCH_HALT_VOTED,
1569         .clkr = {
1570                 .enable_reg = 0x62008,
1571                 .enable_mask = BIT(24),
1572                 .hw.init = &(const struct clk_init_data) {
1573                         .name = "gcc_qupv3_wrap0_s2_clk",
1574                         .parent_hws = (const struct clk_hw*[]) {
1575                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1576                         },
1577                         .num_parents = 1,
1578                         .flags = CLK_SET_RATE_PARENT,
1579                         .ops = &clk_branch2_ops,
1580                 },
1581         },
1582 };
1583
1584 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1585         .halt_reg = 0x283b4,
1586         .halt_check = BRANCH_HALT_VOTED,
1587         .clkr = {
1588                 .enable_reg = 0x62008,
1589                 .enable_mask = BIT(25),
1590                 .hw.init = &(const struct clk_init_data) {
1591                         .name = "gcc_qupv3_wrap0_s3_clk",
1592                         .parent_hws = (const struct clk_hw*[]) {
1593                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1594                         },
1595                         .num_parents = 1,
1596                         .flags = CLK_SET_RATE_PARENT,
1597                         .ops = &clk_branch2_ops,
1598                 },
1599         },
1600 };
1601
1602 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1603         .halt_reg = 0x284ec,
1604         .halt_check = BRANCH_HALT_VOTED,
1605         .clkr = {
1606                 .enable_reg = 0x62008,
1607                 .enable_mask = BIT(26),
1608                 .hw.init = &(const struct clk_init_data) {
1609                         .name = "gcc_qupv3_wrap0_s4_clk",
1610                         .parent_hws = (const struct clk_hw*[]) {
1611                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1612                         },
1613                         .num_parents = 1,
1614                         .flags = CLK_SET_RATE_PARENT,
1615                         .ops = &clk_branch2_ops,
1616                 },
1617         },
1618 };
1619
1620 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1621         .halt_reg = 0x28624,
1622         .halt_check = BRANCH_HALT_VOTED,
1623         .clkr = {
1624                 .enable_reg = 0x62008,
1625                 .enable_mask = BIT(27),
1626                 .hw.init = &(const struct clk_init_data) {
1627                         .name = "gcc_qupv3_wrap0_s5_clk",
1628                         .parent_hws = (const struct clk_hw*[]) {
1629                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1630                         },
1631                         .num_parents = 1,
1632                         .flags = CLK_SET_RATE_PARENT,
1633                         .ops = &clk_branch2_ops,
1634                 },
1635         },
1636 };
1637
1638 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1639         .halt_reg = 0x3317c,
1640         .halt_check = BRANCH_HALT_VOTED,
1641         .clkr = {
1642                 .enable_reg = 0x62010,
1643                 .enable_mask = BIT(3),
1644                 .hw.init = &(const struct clk_init_data) {
1645                         .name = "gcc_qupv3_wrap1_core_2x_clk",
1646                         .ops = &clk_branch2_ops,
1647                 },
1648         },
1649 };
1650
1651 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1652         .halt_reg = 0x3316c,
1653         .halt_check = BRANCH_HALT_VOTED,
1654         .clkr = {
1655                 .enable_reg = 0x62010,
1656                 .enable_mask = BIT(0),
1657                 .hw.init = &(const struct clk_init_data) {
1658                         .name = "gcc_qupv3_wrap1_core_clk",
1659                         .ops = &clk_branch2_ops,
1660                 },
1661         },
1662 };
1663
1664 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1665         .halt_reg = 0x2e00c,
1666         .halt_check = BRANCH_HALT_VOTED,
1667         .clkr = {
1668                 .enable_reg = 0x62010,
1669                 .enable_mask = BIT(4),
1670                 .hw.init = &(const struct clk_init_data) {
1671                         .name = "gcc_qupv3_wrap1_s0_clk",
1672                         .parent_hws = (const struct clk_hw*[]) {
1673                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1674                         },
1675                         .num_parents = 1,
1676                         .flags = CLK_SET_RATE_PARENT,
1677                         .ops = &clk_branch2_ops,
1678                 },
1679         },
1680 };
1681
1682 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1683         .halt_reg = 0x2e144,
1684         .halt_check = BRANCH_HALT_VOTED,
1685         .clkr = {
1686                 .enable_reg = 0x62010,
1687                 .enable_mask = BIT(5),
1688                 .hw.init = &(const struct clk_init_data) {
1689                         .name = "gcc_qupv3_wrap1_s1_clk",
1690                         .parent_hws = (const struct clk_hw*[]) {
1691                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1692                         },
1693                         .num_parents = 1,
1694                         .flags = CLK_SET_RATE_PARENT,
1695                         .ops = &clk_branch2_ops,
1696                 },
1697         },
1698 };
1699
1700 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1701         .halt_reg = 0x2e27c,
1702         .halt_check = BRANCH_HALT_VOTED,
1703         .clkr = {
1704                 .enable_reg = 0x62010,
1705                 .enable_mask = BIT(6),
1706                 .hw.init = &(const struct clk_init_data) {
1707                         .name = "gcc_qupv3_wrap1_s2_clk",
1708                         .parent_hws = (const struct clk_hw*[]) {
1709                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1710                         },
1711                         .num_parents = 1,
1712                         .flags = CLK_SET_RATE_PARENT,
1713                         .ops = &clk_branch2_ops,
1714                 },
1715         },
1716 };
1717
1718 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1719         .halt_reg = 0x2e3b4,
1720         .halt_check = BRANCH_HALT_VOTED,
1721         .clkr = {
1722                 .enable_reg = 0x62010,
1723                 .enable_mask = BIT(7),
1724                 .hw.init = &(const struct clk_init_data) {
1725                         .name = "gcc_qupv3_wrap1_s3_clk",
1726                         .parent_hws = (const struct clk_hw*[]) {
1727                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1728                         },
1729                         .num_parents = 1,
1730                         .flags = CLK_SET_RATE_PARENT,
1731                         .ops = &clk_branch2_ops,
1732                 },
1733         },
1734 };
1735
1736 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1737         .halt_reg = 0x2e4ec,
1738         .halt_check = BRANCH_HALT_VOTED,
1739         .clkr = {
1740                 .enable_reg = 0x62010,
1741                 .enable_mask = BIT(8),
1742                 .hw.init = &(const struct clk_init_data) {
1743                         .name = "gcc_qupv3_wrap1_s4_clk",
1744                         .parent_hws = (const struct clk_hw*[]) {
1745                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1746                         },
1747                         .num_parents = 1,
1748                         .flags = CLK_SET_RATE_PARENT,
1749                         .ops = &clk_branch2_ops,
1750                 },
1751         },
1752 };
1753
1754 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1755         .halt_reg = 0x2e624,
1756         .halt_check = BRANCH_HALT_VOTED,
1757         .clkr = {
1758                 .enable_reg = 0x62010,
1759                 .enable_mask = BIT(9),
1760                 .hw.init = &(const struct clk_init_data) {
1761                         .name = "gcc_qupv3_wrap1_s5_clk",
1762                         .parent_hws = (const struct clk_hw*[]) {
1763                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1764                         },
1765                         .num_parents = 1,
1766                         .flags = CLK_SET_RATE_PARENT,
1767                         .ops = &clk_branch2_ops,
1768                 },
1769         },
1770 };
1771
1772 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1773         .halt_reg = 0x28004,
1774         .halt_check = BRANCH_HALT_VOTED,
1775         .hwcg_reg = 0x28004,
1776         .hwcg_bit = 1,
1777         .clkr = {
1778                 .enable_reg = 0x62008,
1779                 .enable_mask = BIT(20),
1780                 .hw.init = &(const struct clk_init_data) {
1781                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1782                         .ops = &clk_branch2_ops,
1783                 },
1784         },
1785 };
1786
1787 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1788         .halt_reg = 0x28008,
1789         .halt_check = BRANCH_HALT_VOTED,
1790         .hwcg_reg = 0x28008,
1791         .hwcg_bit = 1,
1792         .clkr = {
1793                 .enable_reg = 0x62008,
1794                 .enable_mask = BIT(21),
1795                 .hw.init = &(const struct clk_init_data) {
1796                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1797                         .ops = &clk_branch2_ops,
1798                 },
1799         },
1800 };
1801
1802 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1803         .halt_reg = 0x2e004,
1804         .halt_check = BRANCH_HALT_VOTED,
1805         .hwcg_reg = 0x2e004,
1806         .hwcg_bit = 1,
1807         .clkr = {
1808                 .enable_reg = 0x62010,
1809                 .enable_mask = BIT(2),
1810                 .hw.init = &(const struct clk_init_data) {
1811                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1812                         .ops = &clk_branch2_ops,
1813                 },
1814         },
1815 };
1816
1817 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1818         .halt_reg = 0x2e008,
1819         .halt_check = BRANCH_HALT_VOTED,
1820         .hwcg_reg = 0x2e008,
1821         .hwcg_bit = 1,
1822         .clkr = {
1823                 .enable_reg = 0x62010,
1824                 .enable_mask = BIT(1),
1825                 .hw.init = &(const struct clk_init_data) {
1826                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1827                         .ops = &clk_branch2_ops,
1828                 },
1829         },
1830 };
1831
1832 static struct clk_branch gcc_sdcc1_ahb_clk = {
1833         .halt_reg = 0x26010,
1834         .halt_check = BRANCH_HALT,
1835         .clkr = {
1836                 .enable_reg = 0x26010,
1837                 .enable_mask = BIT(0),
1838                 .hw.init = &(const struct clk_init_data) {
1839                         .name = "gcc_sdcc1_ahb_clk",
1840                         .ops = &clk_branch2_ops,
1841                 },
1842         },
1843 };
1844
1845 static struct clk_branch gcc_sdcc1_apps_clk = {
1846         .halt_reg = 0x26004,
1847         .halt_check = BRANCH_HALT,
1848         .clkr = {
1849                 .enable_reg = 0x26004,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(const struct clk_init_data) {
1852                         .name = "gcc_sdcc1_apps_clk",
1853                         .parent_hws = (const struct clk_hw*[]) {
1854                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
1855                         },
1856                         .num_parents = 1,
1857                         .flags = CLK_SET_RATE_PARENT,
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1864         .halt_reg = 0x26030,
1865         .halt_check = BRANCH_HALT_VOTED,
1866         .hwcg_reg = 0x26030,
1867         .hwcg_bit = 1,
1868         .clkr = {
1869                 .enable_reg = 0x26030,
1870                 .enable_mask = BIT(0),
1871                 .hw.init = &(const struct clk_init_data) {
1872                         .name = "gcc_sdcc1_ice_core_clk",
1873                         .parent_hws = (const struct clk_hw*[]) {
1874                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1875                         },
1876                         .num_parents = 1,
1877                         .flags = CLK_SET_RATE_PARENT,
1878                         .ops = &clk_branch2_ops,
1879                 },
1880         },
1881 };
1882
1883 static struct clk_branch gcc_usb30_prim_master_clk = {
1884         .halt_reg = 0x49018,
1885         .halt_check = BRANCH_HALT,
1886         .clkr = {
1887                 .enable_reg = 0x49018,
1888                 .enable_mask = BIT(0),
1889                 .hw.init = &(const struct clk_init_data) {
1890                         .name = "gcc_usb30_prim_master_clk",
1891                         .parent_hws = (const struct clk_hw*[]) {
1892                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1893                         },
1894                         .num_parents = 1,
1895                         .flags = CLK_SET_RATE_PARENT,
1896                         .ops = &clk_branch2_ops,
1897                 },
1898         },
1899 };
1900
1901 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
1902         .halt_reg = 0x49028,
1903         .halt_check = BRANCH_HALT,
1904         .clkr = {
1905                 .enable_reg = 0x49028,
1906                 .enable_mask = BIT(0),
1907                 .hw.init = &(const struct clk_init_data) {
1908                         .name = "gcc_usb30_prim_mock_utmi_clk",
1909                         .parent_hws = (const struct clk_hw*[]) {
1910                                 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
1911                         },
1912                         .num_parents = 1,
1913                         .flags = CLK_SET_RATE_PARENT,
1914                         .ops = &clk_branch2_ops,
1915                 },
1916         },
1917 };
1918
1919 static struct clk_branch gcc_usb30_prim_sleep_clk = {
1920         .halt_reg = 0x49024,
1921         .halt_check = BRANCH_HALT,
1922         .clkr = {
1923                 .enable_reg = 0x49024,
1924                 .enable_mask = BIT(0),
1925                 .hw.init = &(const struct clk_init_data) {
1926                         .name = "gcc_usb30_prim_sleep_clk",
1927                         .ops = &clk_branch2_ops,
1928                 },
1929         },
1930 };
1931
1932 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
1933         .halt_reg = 0x49060,
1934         .halt_check = BRANCH_HALT,
1935         .clkr = {
1936                 .enable_reg = 0x49060,
1937                 .enable_mask = BIT(0),
1938                 .hw.init = &(const struct clk_init_data) {
1939                         .name = "gcc_usb3_prim_phy_aux_clk",
1940                         .parent_hws = (const struct clk_hw*[]) {
1941                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
1942                         },
1943                         .num_parents = 1,
1944                         .flags = CLK_SET_RATE_PARENT,
1945                         .ops = &clk_branch2_ops,
1946                 },
1947         },
1948 };
1949
1950 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
1951         .halt_reg = 0x49064,
1952         .halt_check = BRANCH_HALT,
1953         .clkr = {
1954                 .enable_reg = 0x49064,
1955                 .enable_mask = BIT(0),
1956                 .hw.init = &(const struct clk_init_data) {
1957                         .name = "gcc_usb3_prim_phy_com_aux_clk",
1958                         .parent_hws = (const struct clk_hw*[]) {
1959                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
1960                         },
1961                         .num_parents = 1,
1962                         .flags = CLK_SET_RATE_PARENT,
1963                         .ops = &clk_branch2_ops,
1964                 },
1965         },
1966 };
1967
1968 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
1969         .halt_reg = 0x49068,
1970         .halt_check = BRANCH_HALT_DELAY,
1971         .hwcg_reg = 0x49068,
1972         .hwcg_bit = 1,
1973         .clkr = {
1974                 .enable_reg = 0x49068,
1975                 .enable_mask = BIT(0),
1976                 .hw.init = &(const struct clk_init_data) {
1977                         .name = "gcc_usb3_prim_phy_pipe_clk",
1978                         .parent_hws = (const struct clk_hw*[]) {
1979                                 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
1980                         },
1981                         .num_parents = 1,
1982                         .flags = CLK_SET_RATE_PARENT,
1983                         .ops = &clk_branch2_ops,
1984                 },
1985         },
1986 };
1987
1988 static struct clk_branch gcc_video_axi0_clk = {
1989         .halt_reg = 0x42018,
1990         .halt_check = BRANCH_HALT_SKIP,
1991         .hwcg_reg = 0x42018,
1992         .hwcg_bit = 1,
1993         .clkr = {
1994                 .enable_reg = 0x42018,
1995                 .enable_mask = BIT(0),
1996                 .hw.init = &(const struct clk_init_data) {
1997                         .name = "gcc_video_axi0_clk",
1998                         .ops = &clk_branch2_ops,
1999                 },
2000         },
2001 };
2002
2003 static struct clk_branch gcc_video_axi1_clk = {
2004         .halt_reg = 0x42024,
2005         .halt_check = BRANCH_HALT_SKIP,
2006         .hwcg_reg = 0x42024,
2007         .hwcg_bit = 1,
2008         .clkr = {
2009                 .enable_reg = 0x42024,
2010                 .enable_mask = BIT(0),
2011                 .hw.init = &(const struct clk_init_data) {
2012                         .name = "gcc_video_axi1_clk",
2013                         .ops = &clk_branch2_ops,
2014                 },
2015         },
2016 };
2017
2018 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_hf0_gdsc = {
2019         .gdscr = 0x8d204,
2020         .pd = {
2021                 .name = "hlos1_vote_mm_snoc_mmu_tbu_hf0_gdsc",
2022         },
2023         .pwrsts = PWRSTS_OFF_ON,
2024         .flags = VOTABLE,
2025 };
2026
2027 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_sf0_gdsc = {
2028         .gdscr = 0x8d054,
2029         .pd = {
2030                 .name = "hlos1_vote_mm_snoc_mmu_tbu_sf0_gdsc",
2031         },
2032         .pwrsts = PWRSTS_OFF_ON,
2033         .flags = VOTABLE,
2034 };
2035
2036 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
2037         .gdscr = 0x8d05c,
2038         .pd = {
2039                 .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
2040         },
2041         .pwrsts = PWRSTS_OFF_ON,
2042         .flags = VOTABLE,
2043 };
2044
2045 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
2046         .gdscr = 0x8d060,
2047         .pd = {
2048                 .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
2049         },
2050         .pwrsts = PWRSTS_OFF_ON,
2051         .flags = VOTABLE,
2052 };
2053
2054 static struct gdsc pcie_0_gdsc = {
2055         .gdscr = 0x7b004,
2056         .collapse_ctrl = 0x62200,
2057         .collapse_mask = BIT(0),
2058         .pd = {
2059                 .name = "pcie_0_gdsc",
2060         },
2061         .pwrsts = PWRSTS_OFF_ON,
2062         .flags = VOTABLE | RETAIN_FF_ENABLE,
2063 };
2064
2065 static struct gdsc pcie_0_phy_gdsc = {
2066         .gdscr = 0x7c000,
2067         .collapse_ctrl = 0x62200,
2068         .collapse_mask = BIT(3),
2069         .pd = {
2070                 .name = "pcie_0_phy_gdsc",
2071         },
2072         .pwrsts = PWRSTS_OFF_ON,
2073         .flags = VOTABLE | RETAIN_FF_ENABLE,
2074 };
2075
2076 static struct gdsc pcie_1_gdsc = {
2077         .gdscr = 0x9d004,
2078         .collapse_ctrl = 0x62200,
2079         .collapse_mask = BIT(1),
2080         .pd = {
2081                 .name = "pcie_1_gdsc",
2082         },
2083         .pwrsts = PWRSTS_OFF_ON,
2084         .flags = VOTABLE | RETAIN_FF_ENABLE,
2085 };
2086
2087 static struct gdsc pcie_1_phy_gdsc = {
2088         .gdscr = 0x9e000,
2089         .collapse_ctrl = 0x62200,
2090         .collapse_mask = BIT(4),
2091         .pd = {
2092                 .name = "pcie_1_phy_gdsc",
2093         },
2094         .pwrsts = PWRSTS_OFF_ON,
2095         .flags = VOTABLE | RETAIN_FF_ENABLE,
2096 };
2097
2098 static struct gdsc usb30_prim_gdsc = {
2099         .gdscr = 0x49004,
2100         .pd = {
2101                 .name = "usb30_prim_gdsc",
2102         },
2103         .pwrsts = PWRSTS_OFF_ON,
2104         .flags = RETAIN_FF_ENABLE,
2105 };
2106
2107 static struct gdsc usb3_phy_gdsc = {
2108         .gdscr = 0x60018,
2109         .pd = {
2110                 .name = "usb3_phy_gdsc",
2111         },
2112         .pwrsts = PWRSTS_OFF_ON,
2113         .flags = RETAIN_FF_ENABLE,
2114 };
2115
2116 static struct clk_regmap *gcc_sar2130p_clocks[] = {
2117         [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
2118         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2119         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2120         [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
2121         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2122         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2123         [GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
2124         [GCC_DDRSS_SPAD_CLK] = &gcc_ddrss_spad_clk.clkr,
2125         [GCC_DDRSS_SPAD_CLK_SRC] = &gcc_ddrss_spad_clk_src.clkr,
2126         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2127         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2128         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2129         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2130         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2131         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2132         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2133         [GCC_GPLL0] = &gcc_gpll0.clkr,
2134         [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
2135         [GCC_GPLL1] = &gcc_gpll1.clkr,
2136         [GCC_GPLL4] = &gcc_gpll4.clkr,
2137         [GCC_GPLL5] = &gcc_gpll5.clkr,
2138         [GCC_GPLL7] = &gcc_gpll7.clkr,
2139         [GCC_GPLL9] = &gcc_gpll9.clkr,
2140         [GCC_GPLL9_OUT_EVEN] = &gcc_gpll9_out_even.clkr,
2141         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2142         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2143         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2144         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2145         [GCC_IRIS_SS_HF_AXI1_CLK] = &gcc_iris_ss_hf_axi1_clk.clkr,
2146         [GCC_IRIS_SS_SPD_AXI1_CLK] = &gcc_iris_ss_spd_axi1_clk.clkr,
2147         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2148         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
2149         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2150         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2151         [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
2152         [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
2153         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2154         [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
2155         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2156         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
2157         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2158         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
2159         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2160         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2161         [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
2162         [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
2163         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2164         [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
2165         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2166         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
2167         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2168         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2169         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2170         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2171         [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
2172         [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
2173         [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
2174         [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
2175         [GCC_QMIP_VIDEO_LSR_AHB_CLK] = &gcc_qmip_video_lsr_ahb_clk.clkr,
2176         [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
2177         [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
2178         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2179         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2180         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2181         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2182         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2183         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2184         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2185         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2186         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2187         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2188         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2189         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2190         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2191         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2192         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2193         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2194         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2195         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2196         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2197         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2198         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2199         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2200         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2201         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2202         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2203         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2204         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2205         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2206         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2207         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2208         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2209         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2210         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2211         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2212         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2213         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2214         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2215         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2216         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2217         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2218         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2219         [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
2220         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2221         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2222         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2223         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2224         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2225         [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
2226         [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
2227         [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
2228 };
2229
2230 static const struct qcom_reset_map gcc_sar2130p_resets[] = {
2231         [GCC_DISPLAY_BCR] = { 0x37000 },
2232         [GCC_GPU_BCR] = { 0x9b000 },
2233         [GCC_PCIE_0_BCR] = { 0x7b000 },
2234         [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
2235         [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
2236         [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
2237         [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
2238         [GCC_PCIE_1_BCR] = { 0x9d000 },
2239         [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
2240         [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
2241         [GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
2242         [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e024 },
2243         [GCC_PCIE_PHY_BCR] = { 0x7f000 },
2244         [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
2245         [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
2246         [GCC_PDM_BCR] = { 0x43000 },
2247         [GCC_QUPV3_WRAPPER_0_BCR] = { 0x28000 },
2248         [GCC_QUPV3_WRAPPER_1_BCR] = { 0x2e000 },
2249         [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
2250         [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
2251         [GCC_SDCC1_BCR] = { 0x26000 },
2252         [GCC_USB30_PRIM_BCR] = { 0x49000 },
2253         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
2254         [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
2255         [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
2256         [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
2257         [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
2258         [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
2259         [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
2260         [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42024, .bit = 2, .udelay = 1000 },
2261         [GCC_VIDEO_BCR] = { 0x42000 },
2262         [GCC_IRIS_SS_HF_AXI_CLK_ARES] = { .reg = 0x42030, .bit = 2 },
2263         [GCC_IRIS_SS_SPD_AXI_CLK_ARES] = { .reg = 0x70020, .bit = 2 },
2264         [GCC_DDRSS_SPAD_CLK_ARES] = { .reg = 0x70000, .bit = 2 },
2265 };
2266
2267 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2268         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2269         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2270         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2271         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2272         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2273         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2274         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2275         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2276         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2277         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2278         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2279         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2280 };
2281
2282 static struct gdsc *gcc_sar2130p_gdscs[] = {
2283         [HLOS1_VOTE_MM_SNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_hf0_gdsc,
2284         [HLOS1_VOTE_MM_SNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_sf0_gdsc,
2285         [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
2286         [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
2287         [PCIE_0_GDSC] = &pcie_0_gdsc,
2288         [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
2289         [PCIE_1_GDSC] = &pcie_1_gdsc,
2290         [PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc,
2291         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2292         [USB3_PHY_GDSC] = &usb3_phy_gdsc,
2293 };
2294
2295 static const struct regmap_config gcc_sar2130p_regmap_config = {
2296         .reg_bits = 32,
2297         .reg_stride = 4,
2298         .val_bits = 32,
2299         .max_register = 0x1f1030,
2300         .fast_io = true,
2301 };
2302
2303 static const struct qcom_cc_desc gcc_sar2130p_desc = {
2304         .config = &gcc_sar2130p_regmap_config,
2305         .clks = gcc_sar2130p_clocks,
2306         .num_clks = ARRAY_SIZE(gcc_sar2130p_clocks),
2307         .resets = gcc_sar2130p_resets,
2308         .num_resets = ARRAY_SIZE(gcc_sar2130p_resets),
2309         .gdscs = gcc_sar2130p_gdscs,
2310         .num_gdscs = ARRAY_SIZE(gcc_sar2130p_gdscs),
2311 };
2312
2313 static const struct of_device_id gcc_sar2130p_match_table[] = {
2314         { .compatible = "qcom,sar2130p-gcc" },
2315         { }
2316 };
2317 MODULE_DEVICE_TABLE(of, gcc_sar2130p_match_table);
2318
2319 static int gcc_sar2130p_probe(struct platform_device *pdev)
2320 {
2321         struct regmap *regmap;
2322         int ret;
2323
2324         regmap = qcom_cc_map(pdev, &gcc_sar2130p_desc);
2325         if (IS_ERR(regmap))
2326                 return PTR_ERR(regmap);
2327
2328         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2329                                        ARRAY_SIZE(gcc_dfs_clocks));
2330         if (ret)
2331                 return ret;
2332
2333         /* Keep some clocks always-on */
2334         qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */
2335         qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */
2336         qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */
2337         qcom_branch_set_clk_en(regmap, 0x9b004); /* GCC_GPU_CFG_AHB_CLK */
2338
2339         /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
2340         regmap_write(regmap, 0x62204, 0x0);
2341
2342         return qcom_cc_really_probe(&pdev->dev, &gcc_sar2130p_desc, regmap);
2343 }
2344
2345 static struct platform_driver gcc_sar2130p_driver = {
2346         .probe = gcc_sar2130p_probe,
2347         .driver = {
2348                 .name = "gcc-sar2130p",
2349                 .of_match_table = gcc_sar2130p_match_table,
2350         },
2351 };
2352
2353 static int __init gcc_sar2130p_init(void)
2354 {
2355         return platform_driver_register(&gcc_sar2130p_driver);
2356 }
2357 subsys_initcall(gcc_sar2130p_init);
2358
2359 static void __exit gcc_sar2130p_exit(void)
2360 {
2361         platform_driver_unregister(&gcc_sar2130p_driver);
2362 }
2363 module_exit(gcc_sar2130p_exit);
2364
2365 MODULE_DESCRIPTION("QTI GCC SAR2130P Driver");
2366 MODULE_LICENSE("GPL");
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