drivers/clk/qcom/gcc-ipq5424.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/regmap.h>
  13
  14 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
  15 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
  16
  17 #include "clk-alpha-pll.h"
  18 #include "clk-branch.h"
  19 #include "clk-rcg.h"
  20 #include "clk-regmap.h"
  21 #include "clk-regmap-divider.h"
  22 #include "clk-regmap-mux.h"
  23 #include "clk-regmap-phy-mux.h"
  24 #include "common.h"
  25 #include "reset.h"
  26
  27 enum {
  28         DT_XO,
  29         DT_SLEEP_CLK,
  30         DT_PCIE30_PHY0_PIPE_CLK,
  31         DT_PCIE30_PHY1_PIPE_CLK,
  32         DT_PCIE30_PHY2_PIPE_CLK,
  33         DT_PCIE30_PHY3_PIPE_CLK,
  34         DT_USB_PCIE_WRAPPER_PIPE_CLK,
  35 };
  36
  37 enum {
  38         P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
  39         P_GPLL0_OUT_AUX,
  40         P_GPLL0_OUT_MAIN,
  41         P_GPLL2_OUT_AUX,
  42         P_GPLL2_OUT_MAIN,
  43         P_GPLL4_OUT_AUX,
  44         P_GPLL4_OUT_MAIN,
  45         P_SLEEP_CLK,
  46         P_XO,
  47         P_USB3PHY_0_PIPE,
  48 };
  49
  50 static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
  51
  52 static struct clk_alpha_pll gpll0 = {
  53         .offset = 0x20000,
  54         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
  55         .clkr = {
  56                 .enable_reg = 0xb000,
  57                 .enable_mask = BIT(0),
  58                 .hw.init = &(const struct clk_init_data) {
  59                         .name = "gpll0",
  60                         .parent_data = &gcc_parent_data_xo,
  61                         .num_parents = 1,
  62                         .ops = &clk_alpha_pll_ops,
  63                 },
  64         },
  65 };
  66
  67 static struct clk_fixed_factor gpll0_div2 = {
  68         .mult = 1,
  69         .div = 2,
  70         .hw.init = &(const struct clk_init_data) {
  71                 .name = "gpll0_div2",
  72                 .parent_hws = (const struct clk_hw *[]) {
  73                         &gpll0.clkr.hw
  74                 },
  75                 .num_parents = 1,
  76                 .ops = &clk_fixed_factor_ops,
  77         },
  78 };
  79
  80 static struct clk_alpha_pll gpll2 = {
  81         .offset = 0x21000,
  82         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
  83         .clkr = {
  84                 .enable_reg = 0xb000,
  85                 .enable_mask = BIT(1),
  86                 .hw.init = &(const struct clk_init_data) {
  87                         .name = "gpll2",
  88                         .parent_data = &gcc_parent_data_xo,
  89                         .num_parents = 1,
  90                         .ops = &clk_alpha_pll_ops,
  91                 },
  92         },
  93 };
  94
  95 static const struct clk_div_table post_div_table_gpll2_out_main[] = {
  96         { 0x1, 2 },
  97         { }
  98 };
  99
 100 static struct clk_alpha_pll_postdiv gpll2_out_main = {
 101         .offset = 0x21000,
 102         .post_div_table = post_div_table_gpll2_out_main,
 103         .num_post_div = ARRAY_SIZE(post_div_table_gpll2_out_main),
 104         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
 105         .clkr.hw.init = &(const struct clk_init_data) {
 106                 .name = "gpll2_out_main",
 107                 .parent_hws = (const struct clk_hw*[]) {
 108                         &gpll2.clkr.hw,
 109                 },
 110                 .num_parents = 1,
 111                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 112         },
 113 };
 114
 115 static struct clk_alpha_pll gpll4 = {
 116         .offset = 0x22000,
 117         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 118         .clkr = {
 119                 .enable_reg = 0xb000,
 120                 .enable_mask = BIT(2),
 121                 .hw.init = &(const struct clk_init_data) {
 122                         .name = "gpll4",
 123                         .parent_data = &gcc_parent_data_xo,
 124                         .num_parents = 1,
 125                         .ops = &clk_alpha_pll_ops,
 126                         /*
 127                          * There are no consumers for this GPLL in kernel yet,
 128                          * (will be added soon), so the clock framework
 129                          * disables this source. But some of the clocks
 130                          * initialized by boot loaders uses this source. So we
 131                          * need to keep this clock ON. Add the
 132                          * CLK_IGNORE_UNUSED flag so the clock will not be
 133                          * disabled. Once the consumer in kernel is added, we
 134                          * can get rid of this flag.
 135                          */
 136                         .flags = CLK_IGNORE_UNUSED,
 137                 },
 138         },
 139 };
 140
 141 static const struct parent_map gcc_parent_map_xo[] = {
 142         { P_XO, 0 },
 143 };
 144
 145 static const struct parent_map gcc_parent_map_0[] = {
 146         { P_XO, 0 },
 147         { P_GPLL0_OUT_MAIN, 1 },
 148         { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 149 };
 150
 151 static const struct clk_parent_data gcc_parent_data_0[] = {
 152         { .index = DT_XO },
 153         { .hw = &gpll0.clkr.hw },
 154         { .hw = &gpll0_div2.hw },
 155 };
 156
 157 static const struct parent_map gcc_parent_map_1[] = {
 158         { P_XO, 0 },
 159         { P_GPLL0_OUT_MAIN, 1 },
 160 };
 161
 162 static const struct clk_parent_data gcc_parent_data_1[] = {
 163         { .index = DT_XO },
 164         { .hw = &gpll0.clkr.hw },
 165 };
 166
 167 static const struct parent_map gcc_parent_map_2[] = {
 168         { P_XO, 0 },
 169         { P_GPLL0_OUT_MAIN, 1 },
 170         { P_GPLL4_OUT_MAIN, 2 },
 171 };
 172
 173 static const struct clk_parent_data gcc_parent_data_2[] = {
 174         { .index = DT_XO },
 175         { .hw = &gpll0.clkr.hw },
 176         { .hw = &gpll4.clkr.hw },
 177 };
 178
 179 static const struct parent_map gcc_parent_map_3[] = {
 180         { P_XO, 0 },
 181         { P_GPLL4_OUT_MAIN, 1 },
 182         { P_GPLL0_OUT_AUX, 2 },
 183         { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 184 };
 185
 186 static const struct clk_parent_data gcc_parent_data_3[] = {
 187         { .index = DT_XO },
 188         { .hw = &gpll4.clkr.hw },
 189         { .hw = &gpll0.clkr.hw },
 190         { .hw = &gpll0_div2.hw },
 191 };
 192
 193 static const struct parent_map gcc_parent_map_4[] = {
 194         { P_XO, 0 },
 195 };
 196
 197 static const struct clk_parent_data gcc_parent_data_4[] = {
 198         { .index = DT_XO },
 199 };
 200
 201 static const struct parent_map gcc_parent_map_5[] = {
 202         { P_XO, 0 },
 203         { P_GPLL4_OUT_AUX, 1 },
 204         { P_GPLL0_OUT_MAIN, 3 },
 205         { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 206 };
 207
 208 static const struct clk_parent_data gcc_parent_data_5[] = {
 209         { .index = DT_XO },
 210         { .hw = &gpll4.clkr.hw },
 211         { .hw = &gpll0.clkr.hw },
 212         { .hw = &gpll0_div2.hw },
 213 };
 214
 215 static const struct parent_map gcc_parent_map_6[] = {
 216         { P_SLEEP_CLK, 6 },
 217 };
 218
 219 static const struct clk_parent_data gcc_parent_data_6[] = {
 220         { .index = DT_SLEEP_CLK },
 221 };
 222
 223 static const struct parent_map gcc_parent_map_7[] = {
 224         { P_XO, 0 },
 225         { P_GPLL0_OUT_MAIN, 1 },
 226         { P_GPLL0_OUT_AUX, 2 },
 227         { P_SLEEP_CLK, 6 },
 228 };
 229
 230 static const struct clk_parent_data gcc_parent_data_7[] = {
 231         { .index = DT_XO },
 232         { .hw = &gpll0.clkr.hw },
 233         { .hw = &gpll0.clkr.hw },
 234         { .index = DT_SLEEP_CLK },
 235 };
 236
 237 static const struct parent_map gcc_parent_map_8[] = {
 238         { P_XO, 0 },
 239         { P_GPLL0_OUT_MAIN, 1 },
 240         { P_GPLL2_OUT_MAIN, 2 },
 241         { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 242 };
 243
 244 static const struct clk_parent_data gcc_parent_data_8[] = {
 245         { .index = DT_XO },
 246         { .hw = &gpll0.clkr.hw },
 247         { .hw = &gpll2_out_main.clkr.hw },
 248         { .hw = &gpll0_div2.hw },
 249 };
 250
 251 static const struct parent_map gcc_parent_map_9[] = {
 252         { P_XO, 0 },
 253         { P_GPLL0_OUT_MAIN, 1 },
 254         { P_GPLL4_OUT_MAIN, 2 },
 255         { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 256 };
 257
 258 static const struct clk_parent_data gcc_parent_data_9[] = {
 259         { .index = DT_XO },
 260         { .hw = &gpll0.clkr.hw },
 261         { .hw = &gpll4.clkr.hw },
 262         { .hw = &gpll0_div2.hw },
 263 };
 264
 265 static const struct parent_map gcc_parent_map_10[] = {
 266         { P_XO, 0 },
 267         { P_GPLL0_OUT_AUX, 2 },
 268         { P_SLEEP_CLK, 6 },
 269 };
 270
 271 static const struct clk_parent_data gcc_parent_data_10[] = {
 272         { .index = DT_XO },
 273         { .hw = &gpll0.clkr.hw },
 274         { .index = DT_SLEEP_CLK },
 275 };
 276
 277 static const struct parent_map gcc_parent_map_11[] = {
 278         { P_XO, 0 },
 279         { P_GPLL0_OUT_MAIN, 1 },
 280         { P_GPLL2_OUT_AUX, 2 },
 281 };
 282
 283 static const struct clk_parent_data gcc_parent_data_11[] = {
 284         { .index = DT_XO },
 285         { .hw = &gpll0.clkr.hw },
 286         { .hw = &gpll2.clkr.hw },
 287 };
 288
 289 static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
 290         F(24000000, P_XO, 1, 0, 0),
 291         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 292         { }
 293 };
 294
 295 static struct clk_rcg2 gcc_adss_pwm_clk_src = {
 296         .cmd_rcgr = 0x1c004,
 297         .mnd_width = 0,
 298         .hid_width = 5,
 299         .parent_map = gcc_parent_map_1,
 300         .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
 301         .clkr.hw.init = &(const struct clk_init_data) {
 302                 .name = "gcc_adss_pwm_clk_src",
 303                 .parent_data = gcc_parent_data_1,
 304                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 305                 .ops = &clk_rcg2_ops,
 306         },
 307 };
 308
 309 static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
 310         F(24000000, P_XO, 1, 0, 0),
 311         { }
 312 };
 313
 314 static struct clk_rcg2 gcc_xo_clk_src = {
 315         .cmd_rcgr = 0x34004,
 316         .mnd_width = 0,
 317         .hid_width = 5,
 318         .parent_map = gcc_parent_map_xo,
 319         .freq_tbl = ftbl_gcc_nss_ts_clk_src,
 320         .clkr.hw.init = &(const struct clk_init_data) {
 321                 .name = "gcc_xo_clk_src",
 322                 .parent_data = &gcc_parent_data_xo,
 323                 .num_parents = 1,
 324                 .ops = &clk_rcg2_ops,
 325         },
 326 };
 327
 328 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
 329         .mult = 1,
 330         .div = 4,
 331         .hw.init = &(const struct clk_init_data) {
 332                 .name = "gcc_xo_div4_clk_src",
 333                 .parent_hws = (const struct clk_hw *[]) {
 334                         &gcc_xo_clk_src.clkr.hw
 335                 },
 336                 .num_parents = 1,
 337                 .flags = CLK_SET_RATE_PARENT,
 338                 .ops = &clk_fixed_factor_ops,
 339         },
 340 };
 341
 342 static struct clk_rcg2 gcc_nss_ts_clk_src = {
 343         .cmd_rcgr = 0x17088,
 344         .mnd_width = 0,
 345         .hid_width = 5,
 346         .parent_map = gcc_parent_map_4,
 347         .freq_tbl = ftbl_gcc_nss_ts_clk_src,
 348         .clkr.hw.init = &(const struct clk_init_data) {
 349                 .name = "gcc_nss_ts_clk_src",
 350                 .parent_data = gcc_parent_data_4,
 351                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 352                 .ops = &clk_rcg2_ops,
 353         },
 354 };
 355
 356 static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] = {
 357         F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
 358         { }
 359 };
 360
 361 static struct clk_rcg2 gcc_pcie0_axi_m_clk_src = {
 362         .cmd_rcgr = 0x28018,
 363         .mnd_width = 0,
 364         .hid_width = 5,
 365         .parent_map = gcc_parent_map_2,
 366         .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 367         .clkr.hw.init = &(const struct clk_init_data) {
 368                 .name = "gcc_pcie0_axi_m_clk_src",
 369                 .parent_data = gcc_parent_data_2,
 370                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 371                 .ops = &clk_rcg2_ops,
 372         },
 373 };
 374
 375 static struct clk_rcg2 gcc_pcie0_axi_s_clk_src = {
 376         .cmd_rcgr = 0x28020,
 377         .mnd_width = 0,
 378         .hid_width = 5,
 379         .parent_map = gcc_parent_map_2,
 380         .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 381         .clkr.hw.init = &(const struct clk_init_data) {
 382                 .name = "gcc_pcie0_axi_s_clk_src",
 383                 .parent_data = gcc_parent_data_2,
 384                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 385                 .ops = &clk_rcg2_ops,
 386         },
 387 };
 388
 389 static struct clk_rcg2 gcc_pcie1_axi_m_clk_src = {
 390         .cmd_rcgr = 0x29018,
 391         .mnd_width = 0,
 392         .hid_width = 5,
 393         .parent_map = gcc_parent_map_2,
 394         .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 395         .clkr.hw.init = &(const struct clk_init_data) {
 396                 .name = "gcc_pcie1_axi_m_clk_src",
 397                 .parent_data = gcc_parent_data_2,
 398                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 399                 .ops = &clk_rcg2_ops,
 400         },
 401 };
 402
 403 static struct clk_rcg2 gcc_pcie1_axi_s_clk_src = {
 404         .cmd_rcgr = 0x29020,
 405         .mnd_width = 0,
 406         .hid_width = 5,
 407         .parent_map = gcc_parent_map_2,
 408         .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 409         .clkr.hw.init = &(const struct clk_init_data) {
 410                 .name = "gcc_pcie1_axi_s_clk_src",
 411                 .parent_data = gcc_parent_data_2,
 412                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 413                 .ops = &clk_rcg2_ops,
 414         },
 415 };
 416
 417 static const struct freq_tbl ftbl_gcc_pcie2_axi_m_clk_src[] = {
 418         F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
 419         { }
 420 };
 421
 422 static struct clk_rcg2 gcc_pcie2_axi_m_clk_src = {
 423         .cmd_rcgr = 0x2a018,
 424         .mnd_width = 0,
 425         .hid_width = 5,
 426         .parent_map = gcc_parent_map_2,
 427         .freq_tbl = ftbl_gcc_pcie2_axi_m_clk_src,
 428         .clkr.hw.init = &(const struct clk_init_data) {
 429                 .name = "gcc_pcie2_axi_m_clk_src",
 430                 .parent_data = gcc_parent_data_2,
 431                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 432                 .ops = &clk_rcg2_ops,
 433         },
 434 };
 435
 436 static struct clk_rcg2 gcc_pcie2_axi_s_clk_src = {
 437         .cmd_rcgr = 0x2a020,
 438         .mnd_width = 0,
 439         .hid_width = 5,
 440         .parent_map = gcc_parent_map_2,
 441         .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 442         .clkr.hw.init = &(const struct clk_init_data) {
 443                 .name = "gcc_pcie2_axi_s_clk_src",
 444                 .parent_data = gcc_parent_data_2,
 445                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 446                 .ops = &clk_rcg2_ops,
 447         },
 448 };
 449
 450 static struct clk_rcg2 gcc_pcie3_axi_m_clk_src = {
 451         .cmd_rcgr = 0x2b018,
 452         .mnd_width = 0,
 453         .hid_width = 5,
 454         .parent_map = gcc_parent_map_2,
 455         .freq_tbl = ftbl_gcc_pcie2_axi_m_clk_src,
 456         .clkr.hw.init = &(const struct clk_init_data) {
 457                 .name = "gcc_pcie3_axi_m_clk_src",
 458                 .parent_data = gcc_parent_data_2,
 459                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 460                 .ops = &clk_rcg2_ops,
 461         },
 462 };
 463
 464 static struct clk_rcg2 gcc_pcie3_axi_s_clk_src = {
 465         .cmd_rcgr = 0x2b020,
 466         .mnd_width = 0,
 467         .hid_width = 5,
 468         .parent_map = gcc_parent_map_2,
 469         .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 470         .clkr.hw.init = &(const struct clk_init_data) {
 471                 .name = "gcc_pcie3_axi_s_clk_src",
 472                 .parent_data = gcc_parent_data_2,
 473                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 474                 .ops = &clk_rcg2_ops,
 475         },
 476 };
 477
 478 static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
 479         F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
 480         { }
 481 };
 482
 483 static struct clk_rcg2 gcc_pcie_aux_clk_src = {
 484         .cmd_rcgr = 0x28004,
 485         .mnd_width = 16,
 486         .hid_width = 5,
 487         .parent_map = gcc_parent_map_7,
 488         .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
 489         .clkr.hw.init = &(const struct clk_init_data) {
 490                 .name = "gcc_pcie_aux_clk_src",
 491                 .parent_data = gcc_parent_data_7,
 492                 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 493                 .ops = &clk_rcg2_ops,
 494         },
 495 };
 496
 497 static const struct freq_tbl ftbl_gcc_qupv3_i2c0_clk_src[] = {
 498         F(4800000, P_XO, 5, 0, 0),
 499         F(9600000, P_XO, 2.5, 0, 0),
 500         F(24000000, P_XO, 1, 0, 0),
 501         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 502         F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 503         { }
 504 };
 505
 506 static struct clk_rcg2 gcc_qupv3_i2c0_clk_src = {
 507         .cmd_rcgr = 0x2018,
 508         .mnd_width = 0,
 509         .hid_width = 5,
 510         .parent_map = gcc_parent_map_0,
 511         .freq_tbl = ftbl_gcc_qupv3_i2c0_clk_src,
 512         .clkr.hw.init = &(const struct clk_init_data) {
 513                 .name = "gcc_qupv3_i2c0_clk_src",
 514                 .parent_data = gcc_parent_data_0,
 515                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 516                 .ops = &clk_rcg2_ops,
 517         },
 518 };
 519
 520 static struct clk_rcg2 gcc_qupv3_i2c1_clk_src = {
 521         .cmd_rcgr = 0x3018,
 522         .mnd_width = 0,
 523         .hid_width = 5,
 524         .parent_map = gcc_parent_map_0,
 525         .freq_tbl = ftbl_gcc_qupv3_i2c0_clk_src,
 526         .clkr.hw.init = &(const struct clk_init_data) {
 527                 .name = "gcc_qupv3_i2c1_clk_src",
 528                 .parent_data = gcc_parent_data_0,
 529                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 530                 .ops = &clk_rcg2_ops,
 531         },
 532 };
 533
 534 static const struct freq_tbl ftbl_gcc_qupv3_spi0_clk_src[] = {
 535         F(960000, P_XO, 10, 2, 5),
 536         F(4800000, P_XO, 5, 0, 0),
 537         F(9600000, P_XO, 2, 4, 5),
 538         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 539         F(24000000, P_XO, 1, 0, 0),
 540         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 541         F(32000000, P_GPLL0_OUT_MAIN, 10, 2, 5),
 542         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 543         { }
 544 };
 545
 546 static struct clk_rcg2 gcc_qupv3_spi0_clk_src = {
 547         .cmd_rcgr = 0x4004,
 548         .mnd_width = 8,
 549         .hid_width = 5,
 550         .parent_map = gcc_parent_map_0,
 551         .freq_tbl = ftbl_gcc_qupv3_spi0_clk_src,
 552         .clkr.hw.init = &(const struct clk_init_data) {
 553                 .name = "gcc_qupv3_spi0_clk_src",
 554                 .parent_data = gcc_parent_data_0,
 555                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 556                 .ops = &clk_rcg2_ops,
 557         },
 558 };
 559
 560 static struct clk_rcg2 gcc_qupv3_spi1_clk_src = {
 561         .cmd_rcgr = 0x5004,
 562         .mnd_width = 8,
 563         .hid_width = 5,
 564         .parent_map = gcc_parent_map_0,
 565         .freq_tbl = ftbl_gcc_qupv3_spi0_clk_src,
 566         .clkr.hw.init = &(const struct clk_init_data) {
 567                 .name = "gcc_qupv3_spi1_clk_src",
 568                 .parent_data = gcc_parent_data_0,
 569                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 570                 .ops = &clk_rcg2_ops,
 571         },
 572 };
 573
 574 static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] = {
 575         F(960000, P_XO, 10, 2, 5),
 576         F(4800000, P_XO, 5, 0, 0),
 577         F(9600000, P_XO, 2, 4, 5),
 578         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 579         F(24000000, P_XO, 1, 0, 0),
 580         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 581         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 582         F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 583         { }
 584 };
 585
 586 static struct clk_rcg2 gcc_qupv3_uart0_clk_src = {
 587         .cmd_rcgr = 0x202c,
 588         .mnd_width = 16,
 589         .hid_width = 5,
 590         .parent_map = gcc_parent_map_0,
 591         .freq_tbl = ftbl_gcc_qupv3_uart0_clk_src,
 592         .clkr.hw.init = &(const struct clk_init_data) {
 593                 .name = "gcc_qupv3_uart0_clk_src",
 594                 .parent_data = gcc_parent_data_0,
 595                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 596                 .ops = &clk_rcg2_ops,
 597         },
 598 };
 599
 600 static struct clk_rcg2 gcc_qupv3_uart1_clk_src = {
 601         .cmd_rcgr = 0x302c,
 602         .mnd_width = 16,
 603         .hid_width = 5,
 604         .parent_map = gcc_parent_map_0,
 605         .freq_tbl = ftbl_gcc_qupv3_uart0_clk_src,
 606         .clkr.hw.init = &(const struct clk_init_data) {
 607                 .name = "gcc_qupv3_uart1_clk_src",
 608                 .parent_data = gcc_parent_data_0,
 609                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 610                 .ops = &clk_rcg2_ops,
 611         },
 612 };
 613
 614 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 615         F(144000, P_XO, 16, 12, 125),
 616         F(400000, P_XO, 12, 1, 5),
 617         F(24000000, P_XO, 1, 0, 0),
 618         F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
 619         F(96000000, P_GPLL2_OUT_MAIN, 6, 1, 2),
 620         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 621         F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
 622         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 623         { }
 624 };
 625
 626 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 627         .cmd_rcgr = 0x33004,
 628         .mnd_width = 8,
 629         .hid_width = 5,
 630         .parent_map = gcc_parent_map_8,
 631         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 632         .clkr.hw.init = &(const struct clk_init_data) {
 633                 .name = "gcc_sdcc1_apps_clk_src",
 634                 .parent_data = gcc_parent_data_8,
 635                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 636                 .ops = &clk_rcg2_floor_ops,
 637         },
 638 };
 639
 640 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 641         F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
 642         { }
 643 };
 644
 645 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 646         .cmd_rcgr = 0x33018,
 647         .mnd_width = 8,
 648         .hid_width = 5,
 649         .parent_map = gcc_parent_map_9,
 650         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 651         .clkr.hw.init = &(const struct clk_init_data) {
 652                 .name = "gcc_sdcc1_ice_core_clk_src",
 653                 .parent_data = gcc_parent_data_9,
 654                 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
 655                 .ops = &clk_rcg2_ops,
 656         },
 657 };
 658
 659 static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
 660         .cmd_rcgr = 0x17090,
 661         .mnd_width = 0,
 662         .hid_width = 5,
 663         .parent_map = gcc_parent_map_4,
 664         .freq_tbl = ftbl_gcc_nss_ts_clk_src,
 665         .clkr.hw.init = &(const struct clk_init_data) {
 666                 .name = "gcc_uniphy_sys_clk_src",
 667                 .parent_data = &gcc_parent_data_xo,
 668                 .num_parents = 1,
 669                 .ops = &clk_rcg2_ops,
 670         },
 671 };
 672
 673 static struct clk_rcg2 gcc_usb0_aux_clk_src = {
 674         .cmd_rcgr = 0x2c018,
 675         .mnd_width = 16,
 676         .hid_width = 5,
 677         .parent_map = gcc_parent_map_10,
 678         .freq_tbl = ftbl_gcc_nss_ts_clk_src,
 679         .clkr.hw.init = &(const struct clk_init_data) {
 680                 .name = "gcc_usb0_aux_clk_src",
 681                 .parent_data = gcc_parent_data_10,
 682                 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
 683                 .ops = &clk_rcg2_ops,
 684         },
 685 };
 686
 687 static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] = {
 688         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 689         { }
 690 };
 691
 692 static struct clk_rcg2 gcc_usb0_master_clk_src = {
 693         .cmd_rcgr = 0x2c004,
 694         .mnd_width = 8,
 695         .hid_width = 5,
 696         .parent_map = gcc_parent_map_0,
 697         .freq_tbl = ftbl_gcc_usb0_master_clk_src,
 698         .clkr.hw.init = &(const struct clk_init_data) {
 699                 .name = "gcc_usb0_master_clk_src",
 700                 .parent_data = gcc_parent_data_0,
 701                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 702                 .ops = &clk_rcg2_ops,
 703         },
 704 };
 705
 706 static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
 707         F(24000000, P_XO, 1, 0, 0),
 708         F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
 709         { }
 710 };
 711
 712 static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
 713         .cmd_rcgr = 0x2c02c,
 714         .mnd_width = 8,
 715         .hid_width = 5,
 716         .parent_map = gcc_parent_map_5,
 717         .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
 718         .clkr.hw.init = &(const struct clk_init_data) {
 719                 .name = "gcc_usb0_mock_utmi_clk_src",
 720                 .parent_data = gcc_parent_data_5,
 721                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 722                 .ops = &clk_rcg2_ops,
 723         },
 724 };
 725
 726 static struct clk_rcg2 gcc_usb1_mock_utmi_clk_src = {
 727         .cmd_rcgr = 0x3c004,
 728         .mnd_width = 8,
 729         .hid_width = 5,
 730         .parent_map = gcc_parent_map_5,
 731         .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
 732         .clkr.hw.init = &(const struct clk_init_data) {
 733                 .name = "gcc_usb1_mock_utmi_clk_src",
 734                 .parent_data = gcc_parent_data_5,
 735                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 736                 .ops = &clk_rcg2_ops,
 737         },
 738 };
 739
 740 static const struct freq_tbl ftbl_gcc_wcss_ahb_clk_src[] = {
 741         F(24000000, P_XO, 1, 0, 0),
 742         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
 743         { }
 744 };
 745
 746 static struct clk_rcg2 gcc_wcss_ahb_clk_src = {
 747         .cmd_rcgr = 0x25030,
 748         .freq_tbl = ftbl_gcc_wcss_ahb_clk_src,
 749         .hid_width = 5,
 750         .parent_map = gcc_parent_map_1,
 751         .clkr.hw.init = &(const struct clk_init_data) {
 752                 .name = "gcc_wcss_ahb_clk_src",
 753                 .parent_data = gcc_parent_data_1,
 754                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 755                 .ops = &clk_rcg2_ops,
 756         },
 757 };
 758
 759 static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
 760         F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
 761         { }
 762 };
 763
 764 static struct clk_rcg2 gcc_qdss_at_clk_src = {
 765         .cmd_rcgr = 0x2d004,
 766         .freq_tbl = ftbl_gcc_qdss_at_clk_src,
 767         .hid_width = 5,
 768         .parent_map = gcc_parent_map_3,
 769         .clkr.hw.init = &(const struct clk_init_data) {
 770                 .name = "gcc_qdss_at_clk_src",
 771                 .parent_data = gcc_parent_data_3,
 772                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 773                 .ops = &clk_rcg2_ops,
 774         },
 775 };
 776
 777 static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
 778         F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
 779         { }
 780 };
 781
 782 static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
 783         .cmd_rcgr = 0x2d01c,
 784         .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
 785         .hid_width = 5,
 786         .parent_map = gcc_parent_map_3,
 787         .clkr.hw.init = &(const struct clk_init_data) {
 788                 .name = "gcc_qdss_tsctr_clk_src",
 789                 .parent_data = gcc_parent_data_3,
 790                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 791                 .ops = &clk_rcg2_ops,
 792         },
 793 };
 794
 795 static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
 796         .mult = 1,
 797         .div = 2,
 798         .hw.init = &(const struct clk_init_data) {
 799                 .name = "gcc_qdss_tsctr_div2_clk_src",
 800                 .parent_hws = (const struct clk_hw *[]) {
 801                         &gcc_qdss_tsctr_clk_src.clkr.hw
 802                 },
 803                 .num_parents = 1,
 804                 .flags = CLK_SET_RATE_PARENT,
 805                 .ops = &clk_fixed_factor_ops,
 806         },
 807 };
 808
 809 static struct clk_fixed_factor gcc_qdss_dap_sync_clk_src = {
 810         .mult = 1,
 811         .div = 4,
 812         .hw.init = &(const struct clk_init_data) {
 813                 .name = "gcc_qdss_dap_sync_clk_src",
 814                 .parent_hws = (const struct clk_hw *[]) {
 815                         &gcc_qdss_tsctr_clk_src.clkr.hw
 816                 },
 817                 .num_parents = 1,
 818                 .ops = &clk_fixed_factor_ops,
 819         },
 820 };
 821
 822 static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
 823         F(24000000, P_XO, 1, 0, 0),
 824         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
 825         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 826         F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
 827         { }
 828 };
 829
 830 static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
 831         .cmd_rcgr = 0x2e004,
 832         .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
 833         .hid_width = 5,
 834         .parent_map = gcc_parent_map_9,
 835         .clkr.hw.init = &(const struct clk_init_data) {
 836                 .name = "gcc_system_noc_bfdcd_clk_src",
 837                 .parent_data = gcc_parent_data_9,
 838                 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
 839                 .ops = &clk_rcg2_ops,
 840         },
 841 };
 842
 843 static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
 844         F(24000000, P_XO, 1, 0, 0),
 845         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 846         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 847         { }
 848 };
 849
 850 static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
 851         .cmd_rcgr = 0x31004,
 852         .mnd_width = 0,
 853         .hid_width = 5,
 854         .parent_map = gcc_parent_map_0,
 855         .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
 856         .clkr.hw.init = &(const struct clk_init_data) {
 857                 .name = "gcc_pcnoc_bfdcd_clk_src",
 858                 .parent_data = gcc_parent_data_0,
 859                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 860                 .ops = &clk_rcg2_ops,
 861         },
 862 };
 863
 864 static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
 865         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
 866         { }
 867 };
 868
 869 static struct clk_rcg2 gcc_lpass_sway_clk_src = {
 870         .cmd_rcgr = 0x27004,
 871         .mnd_width = 0,
 872         .hid_width = 5,
 873         .parent_map = gcc_parent_map_1,
 874         .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
 875         .clkr.hw.init = &(const struct clk_init_data) {
 876                 .name = "gcc_lpass_sway_clk_src",
 877                 .parent_data = gcc_parent_data_1,
 878                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 879                 .ops = &clk_rcg2_ops,
 880         },
 881 };
 882
 883 static struct clk_rcg2 gcc_lpass_axim_clk_src = {
 884         .cmd_rcgr = 0x2700c,
 885         .mnd_width = 0,
 886         .hid_width = 5,
 887         .parent_map = gcc_parent_map_1,
 888         .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
 889         .clkr.hw.init = &(const struct clk_init_data) {
 890                 .name = "gcc_lpass_axim_clk_src",
 891                 .parent_data = gcc_parent_data_1,
 892                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 893                 .ops = &clk_rcg2_ops,
 894         },
 895 };
 896
 897 static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
 898         .mult = 1,
 899         .div = 6,
 900         .hw.init = &(const struct clk_init_data) {
 901                 .name = "gcc_eud_at_div_clk_src",
 902                 .parent_hws = (const struct clk_hw *[]) {
 903                         &gcc_qdss_at_clk_src.clkr.hw },
 904                 .num_parents = 1,
 905                 .flags = CLK_SET_RATE_PARENT,
 906                 .ops = &clk_fixed_factor_ops,
 907         },
 908 };
 909
 910 static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
 911         F(32000, P_SLEEP_CLK, 1, 0, 0),
 912         { }
 913 };
 914
 915 static struct clk_rcg2 gcc_sleep_clk_src = {
 916         .cmd_rcgr = 0x3400c,
 917         .mnd_width = 0,
 918         .hid_width = 5,
 919         .parent_map = gcc_parent_map_6,
 920         .freq_tbl = ftbl_gcc_sleep_clk_src,
 921         .clkr.hw.init = &(const struct clk_init_data) {
 922                 .name = "gcc_sleep_clk_src",
 923                 .parent_data = gcc_parent_data_6,
 924                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 925                 .ops = &clk_rcg2_ops,
 926         },
 927 };
 928
 929 static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
 930         F(24000000, P_XO, 1, 0, 0),
 931         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 932         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 933         F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 934         F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 935         { }
 936 };
 937
 938 static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
 939         .cmd_rcgr = 0x32004,
 940         .mnd_width = 0,
 941         .hid_width = 5,
 942         .parent_map = gcc_parent_map_11,
 943         .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
 944         .clkr.hw.init = &(const struct clk_init_data) {
 945                 .name = "gcc_qpic_io_macro_clk_src",
 946                 .parent_data = gcc_parent_data_11,
 947                 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
 948                 .ops = &clk_rcg2_ops,
 949         },
 950 };
 951
 952 static struct clk_rcg2 gcc_qpic_clk_src = {
 953         .cmd_rcgr = 0x32020,
 954         .mnd_width = 0,
 955         .hid_width = 5,
 956         .parent_map = gcc_parent_map_11,
 957         .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
 958         .clkr.hw.init = &(const struct clk_init_data) {
 959                 .name = "gcc_qpic_clk_src",
 960                 .parent_data = gcc_parent_data_11,
 961                 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
 962                 .ops = &clk_rcg2_ops,
 963         },
 964 };
 965
 966 static struct clk_rcg2 gcc_pcie0_rchng_clk_src = {
 967         .cmd_rcgr = 0x28028,
 968         .mnd_width = 0,
 969         .hid_width = 5,
 970         .parent_map = gcc_parent_map_1,
 971         .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
 972         .clkr.hw.init = &(const struct clk_init_data) {
 973                 .name = "gcc_pcie0_rchng_clk_src",
 974                 .parent_data = gcc_parent_data_1,
 975                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 976                 .ops = &clk_rcg2_ops,
 977         },
 978 };
 979
 980 static struct clk_rcg2 gcc_pcie1_rchng_clk_src = {
 981         .cmd_rcgr = 0x29028,
 982         .mnd_width = 0,
 983         .hid_width = 5,
 984         .parent_map = gcc_parent_map_1,
 985         .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
 986         .clkr.hw.init = &(const struct clk_init_data) {
 987                 .name = "gcc_pcie1_rchng_clk_src",
 988                 .parent_data = gcc_parent_data_1,
 989                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 990                 .ops = &clk_rcg2_ops,
 991         },
 992 };
 993
 994 static struct clk_rcg2 gcc_pcie2_rchng_clk_src = {
 995         .cmd_rcgr = 0x2a028,
 996         .mnd_width = 0,
 997         .hid_width = 5,
 998         .parent_map = gcc_parent_map_1,
 999         .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
1000         .clkr.hw.init = &(const struct clk_init_data) {
1001                 .name = "gcc_pcie2_rchng_clk_src",
1002                 .parent_data = gcc_parent_data_1,
1003                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1004                 .ops = &clk_rcg2_ops,
1005         },
1006 };
1007
1008 static struct clk_rcg2 gcc_pcie3_rchng_clk_src = {
1009         .cmd_rcgr = 0x2b028,
1010         .mnd_width = 0,
1011         .hid_width = 5,
1012         .parent_map = gcc_parent_map_1,
1013         .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
1014         .clkr.hw.init = &(const struct clk_init_data) {
1015                 .name = "gcc_pcie3_rchng_clk_src",
1016                 .parent_data = gcc_parent_data_1,
1017                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1018                 .ops = &clk_rcg2_ops,
1019         },
1020 };
1021
1022 static struct clk_regmap_div gcc_qupv3_i2c0_div_clk_src = {
1023         .reg = 0x2020,
1024         .shift = 0,
1025         .width = 2,
1026         .clkr.hw.init = &(const struct clk_init_data) {
1027                 .name = "gcc_qupv3_i2c0_div_clk_src",
1028                 .parent_hws = (const struct clk_hw*[]) {
1029                         &gcc_qupv3_i2c0_clk_src.clkr.hw,
1030                 },
1031                 .num_parents = 1,
1032                 .flags = CLK_SET_RATE_PARENT,
1033                 .ops = &clk_regmap_div_ro_ops,
1034         },
1035 };
1036
1037 static struct clk_regmap_div gcc_qupv3_i2c1_div_clk_src = {
1038         .reg = 0x3020,
1039         .shift = 0,
1040         .width = 2,
1041         .clkr.hw.init = &(const struct clk_init_data) {
1042                 .name = "gcc_qupv3_i2c1_div_clk_src",
1043                 .parent_hws = (const struct clk_hw*[]) {
1044                         &gcc_qupv3_i2c1_clk_src.clkr.hw,
1045                 },
1046                 .num_parents = 1,
1047                 .flags = CLK_SET_RATE_PARENT,
1048                 .ops = &clk_regmap_div_ro_ops,
1049         },
1050 };
1051
1052 static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
1053         .reg = 0x2c040,
1054         .shift = 0,
1055         .width = 2,
1056         .clkr.hw.init = &(const struct clk_init_data) {
1057                 .name = "gcc_usb0_mock_utmi_div_clk_src",
1058                 .parent_hws = (const struct clk_hw*[]) {
1059                         &gcc_usb0_mock_utmi_clk_src.clkr.hw,
1060                 },
1061                 .num_parents = 1,
1062                 .flags = CLK_SET_RATE_PARENT,
1063                 .ops = &clk_regmap_div_ro_ops,
1064         },
1065 };
1066
1067 static struct clk_regmap_div gcc_usb1_mock_utmi_div_clk_src = {
1068         .reg = 0x3c018,
1069         .shift = 0,
1070         .width = 2,
1071         .clkr.hw.init = &(const struct clk_init_data) {
1072                 .name = "gcc_usb1_mock_utmi_div_clk_src",
1073                 .parent_hws = (const struct clk_hw*[]) {
1074                         &gcc_usb1_mock_utmi_clk_src.clkr.hw,
1075                 },
1076                 .num_parents = 1,
1077                 .flags = CLK_SET_RATE_PARENT,
1078                 .ops = &clk_regmap_div_ro_ops,
1079         },
1080 };
1081
1082 static struct clk_branch gcc_adss_pwm_clk = {
1083         .halt_reg = 0x1c00c,
1084         .halt_check = BRANCH_HALT,
1085         .clkr = {
1086                 .enable_reg = 0x1c00c,
1087                 .enable_mask = BIT(0),
1088                 .hw.init = &(const struct clk_init_data) {
1089                         .name = "gcc_adss_pwm_clk",
1090                         .parent_hws = (const struct clk_hw*[]) {
1091                                 &gcc_adss_pwm_clk_src.clkr.hw,
1092                         },
1093                         .num_parents = 1,
1094                         .flags = CLK_SET_RATE_PARENT,
1095                         .ops = &clk_branch2_ops,
1096                 },
1097         },
1098 };
1099
1100 static struct clk_branch gcc_apss_dbg_clk = {
1101         .halt_reg = 0x2402c,
1102         .halt_check = BRANCH_HALT_VOTED,
1103         .clkr = {
1104                 .enable_reg = 0x2402c,
1105                 .enable_mask = BIT(0),
1106                 .hw.init = &(const struct clk_init_data) {
1107                         .name = "gcc_apss_dbg_clk",
1108                         .parent_hws = (const struct clk_hw*[]) {
1109                                 &gcc_qdss_dap_sync_clk_src.hw
1110                         },
1111                         .num_parents = 1,
1112                         .flags = CLK_SET_RATE_PARENT,
1113                         .ops = &clk_branch2_ops,
1114                 },
1115         },
1116 };
1117
1118 static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk = {
1119         .halt_reg = 0x31088,
1120         .halt_check = BRANCH_HALT,
1121         .clkr = {
1122                 .enable_reg = 0x31088,
1123                 .enable_mask = BIT(0),
1124                 .hw.init = &(const struct clk_init_data) {
1125                         .name = "gcc_cnoc_pcie0_1lane_s_clk",
1126                         .parent_hws = (const struct clk_hw*[]) {
1127                                 &gcc_pcie0_axi_s_clk_src.clkr.hw,
1128                         },
1129                         .num_parents = 1,
1130                         .flags = CLK_SET_RATE_PARENT,
1131                         .ops = &clk_branch2_ops,
1132                 },
1133         },
1134 };
1135
1136 static struct clk_branch gcc_cnoc_pcie1_1lane_s_clk = {
1137         .halt_reg = 0x3108c,
1138         .halt_check = BRANCH_HALT,
1139         .clkr = {
1140                 .enable_reg = 0x3108c,
1141                 .enable_mask = BIT(0),
1142                 .hw.init = &(const struct clk_init_data) {
1143                         .name = "gcc_cnoc_pcie1_1lane_s_clk",
1144                         .parent_hws = (const struct clk_hw*[]) {
1145                                 &gcc_pcie1_axi_s_clk_src.clkr.hw,
1146                         },
1147                         .num_parents = 1,
1148                         .flags = CLK_SET_RATE_PARENT,
1149                         .ops = &clk_branch2_ops,
1150                 },
1151         },
1152 };
1153
1154 static struct clk_branch gcc_cnoc_pcie2_2lane_s_clk = {
1155         .halt_reg = 0x31090,
1156         .halt_check = BRANCH_HALT,
1157         .clkr = {
1158                 .enable_reg = 0x31090,
1159                 .enable_mask = BIT(0),
1160                 .hw.init = &(const struct clk_init_data) {
1161                         .name = "gcc_cnoc_pcie2_2lane_s_clk",
1162                         .parent_hws = (const struct clk_hw*[]) {
1163                                 &gcc_pcie2_axi_s_clk_src.clkr.hw,
1164                         },
1165                         .num_parents = 1,
1166                         .flags = CLK_SET_RATE_PARENT,
1167                         .ops = &clk_branch2_ops,
1168                 },
1169         },
1170 };
1171
1172 static struct clk_branch gcc_cnoc_pcie3_2lane_s_clk = {
1173         .halt_reg = 0x31094,
1174         .halt_check = BRANCH_HALT,
1175         .clkr = {
1176                 .enable_reg = 0x31094,
1177                 .enable_mask = BIT(0),
1178                 .hw.init = &(const struct clk_init_data) {
1179                         .name = "gcc_cnoc_pcie3_2lane_s_clk",
1180                         .parent_hws = (const struct clk_hw*[]) {
1181                                 &gcc_pcie3_axi_s_clk_src.clkr.hw,
1182                         },
1183                         .num_parents = 1,
1184                         .flags = CLK_SET_RATE_PARENT,
1185                         .ops = &clk_branch2_ops,
1186                 },
1187         },
1188 };
1189
1190 static struct clk_branch gcc_cnoc_usb_clk = {
1191         .halt_reg = 0x310a8,
1192         .halt_check = BRANCH_HALT_VOTED,
1193         .clkr = {
1194                 .enable_reg = 0x310a8,
1195                 .enable_mask = BIT(0),
1196                 .hw.init = &(const struct clk_init_data) {
1197                         .name = "gcc_cnoc_usb_clk",
1198                         .parent_hws = (const struct clk_hw*[]) {
1199                                 &gcc_usb0_master_clk_src.clkr.hw,
1200                         },
1201                         .num_parents = 1,
1202                         .flags = CLK_SET_RATE_PARENT,
1203                         .ops = &clk_branch2_ops,
1204                 },
1205         },
1206 };
1207
1208 static struct clk_branch gcc_mdio_ahb_clk = {
1209         .halt_reg = 0x17040,
1210         .halt_check = BRANCH_HALT,
1211         .clkr = {
1212                 .enable_reg = 0x17040,
1213                 .enable_mask = BIT(0),
1214                 .hw.init = &(const struct clk_init_data) {
1215                         .name = "gcc_mdio_ahb_clk",
1216                         .parent_hws = (const struct clk_hw*[]) {
1217                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1218                         },
1219                         .num_parents = 1,
1220                         .flags = CLK_SET_RATE_PARENT,
1221                         .ops = &clk_branch2_ops,
1222                 },
1223         },
1224 };
1225
1226 static struct clk_branch gcc_nss_ts_clk = {
1227         .halt_reg = 0x17018,
1228         .halt_check = BRANCH_HALT_VOTED,
1229         .clkr = {
1230                 .enable_reg = 0x17018,
1231                 .enable_mask = BIT(0),
1232                 .hw.init = &(const struct clk_init_data) {
1233                         .name = "gcc_nss_ts_clk",
1234                         .parent_hws = (const struct clk_hw*[]) {
1235                                 &gcc_nss_ts_clk_src.clkr.hw,
1236                         },
1237                         .num_parents = 1,
1238                         .flags = CLK_SET_RATE_PARENT,
1239                         .ops = &clk_branch2_ops,
1240                 },
1241         },
1242 };
1243
1244 static struct clk_branch gcc_nsscc_clk = {
1245         .halt_reg = 0x17034,
1246         .halt_check = BRANCH_HALT,
1247         .clkr = {
1248                 .enable_reg = 0x17034,
1249                 .enable_mask = BIT(0),
1250                 .hw.init = &(const struct clk_init_data) {
1251                         .name = "gcc_nsscc_clk",
1252                         .parent_hws = (const struct clk_hw*[]) {
1253                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1254                         },
1255                         .num_parents = 1,
1256                         .flags = CLK_SET_RATE_PARENT,
1257                         .ops = &clk_branch2_ops,
1258                 },
1259         },
1260 };
1261
1262 static struct clk_branch gcc_nsscfg_clk = {
1263         .halt_reg = 0x1702c,
1264         .halt_check = BRANCH_HALT,
1265         .clkr = {
1266                 .enable_reg = 0x1702c,
1267                 .enable_mask = BIT(0),
1268                 .hw.init = &(const struct clk_init_data) {
1269                         .name = "gcc_nsscfg_clk",
1270                         .parent_hws = (const struct clk_hw*[]) {
1271                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1272                         },
1273                         .num_parents = 1,
1274                         .flags = CLK_SET_RATE_PARENT,
1275                         .ops = &clk_branch2_ops,
1276                 },
1277         },
1278 };
1279
1280 static struct clk_branch gcc_nssnoc_atb_clk = {
1281         .halt_reg = 0x17014,
1282         .halt_check = BRANCH_HALT,
1283         .clkr = {
1284                 .enable_reg = 0x17014,
1285                 .enable_mask = BIT(0),
1286                 .hw.init = &(const struct clk_init_data) {
1287                         .name = "gcc_nssnoc_atb_clk",
1288                         .parent_hws = (const struct clk_hw*[]) {
1289                                 &gcc_qdss_at_clk_src.clkr.hw,
1290                         },
1291                         .num_parents = 1,
1292                         .flags = CLK_SET_RATE_PARENT,
1293                         .ops = &clk_branch2_ops,
1294                 },
1295         },
1296 };
1297
1298 static struct clk_branch gcc_nssnoc_nsscc_clk = {
1299         .halt_reg = 0x17030,
1300         .halt_check = BRANCH_HALT,
1301         .clkr = {
1302                 .enable_reg = 0x17030,
1303                 .enable_mask = BIT(0),
1304                 .hw.init = &(const struct clk_init_data) {
1305                         .name = "gcc_nssnoc_nsscc_clk",
1306                         .parent_hws = (const struct clk_hw*[]) {
1307                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1308                         },
1309                         .num_parents = 1,
1310                         .flags = CLK_SET_RATE_PARENT,
1311                         .ops = &clk_branch2_ops,
1312                 },
1313         },
1314 };
1315
1316 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
1317         .halt_reg = 0x17080,
1318         .halt_check = BRANCH_HALT,
1319         .clkr = {
1320                 .enable_reg = 0x17080,
1321                 .enable_mask = BIT(0),
1322                 .hw.init = &(const struct clk_init_data) {
1323                         .name = "gcc_nssnoc_pcnoc_1_clk",
1324                         .parent_hws = (const struct clk_hw*[]) {
1325                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1326                         },
1327                         .num_parents = 1,
1328                         .flags = CLK_SET_RATE_PARENT,
1329                         .ops = &clk_branch2_ops,
1330                 },
1331         },
1332 };
1333
1334 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
1335         .halt_reg = 0x1701c,
1336         .halt_check = BRANCH_HALT,
1337         .clkr = {
1338                 .enable_reg = 0x1701c,
1339                 .enable_mask = BIT(0),
1340                 .hw.init = &(const struct clk_init_data) {
1341                         .name = "gcc_nssnoc_qosgen_ref_clk",
1342                         .parent_hws = (const struct clk_hw *[]) {
1343                                 &gcc_xo_div4_clk_src.hw
1344                         },
1345                         .num_parents = 1,
1346                         .flags = CLK_SET_RATE_PARENT,
1347                         .ops = &clk_branch2_ops,
1348                 },
1349         },
1350 };
1351
1352 static struct clk_branch gcc_nssnoc_snoc_1_clk = {
1353         .halt_reg = 0x1707c,
1354         .halt_check = BRANCH_HALT,
1355         .clkr = {
1356                 .enable_reg = 0x1707c,
1357                 .enable_mask = BIT(0),
1358                 .hw.init = &(const struct clk_init_data) {
1359                         .name = "gcc_nssnoc_snoc_1_clk",
1360                         .parent_hws = (const struct clk_hw*[]) {
1361                                 &gcc_system_noc_bfdcd_clk_src.clkr.hw
1362                         },
1363                         .num_parents = 1,
1364                         .flags = CLK_SET_RATE_PARENT,
1365                         .ops = &clk_branch2_ops,
1366                 },
1367         },
1368 };
1369
1370 static struct clk_branch gcc_nssnoc_snoc_clk = {
1371         .halt_reg = 0x17028,
1372         .halt_check = BRANCH_HALT,
1373         .clkr = {
1374                 .enable_reg = 0x17028,
1375                 .enable_mask = BIT(0),
1376                 .hw.init = &(const struct clk_init_data) {
1377                         .name = "gcc_nssnoc_snoc_clk",
1378                         .parent_hws = (const struct clk_hw*[]) {
1379                                 &gcc_system_noc_bfdcd_clk_src.clkr.hw
1380                         },
1381                         .num_parents = 1,
1382                         .flags = CLK_SET_RATE_PARENT,
1383                         .ops = &clk_branch2_ops,
1384                 },
1385         },
1386 };
1387
1388 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
1389         .halt_reg = 0x17020,
1390         .halt_check = BRANCH_HALT,
1391         .clkr = {
1392                 .enable_reg = 0x17020,
1393                 .enable_mask = BIT(0),
1394                 .hw.init = &(const struct clk_init_data) {
1395                         .name = "gcc_nssnoc_timeout_ref_clk",
1396                         .parent_hws = (const struct clk_hw*[]) {
1397                                 &gcc_xo_div4_clk_src.hw,
1398                         },
1399                         .num_parents = 1,
1400                         .flags = CLK_SET_RATE_PARENT,
1401                         .ops = &clk_branch2_ops,
1402                 },
1403         },
1404 };
1405
1406 static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
1407         .halt_reg = 0x17074,
1408         .halt_check = BRANCH_HALT,
1409         .clkr = {
1410                 .enable_reg = 0x17074,
1411                 .enable_mask = BIT(0),
1412                 .hw.init = &(const struct clk_init_data) {
1413                         .name = "gcc_nssnoc_xo_dcd_clk",
1414                         .parent_hws = (const struct clk_hw*[]) {
1415                                 &gcc_xo_clk_src.clkr.hw,
1416                         },
1417                         .num_parents = 1,
1418                         .flags = CLK_SET_RATE_PARENT,
1419                         .ops = &clk_branch2_ops,
1420                 },
1421         },
1422 };
1423
1424 static struct clk_branch gcc_pcie0_ahb_clk = {
1425         .halt_reg = 0x28030,
1426         .halt_check = BRANCH_HALT,
1427         .clkr = {
1428                 .enable_reg = 0x28030,
1429                 .enable_mask = BIT(0),
1430                 .hw.init = &(const struct clk_init_data) {
1431                         .name = "gcc_pcie0_ahb_clk",
1432                         .parent_hws = (const struct clk_hw*[]) {
1433                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1434                         },
1435                         .num_parents = 1,
1436                         .flags = CLK_SET_RATE_PARENT,
1437                         .ops = &clk_branch2_ops,
1438                 },
1439         },
1440 };
1441
1442 static struct clk_branch gcc_pcie0_aux_clk = {
1443         .halt_reg = 0x28070,
1444         .halt_check = BRANCH_HALT,
1445         .clkr = {
1446                 .enable_reg = 0x28070,
1447                 .enable_mask = BIT(0),
1448                 .hw.init = &(const struct clk_init_data) {
1449                         .name = "gcc_pcie0_aux_clk",
1450                         .parent_hws = (const struct clk_hw*[]) {
1451                                 &gcc_pcie_aux_clk_src.clkr.hw,
1452                         },
1453                         .num_parents = 1,
1454                         .flags = CLK_SET_RATE_PARENT,
1455                         .ops = &clk_branch2_ops,
1456                 },
1457         },
1458 };
1459
1460 static struct clk_branch gcc_pcie0_axi_m_clk = {
1461         .halt_reg = 0x28038,
1462         .halt_check = BRANCH_HALT,
1463         .clkr = {
1464                 .enable_reg = 0x28038,
1465                 .enable_mask = BIT(0),
1466                 .hw.init = &(const struct clk_init_data) {
1467                         .name = "gcc_pcie0_axi_m_clk",
1468                         .parent_hws = (const struct clk_hw*[]) {
1469                                 &gcc_pcie0_axi_m_clk_src.clkr.hw,
1470                         },
1471                         .num_parents = 1,
1472                         .flags = CLK_SET_RATE_PARENT,
1473                         .ops = &clk_branch2_ops,
1474                 },
1475         },
1476 };
1477
1478 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
1479         .halt_reg = 0x2e07c,
1480         .halt_check = BRANCH_HALT,
1481         .clkr = {
1482                 .enable_reg = 0x2e07c,
1483                 .enable_mask = BIT(0),
1484                 .hw.init = &(const struct clk_init_data) {
1485                         .name = "gcc_anoc_pcie0_1lane_m_clk",
1486                         .parent_hws = (const struct clk_hw*[]) {
1487                                 &gcc_pcie0_axi_m_clk_src.clkr.hw,
1488                         },
1489                         .num_parents = 1,
1490                         .flags = CLK_SET_RATE_PARENT,
1491                         .ops = &clk_branch2_ops,
1492                 },
1493         },
1494 };
1495
1496 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
1497         .halt_reg = 0x28048,
1498         .halt_check = BRANCH_HALT,
1499         .clkr = {
1500                 .enable_reg = 0x28048,
1501                 .enable_mask = BIT(0),
1502                 .hw.init = &(const struct clk_init_data) {
1503                         .name = "gcc_pcie0_axi_s_bridge_clk",
1504                         .parent_hws = (const struct clk_hw*[]) {
1505                                 &gcc_pcie0_axi_s_clk_src.clkr.hw,
1506                         },
1507                         .num_parents = 1,
1508                         .flags = CLK_SET_RATE_PARENT,
1509                         .ops = &clk_branch2_ops,
1510                 },
1511         },
1512 };
1513
1514 static struct clk_branch gcc_pcie0_axi_s_clk = {
1515         .halt_reg = 0x28040,
1516         .halt_check = BRANCH_HALT,
1517         .clkr = {
1518                 .enable_reg = 0x28040,
1519                 .enable_mask = BIT(0),
1520                 .hw.init = &(const struct clk_init_data) {
1521                         .name = "gcc_pcie0_axi_s_clk",
1522                         .parent_hws = (const struct clk_hw*[]) {
1523                                 &gcc_pcie0_axi_s_clk_src.clkr.hw,
1524                         },
1525                         .num_parents = 1,
1526                         .flags = CLK_SET_RATE_PARENT,
1527                         .ops = &clk_branch2_ops,
1528                 },
1529         },
1530 };
1531
1532 static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src = {
1533         .reg = 0x28064,
1534         .clkr = {
1535                 .hw.init = &(const struct clk_init_data) {
1536                         .name = "pcie0_pipe_clk_src",
1537                         .parent_data = &(const struct clk_parent_data) {
1538                                 .index = DT_PCIE30_PHY0_PIPE_CLK,
1539                         },
1540                         .num_parents = 1,
1541                         .ops = &clk_regmap_phy_mux_ops,
1542                 },
1543         },
1544 };
1545
1546 static struct clk_branch gcc_pcie0_pipe_clk = {
1547         .halt_reg = 0x28068,
1548         .halt_check = BRANCH_HALT_DELAY,
1549         .clkr = {
1550                 .enable_reg = 0x28068,
1551                 .enable_mask = BIT(0),
1552                 .hw.init = &(const struct clk_init_data) {
1553                         .name = "gcc_pcie0_pipe_clk",
1554                         .parent_hws = (const struct clk_hw *[]) {
1555                                 &gcc_pcie0_pipe_clk_src.clkr.hw
1556                         },
1557                         .num_parents = 1,
1558                         .flags = CLK_SET_RATE_PARENT,
1559                         .ops = &clk_branch2_ops,
1560                 },
1561         },
1562 };
1563
1564 static struct clk_branch gcc_pcie1_ahb_clk = {
1565         .halt_reg = 0x29030,
1566         .halt_check = BRANCH_HALT,
1567         .clkr = {
1568                 .enable_reg = 0x29030,
1569                 .enable_mask = BIT(0),
1570                 .hw.init = &(const struct clk_init_data) {
1571                         .name = "gcc_pcie1_ahb_clk",
1572                         .parent_hws = (const struct clk_hw*[]) {
1573                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1574                         },
1575                         .num_parents = 1,
1576                         .flags = CLK_SET_RATE_PARENT,
1577                         .ops = &clk_branch2_ops,
1578                 },
1579         },
1580 };
1581
1582 static struct clk_branch gcc_pcie1_aux_clk = {
1583         .halt_reg = 0x29074,
1584         .halt_check = BRANCH_HALT,
1585         .clkr = {
1586                 .enable_reg = 0x29074,
1587                 .enable_mask = BIT(0),
1588                 .hw.init = &(const struct clk_init_data) {
1589                         .name = "gcc_pcie1_aux_clk",
1590                         .parent_hws = (const struct clk_hw*[]) {
1591                                 &gcc_pcie_aux_clk_src.clkr.hw,
1592                         },
1593                         .num_parents = 1,
1594                         .flags = CLK_SET_RATE_PARENT,
1595                         .ops = &clk_branch2_ops,
1596                 },
1597         },
1598 };
1599
1600 static struct clk_branch gcc_pcie1_axi_m_clk = {
1601         .halt_reg = 0x29038,
1602         .halt_check = BRANCH_HALT,
1603         .clkr = {
1604                 .enable_reg = 0x29038,
1605                 .enable_mask = BIT(0),
1606                 .hw.init = &(const struct clk_init_data) {
1607                         .name = "gcc_pcie1_axi_m_clk",
1608                         .parent_hws = (const struct clk_hw*[]) {
1609                                 &gcc_pcie1_axi_m_clk_src.clkr.hw,
1610                         },
1611                         .num_parents = 1,
1612                         .flags = CLK_SET_RATE_PARENT,
1613                         .ops = &clk_branch2_ops,
1614                 },
1615         },
1616 };
1617
1618 static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
1619         .halt_reg = 0x2e084,
1620         .halt_check = BRANCH_HALT,
1621         .clkr = {
1622                 .enable_reg = 0x2e084,
1623                 .enable_mask = BIT(0),
1624                 .hw.init = &(const struct clk_init_data) {
1625                         .name = "gcc_anoc_pcie1_1lane_m_clk",
1626                         .parent_hws = (const struct clk_hw*[]) {
1627                                 &gcc_pcie1_axi_m_clk_src.clkr.hw,
1628                         },
1629                         .num_parents = 1,
1630                         .flags = CLK_SET_RATE_PARENT,
1631                         .ops = &clk_branch2_ops,
1632                 },
1633         },
1634 };
1635
1636 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
1637         .halt_reg = 0x29048,
1638         .halt_check = BRANCH_HALT,
1639         .clkr = {
1640                 .enable_reg = 0x29048,
1641                 .enable_mask = BIT(0),
1642                 .hw.init = &(const struct clk_init_data) {
1643                         .name = "gcc_pcie1_axi_s_bridge_clk",
1644                         .parent_hws = (const struct clk_hw*[]) {
1645                                 &gcc_pcie1_axi_s_clk_src.clkr.hw,
1646                         },
1647                         .num_parents = 1,
1648                         .flags = CLK_SET_RATE_PARENT,
1649                         .ops = &clk_branch2_ops,
1650                 },
1651         },
1652 };
1653
1654 static struct clk_branch gcc_pcie1_axi_s_clk = {
1655         .halt_reg = 0x29040,
1656         .halt_check = BRANCH_HALT,
1657         .clkr = {
1658                 .enable_reg = 0x29040,
1659                 .enable_mask = BIT(0),
1660                 .hw.init = &(const struct clk_init_data) {
1661                         .name = "gcc_pcie1_axi_s_clk",
1662                         .parent_hws = (const struct clk_hw*[]) {
1663                                 &gcc_pcie1_axi_s_clk_src.clkr.hw,
1664                         },
1665                         .num_parents = 1,
1666                         .flags = CLK_SET_RATE_PARENT,
1667                         .ops = &clk_branch2_ops,
1668                 },
1669         },
1670 };
1671
1672 static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src = {
1673         .reg = 0x29064,
1674         .clkr = {
1675                 .hw.init = &(const struct clk_init_data) {
1676                         .name = "pcie1_pipe_clk_src",
1677                         .parent_data = &(const struct clk_parent_data) {
1678                                 .index = DT_PCIE30_PHY1_PIPE_CLK,
1679                         },
1680                         .num_parents = 1,
1681                         .ops = &clk_regmap_phy_mux_ops,
1682                 },
1683         },
1684 };
1685
1686 static struct clk_branch gcc_pcie1_pipe_clk = {
1687         .halt_reg = 0x29068,
1688         .halt_check = BRANCH_HALT_DELAY,
1689         .clkr = {
1690                 .enable_reg = 0x29068,
1691                 .enable_mask = BIT(0),
1692                 .hw.init = &(const struct clk_init_data) {
1693                         .name = "gcc_pcie1_pipe_clk",
1694                         .parent_hws = (const struct clk_hw *[]) {
1695                                 &gcc_pcie1_pipe_clk_src.clkr.hw
1696                         },
1697                         .num_parents = 1,
1698                         .flags = CLK_SET_RATE_PARENT,
1699
1700                         .ops = &clk_branch2_ops,
1701                 },
1702         },
1703 };
1704
1705 static struct clk_branch gcc_pcie2_ahb_clk = {
1706         .halt_reg = 0x2a030,
1707         .halt_check = BRANCH_HALT,
1708         .clkr = {
1709                 .enable_reg = 0x2a030,
1710                 .enable_mask = BIT(0),
1711                 .hw.init = &(const struct clk_init_data) {
1712                         .name = "gcc_pcie2_ahb_clk",
1713                         .parent_hws = (const struct clk_hw*[]) {
1714                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1715                         },
1716                         .num_parents = 1,
1717                         .flags = CLK_SET_RATE_PARENT,
1718                         .ops = &clk_branch2_ops,
1719                 },
1720         },
1721 };
1722
1723 static struct clk_branch gcc_pcie2_aux_clk = {
1724         .halt_reg = 0x2a078,
1725         .halt_check = BRANCH_HALT,
1726         .clkr = {
1727                 .enable_reg = 0x2a078,
1728                 .enable_mask = BIT(0),
1729                 .hw.init = &(const struct clk_init_data) {
1730                         .name = "gcc_pcie2_aux_clk",
1731                         .parent_hws = (const struct clk_hw*[]) {
1732                                 &gcc_pcie_aux_clk_src.clkr.hw,
1733                         },
1734                         .num_parents = 1,
1735                         .flags = CLK_SET_RATE_PARENT,
1736                         .ops = &clk_branch2_ops,
1737                 },
1738         },
1739 };
1740
1741 static struct clk_branch gcc_pcie2_axi_m_clk = {
1742         .halt_reg = 0x2a038,
1743         .halt_check = BRANCH_HALT,
1744         .clkr = {
1745                 .enable_reg = 0x2a038,
1746                 .enable_mask = BIT(0),
1747                 .hw.init = &(const struct clk_init_data) {
1748                         .name = "gcc_pcie2_axi_m_clk",
1749                         .parent_hws = (const struct clk_hw*[]) {
1750                                 &gcc_pcie2_axi_m_clk_src.clkr.hw,
1751                         },
1752                         .num_parents = 1,
1753                         .flags = CLK_SET_RATE_PARENT,
1754                         .ops = &clk_branch2_ops,
1755                 },
1756         },
1757 };
1758
1759 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
1760         .halt_reg = 0x2e080,
1761         .halt_check = BRANCH_HALT,
1762         .clkr = {
1763                 .enable_reg = 0x2e080,
1764                 .enable_mask = BIT(0),
1765                 .hw.init = &(const struct clk_init_data) {
1766                         .name = "gcc_anoc_pcie2_2lane_m_clk",
1767                         .parent_hws = (const struct clk_hw*[]) {
1768                                 &gcc_pcie2_axi_m_clk_src.clkr.hw,
1769                         },
1770                         .num_parents = 1,
1771                         .flags = CLK_SET_RATE_PARENT,
1772                         .ops = &clk_branch2_ops,
1773                 },
1774         },
1775 };
1776
1777 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
1778         .halt_reg = 0x2a048,
1779         .halt_check = BRANCH_HALT,
1780         .clkr = {
1781                 .enable_reg = 0x2a048,
1782                 .enable_mask = BIT(0),
1783                 .hw.init = &(const struct clk_init_data) {
1784                         .name = "gcc_pcie2_axi_s_bridge_clk",
1785                         .parent_hws = (const struct clk_hw*[]) {
1786                                 &gcc_pcie2_axi_s_clk_src.clkr.hw,
1787                         },
1788                         .num_parents = 1,
1789                         .flags = CLK_SET_RATE_PARENT,
1790                         .ops = &clk_branch2_ops,
1791                 },
1792         },
1793 };
1794
1795 static struct clk_branch gcc_pcie2_axi_s_clk = {
1796         .halt_reg = 0x2a040,
1797         .halt_check = BRANCH_HALT,
1798         .clkr = {
1799                 .enable_reg = 0x2a040,
1800                 .enable_mask = BIT(0),
1801                 .hw.init = &(const struct clk_init_data) {
1802                         .name = "gcc_pcie2_axi_s_clk",
1803                         .parent_hws = (const struct clk_hw*[]) {
1804                                 &gcc_pcie2_axi_s_clk_src.clkr.hw,
1805                         },
1806                         .num_parents = 1,
1807                         .flags = CLK_SET_RATE_PARENT,
1808                         .ops = &clk_branch2_ops,
1809                 },
1810         },
1811 };
1812
1813 static struct clk_regmap_phy_mux gcc_pcie2_pipe_clk_src = {
1814         .reg = 0x2a064,
1815         .clkr = {
1816                 .hw.init = &(const struct clk_init_data) {
1817                         .name = "pcie2_pipe_clk_src",
1818                         .parent_data = &(const struct clk_parent_data) {
1819                                 .index = DT_PCIE30_PHY2_PIPE_CLK,
1820                         },
1821                         .num_parents = 1,
1822                         .ops = &clk_regmap_phy_mux_ops,
1823                 },
1824         },
1825 };
1826
1827 static struct clk_branch gcc_pcie2_pipe_clk = {
1828         .halt_reg = 0x2a068,
1829         .halt_check = BRANCH_HALT_DELAY,
1830         .clkr = {
1831                 .enable_reg = 0x2a068,
1832                 .enable_mask = BIT(0),
1833                 .hw.init = &(const struct clk_init_data) {
1834                         .name = "gcc_pcie2_pipe_clk",
1835                         .parent_hws = (const struct clk_hw *[]) {
1836                                 &gcc_pcie2_pipe_clk_src.clkr.hw
1837                         },
1838                         .num_parents = 1,
1839                         .flags = CLK_SET_RATE_PARENT,
1840                         .ops = &clk_branch2_ops,
1841                 },
1842         },
1843 };
1844
1845 static struct clk_branch gcc_pcie3_ahb_clk = {
1846         .halt_reg = 0x2b030,
1847         .halt_check = BRANCH_HALT,
1848         .clkr = {
1849                 .enable_reg = 0x2b030,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(const struct clk_init_data) {
1852                         .name = "gcc_pcie3_ahb_clk",
1853                         .parent_hws = (const struct clk_hw*[]) {
1854                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1855                         },
1856                         .num_parents = 1,
1857                         .flags = CLK_SET_RATE_PARENT,
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_pcie3_aux_clk = {
1864         .halt_reg = 0x2b07c,
1865         .halt_check = BRANCH_HALT,
1866         .clkr = {
1867                 .enable_reg = 0x2b07c,
1868                 .enable_mask = BIT(0),
1869                 .hw.init = &(const struct clk_init_data) {
1870                         .name = "gcc_pcie3_aux_clk",
1871                         .parent_hws = (const struct clk_hw*[]) {
1872                                 &gcc_pcie_aux_clk_src.clkr.hw,
1873                         },
1874                         .num_parents = 1,
1875                         .flags = CLK_SET_RATE_PARENT,
1876                         .ops = &clk_branch2_ops,
1877                 },
1878         },
1879 };
1880
1881 static struct clk_branch gcc_pcie3_axi_m_clk = {
1882         .halt_reg = 0x2b038,
1883         .halt_check = BRANCH_HALT,
1884         .clkr = {
1885                 .enable_reg = 0x2b038,
1886                 .enable_mask = BIT(0),
1887                 .hw.init = &(const struct clk_init_data) {
1888                         .name = "gcc_pcie3_axi_m_clk",
1889                         .parent_hws = (const struct clk_hw*[]) {
1890                                 &gcc_pcie3_axi_m_clk_src.clkr.hw,
1891                         },
1892                         .num_parents = 1,
1893                         .flags = CLK_SET_RATE_PARENT,
1894                         .ops = &clk_branch2_ops,
1895                 },
1896         },
1897 };
1898
1899 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
1900         .halt_reg = 0x2e090,
1901         .halt_check = BRANCH_HALT,
1902         .clkr = {
1903                 .enable_reg = 0x2e090,
1904                 .enable_mask = BIT(0),
1905                 .hw.init = &(const struct clk_init_data) {
1906                         .name = "gcc_anoc_pcie3_2lane_m_clk",
1907                         .parent_hws = (const struct clk_hw*[]) {
1908                                 &gcc_pcie3_axi_m_clk_src.clkr.hw,
1909                         },
1910                         .num_parents = 1,
1911                         .flags = CLK_SET_RATE_PARENT,
1912                         .ops = &clk_branch2_ops,
1913                 },
1914         },
1915 };
1916
1917 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
1918         .halt_reg = 0x2b048,
1919         .halt_check = BRANCH_HALT,
1920         .clkr = {
1921                 .enable_reg = 0x2b048,
1922                 .enable_mask = BIT(0),
1923                 .hw.init = &(const struct clk_init_data) {
1924                         .name = "gcc_pcie3_axi_s_bridge_clk",
1925                         .parent_hws = (const struct clk_hw*[]) {
1926                                 &gcc_pcie3_axi_s_clk_src.clkr.hw,
1927                         },
1928                         .num_parents = 1,
1929                         .flags = CLK_SET_RATE_PARENT,
1930                         .ops = &clk_branch2_ops,
1931                 },
1932         },
1933 };
1934
1935 static struct clk_branch gcc_pcie3_axi_s_clk = {
1936         .halt_reg = 0x2b040,
1937         .halt_check = BRANCH_HALT,
1938         .clkr = {
1939                 .enable_reg = 0x2b040,
1940                 .enable_mask = BIT(0),
1941                 .hw.init = &(const struct clk_init_data) {
1942                         .name = "gcc_pcie3_axi_s_clk",
1943                         .parent_hws = (const struct clk_hw*[]) {
1944                                 &gcc_pcie3_axi_s_clk_src.clkr.hw,
1945                         },
1946                         .num_parents = 1,
1947                         .flags = CLK_SET_RATE_PARENT,
1948                         .ops = &clk_branch2_ops,
1949                 },
1950         },
1951 };
1952
1953 static struct clk_regmap_phy_mux gcc_pcie3_pipe_clk_src = {
1954         .reg = 0x2b064,
1955         .clkr = {
1956                 .hw.init = &(const struct clk_init_data) {
1957                         .name = "pcie3_pipe_clk_src",
1958                         .parent_data = &(const struct clk_parent_data) {
1959                                 .index = DT_PCIE30_PHY3_PIPE_CLK,
1960                         },
1961                         .num_parents = 1,
1962                         .ops = &clk_regmap_phy_mux_ops,
1963                 },
1964         },
1965 };
1966
1967 static struct clk_branch gcc_pcie3_pipe_clk = {
1968         .halt_reg = 0x2b068,
1969         .halt_check = BRANCH_HALT_DELAY,
1970         .clkr = {
1971                 .enable_reg = 0x2b068,
1972                 .enable_mask = BIT(0),
1973                 .hw.init = &(const struct clk_init_data) {
1974                         .name = "gcc_pcie3_pipe_clk",
1975                         .parent_hws = (const struct clk_hw *[]) {
1976                                 &gcc_pcie3_pipe_clk_src.clkr.hw
1977                         },
1978                         .num_parents = 1,
1979                         .flags = CLK_SET_RATE_PARENT,
1980                         .ops = &clk_branch2_ops,
1981                 },
1982         },
1983 };
1984
1985 static struct clk_branch gcc_prng_ahb_clk = {
1986         .halt_reg = 0x13024,
1987         .halt_check = BRANCH_HALT_VOTED,
1988         .clkr = {
1989                 .enable_reg = 0xb004,
1990                 .enable_mask = BIT(10),
1991                 .hw.init = &(const struct clk_init_data) {
1992                         .name = "gcc_prng_ahb_clk",
1993                         .parent_hws = (const struct clk_hw*[]) {
1994                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1995                         },
1996                         .num_parents = 1,
1997                         .flags = CLK_SET_RATE_PARENT,
1998                         .ops = &clk_branch2_ops,
1999                 },
2000         },
2001 };
2002
2003 static struct clk_branch gcc_qupv3_ahb_mst_clk = {
2004         .halt_reg = 0x1014,
2005         .halt_check = BRANCH_HALT_VOTED,
2006         .clkr = {
2007                 .enable_reg = 0xb004,
2008                 .enable_mask = BIT(14),
2009                 .hw.init = &(const struct clk_init_data) {
2010                         .name = "gcc_qupv3_ahb_mst_clk",
2011                         .parent_hws = (const struct clk_hw*[]) {
2012                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2013                         },
2014                         .num_parents = 1,
2015                         .flags = CLK_SET_RATE_PARENT,
2016                         .ops = &clk_branch2_ops,
2017                 },
2018         },
2019 };
2020
2021 static struct clk_branch gcc_qupv3_ahb_slv_clk = {
2022         .halt_reg = 0x102c,
2023         .halt_check = BRANCH_HALT_VOTED,
2024         .clkr = {
2025                 .enable_reg = 0xb004,
2026                 .enable_mask = BIT(4),
2027                 .hw.init = &(const struct clk_init_data) {
2028                         .name = "gcc_qupv3_ahb_slv_clk",
2029                         .parent_hws = (const struct clk_hw*[]) {
2030                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2031                         },
2032                         .num_parents = 1,
2033                         .flags = CLK_SET_RATE_PARENT,
2034                         .ops = &clk_branch2_ops,
2035                 },
2036         },
2037 };
2038
2039 static struct clk_branch gcc_qupv3_i2c0_clk = {
2040         .halt_reg = 0x2024,
2041         .halt_check = BRANCH_HALT,
2042         .clkr = {
2043                 .enable_reg = 0x2024,
2044                 .enable_mask = BIT(0),
2045                 .hw.init = &(const struct clk_init_data) {
2046                         .name = "gcc_qupv3_i2c0_clk",
2047                         .parent_hws = (const struct clk_hw*[]) {
2048                                 &gcc_qupv3_i2c0_div_clk_src.clkr.hw,
2049                         },
2050                         .num_parents = 1,
2051                         .flags = CLK_SET_RATE_PARENT,
2052                         .ops = &clk_branch2_ops,
2053                 },
2054         },
2055 };
2056
2057 static struct clk_branch gcc_qupv3_i2c1_clk = {
2058         .halt_reg = 0x3024,
2059         .halt_check = BRANCH_HALT,
2060         .clkr = {
2061                 .enable_reg = 0x3024,
2062                 .enable_mask = BIT(0),
2063                 .hw.init = &(const struct clk_init_data) {
2064                         .name = "gcc_qupv3_i2c1_clk",
2065                         .parent_hws = (const struct clk_hw*[]) {
2066                                 &gcc_qupv3_i2c1_div_clk_src.clkr.hw,
2067                         },
2068                         .num_parents = 1,
2069                         .flags = CLK_SET_RATE_PARENT,
2070                         .ops = &clk_branch2_ops,
2071                 },
2072         },
2073 };
2074
2075 static struct clk_branch gcc_qupv3_spi0_clk = {
2076         .halt_reg = 0x4020,
2077         .halt_check = BRANCH_HALT,
2078         .clkr = {
2079                 .enable_reg = 0x4020,
2080                 .enable_mask = BIT(0),
2081                 .hw.init = &(const struct clk_init_data) {
2082                         .name = "gcc_qupv3_spi0_clk",
2083                         .parent_hws = (const struct clk_hw*[]) {
2084                                 &gcc_qupv3_spi0_clk_src.clkr.hw,
2085                         },
2086                         .num_parents = 1,
2087                         .flags = CLK_SET_RATE_PARENT,
2088                         .ops = &clk_branch2_ops,
2089                 },
2090         },
2091 };
2092
2093 static struct clk_branch gcc_qupv3_spi1_clk = {
2094         .halt_reg = 0x5020,
2095         .halt_check = BRANCH_HALT,
2096         .clkr = {
2097                 .enable_reg = 0x5020,
2098                 .enable_mask = BIT(0),
2099                 .hw.init = &(const struct clk_init_data) {
2100                         .name = "gcc_qupv3_spi1_clk",
2101                         .parent_hws = (const struct clk_hw*[]) {
2102                                 &gcc_qupv3_spi1_clk_src.clkr.hw,
2103                         },
2104                         .num_parents = 1,
2105                         .flags = CLK_SET_RATE_PARENT,
2106                         .ops = &clk_branch2_ops,
2107                 },
2108         },
2109 };
2110
2111 static struct clk_branch gcc_qupv3_uart0_clk = {
2112         .halt_reg = 0x2040,
2113         .halt_check = BRANCH_HALT,
2114         .clkr = {
2115                 .enable_reg = 0x2040,
2116                 .enable_mask = BIT(0),
2117                 .hw.init = &(const struct clk_init_data) {
2118                         .name = "gcc_qupv3_uart0_clk",
2119                         .parent_hws = (const struct clk_hw*[]) {
2120                                 &gcc_qupv3_uart0_clk_src.clkr.hw,
2121                         },
2122                         .num_parents = 1,
2123                         .flags = CLK_SET_RATE_PARENT,
2124                         .ops = &clk_branch2_ops,
2125                 },
2126         },
2127 };
2128
2129 static struct clk_branch gcc_qupv3_uart1_clk = {
2130         .halt_reg = 0x3040,
2131         .halt_check = BRANCH_HALT,
2132         .clkr = {
2133                 .enable_reg = 0x3040,
2134                 .enable_mask = BIT(0),
2135                 .hw.init = &(const struct clk_init_data) {
2136                         .name = "gcc_qupv3_uart1_clk",
2137                         .parent_hws = (const struct clk_hw*[]) {
2138                                 &gcc_qupv3_uart1_clk_src.clkr.hw,
2139                         },
2140                         .num_parents = 1,
2141                         .flags = CLK_SET_RATE_PARENT,
2142                         .ops = &clk_branch2_ops,
2143                 },
2144         },
2145 };
2146
2147 static struct clk_branch gcc_sdcc1_ahb_clk = {
2148         .halt_reg = 0x3303c,
2149         .halt_check = BRANCH_HALT,
2150         .clkr = {
2151                 .enable_reg = 0x3303c,
2152                 .enable_mask = BIT(0),
2153                 .hw.init = &(const struct clk_init_data) {
2154                         .name = "gcc_sdcc1_ahb_clk",
2155                         .parent_hws = (const struct clk_hw*[]) {
2156                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2157                         },
2158                         .num_parents = 1,
2159                         .flags = CLK_SET_RATE_PARENT,
2160                         .ops = &clk_branch2_ops,
2161                 },
2162         },
2163 };
2164
2165 static struct clk_branch gcc_sdcc1_apps_clk = {
2166         .halt_reg = 0x3302c,
2167         .halt_check = BRANCH_HALT,
2168         .clkr = {
2169                 .enable_reg = 0x3302c,
2170                 .enable_mask = BIT(0),
2171                 .hw.init = &(const struct clk_init_data) {
2172                         .name = "gcc_sdcc1_apps_clk",
2173                         .parent_hws = (const struct clk_hw*[]) {
2174                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
2175                         },
2176                         .num_parents = 1,
2177                         .flags = CLK_SET_RATE_PARENT,
2178                         .ops = &clk_branch2_ops,
2179                 },
2180         },
2181 };
2182
2183 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2184         .halt_reg = 0x33034,
2185         .halt_check = BRANCH_HALT,
2186         .clkr = {
2187                 .enable_reg = 0x33034,
2188                 .enable_mask = BIT(0),
2189                 .hw.init = &(const struct clk_init_data) {
2190                         .name = "gcc_sdcc1_ice_core_clk",
2191                         .parent_hws = (const struct clk_hw*[]) {
2192                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2193                         },
2194                         .num_parents = 1,
2195                         .flags = CLK_SET_RATE_PARENT,
2196                         .ops = &clk_branch2_ops,
2197                 },
2198         },
2199 };
2200
2201 static struct clk_branch gcc_uniphy0_ahb_clk = {
2202         .halt_reg = 0x1704c,
2203         .halt_check = BRANCH_HALT,
2204         .clkr = {
2205                 .enable_reg = 0x1704c,
2206                 .enable_mask = BIT(0),
2207                 .hw.init = &(const struct clk_init_data) {
2208                         .name = "gcc_uniphy0_ahb_clk",
2209                         .parent_hws = (const struct clk_hw*[]) {
2210                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2211                         },
2212                         .num_parents = 1,
2213                         .flags = CLK_SET_RATE_PARENT,
2214                         .ops = &clk_branch2_ops,
2215                 },
2216         },
2217 };
2218
2219 static struct clk_branch gcc_uniphy0_sys_clk = {
2220         .halt_reg = 0x17048,
2221         .halt_check = BRANCH_HALT_VOTED,
2222         .clkr = {
2223                 .enable_reg = 0x17048,
2224                 .enable_mask = BIT(0),
2225                 .hw.init = &(const struct clk_init_data) {
2226                         .name = "gcc_uniphy0_sys_clk",
2227                         .parent_hws = (const struct clk_hw*[]) {
2228                                 &gcc_uniphy_sys_clk_src.clkr.hw,
2229                         },
2230                         .num_parents = 1,
2231                         .flags = CLK_SET_RATE_PARENT,
2232                         .ops = &clk_branch2_ops,
2233                 },
2234         },
2235 };
2236
2237 static struct clk_branch gcc_uniphy1_ahb_clk = {
2238         .halt_reg = 0x1705c,
2239         .halt_check = BRANCH_HALT,
2240         .clkr = {
2241                 .enable_reg = 0x1705c,
2242                 .enable_mask = BIT(0),
2243                 .hw.init = &(const struct clk_init_data) {
2244                         .name = "gcc_uniphy1_ahb_clk",
2245                         .parent_hws = (const struct clk_hw*[]) {
2246                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2247                         },
2248                         .num_parents = 1,
2249                         .flags = CLK_SET_RATE_PARENT,
2250                         .ops = &clk_branch2_ops,
2251                 },
2252         },
2253 };
2254
2255 static struct clk_branch gcc_uniphy1_sys_clk = {
2256         .halt_reg = 0x17058,
2257         .halt_check = BRANCH_HALT_VOTED,
2258         .clkr = {
2259                 .enable_reg = 0x17058,
2260                 .enable_mask = BIT(0),
2261                 .hw.init = &(const struct clk_init_data) {
2262                         .name = "gcc_uniphy1_sys_clk",
2263                         .parent_hws = (const struct clk_hw*[]) {
2264                                 &gcc_uniphy_sys_clk_src.clkr.hw,
2265                         },
2266                         .num_parents = 1,
2267                         .flags = CLK_SET_RATE_PARENT,
2268                         .ops = &clk_branch2_ops,
2269                 },
2270         },
2271 };
2272
2273 static struct clk_branch gcc_uniphy2_ahb_clk = {
2274         .halt_reg = 0x1706c,
2275         .halt_check = BRANCH_HALT,
2276         .clkr = {
2277                 .enable_reg = 0x1706c,
2278                 .enable_mask = BIT(0),
2279                 .hw.init = &(const struct clk_init_data) {
2280                         .name = "gcc_uniphy2_ahb_clk",
2281                         .parent_hws = (const struct clk_hw*[]) {
2282                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2283                         },
2284                         .num_parents = 1,
2285                         .flags = CLK_SET_RATE_PARENT,
2286                         .ops = &clk_branch2_ops,
2287                 },
2288         },
2289 };
2290
2291 static struct clk_branch gcc_uniphy2_sys_clk = {
2292         .halt_reg = 0x17068,
2293         .halt_check = BRANCH_HALT_VOTED,
2294         .clkr = {
2295                 .enable_reg = 0x17068,
2296                 .enable_mask = BIT(0),
2297                 .hw.init = &(const struct clk_init_data) {
2298                         .name = "gcc_uniphy2_sys_clk",
2299                         .parent_hws = (const struct clk_hw*[]) {
2300                                 &gcc_uniphy_sys_clk_src.clkr.hw,
2301                         },
2302                         .num_parents = 1,
2303                         .flags = CLK_SET_RATE_PARENT,
2304                         .ops = &clk_branch2_ops,
2305                 },
2306         },
2307 };
2308
2309 static struct clk_branch gcc_usb0_aux_clk = {
2310         .halt_reg = 0x2c04c,
2311         .halt_check = BRANCH_HALT_VOTED,
2312         .clkr = {
2313                 .enable_reg = 0x2c04c,
2314                 .enable_mask = BIT(0),
2315                 .hw.init = &(const struct clk_init_data) {
2316                         .name = "gcc_usb0_aux_clk",
2317                         .parent_hws = (const struct clk_hw*[]) {
2318                                 &gcc_usb0_aux_clk_src.clkr.hw,
2319                         },
2320                         .num_parents = 1,
2321                         .flags = CLK_SET_RATE_PARENT,
2322                         .ops = &clk_branch2_ops,
2323                 },
2324         },
2325 };
2326
2327 static struct clk_branch gcc_usb0_master_clk = {
2328         .halt_reg = 0x2c044,
2329         .halt_check = BRANCH_HALT_VOTED,
2330         .clkr = {
2331                 .enable_reg = 0x2c044,
2332                 .enable_mask = BIT(0),
2333                 .hw.init = &(const struct clk_init_data) {
2334                         .name = "gcc_usb0_master_clk",
2335                         .parent_hws = (const struct clk_hw*[]) {
2336                                 &gcc_usb0_master_clk_src.clkr.hw,
2337                         },
2338                         .num_parents = 1,
2339                         .flags = CLK_SET_RATE_PARENT,
2340                         .ops = &clk_branch2_ops,
2341                 },
2342         },
2343 };
2344
2345 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2346         .halt_reg = 0x2c050,
2347         .halt_check = BRANCH_HALT_VOTED,
2348         .clkr = {
2349                 .enable_reg = 0x2c050,
2350                 .enable_mask = BIT(0),
2351                 .hw.init = &(const struct clk_init_data) {
2352                         .name = "gcc_usb0_mock_utmi_clk",
2353                         .parent_hws = (const struct clk_hw*[]) {
2354                                 &gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
2355                         },
2356                         .num_parents = 1,
2357                         .flags = CLK_SET_RATE_PARENT,
2358                         .ops = &clk_branch2_ops,
2359                 },
2360         },
2361 };
2362
2363 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2364         .halt_reg = 0x3c024,
2365         .halt_check = BRANCH_HALT_VOTED,
2366         .clkr = {
2367                 .enable_reg = 0x3c024,
2368                 .enable_mask = BIT(0),
2369                 .hw.init = &(const struct clk_init_data) {
2370                         .name = "gcc_usb1_mock_utmi_clk",
2371                         .parent_hws = (const struct clk_hw*[]) {
2372                                 &gcc_usb1_mock_utmi_div_clk_src.clkr.hw,
2373                         },
2374                         .num_parents = 1,
2375                         .flags = CLK_SET_RATE_PARENT,
2376                         .ops = &clk_branch2_ops,
2377                 },
2378         },
2379 };
2380
2381 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2382         .halt_reg = 0x2c05c,
2383         .halt_check = BRANCH_HALT_VOTED,
2384         .clkr = {
2385                 .enable_reg = 0x2c05c,
2386                 .enable_mask = BIT(0),
2387                 .hw.init = &(const struct clk_init_data) {
2388                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2389                         .parent_hws = (const struct clk_hw*[]) {
2390                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2391                         },
2392                         .num_parents = 1,
2393                         .flags = CLK_SET_RATE_PARENT,
2394                         .ops = &clk_branch2_ops,
2395                 },
2396         },
2397 };
2398
2399 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2400         .halt_reg = 0x3c01c,
2401         .halt_check = BRANCH_HALT_VOTED,
2402         .clkr = {
2403                 .enable_reg = 0x3c01c,
2404                 .enable_mask = BIT(0),
2405                 .hw.init = &(const struct clk_init_data) {
2406                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2407                         .parent_hws = (const struct clk_hw*[]) {
2408                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2409                         },
2410                         .num_parents = 1,
2411                         .flags = CLK_SET_RATE_PARENT,
2412                         .ops = &clk_branch2_ops,
2413                 },
2414         },
2415 };
2416
2417 static struct clk_branch gcc_usb1_master_clk = {
2418         .halt_reg = 0x3c028,
2419         .halt_check = BRANCH_HALT_VOTED,
2420         .clkr = {
2421                 .enable_reg = 0x3c028,
2422                 .enable_mask = BIT(0),
2423                 .hw.init = &(const struct clk_init_data) {
2424                         .name = "gcc_usb1_master_clk",
2425                         .parent_hws = (const struct clk_hw*[]) {
2426                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2427                         },
2428                         .num_parents = 1,
2429                         .flags = CLK_SET_RATE_PARENT,
2430                         .ops = &clk_branch2_ops,
2431                 },
2432         },
2433 };
2434
2435 static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
2436         .reg = 0x2c074,
2437         .clkr = {
2438                 .hw.init = &(const struct clk_init_data) {
2439                         .name = "gcc_usb0_pipe_clk_src",
2440                         .parent_data = &(const struct clk_parent_data) {
2441                                 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
2442                         },
2443                         .num_parents = 1,
2444                         .ops = &clk_regmap_phy_mux_ops,
2445                 },
2446         },
2447 };
2448
2449 static struct clk_branch gcc_usb0_pipe_clk = {
2450         .halt_reg = 0x2c054,
2451         .halt_check = BRANCH_HALT_DELAY,
2452         .clkr = {
2453                 .enable_reg = 0x2c054,
2454                 .enable_mask = BIT(0),
2455                 .hw.init = &(const struct clk_init_data) {
2456                         .name = "gcc_usb0_pipe_clk",
2457                         .parent_hws = (const struct clk_hw *[]) {
2458                                 &gcc_usb0_pipe_clk_src.clkr.hw
2459                         },
2460                         .num_parents = 1,
2461                         .flags = CLK_SET_RATE_PARENT,
2462                         .ops = &clk_branch2_ops,
2463                 },
2464         },
2465 };
2466
2467 static struct clk_branch gcc_usb0_sleep_clk = {
2468         .halt_reg = 0x2c058,
2469         .halt_check = BRANCH_HALT_VOTED,
2470         .clkr = {
2471                 .enable_reg = 0x2c058,
2472                 .enable_mask = BIT(0),
2473                 .hw.init = &(const struct clk_init_data) {
2474                         .name = "gcc_usb0_sleep_clk",
2475                         .parent_hws = (const struct clk_hw*[]) {
2476                                 &gcc_sleep_clk_src.clkr.hw,
2477                         },
2478                         .num_parents = 1,
2479                         .flags = CLK_SET_RATE_PARENT,
2480                         .ops = &clk_branch2_ops,
2481                 },
2482         },
2483 };
2484
2485 static struct clk_branch gcc_usb1_sleep_clk = {
2486         .halt_reg = 0x3c020,
2487         .halt_check = BRANCH_HALT_VOTED,
2488         .clkr = {
2489                 .enable_reg = 0x3c020,
2490                 .enable_mask = BIT(0),
2491                 .hw.init = &(const struct clk_init_data) {
2492                         .name = "gcc_usb1_sleep_clk",
2493                         .parent_hws = (const struct clk_hw*[]) {
2494                                 &gcc_sleep_clk_src.clkr.hw,
2495                         },
2496                         .num_parents = 1,
2497                         .flags = CLK_SET_RATE_PARENT,
2498                         .ops = &clk_branch2_ops,
2499                 },
2500         },
2501 };
2502
2503 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
2504         .halt_reg = 0x3a004,
2505         .halt_check = BRANCH_HALT,
2506         .clkr = {
2507                 .enable_reg = 0x3a004,
2508                 .enable_mask = BIT(0),
2509                 .hw.init = &(const struct clk_init_data) {
2510                         .name = "gcc_cmn_12gpll_ahb_clk",
2511                         .parent_hws = (const struct clk_hw*[]) {
2512                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2513                         },
2514                         .num_parents = 1,
2515                         .flags = CLK_SET_RATE_PARENT,
2516                         .ops = &clk_branch2_ops,
2517                 },
2518         },
2519 };
2520
2521 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
2522         .halt_reg = 0x3a008,
2523         .halt_check = BRANCH_HALT,
2524         .clkr = {
2525                 .enable_reg = 0x3a008,
2526                 .enable_mask = BIT(0),
2527                 .hw.init = &(const struct clk_init_data) {
2528                         .name = "gcc_cmn_12gpll_sys_clk",
2529                         .parent_hws = (const struct clk_hw*[]) {
2530                                 &gcc_uniphy_sys_clk_src.clkr.hw,
2531                         },
2532                         .num_parents = 1,
2533                         .flags = CLK_SET_RATE_PARENT,
2534                         .ops = &clk_branch2_ops,
2535                 },
2536         },
2537 };
2538
2539 static struct clk_branch gcc_lpass_sway_clk = {
2540         .halt_reg = 0x27014,
2541         .halt_check = BRANCH_HALT,
2542         .clkr = {
2543                 .enable_reg = 0x27014,
2544                 .enable_mask = BIT(0),
2545                 .hw.init = &(const struct clk_init_data) {
2546                         .name = "gcc_lpass_sway_clk",
2547                         .parent_hws = (const struct clk_hw*[]) {
2548                                 &gcc_lpass_sway_clk_src.clkr.hw,
2549                         },
2550                         .num_parents = 1,
2551                         .flags = CLK_SET_RATE_PARENT,
2552                         .ops = &clk_branch2_ops,
2553                 },
2554         },
2555 };
2556
2557 static struct clk_branch gcc_cnoc_lpass_cfg_clk = {
2558         .halt_reg = 0x2e028,
2559         .halt_check = BRANCH_HALT,
2560         .clkr = {
2561                 .enable_reg = 0x2e028,
2562                 .enable_mask = BIT(0),
2563                 .hw.init = &(const struct clk_init_data) {
2564                         .name = "gcc_cnoc_lpass_cfg_clk",
2565                         .parent_hws = (const struct clk_hw*[]) {
2566                                 &gcc_lpass_sway_clk_src.clkr.hw,
2567                         },
2568                         .num_parents = 1,
2569                         .flags = CLK_SET_RATE_PARENT,
2570                         .ops = &clk_branch2_ops,
2571                 },
2572         },
2573 };
2574
2575 static struct clk_branch gcc_lpass_core_axim_clk = {
2576         .halt_reg = 0x27018,
2577         .halt_check = BRANCH_HALT_VOTED,
2578         .clkr = {
2579                 .enable_reg = 0x27018,
2580                 .enable_mask = BIT(0),
2581                 .hw.init = &(const struct clk_init_data) {
2582                         .name = "gcc_lpass_core_axim_clk",
2583                         .parent_hws = (const struct clk_hw*[]) {
2584                                 &gcc_lpass_axim_clk_src.clkr.hw,
2585                         },
2586                         .num_parents = 1,
2587                         .flags = CLK_SET_RATE_PARENT,
2588                         .ops = &clk_branch2_ops,
2589                 },
2590         },
2591 };
2592
2593 static struct clk_branch gcc_snoc_lpass_clk = {
2594         .halt_reg = 0x31020,
2595         .halt_check = BRANCH_HALT_VOTED,
2596         .clkr = {
2597                 .enable_reg = 0x31020,
2598                 .enable_mask = BIT(0),
2599                 .hw.init = &(const struct clk_init_data) {
2600                         .name = "gcc_snoc_lpass_clk",
2601                         .parent_hws = (const struct clk_hw*[]) {
2602                                 &gcc_lpass_axim_clk_src.clkr.hw,
2603                         },
2604                         .num_parents = 1,
2605                         .flags = CLK_SET_RATE_PARENT,
2606                         .ops = &clk_branch2_ops,
2607                 },
2608         },
2609 };
2610
2611 static struct clk_branch gcc_usb0_eud_at_clk = {
2612         .halt_reg = 0x30004,
2613         .halt_check = BRANCH_HALT_VOTED,
2614         .clkr = {
2615                 .enable_reg = 0x30004,
2616                 .enable_mask = BIT(0),
2617                 .hw.init = &(const struct clk_init_data) {
2618                         .name = "gcc_usb0_eud_at_clk",
2619                         .parent_hws = (const struct clk_hw*[]) {
2620                                 &gcc_eud_at_div_clk_src.hw,
2621                         },
2622                         .num_parents = 1,
2623                         .flags = CLK_SET_RATE_PARENT,
2624                         .ops = &clk_branch2_ops,
2625                 },
2626         },
2627 };
2628
2629 static struct clk_branch gcc_qpic_ahb_clk = {
2630         .halt_reg = 0x32010,
2631         .halt_check = BRANCH_HALT,
2632         .clkr = {
2633                 .enable_reg = 0x32010,
2634                 .enable_mask = BIT(0),
2635                 .hw.init = &(const struct clk_init_data) {
2636                         .name = "gcc_qpic_ahb_clk",
2637                         .parent_hws = (const struct clk_hw*[]) {
2638                                 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2639                         },
2640                         .num_parents = 1,
2641                         .flags = CLK_SET_RATE_PARENT,
2642                         .ops = &clk_branch2_ops,
2643                 },
2644         },
2645 };
2646
2647 static struct clk_branch gcc_qpic_clk = {
2648         .halt_reg = 0x32028,
2649         .halt_check = BRANCH_HALT,
2650         .clkr = {
2651                 .enable_reg = 0x32028,
2652                 .enable_mask = BIT(0),
2653                 .hw.init = &(const struct clk_init_data) {
2654                         .name = "gcc_qpic_clk",
2655                         .parent_hws = (const struct clk_hw*[]) {
2656                                 &gcc_qpic_clk_src.clkr.hw,
2657                         },
2658                         .num_parents = 1,
2659                         .flags = CLK_SET_RATE_PARENT,
2660                         .ops = &clk_branch2_ops,
2661                 },
2662         },
2663 };
2664
2665 static struct clk_branch gcc_qpic_io_macro_clk = {
2666         .halt_reg = 0x3200c,
2667         .halt_check = BRANCH_HALT,
2668         .clkr = {
2669                 .enable_reg = 0x3200c,
2670                 .enable_mask = BIT(0),
2671                 .hw.init = &(const struct clk_init_data) {
2672                         .name = "gcc_qpic_io_macro_clk",
2673                         .parent_hws = (const struct clk_hw*[]) {
2674                                 &gcc_qpic_io_macro_clk_src.clkr.hw,
2675                         },
2676                         .num_parents = 1,
2677                         .flags = CLK_SET_RATE_PARENT,
2678                         .ops = &clk_branch2_ops,
2679                 },
2680         },
2681 };
2682
2683 static struct clk_branch gcc_qdss_dap_clk = {
2684         .halt_reg = 0x2d058,
2685         .clkr = {
2686                 .enable_reg = 0x2d058,
2687                 .enable_mask = BIT(0),
2688                 .hw.init = &(const struct clk_init_data) {
2689                         .name = "gcc_qdss_dap_clk",
2690                         .parent_hws = (const struct clk_hw *[]) {
2691                                 &gcc_qdss_dap_sync_clk_src.hw
2692                         },
2693                         .num_parents = 1,
2694                         .flags = CLK_SET_RATE_PARENT,
2695                         .ops = &clk_branch2_ops,
2696                 },
2697         },
2698 };
2699
2700 static struct clk_branch gcc_qdss_at_clk = {
2701         .halt_reg = 0x2d034,
2702         .clkr = {
2703                 .enable_reg = 0x2d034,
2704                 .enable_mask = BIT(0),
2705                 .hw.init = &(const struct clk_init_data) {
2706                         .name = "gcc_qdss_at_clk",
2707                         .parent_hws = (const struct clk_hw *[]) {
2708                                 &gcc_qdss_at_clk_src.clkr.hw
2709                         },
2710                         .num_parents = 1,
2711                         .flags = CLK_SET_RATE_PARENT,
2712                         .ops = &clk_branch2_ops,
2713                 },
2714         },
2715 };
2716
2717 static struct clk_branch gcc_pcie0_rchng_clk = {
2718         .halt_reg = 0x28028,
2719         .clkr = {
2720                 .enable_reg = 0x28028,
2721                 .enable_mask = BIT(1),
2722                 .hw.init = &(const struct clk_init_data) {
2723                         .name = "gcc_pcie0_rchng_clk",
2724                         .parent_hws = (const struct clk_hw *[]) {
2725                                 &gcc_pcie0_rchng_clk_src.clkr.hw
2726                         },
2727                         .num_parents = 1,
2728                         .flags = CLK_SET_RATE_PARENT,
2729                         .ops = &clk_branch2_ops,
2730                 },
2731         },
2732 };
2733
2734 static struct clk_branch gcc_pcie1_rchng_clk = {
2735         .halt_reg = 0x29028,
2736         .clkr = {
2737                 .enable_reg = 0x29028,
2738                 .enable_mask = BIT(1),
2739                 .hw.init = &(const struct clk_init_data) {
2740                         .name = "gcc_pcie1_rchng_clk",
2741                         .parent_hws = (const struct clk_hw *[]) {
2742                                 &gcc_pcie1_rchng_clk_src.clkr.hw
2743                         },
2744                         .num_parents = 1,
2745                         .flags = CLK_SET_RATE_PARENT,
2746                         .ops = &clk_branch2_ops,
2747                 },
2748         },
2749 };
2750
2751 static struct clk_branch gcc_pcie2_rchng_clk = {
2752         .halt_reg = 0x2a028,
2753         .clkr = {
2754                 .enable_reg = 0x2a028,
2755                 .enable_mask = BIT(1),
2756                 .hw.init = &(const struct clk_init_data) {
2757                         .name = "gcc_pcie2_rchng_clk",
2758                         .parent_hws = (const struct clk_hw *[]) {
2759                                 &gcc_pcie2_rchng_clk_src.clkr.hw
2760                         },
2761                         .num_parents = 1,
2762                         .flags = CLK_SET_RATE_PARENT,
2763                         .ops = &clk_branch2_ops,
2764                 },
2765         },
2766 };
2767
2768 static struct clk_branch gcc_pcie3_rchng_clk = {
2769         .halt_reg = 0x2b028,
2770         .clkr = {
2771                 .enable_reg = 0x2b028,
2772                 .enable_mask = BIT(1),
2773                 .hw.init = &(const struct clk_init_data) {
2774                         .name = "gcc_pcie3_rchng_clk",
2775                         .parent_hws = (const struct clk_hw *[]) {
2776                                 &gcc_pcie3_rchng_clk_src.clkr.hw
2777                         },
2778                         .num_parents = 1,
2779                         .flags = CLK_SET_RATE_PARENT,
2780                         .ops = &clk_branch2_ops,
2781                 },
2782         },
2783 };
2784
2785 static struct clk_regmap *gcc_ipq5424_clocks[] = {
2786         [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
2787         [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
2788         [GCC_APSS_DBG_CLK] = &gcc_apss_dbg_clk.clkr,
2789         [GCC_CNOC_PCIE0_1LANE_S_CLK] = &gcc_cnoc_pcie0_1lane_s_clk.clkr,
2790         [GCC_CNOC_PCIE1_1LANE_S_CLK] = &gcc_cnoc_pcie1_1lane_s_clk.clkr,
2791         [GCC_CNOC_PCIE2_2LANE_S_CLK] = &gcc_cnoc_pcie2_2lane_s_clk.clkr,
2792         [GCC_CNOC_PCIE3_2LANE_S_CLK] = &gcc_cnoc_pcie3_2lane_s_clk.clkr,
2793         [GCC_CNOC_USB_CLK] = &gcc_cnoc_usb_clk.clkr,
2794         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
2795         [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
2796         [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
2797         [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
2798         [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
2799         [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
2800         [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
2801         [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
2802         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
2803         [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
2804         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
2805         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
2806         [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
2807         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
2808         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
2809         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
2810         [GCC_PCIE0_AXI_M_CLK_SRC] = &gcc_pcie0_axi_m_clk_src.clkr,
2811         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
2812         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
2813         [GCC_PCIE0_AXI_S_CLK_SRC] = &gcc_pcie0_axi_s_clk_src.clkr,
2814         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
2815         [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
2816         [GCC_PCIE0_PIPE_CLK_SRC] = &gcc_pcie0_pipe_clk_src.clkr,
2817         [GCC_PCIE0_RCHNG_CLK_SRC] = &gcc_pcie0_rchng_clk_src.clkr,
2818         [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
2819         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
2820         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
2821         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
2822         [GCC_PCIE1_AXI_M_CLK_SRC] = &gcc_pcie1_axi_m_clk_src.clkr,
2823         [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
2824         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
2825         [GCC_PCIE1_AXI_S_CLK_SRC] = &gcc_pcie1_axi_s_clk_src.clkr,
2826         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
2827         [GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
2828         [GCC_PCIE1_PIPE_CLK_SRC] = &gcc_pcie1_pipe_clk_src.clkr,
2829         [GCC_PCIE1_RCHNG_CLK_SRC] = &gcc_pcie1_rchng_clk_src.clkr,
2830         [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
2831         [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
2832         [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
2833         [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
2834         [GCC_PCIE2_AXI_M_CLK_SRC] = &gcc_pcie2_axi_m_clk_src.clkr,
2835         [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
2836         [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
2837         [GCC_PCIE2_AXI_S_CLK_SRC] = &gcc_pcie2_axi_s_clk_src.clkr,
2838         [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
2839         [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
2840         [GCC_PCIE2_PIPE_CLK_SRC] = &gcc_pcie2_pipe_clk_src.clkr,
2841         [GCC_PCIE2_RCHNG_CLK_SRC] = &gcc_pcie2_rchng_clk_src.clkr,
2842         [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
2843         [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
2844         [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
2845         [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
2846         [GCC_PCIE3_AXI_M_CLK_SRC] = &gcc_pcie3_axi_m_clk_src.clkr,
2847         [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
2848         [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
2849         [GCC_PCIE3_AXI_S_CLK_SRC] = &gcc_pcie3_axi_s_clk_src.clkr,
2850         [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
2851         [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
2852         [GCC_PCIE3_PIPE_CLK_SRC] = &gcc_pcie3_pipe_clk_src.clkr,
2853         [GCC_PCIE3_RCHNG_CLK_SRC] = &gcc_pcie3_rchng_clk_src.clkr,
2854         [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
2855         [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
2856         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2857         [GCC_QUPV3_AHB_MST_CLK] = &gcc_qupv3_ahb_mst_clk.clkr,
2858         [GCC_QUPV3_AHB_SLV_CLK] = &gcc_qupv3_ahb_slv_clk.clkr,
2859         [GCC_QUPV3_I2C0_CLK] = &gcc_qupv3_i2c0_clk.clkr,
2860         [GCC_QUPV3_I2C0_CLK_SRC] = &gcc_qupv3_i2c0_clk_src.clkr,
2861         [GCC_QUPV3_I2C0_DIV_CLK_SRC] = &gcc_qupv3_i2c0_div_clk_src.clkr,
2862         [GCC_QUPV3_I2C1_CLK] = &gcc_qupv3_i2c1_clk.clkr,
2863         [GCC_QUPV3_I2C1_CLK_SRC] = &gcc_qupv3_i2c1_clk_src.clkr,
2864         [GCC_QUPV3_I2C1_DIV_CLK_SRC] = &gcc_qupv3_i2c1_div_clk_src.clkr,
2865         [GCC_QUPV3_SPI0_CLK] = &gcc_qupv3_spi0_clk.clkr,
2866         [GCC_QUPV3_SPI0_CLK_SRC] = &gcc_qupv3_spi0_clk_src.clkr,
2867         [GCC_QUPV3_SPI1_CLK] = &gcc_qupv3_spi1_clk.clkr,
2868         [GCC_QUPV3_SPI1_CLK_SRC] = &gcc_qupv3_spi1_clk_src.clkr,
2869         [GCC_QUPV3_UART0_CLK] = &gcc_qupv3_uart0_clk.clkr,
2870         [GCC_QUPV3_UART0_CLK_SRC] = &gcc_qupv3_uart0_clk_src.clkr,
2871         [GCC_QUPV3_UART1_CLK] = &gcc_qupv3_uart1_clk.clkr,
2872         [GCC_QUPV3_UART1_CLK_SRC] = &gcc_qupv3_uart1_clk_src.clkr,
2873         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2874         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2875         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2876         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2877         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2878         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
2879         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
2880         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
2881         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
2882         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
2883         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
2884         [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
2885         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
2886         [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
2887         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
2888         [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
2889         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
2890         [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
2891         [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
2892         [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
2893         [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
2894         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
2895         [GCC_USB1_MOCK_UTMI_CLK_SRC] = &gcc_usb1_mock_utmi_clk_src.clkr,
2896         [GCC_USB1_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb1_mock_utmi_div_clk_src.clkr,
2897         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
2898         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
2899         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
2900         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
2901         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
2902         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
2903         [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
2904         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
2905         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
2906         [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
2907         [GCC_CNOC_LPASS_CFG_CLK] = &gcc_cnoc_lpass_cfg_clk.clkr,
2908         [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
2909         [GCC_SNOC_LPASS_CLK] = &gcc_snoc_lpass_clk.clkr,
2910         [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
2911         [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr,
2912         [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
2913         [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
2914         [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
2915         [GCC_LPASS_AXIM_CLK_SRC] = &gcc_lpass_axim_clk_src.clkr,
2916         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
2917         [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
2918         [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
2919         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
2920         [GCC_QPIC_CLK_SRC] = &gcc_qpic_clk_src.clkr,
2921         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
2922         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
2923         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2924         [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
2925         [GPLL0] = &gpll0.clkr,
2926         [GPLL2] = &gpll2.clkr,
2927         [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2928         [GPLL4] = &gpll4.clkr,
2929 };
2930
2931 static const struct qcom_reset_map gcc_ipq5424_resets[] = {
2932         [GCC_QUPV3_BCR] = { 0x01000, 0 },
2933         [GCC_QUPV3_I2C0_BCR] = { 0x02000, 0 },
2934         [GCC_QUPV3_UART0_BCR] = { 0x02020, 0 },
2935         [GCC_QUPV3_I2C1_BCR] = { 0x03000, 0 },
2936         [GCC_QUPV3_UART1_BCR] = { 0x03028, 0 },
2937         [GCC_QUPV3_SPI0_BCR] = { 0x04000, 0 },
2938         [GCC_QUPV3_SPI1_BCR] = { 0x05000, 0 },
2939         [GCC_IMEM_BCR] = { 0x0e000, 0 },
2940         [GCC_TME_BCR] = { 0x100000, 0 },
2941         [GCC_DDRSS_BCR] = { 0x11000, 0 },
2942         [GCC_PRNG_BCR] = { 0x13020, 0 },
2943         [GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
2944         [GCC_NSS_BCR] = { 0x17000, 0 },
2945         [GCC_MDIO_BCR] = { 0x1703c, 0 },
2946         [GCC_UNIPHY0_BCR] = { 0x17044, 0 },
2947         [GCC_UNIPHY1_BCR] = { 0x17054, 0 },
2948         [GCC_UNIPHY2_BCR] = { 0x17064, 0 },
2949         [GCC_WCSS_BCR] = { 0x18004, 0 },
2950         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
2951         [GCC_TME_SEC_BUS_BCR] = { 0xa1030, 0 },
2952         [GCC_ADSS_BCR] = { 0x1c000, 0 },
2953         [GCC_LPASS_BCR] = { 0x27000, 0 },
2954         [GCC_PCIE0_BCR] = { 0x28000, 0 },
2955         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
2956         [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
2957         [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
2958         [GCC_PCIE1_BCR] = { 0x29000, 0 },
2959         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
2960         [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
2961         [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
2962         [GCC_PCIE2_BCR] = { 0x2a000, 0 },
2963         [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
2964         [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
2965         [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
2966         [GCC_PCIE3_BCR] = { 0x2b000, 0 },
2967         [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
2968         [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
2969         [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
2970         [GCC_USB_BCR] = { 0x2c000, 0 },
2971         [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
2972         [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
2973         [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
2974         [GCC_QDSS_BCR] = { 0x2d000, 0 },
2975         [GCC_SNOC_BCR] = { 0x2e000, 0 },
2976         [GCC_ANOC_BCR] = { 0x2e074, 0 },
2977         [GCC_PCNOC_BCR] = { 0x31000, 0 },
2978         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
2979         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
2980         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
2981         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
2982         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
2983         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
2984         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
2985         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
2986         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
2987         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
2988         [GCC_QPIC_BCR] = { 0x32000, 0 },
2989         [GCC_SDCC_BCR] = { 0x33000, 0 },
2990         [GCC_DCC_BCR] = { 0x35000, 0 },
2991         [GCC_SPDM_BCR] = { 0x36000, 0 },
2992         [GCC_MPM_BCR] = { 0x37000, 0 },
2993         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
2994         [GCC_RBCPR_BCR] = { 0x39000, 0 },
2995         [GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
2996         [GCC_TCSR_BCR] = { 0x3d000, 0 },
2997         [GCC_TLMM_BCR] = { 0x3e000, 0 },
2998         [GCC_QUPV3_AHB_MST_ARES] = { 0x01014, 2 },
2999         [GCC_QUPV3_CORE_ARES] = { 0x01018, 2 },
3000         [GCC_QUPV3_2X_CORE_ARES] = { 0x01020, 2 },
3001         [GCC_QUPV3_SLEEP_ARES] = { 0x01028, 2 },
3002         [GCC_QUPV3_AHB_SLV_ARES] = { 0x0102c, 2 },
3003         [GCC_QUPV3_I2C0_ARES] = { 0x02024, 2 },
3004         [GCC_QUPV3_UART0_ARES] = { 0x02040, 2 },
3005         [GCC_QUPV3_I2C1_ARES] = { 0x03024, 2 },
3006         [GCC_QUPV3_UART1_ARES] = { 0x03040, 2 },
3007         [GCC_QUPV3_SPI0_ARES] = { 0x04020, 2 },
3008         [GCC_QUPV3_SPI1_ARES] = { 0x05020, 2 },
3009         [GCC_DEBUG_ARES] = { 0x06068, 2 },
3010         [GCC_GP1_ARES] = { 0x08018, 2 },
3011         [GCC_GP2_ARES] = { 0x09018, 2 },
3012         [GCC_GP3_ARES] = { 0x0a018, 2 },
3013         [GCC_IMEM_AXI_ARES] = { 0x0e004, 2 },
3014         [GCC_IMEM_CFG_AHB_ARES] = { 0x0e00c, 2 },
3015         [GCC_TME_ARES] = { 0x100b4, 2 },
3016         [GCC_TME_TS_ARES] = { 0x100c0, 2 },
3017         [GCC_TME_SLOW_ARES] = { 0x100d0, 2 },
3018         [GCC_TME_RTC_TOGGLE_ARES] = { 0x100d8, 2 },
3019         [GCC_TIC_ARES] = { 0x12004, 2 },
3020         [GCC_PRNG_AHB_ARES] = { 0x13024, 2 },
3021         [GCC_BOOT_ROM_AHB_ARES] = { 0x1302c, 2 },
3022         [GCC_NSSNOC_ATB_ARES] = { 0x17014, 2 },
3023         [GCC_NSS_TS_ARES] = { 0x17018, 2 },
3024         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x1701c, 2 },
3025         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17020, 2 },
3026         [GCC_NSSNOC_MEMNOC_ARES] = { 0x17024, 2 },
3027         [GCC_NSSNOC_SNOC_ARES] = { 0x17028, 2 },
3028         [GCC_NSSCFG_ARES] = { 0x1702c, 2 },
3029         [GCC_NSSNOC_NSSCC_ARES] = { 0x17030, 2 },
3030         [GCC_NSSCC_ARES] = { 0x17034, 2 },
3031         [GCC_MDIO_AHB_ARES] = { 0x17040, 2 },
3032         [GCC_UNIPHY0_SYS_ARES] = { 0x17048, 2 },
3033         [GCC_UNIPHY0_AHB_ARES] = { 0x1704c, 2 },
3034         [GCC_UNIPHY1_SYS_ARES] = { 0x17058, 2 },
3035         [GCC_UNIPHY1_AHB_ARES] = { 0x1705c, 2 },
3036         [GCC_UNIPHY2_SYS_ARES] = { 0x17068, 2 },
3037         [GCC_UNIPHY2_AHB_ARES] = { 0x1706c, 2 },
3038         [GCC_NSSNOC_XO_DCD_ARES] = { 0x17074, 2 },
3039         [GCC_NSSNOC_SNOC_1_ARES] = { 0x1707c, 2 },
3040         [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17080, 2 },
3041         [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17084, 2 },
3042         [GCC_DDRSS_ATB_ARES] = { 0x19004, 2 },
3043         [GCC_DDRSS_AHB_ARES] = { 0x19008, 2 },
3044         [GCC_GEMNOC_AHB_ARES] = { 0x1900c, 2 },
3045         [GCC_GEMNOC_Q6_AXI_ARES] = { 0x19010, 2 },
3046         [GCC_GEMNOC_NSSNOC_ARES] = { 0x19014, 2 },
3047         [GCC_GEMNOC_SNOC_ARES] = { 0x19018, 2 },
3048         [GCC_GEMNOC_APSS_ARES] = { 0x1901c, 2 },
3049         [GCC_GEMNOC_QOSGEN_EXTREF_ARES] = { 0x19024, 2 },
3050         [GCC_GEMNOC_TS_ARES] = { 0x19028, 2 },
3051         [GCC_DDRSS_SMS_SLOW_ARES] = { 0x1902c, 2 },
3052         [GCC_GEMNOC_CNOC_ARES] = { 0x19038, 2 },
3053         [GCC_GEMNOC_XO_DBG_ARES] = { 0x19040, 2 },
3054         [GCC_GEMNOC_ANOC_ARES] = { 0x19048, 2 },
3055         [GCC_DDRSS_LLCC_ATB_ARES] = { 0x1904c, 2 },
3056         [GCC_LLCC_TPDM_CFG_ARES] = { 0x19050, 2 },
3057         [GCC_TME_BUS_ARES] = { 0x1a014, 2 },
3058         [GCC_SEC_CTRL_ACC_ARES] = { 0x1a018, 2 },
3059         [GCC_SEC_CTRL_ARES] = { 0x1a020, 2 },
3060         [GCC_SEC_CTRL_SENSE_ARES] = { 0x1a028, 2 },
3061         [GCC_SEC_CTRL_AHB_ARES] = { 0x1a038, 2 },
3062         [GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES] = { 0x1a03c, 2 },
3063         [GCC_ADSS_PWM_ARES] = { 0x1c00c, 2 },
3064         [GCC_TME_ATB_ARES] = { 0x1e030, 2 },
3065         [GCC_TME_DBGAPB_ARES] = { 0x1e034, 2 },
3066         [GCC_TME_DEBUG_ARES] = { 0x1e038, 2 },
3067         [GCC_TME_AT_ARES] = { 0x1e03C, 2 },
3068         [GCC_TME_APB_ARES] = { 0x1e040, 2 },
3069         [GCC_TME_DMI_DBG_HS_ARES] = { 0x1e044, 2 },
3070         [GCC_APSS_AHB_ARES] = { 0x24014, 2 },
3071         [GCC_APSS_AXI_ARES] = { 0x24018, 2 },
3072         [GCC_CPUSS_TRIG_ARES] = { 0x2401c, 2 },
3073         [GCC_APSS_DBG_ARES] = { 0x2402c, 2 },
3074         [GCC_APSS_TS_ARES] = { 0x24030, 2 },
3075         [GCC_APSS_ATB_ARES] = { 0x24034, 2 },
3076         [GCC_Q6_AXIM_ARES] = { 0x2500c, 2 },
3077         [GCC_Q6_AXIS_ARES] = { 0x25010, 2 },
3078         [GCC_Q6_AHB_ARES] = { 0x25014, 2 },
3079         [GCC_Q6_AHB_S_ARES] = { 0x25018, 2 },
3080         [GCC_Q6SS_ATBM_ARES] = { 0x2501c, 2 },
3081         [GCC_Q6_TSCTR_1TO2_ARES] = { 0x25020, 2 },
3082         [GCC_Q6SS_PCLKDBG_ARES] = { 0x25024, 2 },
3083         [GCC_Q6SS_TRIG_ARES] = { 0x25028, 2 },
3084         [GCC_Q6SS_BOOT_CBCR_ARES] = { 0x2502c, 2 },
3085         [GCC_WCSS_DBG_IFC_APB_ARES] = { 0x25038, 2 },
3086         [GCC_WCSS_DBG_IFC_ATB_ARES] = { 0x2503c, 2 },
3087         [GCC_WCSS_DBG_IFC_NTS_ARES] = { 0x25040, 2 },
3088         [GCC_WCSS_DBG_IFC_DAPBUS_ARES] = { 0x25044, 2 },
3089         [GCC_WCSS_DBG_IFC_APB_BDG_ARES] = { 0x25048, 2 },
3090         [GCC_WCSS_DBG_IFC_NTS_BDG_ARES] = { 0x25050, 2 },
3091         [GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES] = { 0x25054, 2 },
3092         [GCC_WCSS_ECAHB_ARES] = { 0x25058, 2 },
3093         [GCC_WCSS_ACMT_ARES] = { 0x2505c, 2 },
3094         [GCC_WCSS_AHB_S_ARES] = { 0x25060, 2 },
3095         [GCC_WCSS_AXI_M_ARES] = { 0x25064, 2 },
3096         [GCC_PCNOC_WAPSS_ARES] = { 0x25080, 2 },
3097         [GCC_SNOC_WAPSS_ARES] = { 0x25090, 2 },
3098         [GCC_LPASS_SWAY_ARES] = { 0x27014, 2 },
3099         [GCC_LPASS_CORE_AXIM_ARES] = { 0x27018, 2 },
3100         [GCC_PCIE0_AHB_ARES] = { 0x28030, 2 },
3101         [GCC_PCIE0_AXI_M_ARES] = { 0x28038, 2 },
3102         [GCC_PCIE0_AXI_S_ARES] = { 0x28040, 2 },
3103         [GCC_PCIE0_AXI_S_BRIDGE_ARES] = { 0x28048, 2},
3104         [GCC_PCIE0_PIPE_ARES] = { 0x28068, 2},
3105         [GCC_PCIE0_AUX_ARES] = { 0x28070, 2 },
3106         [GCC_PCIE1_AHB_ARES] = { 0x29030, 2 },
3107         [GCC_PCIE1_AXI_M_ARES] = { 0x29038, 2 },
3108         [GCC_PCIE1_AXI_S_ARES] = { 0x29040, 2 },
3109         [GCC_PCIE1_AXI_S_BRIDGE_ARES] = { 0x29048, 2 },
3110         [GCC_PCIE1_PIPE_ARES] = { 0x29068, 2 },
3111         [GCC_PCIE1_AUX_ARES] = { 0x29074, 2 },
3112         [GCC_PCIE2_AHB_ARES] = { 0x2a030, 2 },
3113         [GCC_PCIE2_AXI_M_ARES] = { 0x2a038, 2 },
3114         [GCC_PCIE2_AXI_S_ARES] = { 0x2a040, 2 },
3115         [GCC_PCIE2_AXI_S_BRIDGE_ARES] = { 0x2a048, 2 },
3116         [GCC_PCIE2_PIPE_ARES] = { 0x2a068, 2 },
3117         [GCC_PCIE2_AUX_ARES] = { 0x2a078, 2 },
3118         [GCC_PCIE3_AHB_ARES] = { 0x2b030, 2 },
3119         [GCC_PCIE3_AXI_M_ARES] = { 0x2b038, 2 },
3120         [GCC_PCIE3_AXI_S_ARES] = { 0x2b040, 2 },
3121         [GCC_PCIE3_AXI_S_BRIDGE_ARES] = { 0x2b048, 2 },
3122         [GCC_PCIE3_PIPE_ARES] = { 0x2b068, 2 },
3123         [GCC_PCIE3_AUX_ARES] = { 0x2b07C, 2 },
3124         [GCC_USB0_MASTER_ARES] = { 0x2c044, 2 },
3125         [GCC_USB0_AUX_ARES] = { 0x2c04c, 2 },
3126         [GCC_USB0_MOCK_UTMI_ARES] = { 0x2c050, 2 },
3127         [GCC_USB0_PIPE_ARES] = { 0x2c054, 2 },
3128         [GCC_USB0_SLEEP_ARES] = { 0x2c058, 2 },
3129         [GCC_USB0_PHY_CFG_AHB_ARES] = { 0x2c05c, 2 },
3130         [GCC_QDSS_AT_ARES] = { 0x2d034, 2 },
3131         [GCC_QDSS_STM_ARES] = { 0x2d03C, 2 },
3132         [GCC_QDSS_TRACECLKIN_ARES] = { 0x2d040, 2 },
3133         [GCC_QDSS_TSCTR_DIV2_ARES] = { 0x2d044, 2 },
3134         [GCC_QDSS_TSCTR_DIV3_ARES] = { 0x2d048, 2 },
3135         [GCC_QDSS_TSCTR_DIV4_ARES] = { 0x2d04c, 2 },
3136         [GCC_QDSS_TSCTR_DIV8_ARES] = { 0x2d050, 2 },
3137         [GCC_QDSS_TSCTR_DIV16_ARES] = { 0x2d054, 2 },
3138         [GCC_QDSS_DAP_ARES] = { 0x2d058, 2 },
3139         [GCC_QDSS_APB2JTAG_ARES] = { 0x2d05c, 2 },
3140         [GCC_QDSS_ETR_USB_ARES] = { 0x2d060, 2 },
3141         [GCC_QDSS_DAP_AHB_ARES] = { 0x2d064, 2 },
3142         [GCC_QDSS_CFG_AHB_ARES] = { 0x2d068, 2 },
3143         [GCC_QDSS_EUD_AT_ARES] = { 0x2d06c, 2 },
3144         [GCC_QDSS_TS_ARES] = { 0x2d078, 2 },
3145         [GCC_QDSS_USB_ARES] = { 0x2d07c, 2 },
3146         [GCC_SYS_NOC_AXI_ARES] = { 0x2e01c, 2 },
3147         [GCC_SNOC_QOSGEN_EXTREF_ARES] = { 0x2e020, 2 },
3148         [GCC_CNOC_LPASS_CFG_ARES] = { 0x2e028, 2 },
3149         [GCC_SYS_NOC_AT_ARES] = { 0x2e038, 2 },
3150         [GCC_SNOC_PCNOC_AHB_ARES] = { 0x2e03c, 2 },
3151         [GCC_SNOC_TME_ARES] = { 0x2e05c, 2 },
3152         [GCC_SNOC_XO_DCD_ARES] = { 0x2e060, 2 },
3153         [GCC_SNOC_TS_ARES] = { 0x2e068, 2 },
3154         [GCC_ANOC0_AXI_ARES] = { 0x2e078, 2 },
3155         [GCC_ANOC_PCIE0_1LANE_M_ARES] = { 0x2e07c, 2 },
3156         [GCC_ANOC_PCIE2_2LANE_M_ARES] = { 0x2e080, 2 },
3157         [GCC_ANOC_PCIE1_1LANE_M_ARES] = { 0x2e084, 2 },
3158         [GCC_ANOC_PCIE3_2LANE_M_ARES] = { 0x2e090, 2 },
3159         [GCC_ANOC_PCNOC_AHB_ARES] = { 0x2e094, 2 },
3160         [GCC_ANOC_QOSGEN_EXTREF_ARES] = { 0x2e098, 2 },
3161         [GCC_ANOC_XO_DCD_ARES] = { 0x2e09C, 2 },
3162         [GCC_SNOC_XO_DBG_ARES] = { 0x2e0a0, 2 },
3163         [GCC_AGGRNOC_ATB_ARES] = { 0x2e0ac, 2 },
3164         [GCC_AGGRNOC_TS_ARES] = { 0x2e0b0, 2 },
3165         [GCC_USB0_EUD_AT_ARES] = { 0x30004, 2 },
3166         [GCC_PCNOC_TIC_ARES] = { 0x31014, 2 },
3167         [GCC_PCNOC_AHB_ARES] = { 0x31018, 2 },
3168         [GCC_PCNOC_XO_DBG_ARES] = { 0x3101c, 2 },
3169         [GCC_SNOC_LPASS_ARES] = { 0x31020, 2 },
3170         [GCC_PCNOC_AT_ARES] = { 0x31024, 2 },
3171         [GCC_PCNOC_XO_DCD_ARES] = { 0x31028, 2 },
3172         [GCC_PCNOC_TS_ARES] = { 0x3102c, 2 },
3173         [GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES] = { 0x31034, 2 },
3174         [GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES] = { 0x3103c, 2 },
3175         [GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES] = { 0x31044, 2 },
3176         [GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES] = { 0x3104c, 2 },
3177         [GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES] = { 0x31054, 2 },
3178         [GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES] = { 0x3105c, 2 },
3179         [GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES] = { 0x31064, 2 },
3180         [GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES] = { 0x3106c, 2 },
3181         [GCC_Q6_AXIM_RESET] = { 0x2506c, 0 },
3182         [GCC_Q6_AXIS_RESET] = { 0x2506c, 1 },
3183         [GCC_Q6_AHB_S_RESET] = { 0x2506c, 2 },
3184         [GCC_Q6_AHB_RESET] = { 0x2506c, 3 },
3185         [GCC_Q6SS_DBG_RESET] = { 0x2506c, 4 },
3186         [GCC_WCSS_ECAHB_RESET] = { 0x25070, 0 },
3187         [GCC_WCSS_DBG_BDG_RESET] = { 0x25070, 1 },
3188         [GCC_WCSS_DBG_RESET] = { 0x25070, 2 },
3189         [GCC_WCSS_AXI_M_RESET] = { 0x25070, 3 },
3190         [GCC_WCSS_AHB_S_RESET] = { 0x25070, 4 },
3191         [GCC_WCSS_ACMT_RESET] = { 0x25070, 5 },
3192         [GCC_WCSSAON_RESET] = { 0x25074, 0 },
3193         [GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 },
3194         [GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 },
3195         [GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 },
3196         [GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 },
3197         [GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 },
3198         [GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 },
3199         [GCC_PCIE0_AUX_RESET] = { 0x28058, 6 },
3200         [GCC_PCIE0_AHB_RESET] = { 0x28058, 7 },
3201         [GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 },
3202         [GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 },
3203         [GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 },
3204         [GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 },
3205         [GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 },
3206         [GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 },
3207         [GCC_PCIE1_AUX_RESET] = { 0x29058, 6 },
3208         [GCC_PCIE1_AHB_RESET] = { 0x29058, 7 },
3209         [GCC_PCIE2_PIPE_RESET] = { 0x2a058, 0 },
3210         [GCC_PCIE2_CORE_STICKY_RESET] = { 0x2a058, 1 },
3211         [GCC_PCIE2_AXI_S_STICKY_RESET] = { 0x2a058, 2 },
3212         [GCC_PCIE2_AXI_S_RESET] = { 0x2a058, 3 },
3213         [GCC_PCIE2_AXI_M_STICKY_RESET] = { 0x2a058, 4 },
3214         [GCC_PCIE2_AXI_M_RESET] = { 0x2a058, 5 },
3215         [GCC_PCIE2_AUX_RESET] = { 0x2a058, 6 },
3216         [GCC_PCIE2_AHB_RESET] = { 0x2a058, 7 },
3217         [GCC_PCIE3_PIPE_RESET] = { 0x2b058, 0 },
3218         [GCC_PCIE3_CORE_STICKY_RESET] = { 0x2b058, 1 },
3219         [GCC_PCIE3_AXI_S_STICKY_RESET] = { 0x2b058, 2 },
3220         [GCC_PCIE3_AXI_S_RESET] = { 0x2b058, 3 },
3221         [GCC_PCIE3_AXI_M_STICKY_RESET] = { 0x2b058, 4 },
3222         [GCC_PCIE3_AXI_M_RESET] = { 0x2b058, 5 },
3223         [GCC_PCIE3_AUX_RESET] = { 0x2b058, 6 },
3224         [GCC_PCIE3_AHB_RESET] = { 0x2b058, 7 },
3225         [GCC_NSS_PARTIAL_RESET] = { 0x17078, 0 },
3226         [GCC_UNIPHY0_XPCS_ARES] = { 0x17050, 2 },
3227         [GCC_UNIPHY1_XPCS_ARES] = { 0x17060, 2 },
3228         [GCC_UNIPHY2_XPCS_ARES] = { 0x17070, 2 },
3229         [GCC_USB1_BCR] = { 0x3C000, 0 },
3230         [GCC_QUSB2_1_PHY_BCR] = { 0x3C030, 0 },
3231 };
3232
3233 static const struct of_device_id gcc_ipq5424_match_table[] = {
3234         { .compatible = "qcom,ipq5424-gcc" },
3235         { }
3236 };
3237 MODULE_DEVICE_TABLE(of, gcc_ipq5424_match_table);
3238
3239 static const struct regmap_config gcc_ipq5424_regmap_config = {
3240         .reg_bits       = 32,
3241         .reg_stride     = 4,
3242         .val_bits       = 32,
3243         .max_register   = 0x3f024,
3244         .fast_io        = true,
3245 };
3246
3247 static struct clk_hw *gcc_ipq5424_hws[] = {
3248         &gpll0_div2.hw,
3249         &gcc_xo_div4_clk_src.hw,
3250         &gcc_qdss_tsctr_div2_clk_src.hw,
3251         &gcc_qdss_dap_sync_clk_src.hw,
3252         &gcc_eud_at_div_clk_src.hw,
3253 };
3254
3255 static const struct qcom_cc_desc gcc_ipq5424_desc = {
3256         .config = &gcc_ipq5424_regmap_config,
3257         .clks = gcc_ipq5424_clocks,
3258         .num_clks = ARRAY_SIZE(gcc_ipq5424_clocks),
3259         .resets = gcc_ipq5424_resets,
3260         .num_resets = ARRAY_SIZE(gcc_ipq5424_resets),
3261         .clk_hws = gcc_ipq5424_hws,
3262         .num_clk_hws = ARRAY_SIZE(gcc_ipq5424_hws),
3263 };
3264
3265 static int gcc_ipq5424_probe(struct platform_device *pdev)
3266 {
3267         return qcom_cc_probe(pdev, &gcc_ipq5424_desc);
3268 }
3269
3270 static struct platform_driver gcc_ipq5424_driver = {
3271         .probe = gcc_ipq5424_probe,
3272         .driver = {
3273                 .name   = "qcom,gcc-ipq5424",
3274                 .of_match_table = gcc_ipq5424_match_table,
3275         },
3276 };
3277
3278 static int __init gcc_ipq5424_init(void)
3279 {
3280         return platform_driver_register(&gcc_ipq5424_driver);
3281 }
3282 core_initcall(gcc_ipq5424_init);
3283
3284 static void __exit gcc_ipq5424_exit(void)
3285 {
3286         platform_driver_unregister(&gcc_ipq5424_driver);
3287 }
3288 module_exit(gcc_ipq5424_exit);
3289
3290 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5424 Driver");
3291 MODULE_LICENSE("GPL");