drivers/clk/meson/meson8b.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 Endless Mobile, Inc.
   4  * Author: Carlo Caione <[email protected]>
   5  *
   6  * Copyright (c) 2016 BayLibre, Inc.
   7  * Michael Turquette <[email protected]>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/init.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of_address.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/slab.h>
  17 #include <linux/regmap.h>
  18
  19 #include "meson8b.h"
  20 #include "clk-regmap.h"
  21 #include "meson-clkc-utils.h"
  22 #include "clk-pll.h"
  23 #include "clk-mpll.h"
  24
  25 #include <dt-bindings/clock/meson8b-clkc.h>
  26 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  27
  28 struct meson8b_clk_reset {
  29         struct reset_controller_dev reset;
  30         struct regmap *regmap;
  31 };
  32
  33 static const struct pll_params_table sys_pll_params_table[] = {
  34         PLL_PARAMS(50, 1),
  35         PLL_PARAMS(51, 1),
  36         PLL_PARAMS(52, 1),
  37         PLL_PARAMS(53, 1),
  38         PLL_PARAMS(54, 1),
  39         PLL_PARAMS(55, 1),
  40         PLL_PARAMS(56, 1),
  41         PLL_PARAMS(57, 1),
  42         PLL_PARAMS(58, 1),
  43         PLL_PARAMS(59, 1),
  44         PLL_PARAMS(60, 1),
  45         PLL_PARAMS(61, 1),
  46         PLL_PARAMS(62, 1),
  47         PLL_PARAMS(63, 1),
  48         PLL_PARAMS(64, 1),
  49         PLL_PARAMS(65, 1),
  50         PLL_PARAMS(66, 1),
  51         PLL_PARAMS(67, 1),
  52         PLL_PARAMS(68, 1),
  53         PLL_PARAMS(84, 1),
  54         { /* sentinel */ },
  55 };
  56
  57 static struct clk_regmap meson8b_fixed_pll_dco = {
  58         .data = &(struct meson_clk_pll_data){
  59                 .en = {
  60                         .reg_off = HHI_MPLL_CNTL,
  61                         .shift   = 30,
  62                         .width   = 1,
  63                 },
  64                 .m = {
  65                         .reg_off = HHI_MPLL_CNTL,
  66                         .shift   = 0,
  67                         .width   = 9,
  68                 },
  69                 .n = {
  70                         .reg_off = HHI_MPLL_CNTL,
  71                         .shift   = 9,
  72                         .width   = 5,
  73                 },
  74                 .frac = {
  75                         .reg_off = HHI_MPLL_CNTL2,
  76                         .shift   = 0,
  77                         .width   = 12,
  78                 },
  79                 .l = {
  80                         .reg_off = HHI_MPLL_CNTL,
  81                         .shift   = 31,
  82                         .width   = 1,
  83                 },
  84                 .rst = {
  85                         .reg_off = HHI_MPLL_CNTL,
  86                         .shift   = 29,
  87                         .width   = 1,
  88                 },
  89         },
  90         .hw.init = &(struct clk_init_data){
  91                 .name = "fixed_pll_dco",
  92                 .ops = &meson_clk_pll_ro_ops,
  93                 .parent_data = &(const struct clk_parent_data) {
  94                         .fw_name = "xtal",
  95                         .name = "xtal",
  96                         .index = -1,
  97                 },
  98                 .num_parents = 1,
  99         },
 100 };
 101
 102 static struct clk_regmap meson8b_fixed_pll = {
 103         .data = &(struct clk_regmap_div_data){
 104                 .offset = HHI_MPLL_CNTL,
 105                 .shift = 16,
 106                 .width = 2,
 107                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 108         },
 109         .hw.init = &(struct clk_init_data){
 110                 .name = "fixed_pll",
 111                 .ops = &clk_regmap_divider_ro_ops,
 112                 .parent_hws = (const struct clk_hw *[]) {
 113                         &meson8b_fixed_pll_dco.hw
 114                 },
 115                 .num_parents = 1,
 116                 /*
 117                  * This clock won't ever change at runtime so
 118                  * CLK_SET_RATE_PARENT is not required
 119                  */
 120         },
 121 };
 122
 123 static struct clk_fixed_factor hdmi_pll_dco_in = {
 124         .mult = 2,
 125         .div = 1,
 126         .hw.init = &(struct clk_init_data){
 127                 .name = "hdmi_pll_dco_in",
 128                 .ops = &clk_fixed_factor_ops,
 129                 .parent_data = &(const struct clk_parent_data) {
 130                         .fw_name = "xtal",
 131                         .index = -1,
 132                 },
 133                 .num_parents = 1,
 134         },
 135 };
 136
 137 /*
 138  * Taken from the vendor driver for the 2970/2975MHz (both only differ in the
 139  * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8,
 140  * Meson8b and Meson8m2. This doubles the input (or output - it's not clear
 141  * which one but the result is the same) clock. The vendor driver additionally
 142  * has the following comment about: "optimise HPLL VCO 2.97GHz performance".
 143  */
 144 static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = {
 145         { .reg = HHI_VID_PLL_CNTL2,     .def = 0x69c84000 },
 146         { .reg = HHI_VID_PLL_CNTL3,     .def = 0x8a46c023 },
 147         { .reg = HHI_VID_PLL_CNTL4,     .def = 0x4123b100 },
 148         { .reg = HHI_VID_PLL_CNTL5,     .def = 0x00012385 },
 149         { .reg = HHI_VID2_PLL_CNTL2,    .def = 0x0430a800 },
 150 };
 151
 152 static const struct pll_params_table hdmi_pll_params_table[] = {
 153         PLL_PARAMS(40, 1),
 154         PLL_PARAMS(42, 1),
 155         PLL_PARAMS(44, 1),
 156         PLL_PARAMS(45, 1),
 157         PLL_PARAMS(49, 1),
 158         PLL_PARAMS(52, 1),
 159         PLL_PARAMS(54, 1),
 160         PLL_PARAMS(56, 1),
 161         PLL_PARAMS(59, 1),
 162         PLL_PARAMS(60, 1),
 163         PLL_PARAMS(61, 1),
 164         PLL_PARAMS(62, 1),
 165         PLL_PARAMS(64, 1),
 166         PLL_PARAMS(66, 1),
 167         PLL_PARAMS(68, 1),
 168         PLL_PARAMS(71, 1),
 169         PLL_PARAMS(82, 1),
 170         { /* sentinel */ }
 171 };
 172
 173 static struct clk_regmap meson8b_hdmi_pll_dco = {
 174         .data = &(struct meson_clk_pll_data){
 175                 .en = {
 176                         .reg_off = HHI_VID_PLL_CNTL,
 177                         .shift   = 30,
 178                         .width   = 1,
 179                 },
 180                 .m = {
 181                         .reg_off = HHI_VID_PLL_CNTL,
 182                         .shift   = 0,
 183                         .width   = 9,
 184                 },
 185                 .n = {
 186                         .reg_off = HHI_VID_PLL_CNTL,
 187                         .shift   = 10,
 188                         .width   = 5,
 189                 },
 190                 .frac = {
 191                         .reg_off = HHI_VID_PLL_CNTL2,
 192                         .shift   = 0,
 193                         .width   = 12,
 194                 },
 195                 .l = {
 196                         .reg_off = HHI_VID_PLL_CNTL,
 197                         .shift   = 31,
 198                         .width   = 1,
 199                 },
 200                 .rst = {
 201                         .reg_off = HHI_VID_PLL_CNTL,
 202                         .shift   = 29,
 203                         .width   = 1,
 204                 },
 205                 .table = hdmi_pll_params_table,
 206                 .init_regs = meson8b_hdmi_pll_init_regs,
 207                 .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs),
 208         },
 209         .hw.init = &(struct clk_init_data){
 210                 /* sometimes also called "HPLL" or "HPLL PLL" */
 211                 .name = "hdmi_pll_dco",
 212                 .ops = &meson_clk_pll_ops,
 213                 .parent_hws = (const struct clk_hw *[]) {
 214                         &hdmi_pll_dco_in.hw
 215                 },
 216                 .num_parents = 1,
 217         },
 218 };
 219
 220 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
 221         .data = &(struct clk_regmap_div_data){
 222                 .offset = HHI_VID_PLL_CNTL,
 223                 .shift = 16,
 224                 .width = 2,
 225                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 226         },
 227         .hw.init = &(struct clk_init_data){
 228                 .name = "hdmi_pll_lvds_out",
 229                 .ops = &clk_regmap_divider_ops,
 230                 .parent_hws = (const struct clk_hw *[]) {
 231                         &meson8b_hdmi_pll_dco.hw
 232                 },
 233                 .num_parents = 1,
 234                 .flags = CLK_SET_RATE_PARENT,
 235         },
 236 };
 237
 238 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
 239         .data = &(struct clk_regmap_div_data){
 240                 .offset = HHI_VID_PLL_CNTL,
 241                 .shift = 18,
 242                 .width = 2,
 243                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 244         },
 245         .hw.init = &(struct clk_init_data){
 246                 .name = "hdmi_pll_hdmi_out",
 247                 .ops = &clk_regmap_divider_ops,
 248                 .parent_hws = (const struct clk_hw *[]) {
 249                         &meson8b_hdmi_pll_dco.hw
 250                 },
 251                 .num_parents = 1,
 252                 .flags = CLK_SET_RATE_PARENT,
 253         },
 254 };
 255
 256 static struct clk_regmap meson8b_sys_pll_dco = {
 257         .data = &(struct meson_clk_pll_data){
 258                 .en = {
 259                         .reg_off = HHI_SYS_PLL_CNTL,
 260                         .shift   = 30,
 261                         .width   = 1,
 262                 },
 263                 .m = {
 264                         .reg_off = HHI_SYS_PLL_CNTL,
 265                         .shift   = 0,
 266                         .width   = 9,
 267                 },
 268                 .n = {
 269                         .reg_off = HHI_SYS_PLL_CNTL,
 270                         .shift   = 9,
 271                         .width   = 5,
 272                 },
 273                 .l = {
 274                         .reg_off = HHI_SYS_PLL_CNTL,
 275                         .shift   = 31,
 276                         .width   = 1,
 277                 },
 278                 .rst = {
 279                         .reg_off = HHI_SYS_PLL_CNTL,
 280                         .shift   = 29,
 281                         .width   = 1,
 282                 },
 283                 .table = sys_pll_params_table,
 284         },
 285         .hw.init = &(struct clk_init_data){
 286                 .name = "sys_pll_dco",
 287                 .ops = &meson_clk_pll_ops,
 288                 .parent_data = &(const struct clk_parent_data) {
 289                         .fw_name = "xtal",
 290                         .name = "xtal",
 291                         .index = -1,
 292                 },
 293                 .num_parents = 1,
 294         },
 295 };
 296
 297 static struct clk_regmap meson8b_sys_pll = {
 298         .data = &(struct clk_regmap_div_data){
 299                 .offset = HHI_SYS_PLL_CNTL,
 300                 .shift = 16,
 301                 .width = 2,
 302                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 303         },
 304         .hw.init = &(struct clk_init_data){
 305                 .name = "sys_pll",
 306                 .ops = &clk_regmap_divider_ops,
 307                 .parent_hws = (const struct clk_hw *[]) {
 308                         &meson8b_sys_pll_dco.hw
 309                 },
 310                 .num_parents = 1,
 311                 .flags = CLK_SET_RATE_PARENT,
 312         },
 313 };
 314
 315 static struct clk_fixed_factor meson8b_fclk_div2_div = {
 316         .mult = 1,
 317         .div = 2,
 318         .hw.init = &(struct clk_init_data){
 319                 .name = "fclk_div2_div",
 320                 .ops = &clk_fixed_factor_ops,
 321                 .parent_hws = (const struct clk_hw *[]) {
 322                         &meson8b_fixed_pll.hw
 323                 },
 324                 .num_parents = 1,
 325         },
 326 };
 327
 328 static struct clk_regmap meson8b_fclk_div2 = {
 329         .data = &(struct clk_regmap_gate_data){
 330                 .offset = HHI_MPLL_CNTL6,
 331                 .bit_idx = 27,
 332         },
 333         .hw.init = &(struct clk_init_data){
 334                 .name = "fclk_div2",
 335                 .ops = &clk_regmap_gate_ops,
 336                 .parent_hws = (const struct clk_hw *[]) {
 337                         &meson8b_fclk_div2_div.hw
 338                 },
 339                 .num_parents = 1,
 340         },
 341 };
 342
 343 static struct clk_fixed_factor meson8b_fclk_div3_div = {
 344         .mult = 1,
 345         .div = 3,
 346         .hw.init = &(struct clk_init_data){
 347                 .name = "fclk_div3_div",
 348                 .ops = &clk_fixed_factor_ops,
 349                 .parent_hws = (const struct clk_hw *[]) {
 350                         &meson8b_fixed_pll.hw
 351                 },
 352                 .num_parents = 1,
 353         },
 354 };
 355
 356 static struct clk_regmap meson8b_fclk_div3 = {
 357         .data = &(struct clk_regmap_gate_data){
 358                 .offset = HHI_MPLL_CNTL6,
 359                 .bit_idx = 28,
 360         },
 361         .hw.init = &(struct clk_init_data){
 362                 .name = "fclk_div3",
 363                 .ops = &clk_regmap_gate_ops,
 364                 .parent_hws = (const struct clk_hw *[]) {
 365                         &meson8b_fclk_div3_div.hw
 366                 },
 367                 .num_parents = 1,
 368         },
 369 };
 370
 371 static struct clk_fixed_factor meson8b_fclk_div4_div = {
 372         .mult = 1,
 373         .div = 4,
 374         .hw.init = &(struct clk_init_data){
 375                 .name = "fclk_div4_div",
 376                 .ops = &clk_fixed_factor_ops,
 377                 .parent_hws = (const struct clk_hw *[]) {
 378                         &meson8b_fixed_pll.hw
 379                 },
 380                 .num_parents = 1,
 381         },
 382 };
 383
 384 static struct clk_regmap meson8b_fclk_div4 = {
 385         .data = &(struct clk_regmap_gate_data){
 386                 .offset = HHI_MPLL_CNTL6,
 387                 .bit_idx = 29,
 388         },
 389         .hw.init = &(struct clk_init_data){
 390                 .name = "fclk_div4",
 391                 .ops = &clk_regmap_gate_ops,
 392                 .parent_hws = (const struct clk_hw *[]) {
 393                         &meson8b_fclk_div4_div.hw
 394                 },
 395                 .num_parents = 1,
 396         },
 397 };
 398
 399 static struct clk_fixed_factor meson8b_fclk_div5_div = {
 400         .mult = 1,
 401         .div = 5,
 402         .hw.init = &(struct clk_init_data){
 403                 .name = "fclk_div5_div",
 404                 .ops = &clk_fixed_factor_ops,
 405                 .parent_hws = (const struct clk_hw *[]) {
 406                         &meson8b_fixed_pll.hw
 407                 },
 408                 .num_parents = 1,
 409         },
 410 };
 411
 412 static struct clk_regmap meson8b_fclk_div5 = {
 413         .data = &(struct clk_regmap_gate_data){
 414                 .offset = HHI_MPLL_CNTL6,
 415                 .bit_idx = 30,
 416         },
 417         .hw.init = &(struct clk_init_data){
 418                 .name = "fclk_div5",
 419                 .ops = &clk_regmap_gate_ops,
 420                 .parent_hws = (const struct clk_hw *[]) {
 421                         &meson8b_fclk_div5_div.hw
 422                 },
 423                 .num_parents = 1,
 424         },
 425 };
 426
 427 static struct clk_fixed_factor meson8b_fclk_div7_div = {
 428         .mult = 1,
 429         .div = 7,
 430         .hw.init = &(struct clk_init_data){
 431                 .name = "fclk_div7_div",
 432                 .ops = &clk_fixed_factor_ops,
 433                 .parent_hws = (const struct clk_hw *[]) {
 434                         &meson8b_fixed_pll.hw
 435                 },
 436                 .num_parents = 1,
 437         },
 438 };
 439
 440 static struct clk_regmap meson8b_fclk_div7 = {
 441         .data = &(struct clk_regmap_gate_data){
 442                 .offset = HHI_MPLL_CNTL6,
 443                 .bit_idx = 31,
 444         },
 445         .hw.init = &(struct clk_init_data){
 446                 .name = "fclk_div7",
 447                 .ops = &clk_regmap_gate_ops,
 448                 .parent_hws = (const struct clk_hw *[]) {
 449                         &meson8b_fclk_div7_div.hw
 450                 },
 451                 .num_parents = 1,
 452         },
 453 };
 454
 455 static struct clk_regmap meson8b_mpll_prediv = {
 456         .data = &(struct clk_regmap_div_data){
 457                 .offset = HHI_MPLL_CNTL5,
 458                 .shift = 12,
 459                 .width = 1,
 460         },
 461         .hw.init = &(struct clk_init_data){
 462                 .name = "mpll_prediv",
 463                 .ops = &clk_regmap_divider_ro_ops,
 464                 .parent_hws = (const struct clk_hw *[]) {
 465                         &meson8b_fixed_pll.hw
 466                 },
 467                 .num_parents = 1,
 468         },
 469 };
 470
 471 static struct clk_regmap meson8b_mpll0_div = {
 472         .data = &(struct meson_clk_mpll_data){
 473                 .sdm = {
 474                         .reg_off = HHI_MPLL_CNTL7,
 475                         .shift   = 0,
 476                         .width   = 14,
 477                 },
 478                 .sdm_en = {
 479                         .reg_off = HHI_MPLL_CNTL7,
 480                         .shift   = 15,
 481                         .width   = 1,
 482                 },
 483                 .n2 = {
 484                         .reg_off = HHI_MPLL_CNTL7,
 485                         .shift   = 16,
 486                         .width   = 9,
 487                 },
 488                 .ssen = {
 489                         .reg_off = HHI_MPLL_CNTL,
 490                         .shift   = 25,
 491                         .width   = 1,
 492                 },
 493         },
 494         .hw.init = &(struct clk_init_data){
 495                 .name = "mpll0_div",
 496                 .ops = &meson_clk_mpll_ops,
 497                 .parent_hws = (const struct clk_hw *[]) {
 498                         &meson8b_mpll_prediv.hw
 499                 },
 500                 .num_parents = 1,
 501         },
 502 };
 503
 504 static struct clk_regmap meson8b_mpll0 = {
 505         .data = &(struct clk_regmap_gate_data){
 506                 .offset = HHI_MPLL_CNTL7,
 507                 .bit_idx = 14,
 508         },
 509         .hw.init = &(struct clk_init_data){
 510                 .name = "mpll0",
 511                 .ops = &clk_regmap_gate_ops,
 512                 .parent_hws = (const struct clk_hw *[]) {
 513                         &meson8b_mpll0_div.hw
 514                 },
 515                 .num_parents = 1,
 516                 .flags = CLK_SET_RATE_PARENT,
 517         },
 518 };
 519
 520 static struct clk_regmap meson8b_mpll1_div = {
 521         .data = &(struct meson_clk_mpll_data){
 522                 .sdm = {
 523                         .reg_off = HHI_MPLL_CNTL8,
 524                         .shift   = 0,
 525                         .width   = 14,
 526                 },
 527                 .sdm_en = {
 528                         .reg_off = HHI_MPLL_CNTL8,
 529                         .shift   = 15,
 530                         .width   = 1,
 531                 },
 532                 .n2 = {
 533                         .reg_off = HHI_MPLL_CNTL8,
 534                         .shift   = 16,
 535                         .width   = 9,
 536                 },
 537         },
 538         .hw.init = &(struct clk_init_data){
 539                 .name = "mpll1_div",
 540                 .ops = &meson_clk_mpll_ops,
 541                 .parent_hws = (const struct clk_hw *[]) {
 542                         &meson8b_mpll_prediv.hw
 543                 },
 544                 .num_parents = 1,
 545         },
 546 };
 547
 548 static struct clk_regmap meson8b_mpll1 = {
 549         .data = &(struct clk_regmap_gate_data){
 550                 .offset = HHI_MPLL_CNTL8,
 551                 .bit_idx = 14,
 552         },
 553         .hw.init = &(struct clk_init_data){
 554                 .name = "mpll1",
 555                 .ops = &clk_regmap_gate_ops,
 556                 .parent_hws = (const struct clk_hw *[]) {
 557                         &meson8b_mpll1_div.hw
 558                 },
 559                 .num_parents = 1,
 560                 .flags = CLK_SET_RATE_PARENT,
 561         },
 562 };
 563
 564 static struct clk_regmap meson8b_mpll2_div = {
 565         .data = &(struct meson_clk_mpll_data){
 566                 .sdm = {
 567                         .reg_off = HHI_MPLL_CNTL9,
 568                         .shift   = 0,
 569                         .width   = 14,
 570                 },
 571                 .sdm_en = {
 572                         .reg_off = HHI_MPLL_CNTL9,
 573                         .shift   = 15,
 574                         .width   = 1,
 575                 },
 576                 .n2 = {
 577                         .reg_off = HHI_MPLL_CNTL9,
 578                         .shift   = 16,
 579                         .width   = 9,
 580                 },
 581         },
 582         .hw.init = &(struct clk_init_data){
 583                 .name = "mpll2_div",
 584                 .ops = &meson_clk_mpll_ops,
 585                 .parent_hws = (const struct clk_hw *[]) {
 586                         &meson8b_mpll_prediv.hw
 587                 },
 588                 .num_parents = 1,
 589         },
 590 };
 591
 592 static struct clk_regmap meson8b_mpll2 = {
 593         .data = &(struct clk_regmap_gate_data){
 594                 .offset = HHI_MPLL_CNTL9,
 595                 .bit_idx = 14,
 596         },
 597         .hw.init = &(struct clk_init_data){
 598                 .name = "mpll2",
 599                 .ops = &clk_regmap_gate_ops,
 600                 .parent_hws = (const struct clk_hw *[]) {
 601                         &meson8b_mpll2_div.hw
 602                 },
 603                 .num_parents = 1,
 604                 .flags = CLK_SET_RATE_PARENT,
 605         },
 606 };
 607
 608 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 609 static struct clk_regmap meson8b_mpeg_clk_sel = {
 610         .data = &(struct clk_regmap_mux_data){
 611                 .offset = HHI_MPEG_CLK_CNTL,
 612                 .mask = 0x7,
 613                 .shift = 12,
 614                 .table = mux_table_clk81,
 615         },
 616         .hw.init = &(struct clk_init_data){
 617                 .name = "mpeg_clk_sel",
 618                 .ops = &clk_regmap_mux_ro_ops,
 619                 /*
 620                  * FIXME bits 14:12 selects from 8 possible parents:
 621                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 622                  * fclk_div4, fclk_div3, fclk_div5
 623                  */
 624                 .parent_hws = (const struct clk_hw *[]) {
 625                         &meson8b_fclk_div3.hw,
 626                         &meson8b_fclk_div4.hw,
 627                         &meson8b_fclk_div5.hw,
 628                 },
 629                 .num_parents = 3,
 630         },
 631 };
 632
 633 static struct clk_regmap meson8b_mpeg_clk_div = {
 634         .data = &(struct clk_regmap_div_data){
 635                 .offset = HHI_MPEG_CLK_CNTL,
 636                 .shift = 0,
 637                 .width = 7,
 638         },
 639         .hw.init = &(struct clk_init_data){
 640                 .name = "mpeg_clk_div",
 641                 .ops = &clk_regmap_divider_ro_ops,
 642                 .parent_hws = (const struct clk_hw *[]) {
 643                         &meson8b_mpeg_clk_sel.hw
 644                 },
 645                 .num_parents = 1,
 646         },
 647 };
 648
 649 static struct clk_regmap meson8b_clk81 = {
 650         .data = &(struct clk_regmap_gate_data){
 651                 .offset = HHI_MPEG_CLK_CNTL,
 652                 .bit_idx = 7,
 653         },
 654         .hw.init = &(struct clk_init_data){
 655                 .name = "clk81",
 656                 .ops = &clk_regmap_gate_ops,
 657                 .parent_hws = (const struct clk_hw *[]) {
 658                         &meson8b_mpeg_clk_div.hw
 659                 },
 660                 .num_parents = 1,
 661                 .flags = CLK_IS_CRITICAL,
 662         },
 663 };
 664
 665 static struct clk_regmap meson8b_cpu_in_sel = {
 666         .data = &(struct clk_regmap_mux_data){
 667                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 668                 .mask = 0x1,
 669                 .shift = 0,
 670         },
 671         .hw.init = &(struct clk_init_data){
 672                 .name = "cpu_in_sel",
 673                 .ops = &clk_regmap_mux_ops,
 674                 .parent_data = (const struct clk_parent_data[]) {
 675                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 676                         { .hw = &meson8b_sys_pll.hw, },
 677                 },
 678                 .num_parents = 2,
 679                 .flags = (CLK_SET_RATE_PARENT |
 680                           CLK_SET_RATE_NO_REPARENT),
 681         },
 682 };
 683
 684 static struct clk_fixed_factor meson8b_cpu_in_div2 = {
 685         .mult = 1,
 686         .div = 2,
 687         .hw.init = &(struct clk_init_data){
 688                 .name = "cpu_in_div2",
 689                 .ops = &clk_fixed_factor_ops,
 690                 .parent_hws = (const struct clk_hw *[]) {
 691                         &meson8b_cpu_in_sel.hw
 692                 },
 693                 .num_parents = 1,
 694                 .flags = CLK_SET_RATE_PARENT,
 695         },
 696 };
 697
 698 static struct clk_fixed_factor meson8b_cpu_in_div3 = {
 699         .mult = 1,
 700         .div = 3,
 701         .hw.init = &(struct clk_init_data){
 702                 .name = "cpu_in_div3",
 703                 .ops = &clk_fixed_factor_ops,
 704                 .parent_hws = (const struct clk_hw *[]) {
 705                         &meson8b_cpu_in_sel.hw
 706                 },
 707                 .num_parents = 1,
 708                 .flags = CLK_SET_RATE_PARENT,
 709         },
 710 };
 711
 712 static const struct clk_div_table cpu_scale_table[] = {
 713         { .val = 1, .div = 4 },
 714         { .val = 2, .div = 6 },
 715         { .val = 3, .div = 8 },
 716         { .val = 4, .div = 10 },
 717         { .val = 5, .div = 12 },
 718         { .val = 6, .div = 14 },
 719         { .val = 7, .div = 16 },
 720         { .val = 8, .div = 18 },
 721         { /* sentinel */ },
 722 };
 723
 724 static struct clk_regmap meson8b_cpu_scale_div = {
 725         .data = &(struct clk_regmap_div_data){
 726                 .offset =  HHI_SYS_CPU_CLK_CNTL1,
 727                 .shift = 20,
 728                 .width = 10,
 729                 .table = cpu_scale_table,
 730                 .flags = CLK_DIVIDER_ALLOW_ZERO,
 731         },
 732         .hw.init = &(struct clk_init_data){
 733                 .name = "cpu_scale_div",
 734                 .ops = &clk_regmap_divider_ops,
 735                 .parent_hws = (const struct clk_hw *[]) {
 736                         &meson8b_cpu_in_sel.hw
 737                 },
 738                 .num_parents = 1,
 739                 .flags = CLK_SET_RATE_PARENT,
 740         },
 741 };
 742
 743 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
 744 static struct clk_regmap meson8b_cpu_scale_out_sel = {
 745         .data = &(struct clk_regmap_mux_data){
 746                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 747                 .mask = 0x3,
 748                 .shift = 2,
 749                 .table = mux_table_cpu_scale_out_sel,
 750         },
 751         .hw.init = &(struct clk_init_data){
 752                 .name = "cpu_scale_out_sel",
 753                 .ops = &clk_regmap_mux_ops,
 754                 /*
 755                  * NOTE: We are skipping the parent with value 0x2 (which is
 756                  * meson8b_cpu_in_div3) because it results in a duty cycle of
 757                  * 33% which makes the system unstable and can result in a
 758                  * lockup of the whole system.
 759                  */
 760                 .parent_hws = (const struct clk_hw *[]) {
 761                         &meson8b_cpu_in_sel.hw,
 762                         &meson8b_cpu_in_div2.hw,
 763                         &meson8b_cpu_scale_div.hw,
 764                 },
 765                 .num_parents = 3,
 766                 .flags = CLK_SET_RATE_PARENT,
 767         },
 768 };
 769
 770 static struct clk_regmap meson8b_cpu_clk = {
 771         .data = &(struct clk_regmap_mux_data){
 772                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 773                 .mask = 0x1,
 774                 .shift = 7,
 775         },
 776         .hw.init = &(struct clk_init_data){
 777                 .name = "cpu_clk",
 778                 .ops = &clk_regmap_mux_ops,
 779                 .parent_data = (const struct clk_parent_data[]) {
 780                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 781                         { .hw = &meson8b_cpu_scale_out_sel.hw, },
 782                 },
 783                 .num_parents = 2,
 784                 .flags = (CLK_SET_RATE_PARENT |
 785                           CLK_SET_RATE_NO_REPARENT |
 786                           CLK_IS_CRITICAL),
 787         },
 788 };
 789
 790 static struct clk_regmap meson8b_nand_clk_sel = {
 791         .data = &(struct clk_regmap_mux_data){
 792                 .offset = HHI_NAND_CLK_CNTL,
 793                 .mask = 0x7,
 794                 .shift = 9,
 795                 .flags = CLK_MUX_ROUND_CLOSEST,
 796         },
 797         .hw.init = &(struct clk_init_data){
 798                 .name = "nand_clk_sel",
 799                 .ops = &clk_regmap_mux_ops,
 800                 /* FIXME all other parents are unknown: */
 801                 .parent_data = (const struct clk_parent_data[]) {
 802                         { .hw = &meson8b_fclk_div4.hw, },
 803                         { .hw = &meson8b_fclk_div3.hw, },
 804                         { .hw = &meson8b_fclk_div5.hw, },
 805                         { .hw = &meson8b_fclk_div7.hw, },
 806                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 807                 },
 808                 .num_parents = 5,
 809                 .flags = CLK_SET_RATE_PARENT,
 810         },
 811 };
 812
 813 static struct clk_regmap meson8b_nand_clk_div = {
 814         .data = &(struct clk_regmap_div_data){
 815                 .offset =  HHI_NAND_CLK_CNTL,
 816                 .shift = 0,
 817                 .width = 7,
 818                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 819         },
 820         .hw.init = &(struct clk_init_data){
 821                 .name = "nand_clk_div",
 822                 .ops = &clk_regmap_divider_ops,
 823                 .parent_hws = (const struct clk_hw *[]) {
 824                         &meson8b_nand_clk_sel.hw
 825                 },
 826                 .num_parents = 1,
 827                 .flags = CLK_SET_RATE_PARENT,
 828         },
 829 };
 830
 831 static struct clk_regmap meson8b_nand_clk_gate = {
 832         .data = &(struct clk_regmap_gate_data){
 833                 .offset = HHI_NAND_CLK_CNTL,
 834                 .bit_idx = 8,
 835         },
 836         .hw.init = &(struct clk_init_data){
 837                 .name = "nand_clk_gate",
 838                 .ops = &clk_regmap_gate_ops,
 839                 .parent_hws = (const struct clk_hw *[]) {
 840                         &meson8b_nand_clk_div.hw
 841                 },
 842                 .num_parents = 1,
 843                 .flags = CLK_SET_RATE_PARENT,
 844         },
 845 };
 846
 847 static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
 848         .mult = 1,
 849         .div = 2,
 850         .hw.init = &(struct clk_init_data){
 851                 .name = "cpu_clk_div2",
 852                 .ops = &clk_fixed_factor_ops,
 853                 .parent_hws = (const struct clk_hw *[]) {
 854                         &meson8b_cpu_clk.hw
 855                 },
 856                 .num_parents = 1,
 857         },
 858 };
 859
 860 static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
 861         .mult = 1,
 862         .div = 3,
 863         .hw.init = &(struct clk_init_data){
 864                 .name = "cpu_clk_div3",
 865                 .ops = &clk_fixed_factor_ops,
 866                 .parent_hws = (const struct clk_hw *[]) {
 867                         &meson8b_cpu_clk.hw
 868                 },
 869                 .num_parents = 1,
 870         },
 871 };
 872
 873 static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
 874         .mult = 1,
 875         .div = 4,
 876         .hw.init = &(struct clk_init_data){
 877                 .name = "cpu_clk_div4",
 878                 .ops = &clk_fixed_factor_ops,
 879                 .parent_hws = (const struct clk_hw *[]) {
 880                         &meson8b_cpu_clk.hw
 881                 },
 882                 .num_parents = 1,
 883         },
 884 };
 885
 886 static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
 887         .mult = 1,
 888         .div = 5,
 889         .hw.init = &(struct clk_init_data){
 890                 .name = "cpu_clk_div5",
 891                 .ops = &clk_fixed_factor_ops,
 892                 .parent_hws = (const struct clk_hw *[]) {
 893                         &meson8b_cpu_clk.hw
 894                 },
 895                 .num_parents = 1,
 896         },
 897 };
 898
 899 static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
 900         .mult = 1,
 901         .div = 6,
 902         .hw.init = &(struct clk_init_data){
 903                 .name = "cpu_clk_div6",
 904                 .ops = &clk_fixed_factor_ops,
 905                 .parent_hws = (const struct clk_hw *[]) {
 906                         &meson8b_cpu_clk.hw
 907                 },
 908                 .num_parents = 1,
 909         },
 910 };
 911
 912 static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
 913         .mult = 1,
 914         .div = 7,
 915         .hw.init = &(struct clk_init_data){
 916                 .name = "cpu_clk_div7",
 917                 .ops = &clk_fixed_factor_ops,
 918                 .parent_hws = (const struct clk_hw *[]) {
 919                         &meson8b_cpu_clk.hw
 920                 },
 921                 .num_parents = 1,
 922         },
 923 };
 924
 925 static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
 926         .mult = 1,
 927         .div = 8,
 928         .hw.init = &(struct clk_init_data){
 929                 .name = "cpu_clk_div8",
 930                 .ops = &clk_fixed_factor_ops,
 931                 .parent_hws = (const struct clk_hw *[]) {
 932                         &meson8b_cpu_clk.hw
 933                 },
 934                 .num_parents = 1,
 935         },
 936 };
 937
 938 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
 939 static struct clk_regmap meson8b_apb_clk_sel = {
 940         .data = &(struct clk_regmap_mux_data){
 941                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 942                 .mask = 0x7,
 943                 .shift = 3,
 944                 .table = mux_table_apb,
 945         },
 946         .hw.init = &(struct clk_init_data){
 947                 .name = "apb_clk_sel",
 948                 .ops = &clk_regmap_mux_ops,
 949                 .parent_hws = (const struct clk_hw *[]) {
 950                         &meson8b_cpu_clk_div2.hw,
 951                         &meson8b_cpu_clk_div3.hw,
 952                         &meson8b_cpu_clk_div4.hw,
 953                         &meson8b_cpu_clk_div5.hw,
 954                         &meson8b_cpu_clk_div6.hw,
 955                         &meson8b_cpu_clk_div7.hw,
 956                         &meson8b_cpu_clk_div8.hw,
 957                 },
 958                 .num_parents = 7,
 959         },
 960 };
 961
 962 static struct clk_regmap meson8b_apb_clk_gate = {
 963         .data = &(struct clk_regmap_gate_data){
 964                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 965                 .bit_idx = 16,
 966                 .flags = CLK_GATE_SET_TO_DISABLE,
 967         },
 968         .hw.init = &(struct clk_init_data){
 969                 .name = "apb_clk_dis",
 970                 .ops = &clk_regmap_gate_ro_ops,
 971                 .parent_hws = (const struct clk_hw *[]) {
 972                         &meson8b_apb_clk_sel.hw
 973                 },
 974                 .num_parents = 1,
 975                 .flags = CLK_SET_RATE_PARENT,
 976         },
 977 };
 978
 979 static struct clk_regmap meson8b_periph_clk_sel = {
 980         .data = &(struct clk_regmap_mux_data){
 981                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 982                 .mask = 0x7,
 983                 .shift = 6,
 984         },
 985         .hw.init = &(struct clk_init_data){
 986                 .name = "periph_clk_sel",
 987                 .ops = &clk_regmap_mux_ops,
 988                 .parent_hws = (const struct clk_hw *[]) {
 989                         &meson8b_cpu_clk_div2.hw,
 990                         &meson8b_cpu_clk_div3.hw,
 991                         &meson8b_cpu_clk_div4.hw,
 992                         &meson8b_cpu_clk_div5.hw,
 993                         &meson8b_cpu_clk_div6.hw,
 994                         &meson8b_cpu_clk_div7.hw,
 995                         &meson8b_cpu_clk_div8.hw,
 996                 },
 997                 .num_parents = 7,
 998         },
 999 };
1000
1001 static struct clk_regmap meson8b_periph_clk_gate = {
1002         .data = &(struct clk_regmap_gate_data){
1003                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1004                 .bit_idx = 17,
1005                 .flags = CLK_GATE_SET_TO_DISABLE,
1006         },
1007         .hw.init = &(struct clk_init_data){
1008                 .name = "periph_clk_dis",
1009                 .ops = &clk_regmap_gate_ro_ops,
1010                 .parent_hws = (const struct clk_hw *[]) {
1011                         &meson8b_periph_clk_sel.hw
1012                 },
1013                 .num_parents = 1,
1014                 .flags = CLK_SET_RATE_PARENT,
1015         },
1016 };
1017
1018 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
1019 static struct clk_regmap meson8b_axi_clk_sel = {
1020         .data = &(struct clk_regmap_mux_data){
1021                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1022                 .mask = 0x7,
1023                 .shift = 9,
1024                 .table = mux_table_axi,
1025         },
1026         .hw.init = &(struct clk_init_data){
1027                 .name = "axi_clk_sel",
1028                 .ops = &clk_regmap_mux_ops,
1029                 .parent_hws = (const struct clk_hw *[]) {
1030                         &meson8b_cpu_clk_div2.hw,
1031                         &meson8b_cpu_clk_div3.hw,
1032                         &meson8b_cpu_clk_div4.hw,
1033                         &meson8b_cpu_clk_div5.hw,
1034                         &meson8b_cpu_clk_div6.hw,
1035                         &meson8b_cpu_clk_div7.hw,
1036                         &meson8b_cpu_clk_div8.hw,
1037                 },
1038                 .num_parents = 7,
1039         },
1040 };
1041
1042 static struct clk_regmap meson8b_axi_clk_gate = {
1043         .data = &(struct clk_regmap_gate_data){
1044                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1045                 .bit_idx = 18,
1046                 .flags = CLK_GATE_SET_TO_DISABLE,
1047         },
1048         .hw.init = &(struct clk_init_data){
1049                 .name = "axi_clk_dis",
1050                 .ops = &clk_regmap_gate_ro_ops,
1051                 .parent_hws = (const struct clk_hw *[]) {
1052                         &meson8b_axi_clk_sel.hw
1053                 },
1054                 .num_parents = 1,
1055                 .flags = CLK_SET_RATE_PARENT,
1056         },
1057 };
1058
1059 static struct clk_regmap meson8b_l2_dram_clk_sel = {
1060         .data = &(struct clk_regmap_mux_data){
1061                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1062                 .mask = 0x7,
1063                 .shift = 12,
1064         },
1065         .hw.init = &(struct clk_init_data){
1066                 .name = "l2_dram_clk_sel",
1067                 .ops = &clk_regmap_mux_ops,
1068                 .parent_hws = (const struct clk_hw *[]) {
1069                         &meson8b_cpu_clk_div2.hw,
1070                         &meson8b_cpu_clk_div3.hw,
1071                         &meson8b_cpu_clk_div4.hw,
1072                         &meson8b_cpu_clk_div5.hw,
1073                         &meson8b_cpu_clk_div6.hw,
1074                         &meson8b_cpu_clk_div7.hw,
1075                         &meson8b_cpu_clk_div8.hw,
1076                 },
1077                 .num_parents = 7,
1078         },
1079 };
1080
1081 static struct clk_regmap meson8b_l2_dram_clk_gate = {
1082         .data = &(struct clk_regmap_gate_data){
1083                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1084                 .bit_idx = 19,
1085                 .flags = CLK_GATE_SET_TO_DISABLE,
1086         },
1087         .hw.init = &(struct clk_init_data){
1088                 .name = "l2_dram_clk_dis",
1089                 .ops = &clk_regmap_gate_ro_ops,
1090                 .parent_hws = (const struct clk_hw *[]) {
1091                         &meson8b_l2_dram_clk_sel.hw
1092                 },
1093                 .num_parents = 1,
1094                 .flags = CLK_SET_RATE_PARENT,
1095         },
1096 };
1097
1098 /* also called LVDS_CLK_EN */
1099 static struct clk_regmap meson8b_vid_pll_lvds_en = {
1100         .data = &(struct clk_regmap_gate_data){
1101                 .offset = HHI_VID_DIVIDER_CNTL,
1102                 .bit_idx = 11,
1103         },
1104         .hw.init = &(struct clk_init_data){
1105                 .name = "vid_pll_lvds_en",
1106                 .ops = &clk_regmap_gate_ops,
1107                 .parent_hws = (const struct clk_hw *[]) {
1108                         &meson8b_hdmi_pll_lvds_out.hw
1109                 },
1110                 .num_parents = 1,
1111                 .flags = CLK_SET_RATE_PARENT,
1112         },
1113 };
1114
1115 static struct clk_regmap meson8b_vid_pll_in_sel = {
1116         .data = &(struct clk_regmap_mux_data){
1117                 .offset = HHI_VID_DIVIDER_CNTL,
1118                 .mask = 0x1,
1119                 .shift = 15,
1120         },
1121         .hw.init = &(struct clk_init_data){
1122                 .name = "vid_pll_in_sel",
1123                 .ops = &clk_regmap_mux_ops,
1124                 /*
1125                  * TODO: depending on the SoC there is also a second parent:
1126                  * Meson8: unknown
1127                  * Meson8b: hdmi_pll_dco
1128                  * Meson8m2: vid2_pll
1129                  */
1130                 .parent_hws = (const struct clk_hw *[]) {
1131                         &meson8b_vid_pll_lvds_en.hw
1132                 },
1133                 .num_parents = 1,
1134                 .flags = CLK_SET_RATE_PARENT,
1135         },
1136 };
1137
1138 static struct clk_regmap meson8b_vid_pll_in_en = {
1139         .data = &(struct clk_regmap_gate_data){
1140                 .offset = HHI_VID_DIVIDER_CNTL,
1141                 .bit_idx = 16,
1142         },
1143         .hw.init = &(struct clk_init_data){
1144                 .name = "vid_pll_in_en",
1145                 .ops = &clk_regmap_gate_ops,
1146                 .parent_hws = (const struct clk_hw *[]) {
1147                         &meson8b_vid_pll_in_sel.hw
1148                 },
1149                 .num_parents = 1,
1150                 .flags = CLK_SET_RATE_PARENT,
1151         },
1152 };
1153
1154 static struct clk_regmap meson8b_vid_pll_pre_div = {
1155         .data = &(struct clk_regmap_div_data){
1156                 .offset =  HHI_VID_DIVIDER_CNTL,
1157                 .shift = 4,
1158                 .width = 3,
1159         },
1160         .hw.init = &(struct clk_init_data){
1161                 .name = "vid_pll_pre_div",
1162                 .ops = &clk_regmap_divider_ops,
1163                 .parent_hws = (const struct clk_hw *[]) {
1164                         &meson8b_vid_pll_in_en.hw
1165                 },
1166                 .num_parents = 1,
1167                 .flags = CLK_SET_RATE_PARENT,
1168         },
1169 };
1170
1171 static struct clk_regmap meson8b_vid_pll_post_div = {
1172         .data = &(struct clk_regmap_div_data){
1173                 .offset =  HHI_VID_DIVIDER_CNTL,
1174                 .shift = 12,
1175                 .width = 3,
1176         },
1177         .hw.init = &(struct clk_init_data){
1178                 .name = "vid_pll_post_div",
1179                 .ops = &clk_regmap_divider_ops,
1180                 .parent_hws = (const struct clk_hw *[]) {
1181                         &meson8b_vid_pll_pre_div.hw
1182                 },
1183                 .num_parents = 1,
1184                 .flags = CLK_SET_RATE_PARENT,
1185         },
1186 };
1187
1188 static struct clk_regmap meson8b_vid_pll = {
1189         .data = &(struct clk_regmap_mux_data){
1190                 .offset = HHI_VID_DIVIDER_CNTL,
1191                 .mask = 0x3,
1192                 .shift = 8,
1193         },
1194         .hw.init = &(struct clk_init_data){
1195                 .name = "vid_pll",
1196                 .ops = &clk_regmap_mux_ops,
1197                 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
1198                 .parent_hws = (const struct clk_hw *[]) {
1199                         &meson8b_vid_pll_pre_div.hw,
1200                         &meson8b_vid_pll_post_div.hw,
1201                 },
1202                 .num_parents = 2,
1203                 .flags = CLK_SET_RATE_PARENT,
1204         },
1205 };
1206
1207 static struct clk_regmap meson8b_vid_pll_final_div = {
1208         .data = &(struct clk_regmap_div_data){
1209                 .offset =  HHI_VID_CLK_DIV,
1210                 .shift = 0,
1211                 .width = 8,
1212         },
1213         .hw.init = &(struct clk_init_data){
1214                 .name = "vid_pll_final_div",
1215                 .ops = &clk_regmap_divider_ops,
1216                 .parent_hws = (const struct clk_hw *[]) {
1217                         &meson8b_vid_pll.hw
1218                 },
1219                 .num_parents = 1,
1220                 .flags = CLK_SET_RATE_PARENT,
1221         },
1222 };
1223
1224 static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
1225         &meson8b_vid_pll_final_div.hw,
1226         &meson8b_fclk_div4.hw,
1227         &meson8b_fclk_div3.hw,
1228         &meson8b_fclk_div5.hw,
1229         &meson8b_vid_pll_final_div.hw,
1230         &meson8b_fclk_div7.hw,
1231         &meson8b_mpll1.hw,
1232 };
1233
1234 static struct clk_regmap meson8b_vclk_in_sel = {
1235         .data = &(struct clk_regmap_mux_data){
1236                 .offset = HHI_VID_CLK_CNTL,
1237                 .mask = 0x7,
1238                 .shift = 16,
1239         },
1240         .hw.init = &(struct clk_init_data){
1241                 .name = "vclk_in_sel",
1242                 .ops = &clk_regmap_mux_ops,
1243                 .parent_hws = meson8b_vclk_mux_parent_hws,
1244                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1245                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1246         },
1247 };
1248
1249 static struct clk_regmap meson8b_vclk_in_en = {
1250         .data = &(struct clk_regmap_gate_data){
1251                 .offset = HHI_VID_CLK_DIV,
1252                 .bit_idx = 16,
1253         },
1254         .hw.init = &(struct clk_init_data){
1255                 .name = "vclk_in_en",
1256                 .ops = &clk_regmap_gate_ops,
1257                 .parent_hws = (const struct clk_hw *[]) {
1258                         &meson8b_vclk_in_sel.hw
1259                 },
1260                 .num_parents = 1,
1261                 .flags = CLK_SET_RATE_PARENT,
1262         },
1263 };
1264
1265 static struct clk_regmap meson8b_vclk_en = {
1266         .data = &(struct clk_regmap_gate_data){
1267                 .offset = HHI_VID_CLK_CNTL,
1268                 .bit_idx = 19,
1269         },
1270         .hw.init = &(struct clk_init_data){
1271                 .name = "vclk_en",
1272                 .ops = &clk_regmap_gate_ops,
1273                 .parent_hws = (const struct clk_hw *[]) {
1274                         &meson8b_vclk_in_en.hw
1275                 },
1276                 .num_parents = 1,
1277                 .flags = CLK_SET_RATE_PARENT,
1278         },
1279 };
1280
1281 static struct clk_regmap meson8b_vclk_div1_gate = {
1282         .data = &(struct clk_regmap_gate_data){
1283                 .offset = HHI_VID_CLK_CNTL,
1284                 .bit_idx = 0,
1285         },
1286         .hw.init = &(struct clk_init_data){
1287                 .name = "vclk_div1_en",
1288                 .ops = &clk_regmap_gate_ops,
1289                 .parent_hws = (const struct clk_hw *[]) {
1290                         &meson8b_vclk_en.hw
1291                 },
1292                 .num_parents = 1,
1293                 .flags = CLK_SET_RATE_PARENT,
1294         },
1295 };
1296
1297 static struct clk_fixed_factor meson8b_vclk_div2_div = {
1298         .mult = 1,
1299         .div = 2,
1300         .hw.init = &(struct clk_init_data){
1301                 .name = "vclk_div2",
1302                 .ops = &clk_fixed_factor_ops,
1303                 .parent_hws = (const struct clk_hw *[]) {
1304                         &meson8b_vclk_en.hw
1305                 },
1306                 .num_parents = 1,
1307                 .flags = CLK_SET_RATE_PARENT,
1308         }
1309 };
1310
1311 static struct clk_regmap meson8b_vclk_div2_div_gate = {
1312         .data = &(struct clk_regmap_gate_data){
1313                 .offset = HHI_VID_CLK_CNTL,
1314                 .bit_idx = 1,
1315         },
1316         .hw.init = &(struct clk_init_data){
1317                 .name = "vclk_div2_en",
1318                 .ops = &clk_regmap_gate_ops,
1319                 .parent_hws = (const struct clk_hw *[]) {
1320                         &meson8b_vclk_div2_div.hw
1321                 },
1322                 .num_parents = 1,
1323                 .flags = CLK_SET_RATE_PARENT,
1324         },
1325 };
1326
1327 static struct clk_fixed_factor meson8b_vclk_div4_div = {
1328         .mult = 1,
1329         .div = 4,
1330         .hw.init = &(struct clk_init_data){
1331                 .name = "vclk_div4",
1332                 .ops = &clk_fixed_factor_ops,
1333                 .parent_hws = (const struct clk_hw *[]) {
1334                         &meson8b_vclk_en.hw
1335                 },
1336                 .num_parents = 1,
1337                 .flags = CLK_SET_RATE_PARENT,
1338         }
1339 };
1340
1341 static struct clk_regmap meson8b_vclk_div4_div_gate = {
1342         .data = &(struct clk_regmap_gate_data){
1343                 .offset = HHI_VID_CLK_CNTL,
1344                 .bit_idx = 2,
1345         },
1346         .hw.init = &(struct clk_init_data){
1347                 .name = "vclk_div4_en",
1348                 .ops = &clk_regmap_gate_ops,
1349                 .parent_hws = (const struct clk_hw *[]) {
1350                         &meson8b_vclk_div4_div.hw
1351                 },
1352                 .num_parents = 1,
1353                 .flags = CLK_SET_RATE_PARENT,
1354         },
1355 };
1356
1357 static struct clk_fixed_factor meson8b_vclk_div6_div = {
1358         .mult = 1,
1359         .div = 6,
1360         .hw.init = &(struct clk_init_data){
1361                 .name = "vclk_div6",
1362                 .ops = &clk_fixed_factor_ops,
1363                 .parent_hws = (const struct clk_hw *[]) {
1364                         &meson8b_vclk_en.hw
1365                 },
1366                 .num_parents = 1,
1367                 .flags = CLK_SET_RATE_PARENT,
1368         }
1369 };
1370
1371 static struct clk_regmap meson8b_vclk_div6_div_gate = {
1372         .data = &(struct clk_regmap_gate_data){
1373                 .offset = HHI_VID_CLK_CNTL,
1374                 .bit_idx = 3,
1375         },
1376         .hw.init = &(struct clk_init_data){
1377                 .name = "vclk_div6_en",
1378                 .ops = &clk_regmap_gate_ops,
1379                 .parent_hws = (const struct clk_hw *[]) {
1380                         &meson8b_vclk_div6_div.hw
1381                 },
1382                 .num_parents = 1,
1383                 .flags = CLK_SET_RATE_PARENT,
1384         },
1385 };
1386
1387 static struct clk_fixed_factor meson8b_vclk_div12_div = {
1388         .mult = 1,
1389         .div = 12,
1390         .hw.init = &(struct clk_init_data){
1391                 .name = "vclk_div12",
1392                 .ops = &clk_fixed_factor_ops,
1393                 .parent_hws = (const struct clk_hw *[]) {
1394                         &meson8b_vclk_en.hw
1395                 },
1396                 .num_parents = 1,
1397                 .flags = CLK_SET_RATE_PARENT,
1398         }
1399 };
1400
1401 static struct clk_regmap meson8b_vclk_div12_div_gate = {
1402         .data = &(struct clk_regmap_gate_data){
1403                 .offset = HHI_VID_CLK_CNTL,
1404                 .bit_idx = 4,
1405         },
1406         .hw.init = &(struct clk_init_data){
1407                 .name = "vclk_div12_en",
1408                 .ops = &clk_regmap_gate_ops,
1409                 .parent_hws = (const struct clk_hw *[]) {
1410                         &meson8b_vclk_div12_div.hw
1411                 },
1412                 .num_parents = 1,
1413                 .flags = CLK_SET_RATE_PARENT,
1414         },
1415 };
1416
1417 static struct clk_regmap meson8b_vclk2_in_sel = {
1418         .data = &(struct clk_regmap_mux_data){
1419                 .offset = HHI_VIID_CLK_CNTL,
1420                 .mask = 0x7,
1421                 .shift = 16,
1422         },
1423         .hw.init = &(struct clk_init_data){
1424                 .name = "vclk2_in_sel",
1425                 .ops = &clk_regmap_mux_ops,
1426                 .parent_hws = meson8b_vclk_mux_parent_hws,
1427                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1428                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1429         },
1430 };
1431
1432 static struct clk_regmap meson8b_vclk2_clk_in_en = {
1433         .data = &(struct clk_regmap_gate_data){
1434                 .offset = HHI_VIID_CLK_DIV,
1435                 .bit_idx = 16,
1436         },
1437         .hw.init = &(struct clk_init_data){
1438                 .name = "vclk2_in_en",
1439                 .ops = &clk_regmap_gate_ops,
1440                 .parent_hws = (const struct clk_hw *[]) {
1441                         &meson8b_vclk2_in_sel.hw
1442                 },
1443                 .num_parents = 1,
1444                 .flags = CLK_SET_RATE_PARENT,
1445         },
1446 };
1447
1448 static struct clk_regmap meson8b_vclk2_clk_en = {
1449         .data = &(struct clk_regmap_gate_data){
1450                 .offset = HHI_VIID_CLK_DIV,
1451                 .bit_idx = 19,
1452         },
1453         .hw.init = &(struct clk_init_data){
1454                 .name = "vclk2_en",
1455                 .ops = &clk_regmap_gate_ops,
1456                 .parent_hws = (const struct clk_hw *[]) {
1457                         &meson8b_vclk2_clk_in_en.hw
1458                 },
1459                 .num_parents = 1,
1460                 .flags = CLK_SET_RATE_PARENT,
1461         },
1462 };
1463
1464 static struct clk_regmap meson8b_vclk2_div1_gate = {
1465         .data = &(struct clk_regmap_gate_data){
1466                 .offset = HHI_VIID_CLK_DIV,
1467                 .bit_idx = 0,
1468         },
1469         .hw.init = &(struct clk_init_data){
1470                 .name = "vclk2_div1_en",
1471                 .ops = &clk_regmap_gate_ops,
1472                 .parent_hws = (const struct clk_hw *[]) {
1473                         &meson8b_vclk2_clk_en.hw
1474                 },
1475                 .num_parents = 1,
1476                 .flags = CLK_SET_RATE_PARENT,
1477         },
1478 };
1479
1480 static struct clk_fixed_factor meson8b_vclk2_div2_div = {
1481         .mult = 1,
1482         .div = 2,
1483         .hw.init = &(struct clk_init_data){
1484                 .name = "vclk2_div2",
1485                 .ops = &clk_fixed_factor_ops,
1486                 .parent_hws = (const struct clk_hw *[]) {
1487                         &meson8b_vclk2_clk_en.hw
1488                 },
1489                 .num_parents = 1,
1490                 .flags = CLK_SET_RATE_PARENT,
1491         }
1492 };
1493
1494 static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1495         .data = &(struct clk_regmap_gate_data){
1496                 .offset = HHI_VIID_CLK_DIV,
1497                 .bit_idx = 1,
1498         },
1499         .hw.init = &(struct clk_init_data){
1500                 .name = "vclk2_div2_en",
1501                 .ops = &clk_regmap_gate_ops,
1502                 .parent_hws = (const struct clk_hw *[]) {
1503                         &meson8b_vclk2_div2_div.hw
1504                 },
1505                 .num_parents = 1,
1506                 .flags = CLK_SET_RATE_PARENT,
1507         },
1508 };
1509
1510 static struct clk_fixed_factor meson8b_vclk2_div4_div = {
1511         .mult = 1,
1512         .div = 4,
1513         .hw.init = &(struct clk_init_data){
1514                 .name = "vclk2_div4",
1515                 .ops = &clk_fixed_factor_ops,
1516                 .parent_hws = (const struct clk_hw *[]) {
1517                         &meson8b_vclk2_clk_en.hw
1518                 },
1519                 .num_parents = 1,
1520                 .flags = CLK_SET_RATE_PARENT,
1521         }
1522 };
1523
1524 static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1525         .data = &(struct clk_regmap_gate_data){
1526                 .offset = HHI_VIID_CLK_DIV,
1527                 .bit_idx = 2,
1528         },
1529         .hw.init = &(struct clk_init_data){
1530                 .name = "vclk2_div4_en",
1531                 .ops = &clk_regmap_gate_ops,
1532                 .parent_hws = (const struct clk_hw *[]) {
1533                         &meson8b_vclk2_div4_div.hw
1534                 },
1535                 .num_parents = 1,
1536                 .flags = CLK_SET_RATE_PARENT,
1537         },
1538 };
1539
1540 static struct clk_fixed_factor meson8b_vclk2_div6_div = {
1541         .mult = 1,
1542         .div = 6,
1543         .hw.init = &(struct clk_init_data){
1544                 .name = "vclk2_div6",
1545                 .ops = &clk_fixed_factor_ops,
1546                 .parent_hws = (const struct clk_hw *[]) {
1547                         &meson8b_vclk2_clk_en.hw
1548                 },
1549                 .num_parents = 1,
1550                 .flags = CLK_SET_RATE_PARENT,
1551         }
1552 };
1553
1554 static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1555         .data = &(struct clk_regmap_gate_data){
1556                 .offset = HHI_VIID_CLK_DIV,
1557                 .bit_idx = 3,
1558         },
1559         .hw.init = &(struct clk_init_data){
1560                 .name = "vclk2_div6_en",
1561                 .ops = &clk_regmap_gate_ops,
1562                 .parent_hws = (const struct clk_hw *[]) {
1563                         &meson8b_vclk2_div6_div.hw
1564                 },
1565                 .num_parents = 1,
1566                 .flags = CLK_SET_RATE_PARENT,
1567         },
1568 };
1569
1570 static struct clk_fixed_factor meson8b_vclk2_div12_div = {
1571         .mult = 1,
1572         .div = 12,
1573         .hw.init = &(struct clk_init_data){
1574                 .name = "vclk2_div12",
1575                 .ops = &clk_fixed_factor_ops,
1576                 .parent_hws = (const struct clk_hw *[]) {
1577                         &meson8b_vclk2_clk_en.hw
1578                 },
1579                 .num_parents = 1,
1580                 .flags = CLK_SET_RATE_PARENT,
1581         }
1582 };
1583
1584 static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1585         .data = &(struct clk_regmap_gate_data){
1586                 .offset = HHI_VIID_CLK_DIV,
1587                 .bit_idx = 4,
1588         },
1589         .hw.init = &(struct clk_init_data){
1590                 .name = "vclk2_div12_en",
1591                 .ops = &clk_regmap_gate_ops,
1592                 .parent_hws = (const struct clk_hw *[]) {
1593                         &meson8b_vclk2_div12_div.hw
1594                 },
1595                 .num_parents = 1,
1596                 .flags = CLK_SET_RATE_PARENT,
1597         },
1598 };
1599
1600 static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
1601         &meson8b_vclk_div1_gate.hw,
1602         &meson8b_vclk_div2_div_gate.hw,
1603         &meson8b_vclk_div4_div_gate.hw,
1604         &meson8b_vclk_div6_div_gate.hw,
1605         &meson8b_vclk_div12_div_gate.hw,
1606 };
1607
1608 static struct clk_regmap meson8b_cts_enct_sel = {
1609         .data = &(struct clk_regmap_mux_data){
1610                 .offset = HHI_VID_CLK_DIV,
1611                 .mask = 0xf,
1612                 .shift = 20,
1613         },
1614         .hw.init = &(struct clk_init_data){
1615                 .name = "cts_enct_sel",
1616                 .ops = &clk_regmap_mux_ops,
1617                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1618                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1619                 .flags = CLK_SET_RATE_PARENT,
1620         },
1621 };
1622
1623 static struct clk_regmap meson8b_cts_enct = {
1624         .data = &(struct clk_regmap_gate_data){
1625                 .offset = HHI_VID_CLK_CNTL2,
1626                 .bit_idx = 1,
1627         },
1628         .hw.init = &(struct clk_init_data){
1629                 .name = "cts_enct",
1630                 .ops = &clk_regmap_gate_ops,
1631                 .parent_hws = (const struct clk_hw *[]) {
1632                         &meson8b_cts_enct_sel.hw
1633                 },
1634                 .num_parents = 1,
1635                 .flags = CLK_SET_RATE_PARENT,
1636         },
1637 };
1638
1639 static struct clk_regmap meson8b_cts_encp_sel = {
1640         .data = &(struct clk_regmap_mux_data){
1641                 .offset = HHI_VID_CLK_DIV,
1642                 .mask = 0xf,
1643                 .shift = 24,
1644         },
1645         .hw.init = &(struct clk_init_data){
1646                 .name = "cts_encp_sel",
1647                 .ops = &clk_regmap_mux_ops,
1648                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1649                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1650                 .flags = CLK_SET_RATE_PARENT,
1651         },
1652 };
1653
1654 static struct clk_regmap meson8b_cts_encp = {
1655         .data = &(struct clk_regmap_gate_data){
1656                 .offset = HHI_VID_CLK_CNTL2,
1657                 .bit_idx = 2,
1658         },
1659         .hw.init = &(struct clk_init_data){
1660                 .name = "cts_encp",
1661                 .ops = &clk_regmap_gate_ops,
1662                 .parent_hws = (const struct clk_hw *[]) {
1663                         &meson8b_cts_encp_sel.hw
1664                 },
1665                 .num_parents = 1,
1666                 .flags = CLK_SET_RATE_PARENT,
1667         },
1668 };
1669
1670 static struct clk_regmap meson8b_cts_enci_sel = {
1671         .data = &(struct clk_regmap_mux_data){
1672                 .offset = HHI_VID_CLK_DIV,
1673                 .mask = 0xf,
1674                 .shift = 28,
1675         },
1676         .hw.init = &(struct clk_init_data){
1677                 .name = "cts_enci_sel",
1678                 .ops = &clk_regmap_mux_ops,
1679                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1680                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1681                 .flags = CLK_SET_RATE_PARENT,
1682         },
1683 };
1684
1685 static struct clk_regmap meson8b_cts_enci = {
1686         .data = &(struct clk_regmap_gate_data){
1687                 .offset = HHI_VID_CLK_CNTL2,
1688                 .bit_idx = 0,
1689         },
1690         .hw.init = &(struct clk_init_data){
1691                 .name = "cts_enci",
1692                 .ops = &clk_regmap_gate_ops,
1693                 .parent_hws = (const struct clk_hw *[]) {
1694                         &meson8b_cts_enci_sel.hw
1695                 },
1696                 .num_parents = 1,
1697                 .flags = CLK_SET_RATE_PARENT,
1698         },
1699 };
1700
1701 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
1702         .data = &(struct clk_regmap_mux_data){
1703                 .offset = HHI_HDMI_CLK_CNTL,
1704                 .mask = 0xf,
1705                 .shift = 16,
1706         },
1707         .hw.init = &(struct clk_init_data){
1708                 .name = "hdmi_tx_pixel_sel",
1709                 .ops = &clk_regmap_mux_ops,
1710                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1711                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1712                 .flags = CLK_SET_RATE_PARENT,
1713         },
1714 };
1715
1716 static struct clk_regmap meson8b_hdmi_tx_pixel = {
1717         .data = &(struct clk_regmap_gate_data){
1718                 .offset = HHI_VID_CLK_CNTL2,
1719                 .bit_idx = 5,
1720         },
1721         .hw.init = &(struct clk_init_data){
1722                 .name = "hdmi_tx_pixel",
1723                 .ops = &clk_regmap_gate_ops,
1724                 .parent_hws = (const struct clk_hw *[]) {
1725                         &meson8b_hdmi_tx_pixel_sel.hw
1726                 },
1727                 .num_parents = 1,
1728                 .flags = CLK_SET_RATE_PARENT,
1729         },
1730 };
1731
1732 static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
1733         &meson8b_vclk2_div1_gate.hw,
1734         &meson8b_vclk2_div2_div_gate.hw,
1735         &meson8b_vclk2_div4_div_gate.hw,
1736         &meson8b_vclk2_div6_div_gate.hw,
1737         &meson8b_vclk2_div12_div_gate.hw,
1738 };
1739
1740 static struct clk_regmap meson8b_cts_encl_sel = {
1741         .data = &(struct clk_regmap_mux_data){
1742                 .offset = HHI_VIID_CLK_DIV,
1743                 .mask = 0xf,
1744                 .shift = 12,
1745         },
1746         .hw.init = &(struct clk_init_data){
1747                 .name = "cts_encl_sel",
1748                 .ops = &clk_regmap_mux_ops,
1749                 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1750                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1751                 .flags = CLK_SET_RATE_PARENT,
1752         },
1753 };
1754
1755 static struct clk_regmap meson8b_cts_encl = {
1756         .data = &(struct clk_regmap_gate_data){
1757                 .offset = HHI_VID_CLK_CNTL2,
1758                 .bit_idx = 3,
1759         },
1760         .hw.init = &(struct clk_init_data){
1761                 .name = "cts_encl",
1762                 .ops = &clk_regmap_gate_ops,
1763                 .parent_hws = (const struct clk_hw *[]) {
1764                         &meson8b_cts_encl_sel.hw
1765                 },
1766                 .num_parents = 1,
1767                 .flags = CLK_SET_RATE_PARENT,
1768         },
1769 };
1770
1771 static struct clk_regmap meson8b_cts_vdac0_sel = {
1772         .data = &(struct clk_regmap_mux_data){
1773                 .offset = HHI_VIID_CLK_DIV,
1774                 .mask = 0xf,
1775                 .shift = 28,
1776         },
1777         .hw.init = &(struct clk_init_data){
1778                 .name = "cts_vdac0_sel",
1779                 .ops = &clk_regmap_mux_ops,
1780                 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1781                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1782                 .flags = CLK_SET_RATE_PARENT,
1783         },
1784 };
1785
1786 static struct clk_regmap meson8b_cts_vdac0 = {
1787         .data = &(struct clk_regmap_gate_data){
1788                 .offset = HHI_VID_CLK_CNTL2,
1789                 .bit_idx = 4,
1790         },
1791         .hw.init = &(struct clk_init_data){
1792                 .name = "cts_vdac0",
1793                 .ops = &clk_regmap_gate_ops,
1794                 .parent_hws = (const struct clk_hw *[]) {
1795                         &meson8b_cts_vdac0_sel.hw
1796                 },
1797                 .num_parents = 1,
1798                 .flags = CLK_SET_RATE_PARENT,
1799         },
1800 };
1801
1802 static struct clk_regmap meson8b_hdmi_sys_sel = {
1803         .data = &(struct clk_regmap_mux_data){
1804                 .offset = HHI_HDMI_CLK_CNTL,
1805                 .mask = 0x3,
1806                 .shift = 9,
1807                 .flags = CLK_MUX_ROUND_CLOSEST,
1808         },
1809         .hw.init = &(struct clk_init_data){
1810                 .name = "hdmi_sys_sel",
1811                 .ops = &clk_regmap_mux_ops,
1812                 /* FIXME: all other parents are unknown */
1813                 .parent_data = &(const struct clk_parent_data) {
1814                         .fw_name = "xtal",
1815                         .name = "xtal",
1816                         .index = -1,
1817                 },
1818                 .num_parents = 1,
1819                 .flags = CLK_SET_RATE_NO_REPARENT,
1820         },
1821 };
1822
1823 static struct clk_regmap meson8b_hdmi_sys_div = {
1824         .data = &(struct clk_regmap_div_data){
1825                 .offset = HHI_HDMI_CLK_CNTL,
1826                 .shift = 0,
1827                 .width = 7,
1828         },
1829         .hw.init = &(struct clk_init_data){
1830                 .name = "hdmi_sys_div",
1831                 .ops = &clk_regmap_divider_ops,
1832                 .parent_hws = (const struct clk_hw *[]) {
1833                         &meson8b_hdmi_sys_sel.hw
1834                 },
1835                 .num_parents = 1,
1836                 .flags = CLK_SET_RATE_PARENT,
1837         },
1838 };
1839
1840 static struct clk_regmap meson8b_hdmi_sys = {
1841         .data = &(struct clk_regmap_gate_data){
1842                 .offset = HHI_HDMI_CLK_CNTL,
1843                 .bit_idx = 8,
1844         },
1845         .hw.init = &(struct clk_init_data) {
1846                 .name = "hdmi_sys",
1847                 .ops = &clk_regmap_gate_ops,
1848                 .parent_hws = (const struct clk_hw *[]) {
1849                         &meson8b_hdmi_sys_div.hw
1850                 },
1851                 .num_parents = 1,
1852                 .flags = CLK_SET_RATE_PARENT,
1853         },
1854 };
1855
1856 /*
1857  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1858  * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
1859  * actually manage this glitch-free mux because it does top-to-bottom
1860  * updates the each clock tree and switches to the "inactive" one when
1861  * CLK_SET_RATE_GATE is set.
1862  * Meson8 only has mali_0 and no glitch-free mux.
1863  */
1864 static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
1865         { .fw_name = "xtal", .name = "xtal", .index = -1, },
1866         { .hw = &meson8b_mpll2.hw, },
1867         { .hw = &meson8b_mpll1.hw, },
1868         { .hw = &meson8b_fclk_div7.hw, },
1869         { .hw = &meson8b_fclk_div4.hw, },
1870         { .hw = &meson8b_fclk_div3.hw, },
1871         { .hw = &meson8b_fclk_div5.hw, },
1872 };
1873
1874 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1875
1876 static struct clk_regmap meson8b_mali_0_sel = {
1877         .data = &(struct clk_regmap_mux_data){
1878                 .offset = HHI_MALI_CLK_CNTL,
1879                 .mask = 0x7,
1880                 .shift = 9,
1881                 .table = meson8b_mali_0_1_mux_table,
1882         },
1883         .hw.init = &(struct clk_init_data){
1884                 .name = "mali_0_sel",
1885                 .ops = &clk_regmap_mux_ops,
1886                 .parent_data = meson8b_mali_0_1_parent_data,
1887                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1888                 /*
1889                  * Don't propagate rate changes up because the only changeable
1890                  * parents are mpll1 and mpll2 but we need those for audio and
1891                  * RGMII (Ethernet). We don't want to change the audio or
1892                  * Ethernet clocks when setting the GPU frequency.
1893                  */
1894                 .flags = 0,
1895         },
1896 };
1897
1898 static struct clk_regmap meson8b_mali_0_div = {
1899         .data = &(struct clk_regmap_div_data){
1900                 .offset = HHI_MALI_CLK_CNTL,
1901                 .shift = 0,
1902                 .width = 7,
1903         },
1904         .hw.init = &(struct clk_init_data){
1905                 .name = "mali_0_div",
1906                 .ops = &clk_regmap_divider_ops,
1907                 .parent_hws = (const struct clk_hw *[]) {
1908                         &meson8b_mali_0_sel.hw
1909                 },
1910                 .num_parents = 1,
1911                 .flags = CLK_SET_RATE_PARENT,
1912         },
1913 };
1914
1915 static struct clk_regmap meson8b_mali_0 = {
1916         .data = &(struct clk_regmap_gate_data){
1917                 .offset = HHI_MALI_CLK_CNTL,
1918                 .bit_idx = 8,
1919         },
1920         .hw.init = &(struct clk_init_data){
1921                 .name = "mali_0",
1922                 .ops = &clk_regmap_gate_ops,
1923                 .parent_hws = (const struct clk_hw *[]) {
1924                         &meson8b_mali_0_div.hw
1925                 },
1926                 .num_parents = 1,
1927                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1928         },
1929 };
1930
1931 static struct clk_regmap meson8b_mali_1_sel = {
1932         .data = &(struct clk_regmap_mux_data){
1933                 .offset = HHI_MALI_CLK_CNTL,
1934                 .mask = 0x7,
1935                 .shift = 25,
1936                 .table = meson8b_mali_0_1_mux_table,
1937         },
1938         .hw.init = &(struct clk_init_data){
1939                 .name = "mali_1_sel",
1940                 .ops = &clk_regmap_mux_ops,
1941                 .parent_data = meson8b_mali_0_1_parent_data,
1942                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1943                 /*
1944                  * Don't propagate rate changes up because the only changeable
1945                  * parents are mpll1 and mpll2 but we need those for audio and
1946                  * RGMII (Ethernet). We don't want to change the audio or
1947                  * Ethernet clocks when setting the GPU frequency.
1948                  */
1949                 .flags = 0,
1950         },
1951 };
1952
1953 static struct clk_regmap meson8b_mali_1_div = {
1954         .data = &(struct clk_regmap_div_data){
1955                 .offset = HHI_MALI_CLK_CNTL,
1956                 .shift = 16,
1957                 .width = 7,
1958         },
1959         .hw.init = &(struct clk_init_data){
1960                 .name = "mali_1_div",
1961                 .ops = &clk_regmap_divider_ops,
1962                 .parent_hws = (const struct clk_hw *[]) {
1963                         &meson8b_mali_1_sel.hw
1964                 },
1965                 .num_parents = 1,
1966                 .flags = CLK_SET_RATE_PARENT,
1967         },
1968 };
1969
1970 static struct clk_regmap meson8b_mali_1 = {
1971         .data = &(struct clk_regmap_gate_data){
1972                 .offset = HHI_MALI_CLK_CNTL,
1973                 .bit_idx = 24,
1974         },
1975         .hw.init = &(struct clk_init_data){
1976                 .name = "mali_1",
1977                 .ops = &clk_regmap_gate_ops,
1978                 .parent_hws = (const struct clk_hw *[]) {
1979                         &meson8b_mali_1_div.hw
1980                 },
1981                 .num_parents = 1,
1982                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1983         },
1984 };
1985
1986 static struct clk_regmap meson8b_mali = {
1987         .data = &(struct clk_regmap_mux_data){
1988                 .offset = HHI_MALI_CLK_CNTL,
1989                 .mask = 1,
1990                 .shift = 31,
1991         },
1992         .hw.init = &(struct clk_init_data){
1993                 .name = "mali",
1994                 .ops = &clk_regmap_mux_ops,
1995                 .parent_hws = (const struct clk_hw *[]) {
1996                         &meson8b_mali_0.hw,
1997                         &meson8b_mali_1.hw,
1998                 },
1999                 .num_parents = 2,
2000                 .flags = CLK_SET_RATE_PARENT,
2001         },
2002 };
2003
2004 static const struct reg_sequence meson8m2_gp_pll_init_regs[] = {
2005         { .reg = HHI_GP_PLL_CNTL2,      .def = 0x59c88000 },
2006         { .reg = HHI_GP_PLL_CNTL3,      .def = 0xca463823 },
2007         { .reg = HHI_GP_PLL_CNTL4,      .def = 0x0286a027 },
2008         { .reg = HHI_GP_PLL_CNTL5,      .def = 0x00003000 },
2009 };
2010
2011 static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
2012         PLL_PARAMS(182, 3),
2013         { /* sentinel */ },
2014 };
2015
2016 static struct clk_regmap meson8m2_gp_pll_dco = {
2017         .data = &(struct meson_clk_pll_data){
2018                 .en = {
2019                         .reg_off = HHI_GP_PLL_CNTL,
2020                         .shift   = 30,
2021                         .width   = 1,
2022                 },
2023                 .m = {
2024                         .reg_off = HHI_GP_PLL_CNTL,
2025                         .shift   = 0,
2026                         .width   = 9,
2027                 },
2028                 .n = {
2029                         .reg_off = HHI_GP_PLL_CNTL,
2030                         .shift   = 9,
2031                         .width   = 5,
2032                 },
2033                 .l = {
2034                         .reg_off = HHI_GP_PLL_CNTL,
2035                         .shift   = 31,
2036                         .width   = 1,
2037                 },
2038                 .rst = {
2039                         .reg_off = HHI_GP_PLL_CNTL,
2040                         .shift   = 29,
2041                         .width   = 1,
2042                 },
2043                 .table = meson8m2_gp_pll_params_table,
2044                 .init_regs = meson8m2_gp_pll_init_regs,
2045                 .init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs),
2046         },
2047         .hw.init = &(struct clk_init_data){
2048                 .name = "gp_pll_dco",
2049                 .ops = &meson_clk_pll_ops,
2050                 .parent_data = &(const struct clk_parent_data) {
2051                         .fw_name = "xtal",
2052                         .name = "xtal",
2053                         .index = -1,
2054                 },
2055                 .num_parents = 1,
2056         },
2057 };
2058
2059 static struct clk_regmap meson8m2_gp_pll = {
2060         .data = &(struct clk_regmap_div_data){
2061                 .offset = HHI_GP_PLL_CNTL,
2062                 .shift = 16,
2063                 .width = 2,
2064                 .flags = CLK_DIVIDER_POWER_OF_TWO,
2065         },
2066         .hw.init = &(struct clk_init_data){
2067                 .name = "gp_pll",
2068                 .ops = &clk_regmap_divider_ops,
2069                 .parent_hws = (const struct clk_hw *[]) {
2070                         &meson8m2_gp_pll_dco.hw
2071                 },
2072                 .num_parents = 1,
2073                 .flags = CLK_SET_RATE_PARENT,
2074         },
2075 };
2076
2077 static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
2078         &meson8b_fclk_div4.hw,
2079         &meson8b_fclk_div3.hw,
2080         &meson8b_fclk_div5.hw,
2081         &meson8b_fclk_div7.hw,
2082 };
2083
2084 static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
2085         &meson8b_fclk_div4.hw,
2086         &meson8b_fclk_div3.hw,
2087         &meson8b_fclk_div5.hw,
2088         &meson8m2_gp_pll.hw,
2089 };
2090
2091 static struct clk_regmap meson8b_vpu_0_sel = {
2092         .data = &(struct clk_regmap_mux_data){
2093                 .offset = HHI_VPU_CLK_CNTL,
2094                 .mask = 0x3,
2095                 .shift = 9,
2096         },
2097         .hw.init = &(struct clk_init_data){
2098                 .name = "vpu_0_sel",
2099                 .ops = &clk_regmap_mux_ops,
2100                 .parent_hws = meson8b_vpu_0_1_parent_hws,
2101                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2102                 .flags = CLK_SET_RATE_PARENT,
2103         },
2104 };
2105
2106 static struct clk_regmap meson8m2_vpu_0_sel = {
2107         .data = &(struct clk_regmap_mux_data){
2108                 .offset = HHI_VPU_CLK_CNTL,
2109                 .mask = 0x3,
2110                 .shift = 9,
2111         },
2112         .hw.init = &(struct clk_init_data){
2113                 .name = "vpu_0_sel",
2114                 .ops = &clk_regmap_mux_ops,
2115                 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2116                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2117                 .flags = CLK_SET_RATE_PARENT,
2118         },
2119 };
2120
2121 static struct clk_regmap meson8b_vpu_0_div = {
2122         .data = &(struct clk_regmap_div_data){
2123                 .offset = HHI_VPU_CLK_CNTL,
2124                 .shift = 0,
2125                 .width = 7,
2126         },
2127         .hw.init = &(struct clk_init_data){
2128                 .name = "vpu_0_div",
2129                 .ops = &clk_regmap_divider_ops,
2130                 .parent_data = &(const struct clk_parent_data) {
2131                         /*
2132                          * Note:
2133                          * meson8b and meson8m2 have different vpu_0_sels (with
2134                          * different struct clk_hw). We fallback to the global
2135                          * naming string mechanism so vpu_0_div picks up the
2136                          * appropriate one.
2137                          */
2138                         .name = "vpu_0_sel",
2139                         .index = -1,
2140                 },
2141                 .num_parents = 1,
2142                 .flags = CLK_SET_RATE_PARENT,
2143         },
2144 };
2145
2146 static struct clk_regmap meson8b_vpu_0 = {
2147         .data = &(struct clk_regmap_gate_data){
2148                 .offset = HHI_VPU_CLK_CNTL,
2149                 .bit_idx = 8,
2150         },
2151         .hw.init = &(struct clk_init_data) {
2152                 .name = "vpu_0",
2153                 .ops = &clk_regmap_gate_ops,
2154                 .parent_hws = (const struct clk_hw *[]) {
2155                         &meson8b_vpu_0_div.hw
2156                 },
2157                 .num_parents = 1,
2158                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
2159         },
2160 };
2161
2162 static struct clk_regmap meson8b_vpu_1_sel = {
2163         .data = &(struct clk_regmap_mux_data){
2164                 .offset = HHI_VPU_CLK_CNTL,
2165                 .mask = 0x3,
2166                 .shift = 25,
2167         },
2168         .hw.init = &(struct clk_init_data){
2169                 .name = "vpu_1_sel",
2170                 .ops = &clk_regmap_mux_ops,
2171                 .parent_hws = meson8b_vpu_0_1_parent_hws,
2172                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2173                 .flags = CLK_SET_RATE_PARENT,
2174         },
2175 };
2176
2177 static struct clk_regmap meson8m2_vpu_1_sel = {
2178         .data = &(struct clk_regmap_mux_data){
2179                 .offset = HHI_VPU_CLK_CNTL,
2180                 .mask = 0x3,
2181                 .shift = 25,
2182         },
2183         .hw.init = &(struct clk_init_data){
2184                 .name = "vpu_1_sel",
2185                 .ops = &clk_regmap_mux_ops,
2186                 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2187                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2188                 .flags = CLK_SET_RATE_PARENT,
2189         },
2190 };
2191
2192 static struct clk_regmap meson8b_vpu_1_div = {
2193         .data = &(struct clk_regmap_div_data){
2194                 .offset = HHI_VPU_CLK_CNTL,
2195                 .shift = 16,
2196                 .width = 7,
2197         },
2198         .hw.init = &(struct clk_init_data){
2199                 .name = "vpu_1_div",
2200                 .ops = &clk_regmap_divider_ops,
2201                 .parent_data = &(const struct clk_parent_data) {
2202                         /*
2203                          * Note:
2204                          * meson8b and meson8m2 have different vpu_1_sels (with
2205                          * different struct clk_hw). We fallback to the global
2206                          * naming string mechanism so vpu_1_div picks up the
2207                          * appropriate one.
2208                          */
2209                         .name = "vpu_1_sel",
2210                         .index = -1,
2211                 },
2212                 .num_parents = 1,
2213                 .flags = CLK_SET_RATE_PARENT,
2214         },
2215 };
2216
2217 static struct clk_regmap meson8b_vpu_1 = {
2218         .data = &(struct clk_regmap_gate_data){
2219                 .offset = HHI_VPU_CLK_CNTL,
2220                 .bit_idx = 24,
2221         },
2222         .hw.init = &(struct clk_init_data) {
2223                 .name = "vpu_1",
2224                 .ops = &clk_regmap_gate_ops,
2225                 .parent_hws = (const struct clk_hw *[]) {
2226                         &meson8b_vpu_1_div.hw
2227                 },
2228                 .num_parents = 1,
2229                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
2230         },
2231 };
2232
2233 /*
2234  * The VPU clock has two identical clock trees (vpu_0 and vpu_1)
2235  * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
2236  * actually manage this glitch-free mux because it does top-to-bottom
2237  * updates the each clock tree and switches to the "inactive" one when
2238  * CLK_SET_RATE_GATE is set.
2239  * Meson8 only has vpu_0 and no glitch-free mux.
2240  */
2241 static struct clk_regmap meson8b_vpu = {
2242         .data = &(struct clk_regmap_mux_data){
2243                 .offset = HHI_VPU_CLK_CNTL,
2244                 .mask = 1,
2245                 .shift = 31,
2246         },
2247         .hw.init = &(struct clk_init_data){
2248                 .name = "vpu",
2249                 .ops = &clk_regmap_mux_ops,
2250                 .parent_hws = (const struct clk_hw *[]) {
2251                         &meson8b_vpu_0.hw,
2252                         &meson8b_vpu_1.hw,
2253                 },
2254                 .num_parents = 2,
2255                 .flags = CLK_SET_RATE_PARENT,
2256         },
2257 };
2258
2259 static const struct clk_hw *meson8b_vdec_parent_hws[] = {
2260         &meson8b_fclk_div4.hw,
2261         &meson8b_fclk_div3.hw,
2262         &meson8b_fclk_div5.hw,
2263         &meson8b_fclk_div7.hw,
2264         &meson8b_mpll2.hw,
2265         &meson8b_mpll1.hw,
2266 };
2267
2268 static struct clk_regmap meson8b_vdec_1_sel = {
2269         .data = &(struct clk_regmap_mux_data){
2270                 .offset = HHI_VDEC_CLK_CNTL,
2271                 .mask = 0x3,
2272                 .shift = 9,
2273                 .flags = CLK_MUX_ROUND_CLOSEST,
2274         },
2275         .hw.init = &(struct clk_init_data){
2276                 .name = "vdec_1_sel",
2277                 .ops = &clk_regmap_mux_ops,
2278                 .parent_hws = meson8b_vdec_parent_hws,
2279                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2280                 .flags = CLK_SET_RATE_PARENT,
2281         },
2282 };
2283
2284 static struct clk_regmap meson8b_vdec_1_1_div = {
2285         .data = &(struct clk_regmap_div_data){
2286                 .offset = HHI_VDEC_CLK_CNTL,
2287                 .shift = 0,
2288                 .width = 7,
2289                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2290         },
2291         .hw.init = &(struct clk_init_data){
2292                 .name = "vdec_1_1_div",
2293                 .ops = &clk_regmap_divider_ops,
2294                 .parent_hws = (const struct clk_hw *[]) {
2295                         &meson8b_vdec_1_sel.hw
2296                 },
2297                 .num_parents = 1,
2298                 .flags = CLK_SET_RATE_PARENT,
2299         },
2300 };
2301
2302 static struct clk_regmap meson8b_vdec_1_1 = {
2303         .data = &(struct clk_regmap_gate_data){
2304                 .offset = HHI_VDEC_CLK_CNTL,
2305                 .bit_idx = 8,
2306         },
2307         .hw.init = &(struct clk_init_data) {
2308                 .name = "vdec_1_1",
2309                 .ops = &clk_regmap_gate_ops,
2310                 .parent_hws = (const struct clk_hw *[]) {
2311                         &meson8b_vdec_1_1_div.hw
2312                 },
2313                 .num_parents = 1,
2314                 .flags = CLK_SET_RATE_PARENT,
2315         },
2316 };
2317
2318 static struct clk_regmap meson8b_vdec_1_2_div = {
2319         .data = &(struct clk_regmap_div_data){
2320                 .offset = HHI_VDEC3_CLK_CNTL,
2321                 .shift = 0,
2322                 .width = 7,
2323                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2324         },
2325         .hw.init = &(struct clk_init_data){
2326                 .name = "vdec_1_2_div",
2327                 .ops = &clk_regmap_divider_ops,
2328                 .parent_hws = (const struct clk_hw *[]) {
2329                         &meson8b_vdec_1_sel.hw
2330                 },
2331                 .num_parents = 1,
2332                 .flags = CLK_SET_RATE_PARENT,
2333         },
2334 };
2335
2336 static struct clk_regmap meson8b_vdec_1_2 = {
2337         .data = &(struct clk_regmap_gate_data){
2338                 .offset = HHI_VDEC3_CLK_CNTL,
2339                 .bit_idx = 8,
2340         },
2341         .hw.init = &(struct clk_init_data) {
2342                 .name = "vdec_1_2",
2343                 .ops = &clk_regmap_gate_ops,
2344                 .parent_hws = (const struct clk_hw *[]) {
2345                         &meson8b_vdec_1_2_div.hw
2346                 },
2347                 .num_parents = 1,
2348                 .flags = CLK_SET_RATE_PARENT,
2349         },
2350 };
2351
2352 static struct clk_regmap meson8b_vdec_1 = {
2353         .data = &(struct clk_regmap_mux_data){
2354                 .offset = HHI_VDEC3_CLK_CNTL,
2355                 .mask = 0x1,
2356                 .shift = 15,
2357                 .flags = CLK_MUX_ROUND_CLOSEST,
2358         },
2359         .hw.init = &(struct clk_init_data){
2360                 .name = "vdec_1",
2361                 .ops = &clk_regmap_mux_ops,
2362                 .parent_hws = (const struct clk_hw *[]) {
2363                         &meson8b_vdec_1_1.hw,
2364                         &meson8b_vdec_1_2.hw,
2365                 },
2366                 .num_parents = 2,
2367                 .flags = CLK_SET_RATE_PARENT,
2368         },
2369 };
2370
2371 static struct clk_regmap meson8b_vdec_hcodec_sel = {
2372         .data = &(struct clk_regmap_mux_data){
2373                 .offset = HHI_VDEC_CLK_CNTL,
2374                 .mask = 0x3,
2375                 .shift = 25,
2376                 .flags = CLK_MUX_ROUND_CLOSEST,
2377         },
2378         .hw.init = &(struct clk_init_data){
2379                 .name = "vdec_hcodec_sel",
2380                 .ops = &clk_regmap_mux_ops,
2381                 .parent_hws = meson8b_vdec_parent_hws,
2382                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2383                 .flags = CLK_SET_RATE_PARENT,
2384         },
2385 };
2386
2387 static struct clk_regmap meson8b_vdec_hcodec_div = {
2388         .data = &(struct clk_regmap_div_data){
2389                 .offset = HHI_VDEC_CLK_CNTL,
2390                 .shift = 16,
2391                 .width = 7,
2392                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2393         },
2394         .hw.init = &(struct clk_init_data){
2395                 .name = "vdec_hcodec_div",
2396                 .ops = &clk_regmap_divider_ops,
2397                 .parent_hws = (const struct clk_hw *[]) {
2398                         &meson8b_vdec_hcodec_sel.hw
2399                 },
2400                 .num_parents = 1,
2401                 .flags = CLK_SET_RATE_PARENT,
2402         },
2403 };
2404
2405 static struct clk_regmap meson8b_vdec_hcodec = {
2406         .data = &(struct clk_regmap_gate_data){
2407                 .offset = HHI_VDEC_CLK_CNTL,
2408                 .bit_idx = 24,
2409         },
2410         .hw.init = &(struct clk_init_data) {
2411                 .name = "vdec_hcodec",
2412                 .ops = &clk_regmap_gate_ops,
2413                 .parent_hws = (const struct clk_hw *[]) {
2414                         &meson8b_vdec_hcodec_div.hw
2415                 },
2416                 .num_parents = 1,
2417                 .flags = CLK_SET_RATE_PARENT,
2418         },
2419 };
2420
2421 static struct clk_regmap meson8b_vdec_2_sel = {
2422         .data = &(struct clk_regmap_mux_data){
2423                 .offset = HHI_VDEC2_CLK_CNTL,
2424                 .mask = 0x3,
2425                 .shift = 9,
2426                 .flags = CLK_MUX_ROUND_CLOSEST,
2427         },
2428         .hw.init = &(struct clk_init_data){
2429                 .name = "vdec_2_sel",
2430                 .ops = &clk_regmap_mux_ops,
2431                 .parent_hws = meson8b_vdec_parent_hws,
2432                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2433                 .flags = CLK_SET_RATE_PARENT,
2434         },
2435 };
2436
2437 static struct clk_regmap meson8b_vdec_2_div = {
2438         .data = &(struct clk_regmap_div_data){
2439                 .offset = HHI_VDEC2_CLK_CNTL,
2440                 .shift = 0,
2441                 .width = 7,
2442                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2443         },
2444         .hw.init = &(struct clk_init_data){
2445                 .name = "vdec_2_div",
2446                 .ops = &clk_regmap_divider_ops,
2447                 .parent_hws = (const struct clk_hw *[]) {
2448                         &meson8b_vdec_2_sel.hw
2449                 },
2450                 .num_parents = 1,
2451                 .flags = CLK_SET_RATE_PARENT,
2452         },
2453 };
2454
2455 static struct clk_regmap meson8b_vdec_2 = {
2456         .data = &(struct clk_regmap_gate_data){
2457                 .offset = HHI_VDEC2_CLK_CNTL,
2458                 .bit_idx = 8,
2459         },
2460         .hw.init = &(struct clk_init_data) {
2461                 .name = "vdec_2",
2462                 .ops = &clk_regmap_gate_ops,
2463                 .parent_hws = (const struct clk_hw *[]) {
2464                         &meson8b_vdec_2_div.hw
2465                 },
2466                 .num_parents = 1,
2467                 .flags = CLK_SET_RATE_PARENT,
2468         },
2469 };
2470
2471 static struct clk_regmap meson8b_vdec_hevc_sel = {
2472         .data = &(struct clk_regmap_mux_data){
2473                 .offset = HHI_VDEC2_CLK_CNTL,
2474                 .mask = 0x3,
2475                 .shift = 25,
2476                 .flags = CLK_MUX_ROUND_CLOSEST,
2477         },
2478         .hw.init = &(struct clk_init_data){
2479                 .name = "vdec_hevc_sel",
2480                 .ops = &clk_regmap_mux_ops,
2481                 .parent_hws = meson8b_vdec_parent_hws,
2482                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2483                 .flags = CLK_SET_RATE_PARENT,
2484         },
2485 };
2486
2487 static struct clk_regmap meson8b_vdec_hevc_div = {
2488         .data = &(struct clk_regmap_div_data){
2489                 .offset = HHI_VDEC2_CLK_CNTL,
2490                 .shift = 16,
2491                 .width = 7,
2492                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2493         },
2494         .hw.init = &(struct clk_init_data){
2495                 .name = "vdec_hevc_div",
2496                 .ops = &clk_regmap_divider_ops,
2497                 .parent_hws = (const struct clk_hw *[]) {
2498                         &meson8b_vdec_hevc_sel.hw
2499                 },
2500                 .num_parents = 1,
2501                 .flags = CLK_SET_RATE_PARENT,
2502         },
2503 };
2504
2505 static struct clk_regmap meson8b_vdec_hevc_en = {
2506         .data = &(struct clk_regmap_gate_data){
2507                 .offset = HHI_VDEC2_CLK_CNTL,
2508                 .bit_idx = 24,
2509         },
2510         .hw.init = &(struct clk_init_data) {
2511                 .name = "vdec_hevc_en",
2512                 .ops = &clk_regmap_gate_ops,
2513                 .parent_hws = (const struct clk_hw *[]) {
2514                         &meson8b_vdec_hevc_div.hw
2515                 },
2516                 .num_parents = 1,
2517                 .flags = CLK_SET_RATE_PARENT,
2518         },
2519 };
2520
2521 static struct clk_regmap meson8b_vdec_hevc = {
2522         .data = &(struct clk_regmap_mux_data){
2523                 .offset = HHI_VDEC2_CLK_CNTL,
2524                 .mask = 0x1,
2525                 .shift = 31,
2526                 .flags = CLK_MUX_ROUND_CLOSEST,
2527         },
2528         .hw.init = &(struct clk_init_data){
2529                 .name = "vdec_hevc",
2530                 .ops = &clk_regmap_mux_ops,
2531                 /* TODO: The second parent is currently unknown */
2532                 .parent_hws = (const struct clk_hw *[]) {
2533                         &meson8b_vdec_hevc_en.hw
2534                 },
2535                 .num_parents = 1,
2536                 .flags = CLK_SET_RATE_PARENT,
2537         },
2538 };
2539
2540 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2541 static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
2542         &meson8b_mpll0.hw,
2543         &meson8b_mpll1.hw,
2544         &meson8b_mpll2.hw
2545 };
2546
2547 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
2548
2549 static struct clk_regmap meson8b_cts_amclk_sel = {
2550         .data = &(struct clk_regmap_mux_data){
2551                 .offset = HHI_AUD_CLK_CNTL,
2552                 .mask = 0x3,
2553                 .shift = 9,
2554                 .table = meson8b_cts_amclk_mux_table,
2555                 .flags = CLK_MUX_ROUND_CLOSEST,
2556         },
2557         .hw.init = &(struct clk_init_data){
2558                 .name = "cts_amclk_sel",
2559                 .ops = &clk_regmap_mux_ops,
2560                 .parent_hws = meson8b_cts_amclk_parent_hws,
2561                 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
2562         },
2563 };
2564
2565 static struct clk_regmap meson8b_cts_amclk_div = {
2566         .data = &(struct clk_regmap_div_data) {
2567                 .offset = HHI_AUD_CLK_CNTL,
2568                 .shift = 0,
2569                 .width = 8,
2570                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2571         },
2572         .hw.init = &(struct clk_init_data){
2573                 .name = "cts_amclk_div",
2574                 .ops = &clk_regmap_divider_ops,
2575                 .parent_hws = (const struct clk_hw *[]) {
2576                         &meson8b_cts_amclk_sel.hw
2577                 },
2578                 .num_parents = 1,
2579                 .flags = CLK_SET_RATE_PARENT,
2580         },
2581 };
2582
2583 static struct clk_regmap meson8b_cts_amclk = {
2584         .data = &(struct clk_regmap_gate_data){
2585                 .offset = HHI_AUD_CLK_CNTL,
2586                 .bit_idx = 8,
2587         },
2588         .hw.init = &(struct clk_init_data){
2589                 .name = "cts_amclk",
2590                 .ops = &clk_regmap_gate_ops,
2591                 .parent_hws = (const struct clk_hw *[]) {
2592                         &meson8b_cts_amclk_div.hw
2593                 },
2594                 .num_parents = 1,
2595                 .flags = CLK_SET_RATE_PARENT,
2596         },
2597 };
2598
2599 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2600 static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
2601         &meson8b_mpll0.hw,
2602         &meson8b_mpll1.hw,
2603         &meson8b_mpll2.hw
2604 };
2605
2606 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
2607
2608 static struct clk_regmap meson8b_cts_mclk_i958_sel = {
2609         .data = &(struct clk_regmap_mux_data){
2610                 .offset = HHI_AUD_CLK_CNTL2,
2611                 .mask = 0x3,
2612                 .shift = 25,
2613                 .table = meson8b_cts_mclk_i958_mux_table,
2614                 .flags = CLK_MUX_ROUND_CLOSEST,
2615         },
2616         .hw.init = &(struct clk_init_data) {
2617                 .name = "cts_mclk_i958_sel",
2618                 .ops = &clk_regmap_mux_ops,
2619                 .parent_hws = meson8b_cts_mclk_i958_parent_hws,
2620                 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
2621         },
2622 };
2623
2624 static struct clk_regmap meson8b_cts_mclk_i958_div = {
2625         .data = &(struct clk_regmap_div_data){
2626                 .offset = HHI_AUD_CLK_CNTL2,
2627                 .shift = 16,
2628                 .width = 8,
2629                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2630         },
2631         .hw.init = &(struct clk_init_data) {
2632                 .name = "cts_mclk_i958_div",
2633                 .ops = &clk_regmap_divider_ops,
2634                 .parent_hws = (const struct clk_hw *[]) {
2635                         &meson8b_cts_mclk_i958_sel.hw
2636                 },
2637                 .num_parents = 1,
2638                 .flags = CLK_SET_RATE_PARENT,
2639         },
2640 };
2641
2642 static struct clk_regmap meson8b_cts_mclk_i958 = {
2643         .data = &(struct clk_regmap_gate_data){
2644                 .offset = HHI_AUD_CLK_CNTL2,
2645                 .bit_idx = 24,
2646         },
2647         .hw.init = &(struct clk_init_data){
2648                 .name = "cts_mclk_i958",
2649                 .ops = &clk_regmap_gate_ops,
2650                 .parent_hws = (const struct clk_hw *[]) {
2651                         &meson8b_cts_mclk_i958_div.hw
2652                 },
2653                 .num_parents = 1,
2654                 .flags = CLK_SET_RATE_PARENT,
2655         },
2656 };
2657
2658 static struct clk_regmap meson8b_cts_i958 = {
2659         .data = &(struct clk_regmap_mux_data){
2660                 .offset = HHI_AUD_CLK_CNTL2,
2661                 .mask = 0x1,
2662                 .shift = 27,
2663                 },
2664         .hw.init = &(struct clk_init_data){
2665                 .name = "cts_i958",
2666                 .ops = &clk_regmap_mux_ops,
2667                 .parent_hws = (const struct clk_hw *[]) {
2668                         &meson8b_cts_amclk.hw,
2669                         &meson8b_cts_mclk_i958.hw
2670                 },
2671                 .num_parents = 2,
2672                 /*
2673                  * The parent is specific to origin of the audio data. Let the
2674                  * consumer choose the appropriate parent.
2675                  */
2676                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2677         },
2678 };
2679
2680 #define MESON_GATE(_name, _reg, _bit) \
2681         MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2682
2683 /* Everything Else (EE) domain gates */
2684
2685 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
2686 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
2687 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
2688 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
2689 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
2690 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
2691 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
2692 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
2693 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
2694 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
2695 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
2696 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
2697 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
2698 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
2699 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
2700 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
2701 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
2702 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
2703 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
2704
2705 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
2706 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
2707 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
2708 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
2709 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
2710 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
2711 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
2712 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
2713 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
2714 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
2715 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
2716 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
2717 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
2718 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
2719 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
2720 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
2721 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
2722
2723 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2724 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2725 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2726 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2727 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2728 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2729 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
2730 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
2731 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
2732 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
2733 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
2734 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2735 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
2736
2737 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
2738 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
2739 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2740 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2741 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
2742 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2743 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
2744 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
2745 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
2746 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
2747 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
2748 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
2749 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2750 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
2751 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
2752 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
2753
2754 /* AIU gates */
2755 #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
2756         MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
2757
2758 static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
2759 static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2760 static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2761 static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2762 static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2763 static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2764 static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2765 static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
2766
2767 /* Always On (AO) domain gates */
2768
2769 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
2770 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
2771 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
2772 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
2773
2774 static struct clk_hw *meson8_hw_clks[] = {
2775         [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2776         [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2777         [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2778         [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2779         [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2780         [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2781         [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2782         [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2783         [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2784         [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2785         [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2786         [CLKID_CLK81] = &meson8b_clk81.hw,
2787         [CLKID_DDR]                 = &meson8b_ddr.hw,
2788         [CLKID_DOS]                 = &meson8b_dos.hw,
2789         [CLKID_ISA]                 = &meson8b_isa.hw,
2790         [CLKID_PL301]               = &meson8b_pl301.hw,
2791         [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2792         [CLKID_SPICC]               = &meson8b_spicc.hw,
2793         [CLKID_I2C]                 = &meson8b_i2c.hw,
2794         [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2795         [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2796         [CLKID_RNG0]                = &meson8b_rng0.hw,
2797         [CLKID_UART0]               = &meson8b_uart0.hw,
2798         [CLKID_SDHC]                = &meson8b_sdhc.hw,
2799         [CLKID_STREAM]              = &meson8b_stream.hw,
2800         [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2801         [CLKID_SDIO]                = &meson8b_sdio.hw,
2802         [CLKID_ABUF]                = &meson8b_abuf.hw,
2803         [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2804         [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2805         [CLKID_SPI]                 = &meson8b_spi.hw,
2806         [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2807         [CLKID_ETH]                 = &meson8b_eth.hw,
2808         [CLKID_DEMUX]               = &meson8b_demux.hw,
2809         [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2810         [CLKID_IEC958]              = &meson8b_iec958.hw,
2811         [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2812         [CLKID_AMCLK]               = &meson8b_amclk.hw,
2813         [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2814         [CLKID_MIXER]               = &meson8b_mixer.hw,
2815         [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2816         [CLKID_ADC]                 = &meson8b_adc.hw,
2817         [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2818         [CLKID_AIU]                 = &meson8b_aiu.hw,
2819         [CLKID_UART1]               = &meson8b_uart1.hw,
2820         [CLKID_G2D]                 = &meson8b_g2d.hw,
2821         [CLKID_USB0]                = &meson8b_usb0.hw,
2822         [CLKID_USB1]                = &meson8b_usb1.hw,
2823         [CLKID_RESET]               = &meson8b_reset.hw,
2824         [CLKID_NAND]                = &meson8b_nand.hw,
2825         [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2826         [CLKID_USB]                 = &meson8b_usb.hw,
2827         [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2828         [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2829         [CLKID_EFUSE]               = &meson8b_efuse.hw,
2830         [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2831         [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2832         [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2833         [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2834         [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2835         [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2836         [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2837         [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2838         [CLKID_DVIN]                = &meson8b_dvin.hw,
2839         [CLKID_UART2]               = &meson8b_uart2.hw,
2840         [CLKID_SANA]                = &meson8b_sana.hw,
2841         [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2842         [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2843         [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2844         [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2845         [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2846         [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2847         [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2848         [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2849         [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2850         [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2851         [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2852         [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2853         [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2854         [CLKID_RNG1]                = &meson8b_rng1.hw,
2855         [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2856         [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2857         [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2858         [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2859         [CLKID_EDP]                 = &meson8b_edp.hw,
2860         [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
2861         [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
2862         [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
2863         [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
2864         [CLKID_MPLL0]               = &meson8b_mpll0.hw,
2865         [CLKID_MPLL1]               = &meson8b_mpll1.hw,
2866         [CLKID_MPLL2]               = &meson8b_mpll2.hw,
2867         [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
2868         [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
2869         [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
2870         [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
2871         [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
2872         [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
2873         [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
2874         [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
2875         [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
2876         [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
2877         [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
2878         [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
2879         [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
2880         [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
2881         [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
2882         [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
2883         [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
2884         [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
2885         [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
2886         [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
2887         [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
2888         [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
2889         [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
2890         [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
2891         [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
2892         [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
2893         [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
2894         [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
2895         [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
2896         [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
2897         [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
2898         [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
2899         [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
2900         [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
2901         [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
2902         [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
2903         [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
2904         [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
2905         [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
2906         [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
2907         [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
2908         [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
2909         [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
2910         [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
2911         [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
2912         [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
2913         [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
2914         [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
2915         [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
2916         [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
2917         [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
2918         [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
2919         [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
2920         [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
2921         [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
2922         [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
2923         [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
2924         [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
2925         [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
2926         [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
2927         [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
2928         [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
2929         [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
2930         [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
2931         [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
2932         [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
2933         [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
2934         [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
2935         [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
2936         [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
2937         [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
2938         [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
2939         [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
2940         [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
2941         [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
2942         [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
2943         [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
2944         [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
2945         [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
2946         [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
2947         [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
2948         [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
2949         [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
2950         [CLKID_MALI]                = &meson8b_mali_0.hw,
2951         [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
2952         [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
2953         [CLKID_VPU]                 = &meson8b_vpu_0.hw,
2954         [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
2955         [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
2956         [CLKID_VDEC_1]              = &meson8b_vdec_1_1.hw,
2957         [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
2958         [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
2959         [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
2960         [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
2961         [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
2962         [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
2963         [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
2964         [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
2965         [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
2966         [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
2967         [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
2968         [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
2969         [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
2970         [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
2971         [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
2972         [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
2973         [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
2974         [CLKID_VID_PLL_LVDS_EN]     = &meson8b_vid_pll_lvds_en.hw,
2975         [CLKID_HDMI_PLL_DCO_IN]     = &hdmi_pll_dco_in.hw,
2976 };
2977
2978 static struct clk_hw *meson8b_hw_clks[] = {
2979         [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2980         [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2981         [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2982         [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2983         [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2984         [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2985         [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2986         [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2987         [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2988         [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2989         [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2990         [CLKID_CLK81] = &meson8b_clk81.hw,
2991         [CLKID_DDR]                 = &meson8b_ddr.hw,
2992         [CLKID_DOS]                 = &meson8b_dos.hw,
2993         [CLKID_ISA]                 = &meson8b_isa.hw,
2994         [CLKID_PL301]               = &meson8b_pl301.hw,
2995         [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2996         [CLKID_SPICC]               = &meson8b_spicc.hw,
2997         [CLKID_I2C]                 = &meson8b_i2c.hw,
2998         [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2999         [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
3000         [CLKID_RNG0]                = &meson8b_rng0.hw,
3001         [CLKID_UART0]               = &meson8b_uart0.hw,
3002         [CLKID_SDHC]                = &meson8b_sdhc.hw,
3003         [CLKID_STREAM]              = &meson8b_stream.hw,
3004         [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
3005         [CLKID_SDIO]                = &meson8b_sdio.hw,
3006         [CLKID_ABUF]                = &meson8b_abuf.hw,
3007         [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
3008         [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
3009         [CLKID_SPI]                 = &meson8b_spi.hw,
3010         [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
3011         [CLKID_ETH]                 = &meson8b_eth.hw,
3012         [CLKID_DEMUX]               = &meson8b_demux.hw,
3013         [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
3014         [CLKID_IEC958]              = &meson8b_iec958.hw,
3015         [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
3016         [CLKID_AMCLK]               = &meson8b_amclk.hw,
3017         [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
3018         [CLKID_MIXER]               = &meson8b_mixer.hw,
3019         [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
3020         [CLKID_ADC]                 = &meson8b_adc.hw,
3021         [CLKID_BLKMV]               = &meson8b_blkmv.hw,
3022         [CLKID_AIU]                 = &meson8b_aiu.hw,
3023         [CLKID_UART1]               = &meson8b_uart1.hw,
3024         [CLKID_G2D]                 = &meson8b_g2d.hw,
3025         [CLKID_USB0]                = &meson8b_usb0.hw,
3026         [CLKID_USB1]                = &meson8b_usb1.hw,
3027         [CLKID_RESET]               = &meson8b_reset.hw,
3028         [CLKID_NAND]                = &meson8b_nand.hw,
3029         [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
3030         [CLKID_USB]                 = &meson8b_usb.hw,
3031         [CLKID_VDIN1]               = &meson8b_vdin1.hw,
3032         [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
3033         [CLKID_EFUSE]               = &meson8b_efuse.hw,
3034         [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
3035         [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
3036         [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
3037         [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
3038         [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
3039         [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
3040         [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
3041         [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
3042         [CLKID_DVIN]                = &meson8b_dvin.hw,
3043         [CLKID_UART2]               = &meson8b_uart2.hw,
3044         [CLKID_SANA]                = &meson8b_sana.hw,
3045         [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
3046         [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3047         [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
3048         [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
3049         [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
3050         [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
3051         [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
3052         [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
3053         [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
3054         [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
3055         [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
3056         [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
3057         [CLKID_ENC480P]             = &meson8b_enc480p.hw,
3058         [CLKID_RNG1]                = &meson8b_rng1.hw,
3059         [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
3060         [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
3061         [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
3062         [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
3063         [CLKID_EDP]                 = &meson8b_edp.hw,
3064         [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
3065         [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
3066         [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
3067         [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
3068         [CLKID_MPLL0]               = &meson8b_mpll0.hw,
3069         [CLKID_MPLL1]               = &meson8b_mpll1.hw,
3070         [CLKID_MPLL2]               = &meson8b_mpll2.hw,
3071         [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
3072         [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
3073         [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
3074         [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
3075         [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
3076         [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
3077         [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
3078         [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
3079         [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
3080         [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
3081         [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
3082         [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
3083         [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
3084         [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
3085         [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
3086         [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
3087         [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
3088         [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
3089         [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
3090         [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
3091         [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
3092         [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
3093         [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
3094         [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
3095         [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
3096         [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
3097         [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
3098         [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
3099         [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
3100         [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
3101         [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
3102         [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
3103         [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
3104         [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
3105         [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
3106         [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
3107         [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
3108         [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
3109         [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
3110         [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
3111         [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
3112         [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
3113         [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
3114         [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
3115         [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
3116         [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
3117         [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
3118         [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
3119         [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
3120         [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
3121         [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
3122         [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
3123         [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
3124         [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
3125         [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
3126         [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
3127         [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
3128         [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
3129         [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
3130         [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
3131         [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
3132         [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
3133         [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
3134         [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
3135         [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
3136         [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
3137         [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
3138         [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
3139         [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
3140         [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
3141         [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
3142         [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
3143         [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
3144         [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
3145         [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
3146         [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
3147         [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
3148         [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
3149         [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
3150         [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
3151         [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
3152         [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
3153         [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
3154         [CLKID_MALI_0]              = &meson8b_mali_0.hw,
3155         [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
3156         [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
3157         [CLKID_MALI_1]              = &meson8b_mali_1.hw,
3158         [CLKID_MALI]                = &meson8b_mali.hw,
3159         [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
3160         [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
3161         [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
3162         [CLKID_VPU_1_SEL]           = &meson8b_vpu_1_sel.hw,
3163         [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
3164         [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
3165         [CLKID_VPU]                 = &meson8b_vpu.hw,
3166         [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
3167         [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
3168         [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
3169         [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
3170         [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
3171         [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
3172         [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
3173         [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
3174         [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
3175         [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
3176         [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
3177         [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
3178         [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
3179         [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
3180         [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
3181         [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
3182         [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
3183         [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
3184         [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
3185         [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
3186         [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3187         [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3188         [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3189         [CLKID_VID_PLL_LVDS_EN]     = &meson8b_vid_pll_lvds_en.hw,
3190         [CLKID_HDMI_PLL_DCO_IN]     = &hdmi_pll_dco_in.hw,
3191 };
3192
3193 static struct clk_hw *meson8m2_hw_clks[] = {
3194         [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3195         [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3196         [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3197         [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3198         [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3199         [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3200         [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3201         [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3202         [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3203         [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
3204         [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
3205         [CLKID_CLK81] = &meson8b_clk81.hw,
3206         [CLKID_DDR]                 = &meson8b_ddr.hw,
3207         [CLKID_DOS]                 = &meson8b_dos.hw,
3208         [CLKID_ISA]                 = &meson8b_isa.hw,
3209         [CLKID_PL301]               = &meson8b_pl301.hw,
3210         [CLKID_PERIPHS]             = &meson8b_periphs.hw,
3211         [CLKID_SPICC]               = &meson8b_spicc.hw,
3212         [CLKID_I2C]                 = &meson8b_i2c.hw,
3213         [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
3214         [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
3215         [CLKID_RNG0]                = &meson8b_rng0.hw,
3216         [CLKID_UART0]               = &meson8b_uart0.hw,
3217         [CLKID_SDHC]                = &meson8b_sdhc.hw,
3218         [CLKID_STREAM]              = &meson8b_stream.hw,
3219         [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
3220         [CLKID_SDIO]                = &meson8b_sdio.hw,
3221         [CLKID_ABUF]                = &meson8b_abuf.hw,
3222         [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
3223         [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
3224         [CLKID_SPI]                 = &meson8b_spi.hw,
3225         [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
3226         [CLKID_ETH]                 = &meson8b_eth.hw,
3227         [CLKID_DEMUX]               = &meson8b_demux.hw,
3228         [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
3229         [CLKID_IEC958]              = &meson8b_iec958.hw,
3230         [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
3231         [CLKID_AMCLK]               = &meson8b_amclk.hw,
3232         [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
3233         [CLKID_MIXER]               = &meson8b_mixer.hw,
3234         [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
3235         [CLKID_ADC]                 = &meson8b_adc.hw,
3236         [CLKID_BLKMV]               = &meson8b_blkmv.hw,
3237         [CLKID_AIU]                 = &meson8b_aiu.hw,
3238         [CLKID_UART1]               = &meson8b_uart1.hw,
3239         [CLKID_G2D]                 = &meson8b_g2d.hw,
3240         [CLKID_USB0]                = &meson8b_usb0.hw,
3241         [CLKID_USB1]                = &meson8b_usb1.hw,
3242         [CLKID_RESET]               = &meson8b_reset.hw,
3243         [CLKID_NAND]                = &meson8b_nand.hw,
3244         [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
3245         [CLKID_USB]                 = &meson8b_usb.hw,
3246         [CLKID_VDIN1]               = &meson8b_vdin1.hw,
3247         [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
3248         [CLKID_EFUSE]               = &meson8b_efuse.hw,
3249         [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
3250         [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
3251         [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
3252         [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
3253         [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
3254         [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
3255         [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
3256         [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
3257         [CLKID_DVIN]                = &meson8b_dvin.hw,
3258         [CLKID_UART2]               = &meson8b_uart2.hw,
3259         [CLKID_SANA]                = &meson8b_sana.hw,
3260         [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
3261         [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3262         [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
3263         [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
3264         [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
3265         [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
3266         [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
3267         [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
3268         [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
3269         [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
3270         [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
3271         [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
3272         [CLKID_ENC480P]             = &meson8b_enc480p.hw,
3273         [CLKID_RNG1]                = &meson8b_rng1.hw,
3274         [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
3275         [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
3276         [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
3277         [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
3278         [CLKID_EDP]                 = &meson8b_edp.hw,
3279         [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
3280         [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
3281         [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
3282         [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
3283         [CLKID_MPLL0]               = &meson8b_mpll0.hw,
3284         [CLKID_MPLL1]               = &meson8b_mpll1.hw,
3285         [CLKID_MPLL2]               = &meson8b_mpll2.hw,
3286         [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
3287         [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
3288         [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
3289         [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
3290         [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
3291         [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
3292         [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
3293         [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
3294         [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
3295         [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
3296         [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
3297         [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
3298         [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
3299         [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
3300         [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
3301         [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
3302         [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
3303         [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
3304         [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
3305         [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
3306         [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
3307         [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
3308         [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
3309         [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
3310         [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
3311         [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
3312         [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
3313         [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
3314         [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
3315         [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
3316         [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
3317         [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
3318         [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
3319         [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
3320         [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
3321         [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
3322         [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
3323         [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
3324         [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
3325         [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
3326         [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
3327         [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
3328         [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
3329         [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
3330         [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
3331         [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
3332         [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
3333         [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
3334         [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
3335         [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
3336         [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
3337         [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
3338         [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
3339         [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
3340         [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
3341         [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
3342         [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
3343         [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
3344         [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
3345         [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
3346         [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
3347         [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
3348         [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
3349         [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
3350         [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
3351         [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
3352         [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
3353         [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
3354         [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
3355         [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
3356         [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
3357         [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
3358         [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
3359         [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
3360         [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
3361         [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
3362         [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
3363         [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
3364         [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
3365         [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
3366         [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
3367         [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
3368         [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
3369         [CLKID_MALI_0]              = &meson8b_mali_0.hw,
3370         [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
3371         [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
3372         [CLKID_MALI_1]              = &meson8b_mali_1.hw,
3373         [CLKID_MALI]                = &meson8b_mali.hw,
3374         [CLKID_GP_PLL_DCO]          = &meson8m2_gp_pll_dco.hw,
3375         [CLKID_GP_PLL]              = &meson8m2_gp_pll.hw,
3376         [CLKID_VPU_0_SEL]           = &meson8m2_vpu_0_sel.hw,
3377         [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
3378         [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
3379         [CLKID_VPU_1_SEL]           = &meson8m2_vpu_1_sel.hw,
3380         [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
3381         [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
3382         [CLKID_VPU]                 = &meson8b_vpu.hw,
3383         [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
3384         [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
3385         [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
3386         [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
3387         [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
3388         [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
3389         [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
3390         [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
3391         [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
3392         [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
3393         [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
3394         [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
3395         [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
3396         [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
3397         [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
3398         [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
3399         [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
3400         [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
3401         [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
3402         [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
3403         [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3404         [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3405         [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3406         [CLKID_VID_PLL_LVDS_EN]     = &meson8b_vid_pll_lvds_en.hw,
3407         [CLKID_HDMI_PLL_DCO_IN]     = &hdmi_pll_dco_in.hw,
3408 };
3409
3410 static struct clk_regmap *const meson8b_clk_regmaps[] = {
3411         &meson8b_clk81,
3412         &meson8b_ddr,
3413         &meson8b_dos,
3414         &meson8b_isa,
3415         &meson8b_pl301,
3416         &meson8b_periphs,
3417         &meson8b_spicc,
3418         &meson8b_i2c,
3419         &meson8b_sar_adc,
3420         &meson8b_smart_card,
3421         &meson8b_rng0,
3422         &meson8b_uart0,
3423         &meson8b_sdhc,
3424         &meson8b_stream,
3425         &meson8b_async_fifo,
3426         &meson8b_sdio,
3427         &meson8b_abuf,
3428         &meson8b_hiu_iface,
3429         &meson8b_assist_misc,
3430         &meson8b_spi,
3431         &meson8b_i2s_spdif,
3432         &meson8b_eth,
3433         &meson8b_demux,
3434         &meson8b_aiu_glue,
3435         &meson8b_iec958,
3436         &meson8b_i2s_out,
3437         &meson8b_amclk,
3438         &meson8b_aififo2,
3439         &meson8b_mixer,
3440         &meson8b_mixer_iface,
3441         &meson8b_adc,
3442         &meson8b_blkmv,
3443         &meson8b_aiu,
3444         &meson8b_uart1,
3445         &meson8b_g2d,
3446         &meson8b_usb0,
3447         &meson8b_usb1,
3448         &meson8b_reset,
3449         &meson8b_nand,
3450         &meson8b_dos_parser,
3451         &meson8b_usb,
3452         &meson8b_vdin1,
3453         &meson8b_ahb_arb0,
3454         &meson8b_efuse,
3455         &meson8b_boot_rom,
3456         &meson8b_ahb_data_bus,
3457         &meson8b_ahb_ctrl_bus,
3458         &meson8b_hdmi_intr_sync,
3459         &meson8b_hdmi_pclk,
3460         &meson8b_usb1_ddr_bridge,
3461         &meson8b_usb0_ddr_bridge,
3462         &meson8b_mmc_pclk,
3463         &meson8b_dvin,
3464         &meson8b_uart2,
3465         &meson8b_sana,
3466         &meson8b_vpu_intr,
3467         &meson8b_sec_ahb_ahb3_bridge,
3468         &meson8b_clk81_a9,
3469         &meson8b_vclk2_venci0,
3470         &meson8b_vclk2_venci1,
3471         &meson8b_vclk2_vencp0,
3472         &meson8b_vclk2_vencp1,
3473         &meson8b_gclk_venci_int,
3474         &meson8b_gclk_vencp_int,
3475         &meson8b_dac_clk,
3476         &meson8b_aoclk_gate,
3477         &meson8b_iec958_gate,
3478         &meson8b_enc480p,
3479         &meson8b_rng1,
3480         &meson8b_gclk_vencl_int,
3481         &meson8b_vclk2_venclmcc,
3482         &meson8b_vclk2_vencl,
3483         &meson8b_vclk2_other,
3484         &meson8b_edp,
3485         &meson8b_ao_media_cpu,
3486         &meson8b_ao_ahb_sram,
3487         &meson8b_ao_ahb_bus,
3488         &meson8b_ao_iface,
3489         &meson8b_mpeg_clk_div,
3490         &meson8b_mpeg_clk_sel,
3491         &meson8b_mpll0,
3492         &meson8b_mpll1,
3493         &meson8b_mpll2,
3494         &meson8b_mpll0_div,
3495         &meson8b_mpll1_div,
3496         &meson8b_mpll2_div,
3497         &meson8b_fixed_pll,
3498         &meson8b_sys_pll,
3499         &meson8b_cpu_in_sel,
3500         &meson8b_cpu_scale_div,
3501         &meson8b_cpu_scale_out_sel,
3502         &meson8b_cpu_clk,
3503         &meson8b_mpll_prediv,
3504         &meson8b_fclk_div2,
3505         &meson8b_fclk_div3,
3506         &meson8b_fclk_div4,
3507         &meson8b_fclk_div5,
3508         &meson8b_fclk_div7,
3509         &meson8b_nand_clk_sel,
3510         &meson8b_nand_clk_div,
3511         &meson8b_nand_clk_gate,
3512         &meson8b_fixed_pll_dco,
3513         &meson8b_hdmi_pll_dco,
3514         &meson8b_sys_pll_dco,
3515         &meson8b_apb_clk_sel,
3516         &meson8b_apb_clk_gate,
3517         &meson8b_periph_clk_sel,
3518         &meson8b_periph_clk_gate,
3519         &meson8b_axi_clk_sel,
3520         &meson8b_axi_clk_gate,
3521         &meson8b_l2_dram_clk_sel,
3522         &meson8b_l2_dram_clk_gate,
3523         &meson8b_hdmi_pll_lvds_out,
3524         &meson8b_hdmi_pll_hdmi_out,
3525         &meson8b_vid_pll_in_sel,
3526         &meson8b_vid_pll_in_en,
3527         &meson8b_vid_pll_pre_div,
3528         &meson8b_vid_pll_post_div,
3529         &meson8b_vid_pll,
3530         &meson8b_vid_pll_final_div,
3531         &meson8b_vclk_in_sel,
3532         &meson8b_vclk_in_en,
3533         &meson8b_vclk_en,
3534         &meson8b_vclk_div1_gate,
3535         &meson8b_vclk_div2_div_gate,
3536         &meson8b_vclk_div4_div_gate,
3537         &meson8b_vclk_div6_div_gate,
3538         &meson8b_vclk_div12_div_gate,
3539         &meson8b_vclk2_in_sel,
3540         &meson8b_vclk2_clk_in_en,
3541         &meson8b_vclk2_clk_en,
3542         &meson8b_vclk2_div1_gate,
3543         &meson8b_vclk2_div2_div_gate,
3544         &meson8b_vclk2_div4_div_gate,
3545         &meson8b_vclk2_div6_div_gate,
3546         &meson8b_vclk2_div12_div_gate,
3547         &meson8b_cts_enct_sel,
3548         &meson8b_cts_enct,
3549         &meson8b_cts_encp_sel,
3550         &meson8b_cts_encp,
3551         &meson8b_cts_enci_sel,
3552         &meson8b_cts_enci,
3553         &meson8b_hdmi_tx_pixel_sel,
3554         &meson8b_hdmi_tx_pixel,
3555         &meson8b_cts_encl_sel,
3556         &meson8b_cts_encl,
3557         &meson8b_cts_vdac0_sel,
3558         &meson8b_cts_vdac0,
3559         &meson8b_hdmi_sys_sel,
3560         &meson8b_hdmi_sys_div,
3561         &meson8b_hdmi_sys,
3562         &meson8b_mali_0_sel,
3563         &meson8b_mali_0_div,
3564         &meson8b_mali_0,
3565         &meson8b_mali_1_sel,
3566         &meson8b_mali_1_div,
3567         &meson8b_mali_1,
3568         &meson8b_mali,
3569         &meson8m2_gp_pll_dco,
3570         &meson8m2_gp_pll,
3571         &meson8b_vpu_0_sel,
3572         &meson8m2_vpu_0_sel,
3573         &meson8b_vpu_0_div,
3574         &meson8b_vpu_0,
3575         &meson8b_vpu_1_sel,
3576         &meson8m2_vpu_1_sel,
3577         &meson8b_vpu_1_div,
3578         &meson8b_vpu_1,
3579         &meson8b_vpu,
3580         &meson8b_vdec_1_sel,
3581         &meson8b_vdec_1_1_div,
3582         &meson8b_vdec_1_1,
3583         &meson8b_vdec_1_2_div,
3584         &meson8b_vdec_1_2,
3585         &meson8b_vdec_1,
3586         &meson8b_vdec_hcodec_sel,
3587         &meson8b_vdec_hcodec_div,
3588         &meson8b_vdec_hcodec,
3589         &meson8b_vdec_2_sel,
3590         &meson8b_vdec_2_div,
3591         &meson8b_vdec_2,
3592         &meson8b_vdec_hevc_sel,
3593         &meson8b_vdec_hevc_div,
3594         &meson8b_vdec_hevc_en,
3595         &meson8b_vdec_hevc,
3596         &meson8b_cts_amclk,
3597         &meson8b_cts_amclk_sel,
3598         &meson8b_cts_amclk_div,
3599         &meson8b_cts_mclk_i958_sel,
3600         &meson8b_cts_mclk_i958_div,
3601         &meson8b_cts_mclk_i958,
3602         &meson8b_cts_i958,
3603         &meson8b_vid_pll_lvds_en,
3604 };
3605
3606 static const struct meson8b_clk_reset_line {
3607         u32 reg;
3608         u8 bit_idx;
3609         bool active_low;
3610 } meson8b_clk_reset_bits[] = {
3611         [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
3612                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3613                 .bit_idx = 30,
3614                 .active_low = false,
3615         },
3616         [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
3617                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3618                 .bit_idx = 29,
3619                 .active_low = false,
3620         },
3621         [CLKC_RESET_SCU_SOFT_RESET] = {
3622                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3623                 .bit_idx = 28,
3624                 .active_low = false,
3625         },
3626         [CLKC_RESET_CPU3_SOFT_RESET] = {
3627                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3628                 .bit_idx = 27,
3629                 .active_low = false,
3630         },
3631         [CLKC_RESET_CPU2_SOFT_RESET] = {
3632                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3633                 .bit_idx = 26,
3634                 .active_low = false,
3635         },
3636         [CLKC_RESET_CPU1_SOFT_RESET] = {
3637                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3638                 .bit_idx = 25,
3639                 .active_low = false,
3640         },
3641         [CLKC_RESET_CPU0_SOFT_RESET] = {
3642                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3643                 .bit_idx = 24,
3644                 .active_low = false,
3645         },
3646         [CLKC_RESET_A5_GLOBAL_RESET] = {
3647                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3648                 .bit_idx = 18,
3649                 .active_low = false,
3650         },
3651         [CLKC_RESET_A5_AXI_SOFT_RESET] = {
3652                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3653                 .bit_idx = 17,
3654                 .active_low = false,
3655         },
3656         [CLKC_RESET_A5_ABP_SOFT_RESET] = {
3657                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3658                 .bit_idx = 16,
3659                 .active_low = false,
3660         },
3661         [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
3662                 .reg = HHI_SYS_CPU_CLK_CNTL1,
3663                 .bit_idx = 30,
3664                 .active_low = false,
3665         },
3666         [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
3667                 .reg = HHI_VID_CLK_CNTL,
3668                 .bit_idx = 15,
3669                 .active_low = false,
3670         },
3671         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
3672                 .reg = HHI_VID_DIVIDER_CNTL,
3673                 .bit_idx = 7,
3674                 .active_low = false,
3675         },
3676         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
3677                 .reg = HHI_VID_DIVIDER_CNTL,
3678                 .bit_idx = 3,
3679                 .active_low = false,
3680         },
3681         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
3682                 .reg = HHI_VID_DIVIDER_CNTL,
3683                 .bit_idx = 1,
3684                 .active_low = true,
3685         },
3686         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
3687                 .reg = HHI_VID_DIVIDER_CNTL,
3688                 .bit_idx = 0,
3689                 .active_low = true,
3690         },
3691 };
3692
3693 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
3694                                     unsigned long id, bool assert)
3695 {
3696         struct meson8b_clk_reset *meson8b_clk_reset =
3697                 container_of(rcdev, struct meson8b_clk_reset, reset);
3698         const struct meson8b_clk_reset_line *reset;
3699         unsigned int value = 0;
3700
3701         if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
3702                 return -EINVAL;
3703
3704         reset = &meson8b_clk_reset_bits[id];
3705
3706         if (assert != reset->active_low)
3707                 value = BIT(reset->bit_idx);
3708
3709         regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
3710                            BIT(reset->bit_idx), value);
3711
3712         return 0;
3713 }
3714
3715 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
3716                                      unsigned long id)
3717 {
3718         return meson8b_clk_reset_update(rcdev, id, true);
3719 }
3720
3721 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
3722                                        unsigned long id)
3723 {
3724         return meson8b_clk_reset_update(rcdev, id, false);
3725 }
3726
3727 static const struct reset_control_ops meson8b_clk_reset_ops = {
3728         .assert = meson8b_clk_reset_assert,
3729         .deassert = meson8b_clk_reset_deassert,
3730 };
3731
3732 struct meson8b_nb_data {
3733         struct notifier_block nb;
3734         struct clk_hw *cpu_clk;
3735 };
3736
3737 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
3738                                        unsigned long event, void *data)
3739 {
3740         struct meson8b_nb_data *nb_data =
3741                 container_of(nb, struct meson8b_nb_data, nb);
3742         struct clk_hw *parent_clk;
3743         int ret;
3744
3745         switch (event) {
3746         case PRE_RATE_CHANGE:
3747                 /* xtal */
3748                 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
3749                 break;
3750
3751         case POST_RATE_CHANGE:
3752                 /* cpu_scale_out_sel */
3753                 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
3754                 break;
3755
3756         default:
3757                 return NOTIFY_DONE;
3758         }
3759
3760         ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
3761         if (ret)
3762                 return notifier_from_errno(ret);
3763
3764         udelay(100);
3765
3766         return NOTIFY_OK;
3767 }
3768
3769 static struct meson8b_nb_data meson8b_cpu_nb_data = {
3770         .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
3771 };
3772
3773 static struct meson_clk_hw_data meson8_clks = {
3774         .hws = meson8_hw_clks,
3775         .num = ARRAY_SIZE(meson8_hw_clks),
3776 };
3777
3778 static struct meson_clk_hw_data meson8b_clks = {
3779         .hws = meson8b_hw_clks,
3780         .num = ARRAY_SIZE(meson8b_hw_clks),
3781 };
3782
3783 static struct meson_clk_hw_data meson8m2_clks = {
3784         .hws = meson8m2_hw_clks,
3785         .num = ARRAY_SIZE(meson8m2_hw_clks),
3786 };
3787
3788 static void __init meson8b_clkc_init_common(struct device_node *np,
3789                                             struct meson_clk_hw_data *hw_clks)
3790 {
3791         struct meson8b_clk_reset *rstc;
3792         struct device_node *parent_np;
3793         const char *notifier_clk_name;
3794         struct clk *notifier_clk;
3795         struct regmap *map;
3796         int i, ret;
3797
3798         parent_np = of_get_parent(np);
3799         map = syscon_node_to_regmap(parent_np);
3800         of_node_put(parent_np);
3801         if (IS_ERR(map)) {
3802                 pr_err("failed to get HHI regmap - Trying obsolete regs\n");
3803                 return;
3804         }
3805
3806         rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
3807         if (!rstc)
3808                 return;
3809
3810         /* Reset Controller */
3811         rstc->regmap = map;
3812         rstc->reset.ops = &meson8b_clk_reset_ops;
3813         rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
3814         rstc->reset.of_node = np;
3815         ret = reset_controller_register(&rstc->reset);
3816         if (ret) {
3817                 pr_err("%s: Failed to register clkc reset controller: %d\n",
3818                        __func__, ret);
3819                 return;
3820         }
3821
3822         /* Populate regmap for the regmap backed clocks */
3823         for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
3824                 meson8b_clk_regmaps[i]->map = map;
3825
3826         /*
3827          * register all clks and start with the first used ID (which is
3828          * CLKID_PLL_FIXED)
3829          */
3830         for (i = CLKID_PLL_FIXED; i < hw_clks->num; i++) {
3831                 /* array might be sparse */
3832                 if (!hw_clks->hws[i])
3833                         continue;
3834
3835                 ret = of_clk_hw_register(np, hw_clks->hws[i]);
3836                 if (ret)
3837                         return;
3838         }
3839
3840         meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK];
3841
3842         /*
3843          * FIXME we shouldn't program the muxes in notifier handlers. The
3844          * tricky programming sequence will be handled by the forthcoming
3845          * coordinated clock rates mechanism once that feature is released.
3846          */
3847         notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
3848         notifier_clk = __clk_lookup(notifier_clk_name);
3849         ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
3850         if (ret) {
3851                 pr_err("%s: failed to register the CPU clock notifier\n",
3852                        __func__);
3853                 return;
3854         }
3855
3856         ret = of_clk_add_hw_provider(np, meson_clk_hw_get, hw_clks);
3857         if (ret)
3858                 pr_err("%s: failed to register clock provider\n", __func__);
3859 }
3860
3861 static void __init meson8_clkc_init(struct device_node *np)
3862 {
3863         return meson8b_clkc_init_common(np, &meson8_clks);
3864 }
3865
3866 static void __init meson8b_clkc_init(struct device_node *np)
3867 {
3868         return meson8b_clkc_init_common(np, &meson8b_clks);
3869 }
3870
3871 static void __init meson8m2_clkc_init(struct device_node *np)
3872 {
3873         return meson8b_clkc_init_common(np, &meson8m2_clks);
3874 }
3875
3876 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3877                       meson8_clkc_init);
3878 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3879                       meson8b_clkc_init);
3880 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
3881                       meson8m2_clkc_init);