drivers/base/regmap/regmap-irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // regmap based irq_chip
   4 //
   5 // Copyright 2011 Wolfson Microelectronics plc
   6 //
   7 // Author: Mark Brown <[email protected]>
   8
   9 #include <linux/device.h>
  10 #include <linux/export.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/irqdomain.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17
  18 #include "internal.h"
  19
  20 struct regmap_irq_chip_data {
  21         struct mutex lock;
  22         struct irq_chip irq_chip;
  23
  24         struct regmap *map;
  25         const struct regmap_irq_chip *chip;
  26
  27         int irq_base;
  28         struct irq_domain *domain;
  29
  30         int irq;
  31         int wake_count;
  32
  33         void *status_reg_buf;
  34         unsigned int *main_status_buf;
  35         unsigned int *status_buf;
  36         unsigned int *mask_buf;
  37         unsigned int *mask_buf_def;
  38         unsigned int *wake_buf;
  39         unsigned int *type_buf;
  40         unsigned int *type_buf_def;
  41         unsigned int **config_buf;
  42
  43         unsigned int irq_reg_stride;
  44
  45         unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data,
  46                                     unsigned int base, int index);
  47
  48         unsigned int clear_status:1;
  49 };
  50
  51 static inline const
  52 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
  53                                      int irq)
  54 {
  55         return &data->chip->irqs[irq];
  56 }
  57
  58 static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data)
  59 {
  60         struct regmap *map = data->map;
  61
  62         /*
  63          * While possible that a user-defined ->get_irq_reg() callback might
  64          * be linear enough to support bulk reads, most of the time it won't.
  65          * Therefore only allow them if the default callback is being used.
  66          */
  67         return data->irq_reg_stride == 1 && map->reg_stride == 1 &&
  68                data->get_irq_reg == regmap_irq_get_irq_reg_linear &&
  69                !map->use_single_read;
  70 }
  71
  72 static void regmap_irq_lock(struct irq_data *data)
  73 {
  74         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  75
  76         mutex_lock(&d->lock);
  77 }
  78
  79 static void regmap_irq_sync_unlock(struct irq_data *data)
  80 {
  81         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  82         struct regmap *map = d->map;
  83         int i, j, ret;
  84         u32 reg;
  85         u32 val;
  86
  87         if (d->chip->runtime_pm) {
  88                 ret = pm_runtime_get_sync(map->dev);
  89                 if (ret < 0)
  90                         dev_err(map->dev, "IRQ sync failed to resume: %d\n",
  91                                 ret);
  92         }
  93
  94         if (d->clear_status) {
  95                 for (i = 0; i < d->chip->num_regs; i++) {
  96                         reg = d->get_irq_reg(d, d->chip->status_base, i);
  97
  98                         ret = regmap_read(map, reg, &val);
  99                         if (ret)
 100                                 dev_err(d->map->dev,
 101                                         "Failed to clear the interrupt status bits\n");
 102                 }
 103
 104                 d->clear_status = false;
 105         }
 106
 107         /*
 108          * If there's been a change in the mask write it back to the
 109          * hardware.  We rely on the use of the regmap core cache to
 110          * suppress pointless writes.
 111          */
 112         for (i = 0; i < d->chip->num_regs; i++) {
 113                 if (d->chip->handle_mask_sync)
 114                         d->chip->handle_mask_sync(i, d->mask_buf_def[i],
 115                                                   d->mask_buf[i],
 116                                                   d->chip->irq_drv_data);
 117
 118                 if (d->chip->mask_base && !d->chip->handle_mask_sync) {
 119                         reg = d->get_irq_reg(d, d->chip->mask_base, i);
 120                         ret = regmap_update_bits(d->map, reg,
 121                                                  d->mask_buf_def[i],
 122                                                  d->mask_buf[i]);
 123                         if (ret)
 124                                 dev_err(d->map->dev, "Failed to sync masks in %x\n", reg);
 125                 }
 126
 127                 if (d->chip->unmask_base && !d->chip->handle_mask_sync) {
 128                         reg = d->get_irq_reg(d, d->chip->unmask_base, i);
 129                         ret = regmap_update_bits(d->map, reg,
 130                                         d->mask_buf_def[i], ~d->mask_buf[i]);
 131                         if (ret)
 132                                 dev_err(d->map->dev, "Failed to sync masks in %x\n",
 133                                         reg);
 134                 }
 135
 136                 reg = d->get_irq_reg(d, d->chip->wake_base, i);
 137                 if (d->wake_buf) {
 138                         if (d->chip->wake_invert)
 139                                 ret = regmap_update_bits(d->map, reg,
 140                                                          d->mask_buf_def[i],
 141                                                          ~d->wake_buf[i]);
 142                         else
 143                                 ret = regmap_update_bits(d->map, reg,
 144                                                          d->mask_buf_def[i],
 145                                                          d->wake_buf[i]);
 146                         if (ret != 0)
 147                                 dev_err(d->map->dev,
 148                                         "Failed to sync wakes in %x: %d\n",
 149                                         reg, ret);
 150                 }
 151
 152                 if (!d->chip->init_ack_masked)
 153                         continue;
 154                 /*
 155                  * Ack all the masked interrupts unconditionally,
 156                  * OR if there is masked interrupt which hasn't been Acked,
 157                  * it'll be ignored in irq handler, then may introduce irq storm
 158                  */
 159                 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
 160                         reg = d->get_irq_reg(d, d->chip->ack_base, i);
 161
 162                         /* some chips ack by write 0 */
 163                         if (d->chip->ack_invert)
 164                                 ret = regmap_write(map, reg, ~d->mask_buf[i]);
 165                         else
 166                                 ret = regmap_write(map, reg, d->mask_buf[i]);
 167                         if (d->chip->clear_ack) {
 168                                 if (d->chip->ack_invert && !ret)
 169                                         ret = regmap_write(map, reg, UINT_MAX);
 170                                 else if (!ret)
 171                                         ret = regmap_write(map, reg, 0);
 172                         }
 173                         if (ret != 0)
 174                                 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
 175                                         reg, ret);
 176                 }
 177         }
 178
 179         for (i = 0; i < d->chip->num_config_bases; i++) {
 180                 for (j = 0; j < d->chip->num_config_regs; j++) {
 181                         reg = d->get_irq_reg(d, d->chip->config_base[i], j);
 182                         ret = regmap_write(map, reg, d->config_buf[i][j]);
 183                         if (ret)
 184                                 dev_err(d->map->dev,
 185                                         "Failed to write config %x: %d\n",
 186                                         reg, ret);
 187                 }
 188         }
 189
 190         if (d->chip->runtime_pm)
 191                 pm_runtime_put(map->dev);
 192
 193         /* If we've changed our wakeup count propagate it to the parent */
 194         if (d->wake_count < 0)
 195                 for (i = d->wake_count; i < 0; i++)
 196                         irq_set_irq_wake(d->irq, 0);
 197         else if (d->wake_count > 0)
 198                 for (i = 0; i < d->wake_count; i++)
 199                         irq_set_irq_wake(d->irq, 1);
 200
 201         d->wake_count = 0;
 202
 203         mutex_unlock(&d->lock);
 204 }
 205
 206 static void regmap_irq_enable(struct irq_data *data)
 207 {
 208         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 209         struct regmap *map = d->map;
 210         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 211         unsigned int reg = irq_data->reg_offset / map->reg_stride;
 212         unsigned int mask;
 213
 214         /*
 215          * The type_in_mask flag means that the underlying hardware uses
 216          * separate mask bits for each interrupt trigger type, but we want
 217          * to have a single logical interrupt with a configurable type.
 218          *
 219          * If the interrupt we're enabling defines any supported types
 220          * then instead of using the regular mask bits for this interrupt,
 221          * use the value previously written to the type buffer at the
 222          * corresponding offset in regmap_irq_set_type().
 223          */
 224         if (d->chip->type_in_mask && irq_data->type.types_supported)
 225                 mask = d->type_buf[reg] & irq_data->mask;
 226         else
 227                 mask = irq_data->mask;
 228
 229         if (d->chip->clear_on_unmask)
 230                 d->clear_status = true;
 231
 232         d->mask_buf[reg] &= ~mask;
 233 }
 234
 235 static void regmap_irq_disable(struct irq_data *data)
 236 {
 237         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 238         struct regmap *map = d->map;
 239         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 240
 241         d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
 242 }
 243
 244 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 245 {
 246         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 247         struct regmap *map = d->map;
 248         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 249         int reg, ret;
 250         const struct regmap_irq_type *t = &irq_data->type;
 251
 252         if ((t->types_supported & type) != type)
 253                 return 0;
 254
 255         reg = t->type_reg_offset / map->reg_stride;
 256
 257         if (d->chip->type_in_mask) {
 258                 ret = regmap_irq_set_type_config_simple(&d->type_buf, type,
 259                                                         irq_data, reg, d->chip->irq_drv_data);
 260                 if (ret)
 261                         return ret;
 262         }
 263
 264         if (d->chip->set_type_config) {
 265                 ret = d->chip->set_type_config(d->config_buf, type, irq_data,
 266                                                reg, d->chip->irq_drv_data);
 267                 if (ret)
 268                         return ret;
 269         }
 270
 271         return 0;
 272 }
 273
 274 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
 275 {
 276         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 277         struct regmap *map = d->map;
 278         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 279
 280         if (on) {
 281                 if (d->wake_buf)
 282                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 283                                 &= ~irq_data->mask;
 284                 d->wake_count++;
 285         } else {
 286                 if (d->wake_buf)
 287                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 288                                 |= irq_data->mask;
 289                 d->wake_count--;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static const struct irq_chip regmap_irq_chip = {
 296         .irq_bus_lock           = regmap_irq_lock,
 297         .irq_bus_sync_unlock    = regmap_irq_sync_unlock,
 298         .irq_disable            = regmap_irq_disable,
 299         .irq_enable             = regmap_irq_enable,
 300         .irq_set_type           = regmap_irq_set_type,
 301         .irq_set_wake           = regmap_irq_set_wake,
 302 };
 303
 304 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 305                                            unsigned int b)
 306 {
 307         const struct regmap_irq_chip *chip = data->chip;
 308         const struct regmap_irq_sub_irq_map *subreg;
 309         struct regmap *map = data->map;
 310         unsigned int reg;
 311         int i, ret = 0;
 312
 313         if (!chip->sub_reg_offsets) {
 314                 reg = data->get_irq_reg(data, chip->status_base, b);
 315                 ret = regmap_read(map, reg, &data->status_buf[b]);
 316         } else {
 317                 /*
 318                  * Note we can't use ->get_irq_reg() here because the offsets
 319                  * in 'subreg' are *not* interchangeable with indices.
 320                  */
 321                 subreg = &chip->sub_reg_offsets[b];
 322                 for (i = 0; i < subreg->num_regs; i++) {
 323                         unsigned int offset = subreg->offset[i];
 324                         unsigned int index = offset / map->reg_stride;
 325
 326                         ret = regmap_read(map, chip->status_base + offset,
 327                                           &data->status_buf[index]);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332         return ret;
 333 }
 334
 335 static irqreturn_t regmap_irq_thread(int irq, void *d)
 336 {
 337         struct regmap_irq_chip_data *data = d;
 338         const struct regmap_irq_chip *chip = data->chip;
 339         struct regmap *map = data->map;
 340         int ret, i;
 341         bool handled = false;
 342         u32 reg;
 343
 344         if (chip->handle_pre_irq)
 345                 chip->handle_pre_irq(chip->irq_drv_data);
 346
 347         if (chip->runtime_pm) {
 348                 ret = pm_runtime_get_sync(map->dev);
 349                 if (ret < 0) {
 350                         dev_err(map->dev, "IRQ thread failed to resume: %d\n",
 351                                 ret);
 352                         goto exit;
 353                 }
 354         }
 355
 356         /*
 357          * Read only registers with active IRQs if the chip has 'main status
 358          * register'. Else read in the statuses, using a single bulk read if
 359          * possible in order to reduce the I/O overheads.
 360          */
 361
 362         if (chip->no_status) {
 363                 /* no status register so default to all active */
 364                 memset32(data->status_buf, GENMASK(31, 0), chip->num_regs);
 365         } else if (chip->num_main_regs) {
 366                 unsigned int max_main_bits;
 367
 368                 max_main_bits = (chip->num_main_status_bits) ?
 369                                  chip->num_main_status_bits : chip->num_regs;
 370                 /* Clear the status buf as we don't read all status regs */
 371                 memset32(data->status_buf, 0, chip->num_regs);
 372
 373                 /* We could support bulk read for main status registers
 374                  * but I don't expect to see devices with really many main
 375                  * status registers so let's only support single reads for the
 376                  * sake of simplicity. and add bulk reads only if needed
 377                  */
 378                 for (i = 0; i < chip->num_main_regs; i++) {
 379                         reg = data->get_irq_reg(data, chip->main_status, i);
 380                         ret = regmap_read(map, reg, &data->main_status_buf[i]);
 381                         if (ret) {
 382                                 dev_err(map->dev,
 383                                         "Failed to read IRQ status %d\n",
 384                                         ret);
 385                                 goto exit;
 386                         }
 387                 }
 388
 389                 /* Read sub registers with active IRQs */
 390                 for (i = 0; i < chip->num_main_regs; i++) {
 391                         unsigned int b;
 392                         const unsigned long mreg = data->main_status_buf[i];
 393
 394                         for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
 395                                 if (i * map->format.val_bytes * 8 + b >
 396                                     max_main_bits)
 397                                         break;
 398                                 ret = read_sub_irq_data(data, b);
 399
 400                                 if (ret != 0) {
 401                                         dev_err(map->dev,
 402                                                 "Failed to read IRQ status %d\n",
 403                                                 ret);
 404                                         goto exit;
 405                                 }
 406                         }
 407
 408                 }
 409         } else if (regmap_irq_can_bulk_read_status(data)) {
 410
 411                 u8 *buf8 = data->status_reg_buf;
 412                 u16 *buf16 = data->status_reg_buf;
 413                 u32 *buf32 = data->status_reg_buf;
 414
 415                 BUG_ON(!data->status_reg_buf);
 416
 417                 ret = regmap_bulk_read(map, chip->status_base,
 418                                        data->status_reg_buf,
 419                                        chip->num_regs);
 420                 if (ret != 0) {
 421                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 422                                 ret);
 423                         goto exit;
 424                 }
 425
 426                 for (i = 0; i < data->chip->num_regs; i++) {
 427                         switch (map->format.val_bytes) {
 428                         case 1:
 429                                 data->status_buf[i] = buf8[i];
 430                                 break;
 431                         case 2:
 432                                 data->status_buf[i] = buf16[i];
 433                                 break;
 434                         case 4:
 435                                 data->status_buf[i] = buf32[i];
 436                                 break;
 437                         default:
 438                                 BUG();
 439                                 goto exit;
 440                         }
 441                 }
 442
 443         } else {
 444                 for (i = 0; i < data->chip->num_regs; i++) {
 445                         unsigned int reg = data->get_irq_reg(data,
 446                                         data->chip->status_base, i);
 447                         ret = regmap_read(map, reg, &data->status_buf[i]);
 448
 449                         if (ret != 0) {
 450                                 dev_err(map->dev,
 451                                         "Failed to read IRQ status: %d\n",
 452                                         ret);
 453                                 goto exit;
 454                         }
 455                 }
 456         }
 457
 458         if (chip->status_invert)
 459                 for (i = 0; i < data->chip->num_regs; i++)
 460                         data->status_buf[i] = ~data->status_buf[i];
 461
 462         /*
 463          * Ignore masked IRQs and ack if we need to; we ack early so
 464          * there is no race between handling and acknowledging the
 465          * interrupt.  We assume that typically few of the interrupts
 466          * will fire simultaneously so don't worry about overhead from
 467          * doing a write per register.
 468          */
 469         for (i = 0; i < data->chip->num_regs; i++) {
 470                 data->status_buf[i] &= ~data->mask_buf[i];
 471
 472                 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 473                         reg = data->get_irq_reg(data, data->chip->ack_base, i);
 474
 475                         if (chip->ack_invert)
 476                                 ret = regmap_write(map, reg,
 477                                                 ~data->status_buf[i]);
 478                         else
 479                                 ret = regmap_write(map, reg,
 480                                                 data->status_buf[i]);
 481                         if (chip->clear_ack) {
 482                                 if (chip->ack_invert && !ret)
 483                                         ret = regmap_write(map, reg, UINT_MAX);
 484                                 else if (!ret)
 485                                         ret = regmap_write(map, reg, 0);
 486                         }
 487                         if (ret != 0)
 488                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 489                                         reg, ret);
 490                 }
 491         }
 492
 493         for (i = 0; i < chip->num_irqs; i++) {
 494                 if (data->status_buf[chip->irqs[i].reg_offset /
 495                                      map->reg_stride] & chip->irqs[i].mask) {
 496                         handle_nested_irq(irq_find_mapping(data->domain, i));
 497                         handled = true;
 498                 }
 499         }
 500
 501 exit:
 502         if (chip->handle_post_irq)
 503                 chip->handle_post_irq(chip->irq_drv_data);
 504
 505         if (chip->runtime_pm)
 506                 pm_runtime_put(map->dev);
 507
 508         if (handled)
 509                 return IRQ_HANDLED;
 510         else
 511                 return IRQ_NONE;
 512 }
 513
 514 static struct lock_class_key regmap_irq_lock_class;
 515 static struct lock_class_key regmap_irq_request_class;
 516
 517 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
 518                           irq_hw_number_t hw)
 519 {
 520         struct regmap_irq_chip_data *data = h->host_data;
 521
 522         irq_set_chip_data(virq, data);
 523         irq_set_lockdep_class(virq, &regmap_irq_lock_class, &regmap_irq_request_class);
 524         irq_set_chip(virq, &data->irq_chip);
 525         irq_set_nested_thread(virq, 1);
 526         irq_set_parent(virq, data->irq);
 527         irq_set_noprobe(virq);
 528
 529         return 0;
 530 }
 531
 532 static const struct irq_domain_ops regmap_domain_ops = {
 533         .map    = regmap_irq_map,
 534         .xlate  = irq_domain_xlate_onetwocell,
 535 };
 536
 537 /**
 538  * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback.
 539  * @data: Data for the &struct regmap_irq_chip
 540  * @base: Base register
 541  * @index: Register index
 542  *
 543  * Returns the register address corresponding to the given @base and @index
 544  * by the formula ``base + index * regmap_stride * irq_reg_stride``.
 545  */
 546 unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data,
 547                                            unsigned int base, int index)
 548 {
 549         struct regmap *map = data->map;
 550
 551         return base + index * map->reg_stride * data->irq_reg_stride;
 552 }
 553 EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear);
 554
 555 /**
 556  * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback.
 557  * @buf: Buffer containing configuration register values, this is a 2D array of
 558  *       `num_config_bases` rows, each of `num_config_regs` elements.
 559  * @type: The requested IRQ type.
 560  * @irq_data: The IRQ being configured.
 561  * @idx: Index of the irq's config registers within each array `buf[i]`
 562  * @irq_drv_data: Driver specific IRQ data
 563  *
 564  * This is a &struct regmap_irq_chip->set_type_config callback suitable for
 565  * chips with one config register. Register values are updated according to
 566  * the &struct regmap_irq_type data associated with an IRQ.
 567  */
 568 int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type,
 569                                       const struct regmap_irq *irq_data,
 570                                       int idx, void *irq_drv_data)
 571 {
 572         const struct regmap_irq_type *t = &irq_data->type;
 573
 574         if (t->type_reg_mask)
 575                 buf[0][idx] &= ~t->type_reg_mask;
 576         else
 577                 buf[0][idx] &= ~(t->type_falling_val |
 578                                  t->type_rising_val |
 579                                  t->type_level_low_val |
 580                                  t->type_level_high_val);
 581
 582         switch (type) {
 583         case IRQ_TYPE_EDGE_FALLING:
 584                 buf[0][idx] |= t->type_falling_val;
 585                 break;
 586
 587         case IRQ_TYPE_EDGE_RISING:
 588                 buf[0][idx] |= t->type_rising_val;
 589                 break;
 590
 591         case IRQ_TYPE_EDGE_BOTH:
 592                 buf[0][idx] |= (t->type_falling_val |
 593                                 t->type_rising_val);
 594                 break;
 595
 596         case IRQ_TYPE_LEVEL_HIGH:
 597                 buf[0][idx] |= t->type_level_high_val;
 598                 break;
 599
 600         case IRQ_TYPE_LEVEL_LOW:
 601                 buf[0][idx] |= t->type_level_low_val;
 602                 break;
 603
 604         default:
 605                 return -EINVAL;
 606         }
 607
 608         return 0;
 609 }
 610 EXPORT_SYMBOL_GPL(regmap_irq_set_type_config_simple);
 611
 612 static int regmap_irq_create_domain(struct fwnode_handle *fwnode, int irq_base,
 613                                     const struct regmap_irq_chip *chip,
 614                                     struct regmap_irq_chip_data *d)
 615 {
 616         struct irq_domain_info info = {
 617                 .fwnode = fwnode,
 618                 .size = chip->num_irqs,
 619                 .hwirq_max = chip->num_irqs,
 620                 .virq_base = irq_base,
 621                 .ops = &regmap_domain_ops,
 622                 .host_data = d,
 623                 .name_suffix = chip->domain_suffix,
 624         };
 625
 626         d->domain = irq_domain_instantiate(&info);
 627         if (IS_ERR(d->domain)) {
 628                 dev_err(d->map->dev, "Failed to create IRQ domain\n");
 629                 return PTR_ERR(d->domain);
 630         }
 631
 632         return 0;
 633 }
 634
 635
 636 /**
 637  * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
 638  *
 639  * @fwnode: The firmware node where the IRQ domain should be added to.
 640  * @map: The regmap for the device.
 641  * @irq: The IRQ the device uses to signal interrupts.
 642  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 643  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 644  * @chip: Configuration for the interrupt controller.
 645  * @data: Runtime data structure for the controller, allocated on success.
 646  *
 647  * Returns 0 on success or an errno on failure.
 648  *
 649  * In order for this to be efficient the chip really should use a
 650  * register cache.  The chip driver is responsible for restoring the
 651  * register values used by the IRQ controller over suspend and resume.
 652  */
 653 int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode,
 654                                struct regmap *map, int irq,
 655                                int irq_flags, int irq_base,
 656                                const struct regmap_irq_chip *chip,
 657                                struct regmap_irq_chip_data **data)
 658 {
 659         struct regmap_irq_chip_data *d;
 660         int i;
 661         int ret = -ENOMEM;
 662         u32 reg;
 663
 664         if (chip->num_regs <= 0)
 665                 return -EINVAL;
 666
 667         if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
 668                 return -EINVAL;
 669
 670         if (chip->mask_base && chip->unmask_base && !chip->mask_unmask_non_inverted)
 671                 return -EINVAL;
 672
 673         for (i = 0; i < chip->num_irqs; i++) {
 674                 if (chip->irqs[i].reg_offset % map->reg_stride)
 675                         return -EINVAL;
 676                 if (chip->irqs[i].reg_offset / map->reg_stride >=
 677                     chip->num_regs)
 678                         return -EINVAL;
 679         }
 680
 681         if (irq_base) {
 682                 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
 683                 if (irq_base < 0) {
 684                         dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
 685                                  irq_base);
 686                         return irq_base;
 687                 }
 688         }
 689
 690         d = kzalloc(sizeof(*d), GFP_KERNEL);
 691         if (!d)
 692                 return -ENOMEM;
 693
 694         if (chip->num_main_regs) {
 695                 d->main_status_buf = kcalloc(chip->num_main_regs,
 696                                              sizeof(*d->main_status_buf),
 697                                              GFP_KERNEL);
 698
 699                 if (!d->main_status_buf)
 700                         goto err_alloc;
 701         }
 702
 703         d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf),
 704                                 GFP_KERNEL);
 705         if (!d->status_buf)
 706                 goto err_alloc;
 707
 708         d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf),
 709                               GFP_KERNEL);
 710         if (!d->mask_buf)
 711                 goto err_alloc;
 712
 713         d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def),
 714                                   GFP_KERNEL);
 715         if (!d->mask_buf_def)
 716                 goto err_alloc;
 717
 718         if (chip->wake_base) {
 719                 d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf),
 720                                       GFP_KERNEL);
 721                 if (!d->wake_buf)
 722                         goto err_alloc;
 723         }
 724
 725         if (chip->type_in_mask) {
 726                 d->type_buf_def = kcalloc(chip->num_regs,
 727                                           sizeof(*d->type_buf_def), GFP_KERNEL);
 728                 if (!d->type_buf_def)
 729                         goto err_alloc;
 730
 731                 d->type_buf = kcalloc(chip->num_regs, sizeof(*d->type_buf), GFP_KERNEL);
 732                 if (!d->type_buf)
 733                         goto err_alloc;
 734         }
 735
 736         if (chip->num_config_bases && chip->num_config_regs) {
 737                 /*
 738                  * Create config_buf[num_config_bases][num_config_regs]
 739                  */
 740                 d->config_buf = kcalloc(chip->num_config_bases,
 741                                         sizeof(*d->config_buf), GFP_KERNEL);
 742                 if (!d->config_buf)
 743                         goto err_alloc;
 744
 745                 for (i = 0; i < chip->num_config_bases; i++) {
 746                         d->config_buf[i] = kcalloc(chip->num_config_regs,
 747                                                    sizeof(**d->config_buf),
 748                                                    GFP_KERNEL);
 749                         if (!d->config_buf[i])
 750                                 goto err_alloc;
 751                 }
 752         }
 753
 754         d->irq_chip = regmap_irq_chip;
 755         d->irq_chip.name = chip->name;
 756         d->irq = irq;
 757         d->map = map;
 758         d->chip = chip;
 759         d->irq_base = irq_base;
 760
 761         if (chip->irq_reg_stride)
 762                 d->irq_reg_stride = chip->irq_reg_stride;
 763         else
 764                 d->irq_reg_stride = 1;
 765
 766         if (chip->get_irq_reg)
 767                 d->get_irq_reg = chip->get_irq_reg;
 768         else
 769                 d->get_irq_reg = regmap_irq_get_irq_reg_linear;
 770
 771         if (regmap_irq_can_bulk_read_status(d)) {
 772                 d->status_reg_buf = kmalloc_array(chip->num_regs,
 773                                                   map->format.val_bytes,
 774                                                   GFP_KERNEL);
 775                 if (!d->status_reg_buf)
 776                         goto err_alloc;
 777         }
 778
 779         mutex_init(&d->lock);
 780
 781         for (i = 0; i < chip->num_irqs; i++)
 782                 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
 783                         |= chip->irqs[i].mask;
 784
 785         /* Mask all the interrupts by default */
 786         for (i = 0; i < chip->num_regs; i++) {
 787                 d->mask_buf[i] = d->mask_buf_def[i];
 788
 789                 if (chip->handle_mask_sync) {
 790                         ret = chip->handle_mask_sync(i, d->mask_buf_def[i],
 791                                                      d->mask_buf[i],
 792                                                      chip->irq_drv_data);
 793                         if (ret)
 794                                 goto err_alloc;
 795                 }
 796
 797                 if (chip->mask_base && !chip->handle_mask_sync) {
 798                         reg = d->get_irq_reg(d, chip->mask_base, i);
 799                         ret = regmap_update_bits(d->map, reg,
 800                                                  d->mask_buf_def[i],
 801                                                  d->mask_buf[i]);
 802                         if (ret) {
 803                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 804                                         reg, ret);
 805                                 goto err_alloc;
 806                         }
 807                 }
 808
 809                 if (chip->unmask_base && !chip->handle_mask_sync) {
 810                         reg = d->get_irq_reg(d, chip->unmask_base, i);
 811                         ret = regmap_update_bits(d->map, reg,
 812                                         d->mask_buf_def[i], ~d->mask_buf[i]);
 813                         if (ret) {
 814                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 815                                         reg, ret);
 816                                 goto err_alloc;
 817                         }
 818                 }
 819
 820                 if (!chip->init_ack_masked)
 821                         continue;
 822
 823                 /* Ack masked but set interrupts */
 824                 if (d->chip->no_status) {
 825                         /* no status register so default to all active */
 826                         d->status_buf[i] = GENMASK(31, 0);
 827                 } else {
 828                         reg = d->get_irq_reg(d, d->chip->status_base, i);
 829                         ret = regmap_read(map, reg, &d->status_buf[i]);
 830                         if (ret != 0) {
 831                                 dev_err(map->dev, "Failed to read IRQ status: %d\n",
 832                                         ret);
 833                                 goto err_alloc;
 834                         }
 835                 }
 836
 837                 if (chip->status_invert)
 838                         d->status_buf[i] = ~d->status_buf[i];
 839
 840                 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 841                         reg = d->get_irq_reg(d, d->chip->ack_base, i);
 842                         if (chip->ack_invert)
 843                                 ret = regmap_write(map, reg,
 844                                         ~(d->status_buf[i] & d->mask_buf[i]));
 845                         else
 846                                 ret = regmap_write(map, reg,
 847                                         d->status_buf[i] & d->mask_buf[i]);
 848                         if (chip->clear_ack) {
 849                                 if (chip->ack_invert && !ret)
 850                                         ret = regmap_write(map, reg, UINT_MAX);
 851                                 else if (!ret)
 852                                         ret = regmap_write(map, reg, 0);
 853                         }
 854                         if (ret != 0) {
 855                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 856                                         reg, ret);
 857                                 goto err_alloc;
 858                         }
 859                 }
 860         }
 861
 862         /* Wake is disabled by default */
 863         if (d->wake_buf) {
 864                 for (i = 0; i < chip->num_regs; i++) {
 865                         d->wake_buf[i] = d->mask_buf_def[i];
 866                         reg = d->get_irq_reg(d, d->chip->wake_base, i);
 867
 868                         if (chip->wake_invert)
 869                                 ret = regmap_update_bits(d->map, reg,
 870                                                          d->mask_buf_def[i],
 871                                                          0);
 872                         else
 873                                 ret = regmap_update_bits(d->map, reg,
 874                                                          d->mask_buf_def[i],
 875                                                          d->wake_buf[i]);
 876                         if (ret != 0) {
 877                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 878                                         reg, ret);
 879                                 goto err_alloc;
 880                         }
 881                 }
 882         }
 883
 884         ret = regmap_irq_create_domain(fwnode, irq_base, chip, d);
 885         if (ret)
 886                 goto err_alloc;
 887
 888         ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
 889                                    irq_flags | IRQF_ONESHOT,
 890                                    chip->name, d);
 891         if (ret != 0) {
 892                 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
 893                         irq, chip->name, ret);
 894                 goto err_domain;
 895         }
 896
 897         *data = d;
 898
 899         return 0;
 900
 901 err_domain:
 902         /* Should really dispose of the domain but... */
 903 err_alloc:
 904         kfree(d->type_buf);
 905         kfree(d->type_buf_def);
 906         kfree(d->wake_buf);
 907         kfree(d->mask_buf_def);
 908         kfree(d->mask_buf);
 909         kfree(d->status_buf);
 910         kfree(d->status_reg_buf);
 911         if (d->config_buf) {
 912                 for (i = 0; i < chip->num_config_bases; i++)
 913                         kfree(d->config_buf[i]);
 914                 kfree(d->config_buf);
 915         }
 916         kfree(d);
 917         return ret;
 918 }
 919 EXPORT_SYMBOL_GPL(regmap_add_irq_chip_fwnode);
 920
 921 /**
 922  * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
 923  *
 924  * @map: The regmap for the device.
 925  * @irq: The IRQ the device uses to signal interrupts.
 926  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 927  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 928  * @chip: Configuration for the interrupt controller.
 929  * @data: Runtime data structure for the controller, allocated on success.
 930  *
 931  * Returns 0 on success or an errno on failure.
 932  *
 933  * This is the same as regmap_add_irq_chip_fwnode, except that the firmware
 934  * node of the regmap is used.
 935  */
 936 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 937                         int irq_base, const struct regmap_irq_chip *chip,
 938                         struct regmap_irq_chip_data **data)
 939 {
 940         return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq,
 941                                           irq_flags, irq_base, chip, data);
 942 }
 943 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 944
 945 /**
 946  * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
 947  *
 948  * @irq: Primary IRQ for the device
 949  * @d: &regmap_irq_chip_data allocated by regmap_add_irq_chip()
 950  *
 951  * This function also disposes of all mapped IRQs on the chip.
 952  */
 953 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 954 {
 955         unsigned int virq;
 956         int i, hwirq;
 957
 958         if (!d)
 959                 return;
 960
 961         free_irq(irq, d);
 962
 963         /* Dispose all virtual irq from irq domain before removing it */
 964         for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
 965                 /* Ignore hwirq if holes in the IRQ list */
 966                 if (!d->chip->irqs[hwirq].mask)
 967                         continue;
 968
 969                 /*
 970                  * Find the virtual irq of hwirq on chip and if it is
 971                  * there then dispose it
 972                  */
 973                 virq = irq_find_mapping(d->domain, hwirq);
 974                 if (virq)
 975                         irq_dispose_mapping(virq);
 976         }
 977
 978         irq_domain_remove(d->domain);
 979         kfree(d->type_buf);
 980         kfree(d->type_buf_def);
 981         kfree(d->wake_buf);
 982         kfree(d->mask_buf_def);
 983         kfree(d->mask_buf);
 984         kfree(d->status_reg_buf);
 985         kfree(d->status_buf);
 986         if (d->config_buf) {
 987                 for (i = 0; i < d->chip->num_config_bases; i++)
 988                         kfree(d->config_buf[i]);
 989                 kfree(d->config_buf);
 990         }
 991         kfree(d);
 992 }
 993 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
 994
 995 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
 996 {
 997         struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
 998
 999         regmap_del_irq_chip(d->irq, d);
1000 }
1001
1002 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
1003
1004 {
1005         struct regmap_irq_chip_data **r = res;
1006
1007         if (!r || !*r) {
1008                 WARN_ON(!r || !*r);
1009                 return 0;
1010         }
1011         return *r == data;
1012 }
1013
1014 /**
1015  * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1016  *
1017  * @dev: The device pointer on which irq_chip belongs to.
1018  * @fwnode: The firmware node where the IRQ domain should be added to.
1019  * @map: The regmap for the device.
1020  * @irq: The IRQ the device uses to signal interrupts
1021  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
1022  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
1023  * @chip: Configuration for the interrupt controller.
1024  * @data: Runtime data structure for the controller, allocated on success
1025  *
1026  * Returns 0 on success or an errno on failure.
1027  *
1028  * The &regmap_irq_chip_data will be automatically released when the device is
1029  * unbound.
1030  */
1031 int devm_regmap_add_irq_chip_fwnode(struct device *dev,
1032                                     struct fwnode_handle *fwnode,
1033                                     struct regmap *map, int irq,
1034                                     int irq_flags, int irq_base,
1035                                     const struct regmap_irq_chip *chip,
1036                                     struct regmap_irq_chip_data **data)
1037 {
1038         struct regmap_irq_chip_data **ptr, *d;
1039         int ret;
1040
1041         ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
1042                            GFP_KERNEL);
1043         if (!ptr)
1044                 return -ENOMEM;
1045
1046         ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base,
1047                                          chip, &d);
1048         if (ret < 0) {
1049                 devres_free(ptr);
1050                 return ret;
1051         }
1052
1053         *ptr = d;
1054         devres_add(dev, ptr);
1055         *data = d;
1056         return 0;
1057 }
1058 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip_fwnode);
1059
1060 /**
1061  * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip()
1062  *
1063  * @dev: The device pointer on which irq_chip belongs to.
1064  * @map: The regmap for the device.
1065  * @irq: The IRQ the device uses to signal interrupts
1066  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
1067  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
1068  * @chip: Configuration for the interrupt controller.
1069  * @data: Runtime data structure for the controller, allocated on success
1070  *
1071  * Returns 0 on success or an errno on failure.
1072  *
1073  * The &regmap_irq_chip_data will be automatically released when the device is
1074  * unbound.
1075  */
1076 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
1077                              int irq_flags, int irq_base,
1078                              const struct regmap_irq_chip *chip,
1079                              struct regmap_irq_chip_data **data)
1080 {
1081         return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map,
1082                                                irq, irq_flags, irq_base, chip,
1083                                                data);
1084 }
1085 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
1086
1087 /**
1088  * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1089  *
1090  * @dev: Device for which the resource was allocated.
1091  * @irq: Primary IRQ for the device.
1092  * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
1093  *
1094  * A resource managed version of regmap_del_irq_chip().
1095  */
1096 void devm_regmap_del_irq_chip(struct device *dev, int irq,
1097                               struct regmap_irq_chip_data *data)
1098 {
1099         int rc;
1100
1101         WARN_ON(irq != data->irq);
1102         rc = devres_release(dev, devm_regmap_irq_chip_release,
1103                             devm_regmap_irq_chip_match, data);
1104
1105         if (rc != 0)
1106                 WARN_ON(rc);
1107 }
1108 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
1109
1110 /**
1111  * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1112  *
1113  * @data: regmap irq controller to operate on.
1114  *
1115  * Useful for drivers to request their own IRQs.
1116  */
1117 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
1118 {
1119         WARN_ON(!data->irq_base);
1120         return data->irq_base;
1121 }
1122 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
1123
1124 /**
1125  * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1126  *
1127  * @data: regmap irq controller to operate on.
1128  * @irq: index of the interrupt requested in the chip IRQs.
1129  *
1130  * Useful for drivers to request their own IRQs.
1131  */
1132 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
1133 {
1134         /* Handle holes in the IRQ list */
1135         if (!data->chip->irqs[irq].mask)
1136                 return -EINVAL;
1137
1138         return irq_create_mapping(data->domain, irq);
1139 }
1140 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
1141
1142 /**
1143  * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1144  *
1145  * @data: regmap_irq controller to operate on.
1146  *
1147  * Useful for drivers to request their own IRQs and for integration
1148  * with subsystems.  For ease of integration NULL is accepted as a
1149  * domain, allowing devices to just call this even if no domain is
1150  * allocated.
1151  */
1152 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
1153 {
1154         if (data)
1155                 return data->domain;
1156         else
1157                 return NULL;
1158 }
1159 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);