arch/x86/kernel/cpu/mce/amd.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  (c) 2005-2016 Advanced Micro Devices, Inc.
   4  *
   5  *  Written by Jacob Shin - AMD, Inc.
   6  *  Maintained by: Borislav Petkov <[email protected]>
   7  *
   8  *  All MC4_MISCi registers are shared between cores on a node.
   9  */
  10 #include <linux/interrupt.h>
  11 #include <linux/notifier.h>
  12 #include <linux/kobject.h>
  13 #include <linux/percpu.h>
  14 #include <linux/errno.h>
  15 #include <linux/sched.h>
  16 #include <linux/sysfs.h>
  17 #include <linux/slab.h>
  18 #include <linux/init.h>
  19 #include <linux/cpu.h>
  20 #include <linux/smp.h>
  21 #include <linux/string.h>
  22
  23 #include <asm/amd_nb.h>
  24 #include <asm/traps.h>
  25 #include <asm/apic.h>
  26 #include <asm/mce.h>
  27 #include <asm/msr.h>
  28 #include <asm/trace/irq_vectors.h>
  29
  30 #include "internal.h"
  31
  32 #define NR_BLOCKS         5
  33 #define THRESHOLD_MAX     0xFFF
  34 #define INT_TYPE_APIC     0x00020000
  35 #define MASK_VALID_HI     0x80000000
  36 #define MASK_CNTP_HI      0x40000000
  37 #define MASK_LOCKED_HI    0x20000000
  38 #define MASK_LVTOFF_HI    0x00F00000
  39 #define MASK_COUNT_EN_HI  0x00080000
  40 #define MASK_INT_TYPE_HI  0x00060000
  41 #define MASK_OVERFLOW_HI  0x00010000
  42 #define MASK_ERR_COUNT_HI 0x00000FFF
  43 #define MASK_BLKPTR_LO    0xFF000000
  44 #define MCG_XBLK_ADDR     0xC0000400
  45
  46 /* Deferred error settings */
  47 #define MSR_CU_DEF_ERR          0xC0000410
  48 #define MASK_DEF_LVTOFF         0x000000F0
  49 #define MASK_DEF_INT_TYPE       0x00000006
  50 #define DEF_LVT_OFF             0x2
  51 #define DEF_INT_TYPE_APIC       0x2
  52
  53 /* Scalable MCA: */
  54
  55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
  56 #define SMCA_THR_LVT_OFF        0xF000
  57
  58 static bool thresholding_irq_en;
  59
  60 static const char * const th_names[] = {
  61         "load_store",
  62         "insn_fetch",
  63         "combined_unit",
  64         "decode_unit",
  65         "northbridge",
  66         "execution_unit",
  67 };
  68
  69 static const char * const smca_umc_block_names[] = {
  70         "dram_ecc",
  71         "misc_umc"
  72 };
  73
  74 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
  75
  76 struct smca_hwid {
  77         unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
  78         u32 hwid_mcatype;       /* (hwid,mcatype) tuple */
  79 };
  80
  81 struct smca_bank {
  82         const struct smca_hwid *hwid;
  83         u32 id;                 /* Value of MCA_IPID[InstanceId]. */
  84         u8 sysfs_id;            /* Value used for sysfs name. */
  85 };
  86
  87 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
  88 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
  89
  90 static const char * const smca_names[] = {
  91         [SMCA_LS ... SMCA_LS_V2]        = "load_store",
  92         [SMCA_IF]                       = "insn_fetch",
  93         [SMCA_L2_CACHE]                 = "l2_cache",
  94         [SMCA_DE]                       = "decode_unit",
  95         [SMCA_RESERVED]                 = "reserved",
  96         [SMCA_EX]                       = "execution_unit",
  97         [SMCA_FP]                       = "floating_point",
  98         [SMCA_L3_CACHE]                 = "l3_cache",
  99         [SMCA_CS ... SMCA_CS_V2]        = "coherent_slave",
 100         [SMCA_PIE]                      = "pie",
 101
 102         /* UMC v2 is separate because both of them can exist in a single system. */
 103         [SMCA_UMC]                      = "umc",
 104         [SMCA_UMC_V2]                   = "umc_v2",
 105         [SMCA_MA_LLC]                   = "ma_llc",
 106         [SMCA_PB]                       = "param_block",
 107         [SMCA_PSP ... SMCA_PSP_V2]      = "psp",
 108         [SMCA_SMU ... SMCA_SMU_V2]      = "smu",
 109         [SMCA_MP5]                      = "mp5",
 110         [SMCA_MPDMA]                    = "mpdma",
 111         [SMCA_NBIO]                     = "nbio",
 112         [SMCA_PCIE ... SMCA_PCIE_V2]    = "pcie",
 113         [SMCA_XGMI_PCS]                 = "xgmi_pcs",
 114         [SMCA_NBIF]                     = "nbif",
 115         [SMCA_SHUB]                     = "shub",
 116         [SMCA_SATA]                     = "sata",
 117         [SMCA_USB]                      = "usb",
 118         [SMCA_USR_DP]                   = "usr_dp",
 119         [SMCA_USR_CP]                   = "usr_cp",
 120         [SMCA_GMI_PCS]                  = "gmi_pcs",
 121         [SMCA_XGMI_PHY]                 = "xgmi_phy",
 122         [SMCA_WAFL_PHY]                 = "wafl_phy",
 123         [SMCA_GMI_PHY]                  = "gmi_phy",
 124 };
 125
 126 static const char *smca_get_name(enum smca_bank_types t)
 127 {
 128         if (t >= N_SMCA_BANK_TYPES)
 129                 return NULL;
 130
 131         return smca_names[t];
 132 }
 133
 134 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)
 135 {
 136         struct smca_bank *b;
 137
 138         if (bank >= MAX_NR_BANKS)
 139                 return N_SMCA_BANK_TYPES;
 140
 141         b = &per_cpu(smca_banks, cpu)[bank];
 142         if (!b->hwid)
 143                 return N_SMCA_BANK_TYPES;
 144
 145         return b->hwid->bank_type;
 146 }
 147 EXPORT_SYMBOL_GPL(smca_get_bank_type);
 148
 149 static const struct smca_hwid smca_hwid_mcatypes[] = {
 150         /* { bank_type, hwid_mcatype } */
 151
 152         /* Reserved type */
 153         { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0)        },
 154
 155         /* ZN Core (HWID=0xB0) MCA types */
 156         { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0)        },
 157         { SMCA_LS_V2,    HWID_MCATYPE(0xB0, 0x10)       },
 158         { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1)        },
 159         { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2)        },
 160         { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3)        },
 161         /* HWID 0xB0 MCATYPE 0x4 is Reserved */
 162         { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5)        },
 163         { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6)        },
 164         { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7)        },
 165
 166         /* Data Fabric MCA types */
 167         { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0)        },
 168         { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1)        },
 169         { SMCA_CS_V2,    HWID_MCATYPE(0x2E, 0x2)        },
 170         { SMCA_MA_LLC,   HWID_MCATYPE(0x2E, 0x4)        },
 171
 172         /* Unified Memory Controller MCA type */
 173         { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0)        },
 174         { SMCA_UMC_V2,   HWID_MCATYPE(0x96, 0x1)        },
 175
 176         /* Parameter Block MCA type */
 177         { SMCA_PB,       HWID_MCATYPE(0x05, 0x0)        },
 178
 179         /* Platform Security Processor MCA type */
 180         { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0)        },
 181         { SMCA_PSP_V2,   HWID_MCATYPE(0xFF, 0x1)        },
 182
 183         /* System Management Unit MCA type */
 184         { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0)        },
 185         { SMCA_SMU_V2,   HWID_MCATYPE(0x01, 0x1)        },
 186
 187         /* Microprocessor 5 Unit MCA type */
 188         { SMCA_MP5,      HWID_MCATYPE(0x01, 0x2)        },
 189
 190         /* MPDMA MCA type */
 191         { SMCA_MPDMA,    HWID_MCATYPE(0x01, 0x3)        },
 192
 193         /* Northbridge IO Unit MCA type */
 194         { SMCA_NBIO,     HWID_MCATYPE(0x18, 0x0)        },
 195
 196         /* PCI Express Unit MCA type */
 197         { SMCA_PCIE,     HWID_MCATYPE(0x46, 0x0)        },
 198         { SMCA_PCIE_V2,  HWID_MCATYPE(0x46, 0x1)        },
 199
 200         { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0)        },
 201         { SMCA_NBIF,     HWID_MCATYPE(0x6C, 0x0)        },
 202         { SMCA_SHUB,     HWID_MCATYPE(0x80, 0x0)        },
 203         { SMCA_SATA,     HWID_MCATYPE(0xA8, 0x0)        },
 204         { SMCA_USB,      HWID_MCATYPE(0xAA, 0x0)        },
 205         { SMCA_USR_DP,   HWID_MCATYPE(0x170, 0x0)       },
 206         { SMCA_USR_CP,   HWID_MCATYPE(0x180, 0x0)       },
 207         { SMCA_GMI_PCS,  HWID_MCATYPE(0x241, 0x0)       },
 208         { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0)       },
 209         { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0)       },
 210         { SMCA_GMI_PHY,  HWID_MCATYPE(0x269, 0x0)       },
 211 };
 212
 213 /*
 214  * In SMCA enabled processors, we can have multiple banks for a given IP type.
 215  * So to define a unique name for each bank, we use a temp c-string to append
 216  * the MCA_IPID[InstanceId] to type's name in get_name().
 217  *
 218  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
 219  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
 220  */
 221 #define MAX_MCATYPE_NAME_LEN    30
 222 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
 223
 224 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
 225
 226 /*
 227  * A list of the banks enabled on each logical CPU. Controls which respective
 228  * descriptors to initialize later in mce_threshold_create_device().
 229  */
 230 static DEFINE_PER_CPU(u64, bank_map);
 231
 232 /* Map of banks that have more than MCA_MISC0 available. */
 233 static DEFINE_PER_CPU(u64, smca_misc_banks_map);
 234
 235 static void amd_threshold_interrupt(void);
 236 static void amd_deferred_error_interrupt(void);
 237
 238 static void default_deferred_error_interrupt(void)
 239 {
 240         pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
 241 }
 242 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
 243
 244 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)
 245 {
 246         u32 low, high;
 247
 248         /*
 249          * For SMCA enabled processors, BLKPTR field of the first MISC register
 250          * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
 251          */
 252         if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
 253                 return;
 254
 255         if (!(low & MCI_CONFIG_MCAX))
 256                 return;
 257
 258         if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high))
 259                 return;
 260
 261         if (low & MASK_BLKPTR_LO)
 262                 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank);
 263
 264 }
 265
 266 static void smca_configure(unsigned int bank, unsigned int cpu)
 267 {
 268         u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
 269         const struct smca_hwid *s_hwid;
 270         unsigned int i, hwid_mcatype;
 271         u32 high, low;
 272         u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
 273
 274         /* Set appropriate bits in MCA_CONFIG */
 275         if (!rdmsr_safe(smca_config, &low, &high)) {
 276                 /*
 277                  * OS is required to set the MCAX bit to acknowledge that it is
 278                  * now using the new MSR ranges and new registers under each
 279                  * bank. It also means that the OS will configure deferred
 280                  * errors in the new MCx_CONFIG register. If the bit is not set,
 281                  * uncorrectable errors will cause a system panic.
 282                  *
 283                  * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
 284                  */
 285                 high |= BIT(0);
 286
 287                 /*
 288                  * SMCA sets the Deferred Error Interrupt type per bank.
 289                  *
 290                  * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
 291                  * if the DeferredIntType bit field is available.
 292                  *
 293                  * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
 294                  * high portion of the MSR). OS should set this to 0x1 to enable
 295                  * APIC based interrupt. First, check that no interrupt has been
 296                  * set.
 297                  */
 298                 if ((low & BIT(5)) && !((high >> 5) & 0x3))
 299                         high |= BIT(5);
 300
 301                 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
 302
 303                 wrmsr(smca_config, low, high);
 304         }
 305
 306         smca_set_misc_banks_map(bank, cpu);
 307
 308         if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
 309                 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
 310                 return;
 311         }
 312
 313         hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
 314                                     (high & MCI_IPID_MCATYPE) >> 16);
 315
 316         for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
 317                 s_hwid = &smca_hwid_mcatypes[i];
 318
 319                 if (hwid_mcatype == s_hwid->hwid_mcatype) {
 320                         this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;
 321                         this_cpu_ptr(smca_banks)[bank].id = low;
 322                         this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;
 323                         break;
 324                 }
 325         }
 326 }
 327
 328 struct thresh_restart {
 329         struct threshold_block  *b;
 330         int                     reset;
 331         int                     set_lvt_off;
 332         int                     lvt_off;
 333         u16                     old_limit;
 334 };
 335
 336 static inline bool is_shared_bank(int bank)
 337 {
 338         /*
 339          * Scalable MCA provides for only one core to have access to the MSRs of
 340          * a shared bank.
 341          */
 342         if (mce_flags.smca)
 343                 return false;
 344
 345         /* Bank 4 is for northbridge reporting and is thus shared */
 346         return (bank == 4);
 347 }
 348
 349 static const char *bank4_names(const struct threshold_block *b)
 350 {
 351         switch (b->address) {
 352         /* MSR4_MISC0 */
 353         case 0x00000413:
 354                 return "dram";
 355
 356         case 0xc0000408:
 357                 return "ht_links";
 358
 359         case 0xc0000409:
 360                 return "l3_cache";
 361
 362         default:
 363                 WARN(1, "Funny MSR: 0x%08x\n", b->address);
 364                 return "";
 365         }
 366 };
 367
 368
 369 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
 370 {
 371         /*
 372          * bank 4 supports APIC LVT interrupts implicitly since forever.
 373          */
 374         if (bank == 4)
 375                 return true;
 376
 377         /*
 378          * IntP: interrupt present; if this bit is set, the thresholding
 379          * bank can generate APIC LVT interrupts
 380          */
 381         return msr_high_bits & BIT(28);
 382 }
 383
 384 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 385 {
 386         int msr = (hi & MASK_LVTOFF_HI) >> 20;
 387
 388         if (apic < 0) {
 389                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
 390                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
 391                        b->bank, b->block, b->address, hi, lo);
 392                 return 0;
 393         }
 394
 395         if (apic != msr) {
 396                 /*
 397                  * On SMCA CPUs, LVT offset is programmed at a different MSR, and
 398                  * the BIOS provides the value. The original field where LVT offset
 399                  * was set is reserved. Return early here:
 400                  */
 401                 if (mce_flags.smca)
 402                         return 0;
 403
 404                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 405                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 406                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
 407                 return 0;
 408         }
 409
 410         return 1;
 411 };
 412
 413 /* Reprogram MCx_MISC MSR behind this threshold bank. */
 414 static void threshold_restart_bank(void *_tr)
 415 {
 416         struct thresh_restart *tr = _tr;
 417         u32 hi, lo;
 418
 419         /* sysfs write might race against an offline operation */
 420         if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
 421                 return;
 422
 423         rdmsr(tr->b->address, lo, hi);
 424
 425         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
 426                 tr->reset = 1;  /* limit cannot be lower than err count */
 427
 428         if (tr->reset) {                /* reset err count and overflow bit */
 429                 hi =
 430                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
 431                     (THRESHOLD_MAX - tr->b->threshold_limit);
 432         } else if (tr->old_limit) {     /* change limit w/o reset */
 433                 int new_count = (hi & THRESHOLD_MAX) +
 434                     (tr->old_limit - tr->b->threshold_limit);
 435
 436                 hi = (hi & ~MASK_ERR_COUNT_HI) |
 437                     (new_count & THRESHOLD_MAX);
 438         }
 439
 440         /* clear IntType */
 441         hi &= ~MASK_INT_TYPE_HI;
 442
 443         if (!tr->b->interrupt_capable)
 444                 goto done;
 445
 446         if (tr->set_lvt_off) {
 447                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
 448                         /* set new lvt offset */
 449                         hi &= ~MASK_LVTOFF_HI;
 450                         hi |= tr->lvt_off << 20;
 451                 }
 452         }
 453
 454         if (tr->b->interrupt_enable)
 455                 hi |= INT_TYPE_APIC;
 456
 457  done:
 458
 459         hi |= MASK_COUNT_EN_HI;
 460         wrmsr(tr->b->address, lo, hi);
 461 }
 462
 463 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 464 {
 465         struct thresh_restart tr = {
 466                 .b                      = b,
 467                 .set_lvt_off            = 1,
 468                 .lvt_off                = offset,
 469         };
 470
 471         b->threshold_limit              = THRESHOLD_MAX;
 472         threshold_restart_bank(&tr);
 473 };
 474
 475 static int setup_APIC_mce_threshold(int reserved, int new)
 476 {
 477         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
 478                                               APIC_EILVT_MSG_FIX, 0))
 479                 return new;
 480
 481         return reserved;
 482 }
 483
 484 static int setup_APIC_deferred_error(int reserved, int new)
 485 {
 486         if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
 487                                               APIC_EILVT_MSG_FIX, 0))
 488                 return new;
 489
 490         return reserved;
 491 }
 492
 493 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 494 {
 495         u32 low = 0, high = 0;
 496         int def_offset = -1, def_new;
 497
 498         if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
 499                 return;
 500
 501         def_new = (low & MASK_DEF_LVTOFF) >> 4;
 502         if (!(low & MASK_DEF_LVTOFF)) {
 503                 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
 504                 def_new = DEF_LVT_OFF;
 505                 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
 506         }
 507
 508         def_offset = setup_APIC_deferred_error(def_offset, def_new);
 509         if ((def_offset == def_new) &&
 510             (deferred_error_int_vector != amd_deferred_error_interrupt))
 511                 deferred_error_int_vector = amd_deferred_error_interrupt;
 512
 513         if (!mce_flags.smca)
 514                 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
 515
 516         wrmsr(MSR_CU_DEF_ERR, low, high);
 517 }
 518
 519 static u32 smca_get_block_address(unsigned int bank, unsigned int block,
 520                                   unsigned int cpu)
 521 {
 522         if (!block)
 523                 return MSR_AMD64_SMCA_MCx_MISC(bank);
 524
 525         if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank)))
 526                 return 0;
 527
 528         return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
 529 }
 530
 531 static u32 get_block_address(u32 current_addr, u32 low, u32 high,
 532                              unsigned int bank, unsigned int block,
 533                              unsigned int cpu)
 534 {
 535         u32 addr = 0, offset = 0;
 536
 537         if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))
 538                 return addr;
 539
 540         if (mce_flags.smca)
 541                 return smca_get_block_address(bank, block, cpu);
 542
 543         /* Fall back to method we used for older processors: */
 544         switch (block) {
 545         case 0:
 546                 addr = mca_msr_reg(bank, MCA_MISC);
 547                 break;
 548         case 1:
 549                 offset = ((low & MASK_BLKPTR_LO) >> 21);
 550                 if (offset)
 551                         addr = MCG_XBLK_ADDR + offset;
 552                 break;
 553         default:
 554                 addr = ++current_addr;
 555         }
 556         return addr;
 557 }
 558
 559 static int
 560 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 561                         int offset, u32 misc_high)
 562 {
 563         unsigned int cpu = smp_processor_id();
 564         u32 smca_low, smca_high;
 565         struct threshold_block b;
 566         int new;
 567
 568         if (!block)
 569                 per_cpu(bank_map, cpu) |= BIT_ULL(bank);
 570
 571         memset(&b, 0, sizeof(b));
 572         b.cpu                   = cpu;
 573         b.bank                  = bank;
 574         b.block                 = block;
 575         b.address               = addr;
 576         b.interrupt_capable     = lvt_interrupt_supported(bank, misc_high);
 577
 578         if (!b.interrupt_capable)
 579                 goto done;
 580
 581         b.interrupt_enable = 1;
 582
 583         if (!mce_flags.smca) {
 584                 new = (misc_high & MASK_LVTOFF_HI) >> 20;
 585                 goto set_offset;
 586         }
 587
 588         /* Gather LVT offset for thresholding: */
 589         if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
 590                 goto out;
 591
 592         new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
 593
 594 set_offset:
 595         offset = setup_APIC_mce_threshold(offset, new);
 596         if (offset == new)
 597                 thresholding_irq_en = true;
 598
 599 done:
 600         mce_threshold_block_init(&b, offset);
 601
 602 out:
 603         return offset;
 604 }
 605
 606 bool amd_filter_mce(struct mce *m)
 607 {
 608         enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);
 609         struct cpuinfo_x86 *c = &boot_cpu_data;
 610
 611         /* See Family 17h Models 10h-2Fh Erratum #1114. */
 612         if (c->x86 == 0x17 &&
 613             c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
 614             bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10)
 615                 return true;
 616
 617         /* NB GART TLB error reporting is disabled by default. */
 618         if (c->x86 < 0x17) {
 619                 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)
 620                         return true;
 621         }
 622
 623         return false;
 624 }
 625
 626 /*
 627  * Turn off thresholding banks for the following conditions:
 628  * - MC4_MISC thresholding is not supported on Family 0x15.
 629  * - Prevent possible spurious interrupts from the IF bank on Family 0x17
 630  *   Models 0x10-0x2F due to Erratum #1114.
 631  */
 632 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
 633 {
 634         int i, num_msrs;
 635         u64 hwcr;
 636         bool need_toggle;
 637         u32 msrs[NR_BLOCKS];
 638
 639         if (c->x86 == 0x15 && bank == 4) {
 640                 msrs[0] = 0x00000413; /* MC4_MISC0 */
 641                 msrs[1] = 0xc0000408; /* MC4_MISC1 */
 642                 num_msrs = 2;
 643         } else if (c->x86 == 0x17 &&
 644                    (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
 645
 646                 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF)
 647                         return;
 648
 649                 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
 650                 num_msrs = 1;
 651         } else {
 652                 return;
 653         }
 654
 655         rdmsrl(MSR_K7_HWCR, hwcr);
 656
 657         /* McStatusWrEn has to be set */
 658         need_toggle = !(hwcr & BIT(18));
 659         if (need_toggle)
 660                 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
 661
 662         /* Clear CntP bit safely */
 663         for (i = 0; i < num_msrs; i++)
 664                 msr_clear_bit(msrs[i], 62);
 665
 666         /* restore old settings */
 667         if (need_toggle)
 668                 wrmsrl(MSR_K7_HWCR, hwcr);
 669 }
 670
 671 /* cpu init entry point, called from mce.c with preempt off */
 672 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 673 {
 674         unsigned int bank, block, cpu = smp_processor_id();
 675         u32 low = 0, high = 0, address = 0;
 676         int offset = -1;
 677
 678
 679         for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
 680                 if (mce_flags.smca)
 681                         smca_configure(bank, cpu);
 682
 683                 disable_err_thresholding(c, bank);
 684
 685                 for (block = 0; block < NR_BLOCKS; ++block) {
 686                         address = get_block_address(address, low, high, bank, block, cpu);
 687                         if (!address)
 688                                 break;
 689
 690                         if (rdmsr_safe(address, &low, &high))
 691                                 break;
 692
 693                         if (!(high & MASK_VALID_HI))
 694                                 continue;
 695
 696                         if (!(high & MASK_CNTP_HI)  ||
 697                              (high & MASK_LOCKED_HI))
 698                                 continue;
 699
 700                         offset = prepare_threshold_block(bank, block, address, offset, high);
 701                 }
 702         }
 703
 704         if (mce_flags.succor)
 705                 deferred_error_interrupt_enable(c);
 706 }
 707
 708 /*
 709  * DRAM ECC errors are reported in the Northbridge (bank 4) with
 710  * Extended Error Code 8.
 711  */
 712 static bool legacy_mce_is_memory_error(struct mce *m)
 713 {
 714         return m->bank == 4 && XEC(m->status, 0x1f) == 8;
 715 }
 716
 717 /*
 718  * DRAM ECC errors are reported in Unified Memory Controllers with
 719  * Extended Error Code 0.
 720  */
 721 static bool smca_mce_is_memory_error(struct mce *m)
 722 {
 723         enum smca_bank_types bank_type;
 724
 725         if (XEC(m->status, 0x3f))
 726                 return false;
 727
 728         bank_type = smca_get_bank_type(m->extcpu, m->bank);
 729
 730         return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2;
 731 }
 732
 733 bool amd_mce_is_memory_error(struct mce *m)
 734 {
 735         if (mce_flags.smca)
 736                 return smca_mce_is_memory_error(m);
 737         else
 738                 return legacy_mce_is_memory_error(m);
 739 }
 740
 741 /*
 742  * AMD systems do not have an explicit indicator that the value in MCA_ADDR is
 743  * a system physical address. Therefore, individual cases need to be detected.
 744  * Future cases and checks will be added as needed.
 745  *
 746  * 1) General case
 747  *      a) Assume address is not usable.
 748  * 2) Poison errors
 749  *      a) Indicated by MCA_STATUS[43]: poison. Defined for all banks except legacy
 750  *         northbridge (bank 4).
 751  *      b) Refers to poison consumption in the core. Does not include "no action",
 752  *         "action optional", or "deferred" error severities.
 753  *      c) Will include a usable address so that immediate action can be taken.
 754  * 3) Northbridge DRAM ECC errors
 755  *      a) Reported in legacy bank 4 with extended error code (XEC) 8.
 756  *      b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore,
 757  *         this bit should not be checked.
 758  *
 759  * NOTE: SMCA UMC memory errors fall into case #1.
 760  */
 761 bool amd_mce_usable_address(struct mce *m)
 762 {
 763         /* Check special northbridge case 3) first. */
 764         if (!mce_flags.smca) {
 765                 if (legacy_mce_is_memory_error(m))
 766                         return true;
 767                 else if (m->bank == 4)
 768                         return false;
 769         }
 770
 771         /* Check poison bit for all other bank types. */
 772         if (m->status & MCI_STATUS_POISON)
 773                 return true;
 774
 775         /* Assume address is not usable for all others. */
 776         return false;
 777 }
 778
 779 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 780 {
 781         struct mce_hw_err err;
 782         struct mce *m = &err.m;
 783
 784         mce_prep_record(&err);
 785
 786         m->status = status;
 787         m->misc   = misc;
 788         m->bank   = bank;
 789         m->tsc   = rdtsc();
 790
 791         if (m->status & MCI_STATUS_ADDRV) {
 792                 m->addr = addr;
 793
 794                 smca_extract_err_addr(m);
 795         }
 796
 797         if (mce_flags.smca) {
 798                 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid);
 799
 800                 if (m->status & MCI_STATUS_SYNDV) {
 801                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd);
 802                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1);
 803                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2);
 804                 }
 805         }
 806
 807         mce_log(&err);
 808 }
 809
 810 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error)
 811 {
 812         trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
 813         inc_irq_stat(irq_deferred_error_count);
 814         deferred_error_int_vector();
 815         trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
 816         apic_eoi();
 817 }
 818
 819 /*
 820  * Returns true if the logged error is deferred. False, otherwise.
 821  */
 822 static inline bool
 823 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
 824 {
 825         u64 status, addr = 0;
 826
 827         rdmsrl(msr_stat, status);
 828         if (!(status & MCI_STATUS_VAL))
 829                 return false;
 830
 831         if (status & MCI_STATUS_ADDRV)
 832                 rdmsrl(msr_addr, addr);
 833
 834         __log_error(bank, status, addr, misc);
 835
 836         wrmsrl(msr_stat, 0);
 837
 838         return status & MCI_STATUS_DEFERRED;
 839 }
 840
 841 static bool _log_error_deferred(unsigned int bank, u32 misc)
 842 {
 843         if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),
 844                              mca_msr_reg(bank, MCA_ADDR), misc))
 845                 return false;
 846
 847         /*
 848          * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers.
 849          * Return true here to avoid accessing these registers.
 850          */
 851         if (!mce_flags.smca)
 852                 return true;
 853
 854         /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */
 855         wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
 856         return true;
 857 }
 858
 859 /*
 860  * We have three scenarios for checking for Deferred errors:
 861  *
 862  * 1) Non-SMCA systems check MCA_STATUS and log error if found.
 863  * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
 864  *    clear MCA_DESTAT.
 865  * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
 866  *    log it.
 867  */
 868 static void log_error_deferred(unsigned int bank)
 869 {
 870         if (_log_error_deferred(bank, 0))
 871                 return;
 872
 873         /*
 874          * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
 875          * for a valid error.
 876          */
 877         _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
 878                               MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
 879 }
 880
 881 /* APIC interrupt handler for deferred errors */
 882 static void amd_deferred_error_interrupt(void)
 883 {
 884         unsigned int bank;
 885
 886         for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)
 887                 log_error_deferred(bank);
 888 }
 889
 890 static void log_error_thresholding(unsigned int bank, u64 misc)
 891 {
 892         _log_error_deferred(bank, misc);
 893 }
 894
 895 static void log_and_reset_block(struct threshold_block *block)
 896 {
 897         struct thresh_restart tr;
 898         u32 low = 0, high = 0;
 899
 900         if (!block)
 901                 return;
 902
 903         if (rdmsr_safe(block->address, &low, &high))
 904                 return;
 905
 906         if (!(high & MASK_OVERFLOW_HI))
 907                 return;
 908
 909         /* Log the MCE which caused the threshold event. */
 910         log_error_thresholding(block->bank, ((u64)high << 32) | low);
 911
 912         /* Reset threshold block after logging error. */
 913         memset(&tr, 0, sizeof(tr));
 914         tr.b = block;
 915         threshold_restart_bank(&tr);
 916 }
 917
 918 /*
 919  * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
 920  * goes off when error_count reaches threshold_limit.
 921  */
 922 static void amd_threshold_interrupt(void)
 923 {
 924         struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
 925         struct threshold_bank **bp = this_cpu_read(threshold_banks);
 926         unsigned int bank, cpu = smp_processor_id();
 927
 928         /*
 929          * Validate that the threshold bank has been initialized already. The
 930          * handler is installed at boot time, but on a hotplug event the
 931          * interrupt might fire before the data has been initialized.
 932          */
 933         if (!bp)
 934                 return;
 935
 936         for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
 937                 if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank)))
 938                         continue;
 939
 940                 first_block = bp[bank]->blocks;
 941                 if (!first_block)
 942                         continue;
 943
 944                 /*
 945                  * The first block is also the head of the list. Check it first
 946                  * before iterating over the rest.
 947                  */
 948                 log_and_reset_block(first_block);
 949                 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
 950                         log_and_reset_block(block);
 951         }
 952 }
 953
 954 /*
 955  * Sysfs Interface
 956  */
 957
 958 struct threshold_attr {
 959         struct attribute attr;
 960         ssize_t (*show) (struct threshold_block *, char *);
 961         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
 962 };
 963
 964 #define SHOW_FIELDS(name)                                               \
 965 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
 966 {                                                                       \
 967         return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
 968 }
 969 SHOW_FIELDS(interrupt_enable)
 970 SHOW_FIELDS(threshold_limit)
 971
 972 static ssize_t
 973 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
 974 {
 975         struct thresh_restart tr;
 976         unsigned long new;
 977
 978         if (!b->interrupt_capable)
 979                 return -EINVAL;
 980
 981         if (kstrtoul(buf, 0, &new) < 0)
 982                 return -EINVAL;
 983
 984         b->interrupt_enable = !!new;
 985
 986         memset(&tr, 0, sizeof(tr));
 987         tr.b            = b;
 988
 989         if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1))
 990                 return -ENODEV;
 991
 992         return size;
 993 }
 994
 995 static ssize_t
 996 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
 997 {
 998         struct thresh_restart tr;
 999         unsigned long new;
1000
1001         if (kstrtoul(buf, 0, &new) < 0)
1002                 return -EINVAL;
1003
1004         if (new > THRESHOLD_MAX)
1005                 new = THRESHOLD_MAX;
1006         if (new < 1)
1007                 new = 1;
1008
1009         memset(&tr, 0, sizeof(tr));
1010         tr.old_limit = b->threshold_limit;
1011         b->threshold_limit = new;
1012         tr.b = b;
1013
1014         if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1))
1015                 return -ENODEV;
1016
1017         return size;
1018 }
1019
1020 static ssize_t show_error_count(struct threshold_block *b, char *buf)
1021 {
1022         u32 lo, hi;
1023
1024         /* CPU might be offline by now */
1025         if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi))
1026                 return -ENODEV;
1027
1028         return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
1029                                      (THRESHOLD_MAX - b->threshold_limit)));
1030 }
1031
1032 static struct threshold_attr error_count = {
1033         .attr = {.name = __stringify(error_count), .mode = 0444 },
1034         .show = show_error_count,
1035 };
1036
1037 #define RW_ATTR(val)                                                    \
1038 static struct threshold_attr val = {                                    \
1039         .attr   = {.name = __stringify(val), .mode = 0644 },            \
1040         .show   = show_## val,                                          \
1041         .store  = store_## val,                                         \
1042 };
1043
1044 RW_ATTR(interrupt_enable);
1045 RW_ATTR(threshold_limit);
1046
1047 static struct attribute *default_attrs[] = {
1048         &threshold_limit.attr,
1049         &error_count.attr,
1050         NULL,   /* possibly interrupt_enable if supported, see below */
1051         NULL,
1052 };
1053 ATTRIBUTE_GROUPS(default);
1054
1055 #define to_block(k)     container_of(k, struct threshold_block, kobj)
1056 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
1057
1058 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1059 {
1060         struct threshold_block *b = to_block(kobj);
1061         struct threshold_attr *a = to_attr(attr);
1062         ssize_t ret;
1063
1064         ret = a->show ? a->show(b, buf) : -EIO;
1065
1066         return ret;
1067 }
1068
1069 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1070                      const char *buf, size_t count)
1071 {
1072         struct threshold_block *b = to_block(kobj);
1073         struct threshold_attr *a = to_attr(attr);
1074         ssize_t ret;
1075
1076         ret = a->store ? a->store(b, buf, count) : -EIO;
1077
1078         return ret;
1079 }
1080
1081 static const struct sysfs_ops threshold_ops = {
1082         .show                   = show,
1083         .store                  = store,
1084 };
1085
1086 static void threshold_block_release(struct kobject *kobj);
1087
1088 static const struct kobj_type threshold_ktype = {
1089         .sysfs_ops              = &threshold_ops,
1090         .default_groups         = default_groups,
1091         .release                = threshold_block_release,
1092 };
1093
1094 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b)
1095 {
1096         enum smca_bank_types bank_type;
1097
1098         if (!mce_flags.smca) {
1099                 if (b && bank == 4)
1100                         return bank4_names(b);
1101
1102                 return th_names[bank];
1103         }
1104
1105         bank_type = smca_get_bank_type(cpu, bank);
1106         if (bank_type >= N_SMCA_BANK_TYPES)
1107                 return NULL;
1108
1109         if (b && (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2)) {
1110                 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1111                         return smca_umc_block_names[b->block];
1112                 return NULL;
1113         }
1114
1115         if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1)
1116                 return smca_get_name(bank_type);
1117
1118         snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1119                  "%s_%u", smca_get_name(bank_type),
1120                           per_cpu(smca_banks, cpu)[bank].sysfs_id);
1121         return buf_mcatype;
1122 }
1123
1124 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb,
1125                                      unsigned int bank, unsigned int block,
1126                                      u32 address)
1127 {
1128         struct threshold_block *b = NULL;
1129         u32 low, high;
1130         int err;
1131
1132         if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
1133                 return 0;
1134
1135         if (rdmsr_safe(address, &low, &high))
1136                 return 0;
1137
1138         if (!(high & MASK_VALID_HI)) {
1139                 if (block)
1140                         goto recurse;
1141                 else
1142                         return 0;
1143         }
1144
1145         if (!(high & MASK_CNTP_HI)  ||
1146              (high & MASK_LOCKED_HI))
1147                 goto recurse;
1148
1149         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1150         if (!b)
1151                 return -ENOMEM;
1152
1153         b->block                = block;
1154         b->bank                 = bank;
1155         b->cpu                  = cpu;
1156         b->address              = address;
1157         b->interrupt_enable     = 0;
1158         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1159         b->threshold_limit      = THRESHOLD_MAX;
1160
1161         if (b->interrupt_capable) {
1162                 default_attrs[2] = &interrupt_enable.attr;
1163                 b->interrupt_enable = 1;
1164         } else {
1165                 default_attrs[2] = NULL;
1166         }
1167
1168         INIT_LIST_HEAD(&b->miscj);
1169
1170         /* This is safe as @tb is not visible yet */
1171         if (tb->blocks)
1172                 list_add(&b->miscj, &tb->blocks->miscj);
1173         else
1174                 tb->blocks = b;
1175
1176         err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));
1177         if (err)
1178                 goto out_free;
1179 recurse:
1180         address = get_block_address(address, low, high, bank, ++block, cpu);
1181         if (!address)
1182                 return 0;
1183
1184         err = allocate_threshold_blocks(cpu, tb, bank, block, address);
1185         if (err)
1186                 goto out_free;
1187
1188         if (b)
1189                 kobject_uevent(&b->kobj, KOBJ_ADD);
1190
1191         return 0;
1192
1193 out_free:
1194         if (b) {
1195                 list_del(&b->miscj);
1196                 kobject_put(&b->kobj);
1197         }
1198         return err;
1199 }
1200
1201 static int __threshold_add_blocks(struct threshold_bank *b)
1202 {
1203         struct list_head *head = &b->blocks->miscj;
1204         struct threshold_block *pos = NULL;
1205         struct threshold_block *tmp = NULL;
1206         int err = 0;
1207
1208         err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1209         if (err)
1210                 return err;
1211
1212         list_for_each_entry_safe(pos, tmp, head, miscj) {
1213
1214                 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1215                 if (err) {
1216                         list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1217                                 kobject_del(&pos->kobj);
1218
1219                         return err;
1220                 }
1221         }
1222         return err;
1223 }
1224
1225 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
1226                                  unsigned int bank)
1227 {
1228         struct device *dev = this_cpu_read(mce_device);
1229         struct amd_northbridge *nb = NULL;
1230         struct threshold_bank *b = NULL;
1231         const char *name = get_name(cpu, bank, NULL);
1232         int err = 0;
1233
1234         if (!dev)
1235                 return -ENODEV;
1236
1237         if (is_shared_bank(bank)) {
1238                 nb = node_to_amd_nb(topology_amd_node_id(cpu));
1239
1240                 /* threshold descriptor already initialized on this node? */
1241                 if (nb && nb->bank4) {
1242                         /* yes, use it */
1243                         b = nb->bank4;
1244                         err = kobject_add(b->kobj, &dev->kobj, name);
1245                         if (err)
1246                                 goto out;
1247
1248                         bp[bank] = b;
1249                         refcount_inc(&b->cpus);
1250
1251                         err = __threshold_add_blocks(b);
1252
1253                         goto out;
1254                 }
1255         }
1256
1257         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1258         if (!b) {
1259                 err = -ENOMEM;
1260                 goto out;
1261         }
1262
1263         /* Associate the bank with the per-CPU MCE device */
1264         b->kobj = kobject_create_and_add(name, &dev->kobj);
1265         if (!b->kobj) {
1266                 err = -EINVAL;
1267                 goto out_free;
1268         }
1269
1270         if (is_shared_bank(bank)) {
1271                 b->shared = 1;
1272                 refcount_set(&b->cpus, 1);
1273
1274                 /* nb is already initialized, see above */
1275                 if (nb) {
1276                         WARN_ON(nb->bank4);
1277                         nb->bank4 = b;
1278                 }
1279         }
1280
1281         err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));
1282         if (err)
1283                 goto out_kobj;
1284
1285         bp[bank] = b;
1286         return 0;
1287
1288 out_kobj:
1289         kobject_put(b->kobj);
1290 out_free:
1291         kfree(b);
1292 out:
1293         return err;
1294 }
1295
1296 static void threshold_block_release(struct kobject *kobj)
1297 {
1298         kfree(to_block(kobj));
1299 }
1300
1301 static void deallocate_threshold_blocks(struct threshold_bank *bank)
1302 {
1303         struct threshold_block *pos, *tmp;
1304
1305         list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) {
1306                 list_del(&pos->miscj);
1307                 kobject_put(&pos->kobj);
1308         }
1309
1310         kobject_put(&bank->blocks->kobj);
1311 }
1312
1313 static void __threshold_remove_blocks(struct threshold_bank *b)
1314 {
1315         struct threshold_block *pos = NULL;
1316         struct threshold_block *tmp = NULL;
1317
1318         kobject_put(b->kobj);
1319
1320         list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1321                 kobject_put(b->kobj);
1322 }
1323
1324 static void threshold_remove_bank(struct threshold_bank *bank)
1325 {
1326         struct amd_northbridge *nb;
1327
1328         if (!bank->blocks)
1329                 goto out_free;
1330
1331         if (!bank->shared)
1332                 goto out_dealloc;
1333
1334         if (!refcount_dec_and_test(&bank->cpus)) {
1335                 __threshold_remove_blocks(bank);
1336                 return;
1337         } else {
1338                 /*
1339                  * The last CPU on this node using the shared bank is going
1340                  * away, remove that bank now.
1341                  */
1342                 nb = node_to_amd_nb(topology_amd_node_id(smp_processor_id()));
1343                 nb->bank4 = NULL;
1344         }
1345
1346 out_dealloc:
1347         deallocate_threshold_blocks(bank);
1348
1349 out_free:
1350         kobject_put(bank->kobj);
1351         kfree(bank);
1352 }
1353
1354 static void __threshold_remove_device(struct threshold_bank **bp)
1355 {
1356         unsigned int bank, numbanks = this_cpu_read(mce_num_banks);
1357
1358         for (bank = 0; bank < numbanks; bank++) {
1359                 if (!bp[bank])
1360                         continue;
1361
1362                 threshold_remove_bank(bp[bank]);
1363                 bp[bank] = NULL;
1364         }
1365         kfree(bp);
1366 }
1367
1368 int mce_threshold_remove_device(unsigned int cpu)
1369 {
1370         struct threshold_bank **bp = this_cpu_read(threshold_banks);
1371
1372         if (!bp)
1373                 return 0;
1374
1375         /*
1376          * Clear the pointer before cleaning up, so that the interrupt won't
1377          * touch anything of this.
1378          */
1379         this_cpu_write(threshold_banks, NULL);
1380
1381         __threshold_remove_device(bp);
1382         return 0;
1383 }
1384
1385 /**
1386  * mce_threshold_create_device - Create the per-CPU MCE threshold device
1387  * @cpu:        The plugged in CPU
1388  *
1389  * Create directories and files for all valid threshold banks.
1390  *
1391  * This is invoked from the CPU hotplug callback which was installed in
1392  * mcheck_init_device(). The invocation happens in context of the hotplug
1393  * thread running on @cpu.  The callback is invoked on all CPUs which are
1394  * online when the callback is installed or during a real hotplug event.
1395  */
1396 int mce_threshold_create_device(unsigned int cpu)
1397 {
1398         unsigned int numbanks, bank;
1399         struct threshold_bank **bp;
1400         int err;
1401
1402         if (!mce_flags.amd_threshold)
1403                 return 0;
1404
1405         bp = this_cpu_read(threshold_banks);
1406         if (bp)
1407                 return 0;
1408
1409         numbanks = this_cpu_read(mce_num_banks);
1410         bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL);
1411         if (!bp)
1412                 return -ENOMEM;
1413
1414         for (bank = 0; bank < numbanks; ++bank) {
1415                 if (!(this_cpu_read(bank_map) & BIT_ULL(bank)))
1416                         continue;
1417                 err = threshold_create_bank(bp, cpu, bank);
1418                 if (err) {
1419                         __threshold_remove_device(bp);
1420                         return err;
1421                 }
1422         }
1423         this_cpu_write(threshold_banks, bp);
1424
1425         if (thresholding_irq_en)
1426                 mce_threshold_vector = amd_threshold_interrupt;
1427         return 0;
1428 }