arch/sparc/mm/init_64.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  arch/sparc64/mm/init.c
   4  *
   5  *  Copyright (C) 1996-1999 David S. Miller ([email protected])
   6  *  Copyright (C) 1997-1999 Jakub Jelinek ([email protected])
   7  */
   8
   9 #include <linux/extable.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/string.h>
  13 #include <linux/init.h>
  14 #include <linux/memblock.h>
  15 #include <linux/mm.h>
  16 #include <linux/hugetlb.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/poison.h>
  21 #include <linux/fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/kprobes.h>
  24 #include <linux/cache.h>
  25 #include <linux/sort.h>
  26 #include <linux/ioport.h>
  27 #include <linux/percpu.h>
  28 #include <linux/mmzone.h>
  29 #include <linux/gfp.h>
  30 #include <linux/bootmem_info.h>
  31
  32 #include <asm/head.h>
  33 #include <asm/page.h>
  34 #include <asm/pgalloc.h>
  35 #include <asm/oplib.h>
  36 #include <asm/iommu.h>
  37 #include <asm/io.h>
  38 #include <linux/uaccess.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/tlbflush.h>
  41 #include <asm/dma.h>
  42 #include <asm/starfire.h>
  43 #include <asm/tlb.h>
  44 #include <asm/spitfire.h>
  45 #include <asm/sections.h>
  46 #include <asm/tsb.h>
  47 #include <asm/hypervisor.h>
  48 #include <asm/prom.h>
  49 #include <asm/mdesc.h>
  50 #include <asm/cpudata.h>
  51 #include <asm/setup.h>
  52 #include <asm/irq.h>
  53
  54 #include "init_64.h"
  55
  56 unsigned long kern_linear_pte_xor[4] __read_mostly;
  57 static unsigned long page_cache4v_flag;
  58
  59 /* A bitmap, two bits for every 256MB of physical memory.  These two
  60  * bits determine what page size we use for kernel linear
  61  * translations.  They form an index into kern_linear_pte_xor[].  The
  62  * value in the indexed slot is XOR'd with the TLB miss virtual
  63  * address to form the resulting TTE.  The mapping is:
  64  *
  65  *      0       ==>     4MB
  66  *      1       ==>     256MB
  67  *      2       ==>     2GB
  68  *      3       ==>     16GB
  69  *
  70  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  71  * support 2GB pages, and hopefully future cpus will support the 16GB
  72  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  73  * if these larger page sizes are not supported by the cpu.
  74  *
  75  * It would be nice to determine this from the machine description
  76  * 'cpu' properties, but we need to have this table setup before the
  77  * MDESC is initialized.
  78  */
  79
  80 #ifndef CONFIG_DEBUG_PAGEALLOC
  81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  82  * Space is allocated for this right after the trap table in
  83  * arch/sparc64/kernel/head.S
  84  */
  85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  86 #endif
  87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
  88
  89 static unsigned long cpu_pgsz_mask;
  90
  91 #define MAX_BANKS       1024
  92
  93 static struct linux_prom64_registers pavail[MAX_BANKS];
  94 static int pavail_ents;
  95
  96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
  97
  98 static int cmp_p64(const void *a, const void *b)
  99 {
 100         const struct linux_prom64_registers *x = a, *y = b;
 101
 102         if (x->phys_addr > y->phys_addr)
 103                 return 1;
 104         if (x->phys_addr < y->phys_addr)
 105                 return -1;
 106         return 0;
 107 }
 108
 109 static void __init read_obp_memory(const char *property,
 110                                    struct linux_prom64_registers *regs,
 111                                    int *num_ents)
 112 {
 113         phandle node = prom_finddevice("/memory");
 114         int prop_size = prom_getproplen(node, property);
 115         int ents, ret, i;
 116
 117         ents = prop_size / sizeof(struct linux_prom64_registers);
 118         if (ents > MAX_BANKS) {
 119                 prom_printf("The machine has more %s property entries than "
 120                             "this kernel can support (%d).\n",
 121                             property, MAX_BANKS);
 122                 prom_halt();
 123         }
 124
 125         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 126         if (ret == -1) {
 127                 prom_printf("Couldn't get %s property from /memory.\n",
 128                                 property);
 129                 prom_halt();
 130         }
 131
 132         /* Sanitize what we got from the firmware, by page aligning
 133          * everything.
 134          */
 135         for (i = 0; i < ents; i++) {
 136                 unsigned long base, size;
 137
 138                 base = regs[i].phys_addr;
 139                 size = regs[i].reg_size;
 140
 141                 size &= PAGE_MASK;
 142                 if (base & ~PAGE_MASK) {
 143                         unsigned long new_base = PAGE_ALIGN(base);
 144
 145                         size -= new_base - base;
 146                         if ((long) size < 0L)
 147                                 size = 0UL;
 148                         base = new_base;
 149                 }
 150                 if (size == 0UL) {
 151                         /* If it is empty, simply get rid of it.
 152                          * This simplifies the logic of the other
 153                          * functions that process these arrays.
 154                          */
 155                         memmove(&regs[i], &regs[i + 1],
 156                                 (ents - i - 1) * sizeof(regs[0]));
 157                         i--;
 158                         ents--;
 159                         continue;
 160                 }
 161                 regs[i].phys_addr = base;
 162                 regs[i].reg_size = size;
 163         }
 164
 165         *num_ents = ents;
 166
 167         sort(regs, ents, sizeof(struct linux_prom64_registers),
 168              cmp_p64, NULL);
 169 }
 170
 171 /* Kernel physical address base and size in bytes.  */
 172 unsigned long kern_base __read_mostly;
 173 unsigned long kern_size __read_mostly;
 174
 175 /* Initial ramdisk setup */
 176 extern unsigned long sparc_ramdisk_image64;
 177 extern unsigned int sparc_ramdisk_image;
 178 extern unsigned int sparc_ramdisk_size;
 179
 180 struct page *mem_map_zero __read_mostly;
 181 EXPORT_SYMBOL(mem_map_zero);
 182
 183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 184
 185 unsigned long sparc64_kern_pri_context __read_mostly;
 186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 187 unsigned long sparc64_kern_sec_context __read_mostly;
 188
 189 int num_kernel_image_mappings;
 190
 191 #ifdef CONFIG_DEBUG_DCFLUSH
 192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 193 #ifdef CONFIG_SMP
 194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 195 #endif
 196 #endif
 197
 198 inline void flush_dcache_folio_impl(struct folio *folio)
 199 {
 200         unsigned int i, nr = folio_nr_pages(folio);
 201
 202         BUG_ON(tlb_type == hypervisor);
 203 #ifdef CONFIG_DEBUG_DCFLUSH
 204         atomic_inc(&dcpage_flushes);
 205 #endif
 206
 207 #ifdef DCACHE_ALIASING_POSSIBLE
 208         for (i = 0; i < nr; i++)
 209                 __flush_dcache_page(folio_address(folio) + i * PAGE_SIZE,
 210                                     ((tlb_type == spitfire) &&
 211                                      folio_flush_mapping(folio) != NULL));
 212 #else
 213         if (folio_flush_mapping(folio) != NULL &&
 214             tlb_type == spitfire) {
 215                 for (i = 0; i < nr; i++)
 216                         __flush_icache_page((pfn + i) * PAGE_SIZE);
 217         }
 218 #endif
 219 }
 220
 221 #define PG_dcache_dirty         PG_arch_1
 222 #define PG_dcache_cpu_shift     32UL
 223 #define PG_dcache_cpu_mask      \
 224         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 225
 226 #define dcache_dirty_cpu(folio) \
 227         (((folio)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 228
 229 static inline void set_dcache_dirty(struct folio *folio, int this_cpu)
 230 {
 231         unsigned long mask = this_cpu;
 232         unsigned long non_cpu_bits;
 233
 234         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 235         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 236
 237         __asm__ __volatile__("1:\n\t"
 238                              "ldx       [%2], %%g7\n\t"
 239                              "and       %%g7, %1, %%g1\n\t"
 240                              "or        %%g1, %0, %%g1\n\t"
 241                              "casx      [%2], %%g7, %%g1\n\t"
 242                              "cmp       %%g7, %%g1\n\t"
 243                              "bne,pn    %%xcc, 1b\n\t"
 244                              " nop"
 245                              : /* no outputs */
 246                              : "r" (mask), "r" (non_cpu_bits), "r" (&folio->flags)
 247                              : "g1", "g7");
 248 }
 249
 250 static inline void clear_dcache_dirty_cpu(struct folio *folio, unsigned long cpu)
 251 {
 252         unsigned long mask = (1UL << PG_dcache_dirty);
 253
 254         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 255                              "1:\n\t"
 256                              "ldx       [%2], %%g7\n\t"
 257                              "srlx      %%g7, %4, %%g1\n\t"
 258                              "and       %%g1, %3, %%g1\n\t"
 259                              "cmp       %%g1, %0\n\t"
 260                              "bne,pn    %%icc, 2f\n\t"
 261                              " andn     %%g7, %1, %%g1\n\t"
 262                              "casx      [%2], %%g7, %%g1\n\t"
 263                              "cmp       %%g7, %%g1\n\t"
 264                              "bne,pn    %%xcc, 1b\n\t"
 265                              " nop\n"
 266                              "2:"
 267                              : /* no outputs */
 268                              : "r" (cpu), "r" (mask), "r" (&folio->flags),
 269                                "i" (PG_dcache_cpu_mask),
 270                                "i" (PG_dcache_cpu_shift)
 271                              : "g1", "g7");
 272 }
 273
 274 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 275 {
 276         unsigned long tsb_addr = (unsigned long) ent;
 277
 278         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 279                 tsb_addr = __pa(tsb_addr);
 280
 281         __tsb_insert(tsb_addr, tag, pte);
 282 }
 283
 284 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 285
 286 static void flush_dcache(unsigned long pfn)
 287 {
 288         struct page *page;
 289
 290         page = pfn_to_page(pfn);
 291         if (page) {
 292                 struct folio *folio = page_folio(page);
 293                 unsigned long pg_flags;
 294
 295                 pg_flags = folio->flags;
 296                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 297                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 298                                    PG_dcache_cpu_mask);
 299                         int this_cpu = get_cpu();
 300
 301                         /* This is just to optimize away some function calls
 302                          * in the SMP case.
 303                          */
 304                         if (cpu == this_cpu)
 305                                 flush_dcache_folio_impl(folio);
 306                         else
 307                                 smp_flush_dcache_folio_impl(folio, cpu);
 308
 309                         clear_dcache_dirty_cpu(folio, cpu);
 310
 311                         put_cpu();
 312                 }
 313         }
 314 }
 315
 316 /* mm->context.lock must be held */
 317 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 318                                     unsigned long tsb_hash_shift, unsigned long address,
 319                                     unsigned long tte)
 320 {
 321         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 322         unsigned long tag;
 323
 324         if (unlikely(!tsb))
 325                 return;
 326
 327         tsb += ((address >> tsb_hash_shift) &
 328                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 329         tag = (address >> 22UL);
 330         tsb_insert(tsb, tag, tte);
 331 }
 332
 333 #ifdef CONFIG_HUGETLB_PAGE
 334 static int __init hugetlbpage_init(void)
 335 {
 336         hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
 337         hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
 338         hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
 339         hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
 340
 341         return 0;
 342 }
 343
 344 arch_initcall(hugetlbpage_init);
 345
 346 static void __init pud_huge_patch(void)
 347 {
 348         struct pud_huge_patch_entry *p;
 349         unsigned long addr;
 350
 351         p = &__pud_huge_patch;
 352         addr = p->addr;
 353         *(unsigned int *)addr = p->insn;
 354
 355         __asm__ __volatile__("flush %0" : : "r" (addr));
 356 }
 357
 358 bool __init arch_hugetlb_valid_size(unsigned long size)
 359 {
 360         unsigned int hugepage_shift = ilog2(size);
 361         unsigned short hv_pgsz_idx;
 362         unsigned int hv_pgsz_mask;
 363
 364         switch (hugepage_shift) {
 365         case HPAGE_16GB_SHIFT:
 366                 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
 367                 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
 368                 pud_huge_patch();
 369                 break;
 370         case HPAGE_2GB_SHIFT:
 371                 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
 372                 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
 373                 break;
 374         case HPAGE_256MB_SHIFT:
 375                 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
 376                 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
 377                 break;
 378         case HPAGE_SHIFT:
 379                 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
 380                 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
 381                 break;
 382         case HPAGE_64K_SHIFT:
 383                 hv_pgsz_mask = HV_PGSZ_MASK_64K;
 384                 hv_pgsz_idx = HV_PGSZ_IDX_64K;
 385                 break;
 386         default:
 387                 hv_pgsz_mask = 0;
 388         }
 389
 390         if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
 391                 return false;
 392
 393         return true;
 394 }
 395 #endif  /* CONFIG_HUGETLB_PAGE */
 396
 397 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
 398                 unsigned long address, pte_t *ptep, unsigned int nr)
 399 {
 400         struct mm_struct *mm;
 401         unsigned long flags;
 402         bool is_huge_tsb;
 403         pte_t pte = *ptep;
 404         unsigned int i;
 405
 406         if (tlb_type != hypervisor) {
 407                 unsigned long pfn = pte_pfn(pte);
 408
 409                 if (pfn_valid(pfn))
 410                         flush_dcache(pfn);
 411         }
 412
 413         mm = vma->vm_mm;
 414
 415         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
 416         if (!pte_accessible(mm, pte))
 417                 return;
 418
 419         spin_lock_irqsave(&mm->context.lock, flags);
 420
 421         is_huge_tsb = false;
 422 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 423         if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
 424                 unsigned long hugepage_size = PAGE_SIZE;
 425
 426                 if (is_vm_hugetlb_page(vma))
 427                         hugepage_size = huge_page_size(hstate_vma(vma));
 428
 429                 if (hugepage_size >= PUD_SIZE) {
 430                         unsigned long mask = 0x1ffc00000UL;
 431
 432                         /* Transfer bits [32:22] from address to resolve
 433                          * at 4M granularity.
 434                          */
 435                         pte_val(pte) &= ~mask;
 436                         pte_val(pte) |= (address & mask);
 437                 } else if (hugepage_size >= PMD_SIZE) {
 438                         /* We are fabricating 8MB pages using 4MB
 439                          * real hw pages.
 440                          */
 441                         pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
 442                 }
 443
 444                 if (hugepage_size >= PMD_SIZE) {
 445                         __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
 446                                 REAL_HPAGE_SHIFT, address, pte_val(pte));
 447                         is_huge_tsb = true;
 448                 }
 449         }
 450 #endif
 451         if (!is_huge_tsb) {
 452                 for (i = 0; i < nr; i++) {
 453                         __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 454                                                 address, pte_val(pte));
 455                         address += PAGE_SIZE;
 456                         pte_val(pte) += PAGE_SIZE;
 457                 }
 458         }
 459
 460         spin_unlock_irqrestore(&mm->context.lock, flags);
 461 }
 462
 463 void flush_dcache_folio(struct folio *folio)
 464 {
 465         unsigned long pfn = folio_pfn(folio);
 466         struct address_space *mapping;
 467         int this_cpu;
 468
 469         if (tlb_type == hypervisor)
 470                 return;
 471
 472         /* Do not bother with the expensive D-cache flush if it
 473          * is merely the zero page.  The 'bigcore' testcase in GDB
 474          * causes this case to run millions of times.
 475          */
 476         if (is_zero_pfn(pfn))
 477                 return;
 478
 479         this_cpu = get_cpu();
 480
 481         mapping = folio_flush_mapping(folio);
 482         if (mapping && !mapping_mapped(mapping)) {
 483                 bool dirty = test_bit(PG_dcache_dirty, &folio->flags);
 484                 if (dirty) {
 485                         int dirty_cpu = dcache_dirty_cpu(folio);
 486
 487                         if (dirty_cpu == this_cpu)
 488                                 goto out;
 489                         smp_flush_dcache_folio_impl(folio, dirty_cpu);
 490                 }
 491                 set_dcache_dirty(folio, this_cpu);
 492         } else {
 493                 /* We could delay the flush for the !folio_mapping
 494                  * case too.  But that case is for exec env/arg
 495                  * pages and those are %99 certainly going to get
 496                  * faulted into the tlb (and thus flushed) anyways.
 497                  */
 498                 flush_dcache_folio_impl(folio);
 499         }
 500
 501 out:
 502         put_cpu();
 503 }
 504 EXPORT_SYMBOL(flush_dcache_folio);
 505
 506 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 507 {
 508         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 509         if (tlb_type == spitfire) {
 510                 unsigned long kaddr;
 511
 512                 /* This code only runs on Spitfire cpus so this is
 513                  * why we can assume _PAGE_PADDR_4U.
 514                  */
 515                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 516                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 517
 518                         if (kaddr >= PAGE_OFFSET)
 519                                 paddr = kaddr & mask;
 520                         else {
 521                                 pte_t *ptep = virt_to_kpte(kaddr);
 522
 523                                 paddr = pte_val(*ptep) & mask;
 524                         }
 525                         __flush_icache_page(paddr);
 526                 }
 527         }
 528 }
 529 EXPORT_SYMBOL(flush_icache_range);
 530
 531 void mmu_info(struct seq_file *m)
 532 {
 533         static const char *pgsz_strings[] = {
 534                 "8K", "64K", "512K", "4MB", "32MB",
 535                 "256MB", "2GB", "16GB",
 536         };
 537         int i, printed;
 538
 539         if (tlb_type == cheetah)
 540                 seq_printf(m, "MMU Type\t: Cheetah\n");
 541         else if (tlb_type == cheetah_plus)
 542                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 543         else if (tlb_type == spitfire)
 544                 seq_printf(m, "MMU Type\t: Spitfire\n");
 545         else if (tlb_type == hypervisor)
 546                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 547         else
 548                 seq_printf(m, "MMU Type\t: ???\n");
 549
 550         seq_printf(m, "MMU PGSZs\t: ");
 551         printed = 0;
 552         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 553                 if (cpu_pgsz_mask & (1UL << i)) {
 554                         seq_printf(m, "%s%s",
 555                                    printed ? "," : "", pgsz_strings[i]);
 556                         printed++;
 557                 }
 558         }
 559         seq_putc(m, '\n');
 560
 561 #ifdef CONFIG_DEBUG_DCFLUSH
 562         seq_printf(m, "DCPageFlushes\t: %d\n",
 563                    atomic_read(&dcpage_flushes));
 564 #ifdef CONFIG_SMP
 565         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 566                    atomic_read(&dcpage_flushes_xcall));
 567 #endif /* CONFIG_SMP */
 568 #endif /* CONFIG_DEBUG_DCFLUSH */
 569 }
 570
 571 struct linux_prom_translation prom_trans[512] __read_mostly;
 572 unsigned int prom_trans_ents __read_mostly;
 573
 574 unsigned long kern_locked_tte_data;
 575
 576 /* The obp translations are saved based on 8k pagesize, since obp can
 577  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 578  * HI_OBP_ADDRESS range are handled in ktlb.S.
 579  */
 580 static inline int in_obp_range(unsigned long vaddr)
 581 {
 582         return (vaddr >= LOW_OBP_ADDRESS &&
 583                 vaddr < HI_OBP_ADDRESS);
 584 }
 585
 586 static int cmp_ptrans(const void *a, const void *b)
 587 {
 588         const struct linux_prom_translation *x = a, *y = b;
 589
 590         if (x->virt > y->virt)
 591                 return 1;
 592         if (x->virt < y->virt)
 593                 return -1;
 594         return 0;
 595 }
 596
 597 /* Read OBP translations property into 'prom_trans[]'.  */
 598 static void __init read_obp_translations(void)
 599 {
 600         int n, node, ents, first, last, i;
 601
 602         node = prom_finddevice("/virtual-memory");
 603         n = prom_getproplen(node, "translations");
 604         if (unlikely(n == 0 || n == -1)) {
 605                 prom_printf("prom_mappings: Couldn't get size.\n");
 606                 prom_halt();
 607         }
 608         if (unlikely(n > sizeof(prom_trans))) {
 609                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 610                 prom_halt();
 611         }
 612
 613         if ((n = prom_getproperty(node, "translations",
 614                                   (char *)&prom_trans[0],
 615                                   sizeof(prom_trans))) == -1) {
 616                 prom_printf("prom_mappings: Couldn't get property.\n");
 617                 prom_halt();
 618         }
 619
 620         n = n / sizeof(struct linux_prom_translation);
 621
 622         ents = n;
 623
 624         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 625              cmp_ptrans, NULL);
 626
 627         /* Now kick out all the non-OBP entries.  */
 628         for (i = 0; i < ents; i++) {
 629                 if (in_obp_range(prom_trans[i].virt))
 630                         break;
 631         }
 632         first = i;
 633         for (; i < ents; i++) {
 634                 if (!in_obp_range(prom_trans[i].virt))
 635                         break;
 636         }
 637         last = i;
 638
 639         for (i = 0; i < (last - first); i++) {
 640                 struct linux_prom_translation *src = &prom_trans[i + first];
 641                 struct linux_prom_translation *dest = &prom_trans[i];
 642
 643                 *dest = *src;
 644         }
 645         for (; i < ents; i++) {
 646                 struct linux_prom_translation *dest = &prom_trans[i];
 647                 dest->virt = dest->size = dest->data = 0x0UL;
 648         }
 649
 650         prom_trans_ents = last - first;
 651
 652         if (tlb_type == spitfire) {
 653                 /* Clear diag TTE bits. */
 654                 for (i = 0; i < prom_trans_ents; i++)
 655                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 656         }
 657
 658         /* Force execute bit on.  */
 659         for (i = 0; i < prom_trans_ents; i++)
 660                 prom_trans[i].data |= (tlb_type == hypervisor ?
 661                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 662 }
 663
 664 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 665                                        unsigned long pte,
 666                                        unsigned long mmu)
 667 {
 668         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 669
 670         if (ret != 0) {
 671                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 672                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 673                 prom_halt();
 674         }
 675 }
 676
 677 static unsigned long kern_large_tte(unsigned long paddr);
 678
 679 static void __init remap_kernel(void)
 680 {
 681         unsigned long phys_page, tte_vaddr, tte_data;
 682         int i, tlb_ent = sparc64_highest_locked_tlbent();
 683
 684         tte_vaddr = (unsigned long) KERNBASE;
 685         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
 686         tte_data = kern_large_tte(phys_page);
 687
 688         kern_locked_tte_data = tte_data;
 689
 690         /* Now lock us into the TLBs via Hypervisor or OBP. */
 691         if (tlb_type == hypervisor) {
 692                 for (i = 0; i < num_kernel_image_mappings; i++) {
 693                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 694                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 695                         tte_vaddr += 0x400000;
 696                         tte_data += 0x400000;
 697                 }
 698         } else {
 699                 for (i = 0; i < num_kernel_image_mappings; i++) {
 700                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 701                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 702                         tte_vaddr += 0x400000;
 703                         tte_data += 0x400000;
 704                 }
 705                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 706         }
 707         if (tlb_type == cheetah_plus) {
 708                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 709                                             CTX_CHEETAH_PLUS_NUC);
 710                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 711                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 712         }
 713 }
 714
 715
 716 static void __init inherit_prom_mappings(void)
 717 {
 718         /* Now fixup OBP's idea about where we really are mapped. */
 719         printk("Remapping the kernel... ");
 720         remap_kernel();
 721         printk("done.\n");
 722 }
 723
 724 void prom_world(int enter)
 725 {
 726         /*
 727          * No need to change the address space any more, just flush
 728          * the register windows
 729          */
 730         __asm__ __volatile__("flushw");
 731 }
 732
 733 void __flush_dcache_range(unsigned long start, unsigned long end)
 734 {
 735         unsigned long va;
 736
 737         if (tlb_type == spitfire) {
 738                 int n = 0;
 739
 740                 for (va = start; va < end; va += 32) {
 741                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 742                         if (++n >= 512)
 743                                 break;
 744                 }
 745         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 746                 start = __pa(start);
 747                 end = __pa(end);
 748                 for (va = start; va < end; va += 32)
 749                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 750                                              "membar #Sync"
 751                                              : /* no outputs */
 752                                              : "r" (va),
 753                                                "i" (ASI_DCACHE_INVALIDATE));
 754         }
 755 }
 756 EXPORT_SYMBOL(__flush_dcache_range);
 757
 758 /* get_new_mmu_context() uses "cache + 1".  */
 759 DEFINE_SPINLOCK(ctx_alloc_lock);
 760 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
 761 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 762 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 763 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 764 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
 765
 766 static void mmu_context_wrap(void)
 767 {
 768         unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
 769         unsigned long new_ver, new_ctx, old_ctx;
 770         struct mm_struct *mm;
 771         int cpu;
 772
 773         bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
 774
 775         /* Reserve kernel context */
 776         set_bit(0, mmu_context_bmap);
 777
 778         new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
 779         if (unlikely(new_ver == 0))
 780                 new_ver = CTX_FIRST_VERSION;
 781         tlb_context_cache = new_ver;
 782
 783         /*
 784          * Make sure that any new mm that are added into per_cpu_secondary_mm,
 785          * are going to go through get_new_mmu_context() path.
 786          */
 787         mb();
 788
 789         /*
 790          * Updated versions to current on those CPUs that had valid secondary
 791          * contexts
 792          */
 793         for_each_online_cpu(cpu) {
 794                 /*
 795                  * If a new mm is stored after we took this mm from the array,
 796                  * it will go into get_new_mmu_context() path, because we
 797                  * already bumped the version in tlb_context_cache.
 798                  */
 799                 mm = per_cpu(per_cpu_secondary_mm, cpu);
 800
 801                 if (unlikely(!mm || mm == &init_mm))
 802                         continue;
 803
 804                 old_ctx = mm->context.sparc64_ctx_val;
 805                 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
 806                         new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
 807                         set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
 808                         mm->context.sparc64_ctx_val = new_ctx;
 809                 }
 810         }
 811 }
 812
 813 /* Caller does TLB context flushing on local CPU if necessary.
 814  * The caller also ensures that CTX_VALID(mm->context) is false.
 815  *
 816  * We must be careful about boundary cases so that we never
 817  * let the user have CTX 0 (nucleus) or we ever use a CTX
 818  * version of zero (and thus NO_CONTEXT would not be caught
 819  * by version mis-match tests in mmu_context.h).
 820  *
 821  * Always invoked with interrupts disabled.
 822  */
 823 void get_new_mmu_context(struct mm_struct *mm)
 824 {
 825         unsigned long ctx, new_ctx;
 826         unsigned long orig_pgsz_bits;
 827
 828         spin_lock(&ctx_alloc_lock);
 829 retry:
 830         /* wrap might have happened, test again if our context became valid */
 831         if (unlikely(CTX_VALID(mm->context)))
 832                 goto out;
 833         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 834         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 835         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 836         if (new_ctx >= (1 << CTX_NR_BITS)) {
 837                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 838                 if (new_ctx >= ctx) {
 839                         mmu_context_wrap();
 840                         goto retry;
 841                 }
 842         }
 843         if (mm->context.sparc64_ctx_val)
 844                 cpumask_clear(mm_cpumask(mm));
 845         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 846         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 847         tlb_context_cache = new_ctx;
 848         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 849 out:
 850         spin_unlock(&ctx_alloc_lock);
 851 }
 852
 853 static int numa_enabled = 1;
 854 static int numa_debug;
 855
 856 static int __init early_numa(char *p)
 857 {
 858         if (!p)
 859                 return 0;
 860
 861         if (strstr(p, "off"))
 862                 numa_enabled = 0;
 863
 864         if (strstr(p, "debug"))
 865                 numa_debug = 1;
 866
 867         return 0;
 868 }
 869 early_param("numa", early_numa);
 870
 871 #define numadbg(f, a...) \
 872 do {    if (numa_debug) \
 873                 printk(KERN_INFO f, ## a); \
 874 } while (0)
 875
 876 static void __init find_ramdisk(unsigned long phys_base)
 877 {
 878 #ifdef CONFIG_BLK_DEV_INITRD
 879         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 880                 unsigned long ramdisk_image;
 881
 882                 /* Older versions of the bootloader only supported a
 883                  * 32-bit physical address for the ramdisk image
 884                  * location, stored at sparc_ramdisk_image.  Newer
 885                  * SILO versions set sparc_ramdisk_image to zero and
 886                  * provide a full 64-bit physical address at
 887                  * sparc_ramdisk_image64.
 888                  */
 889                 ramdisk_image = sparc_ramdisk_image;
 890                 if (!ramdisk_image)
 891                         ramdisk_image = sparc_ramdisk_image64;
 892
 893                 /* Another bootloader quirk.  The bootloader normalizes
 894                  * the physical address to KERNBASE, so we have to
 895                  * factor that back out and add in the lowest valid
 896                  * physical page address to get the true physical address.
 897                  */
 898                 ramdisk_image -= KERNBASE;
 899                 ramdisk_image += phys_base;
 900
 901                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 902                         ramdisk_image, sparc_ramdisk_size);
 903
 904                 initrd_start = ramdisk_image;
 905                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 906
 907                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 908
 909                 initrd_start += PAGE_OFFSET;
 910                 initrd_end += PAGE_OFFSET;
 911         }
 912 #endif
 913 }
 914
 915 struct node_mem_mask {
 916         unsigned long mask;
 917         unsigned long match;
 918 };
 919 static struct node_mem_mask node_masks[MAX_NUMNODES];
 920 static int num_node_masks;
 921
 922 #ifdef CONFIG_NUMA
 923
 924 struct mdesc_mlgroup {
 925         u64     node;
 926         u64     latency;
 927         u64     match;
 928         u64     mask;
 929 };
 930
 931 static struct mdesc_mlgroup *mlgroups;
 932 static int num_mlgroups;
 933
 934 int numa_cpu_lookup_table[NR_CPUS];
 935 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 936
 937 struct mdesc_mblock {
 938         u64     base;
 939         u64     size;
 940         u64     offset; /* RA-to-PA */
 941 };
 942 static struct mdesc_mblock *mblocks;
 943 static int num_mblocks;
 944
 945 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
 946 {
 947         struct mdesc_mblock *m = NULL;
 948         int i;
 949
 950         for (i = 0; i < num_mblocks; i++) {
 951                 m = &mblocks[i];
 952
 953                 if (addr >= m->base &&
 954                     addr < (m->base + m->size)) {
 955                         break;
 956                 }
 957         }
 958
 959         return m;
 960 }
 961
 962 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
 963 {
 964         int prev_nid, new_nid;
 965
 966         prev_nid = NUMA_NO_NODE;
 967         for ( ; start < end; start += PAGE_SIZE) {
 968                 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
 969                         struct node_mem_mask *p = &node_masks[new_nid];
 970
 971                         if ((start & p->mask) == p->match) {
 972                                 if (prev_nid == NUMA_NO_NODE)
 973                                         prev_nid = new_nid;
 974                                 break;
 975                         }
 976                 }
 977
 978                 if (new_nid == num_node_masks) {
 979                         prev_nid = 0;
 980                         WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
 981                                   start);
 982                         break;
 983                 }
 984
 985                 if (prev_nid != new_nid)
 986                         break;
 987         }
 988         *nid = prev_nid;
 989
 990         return start > end ? end : start;
 991 }
 992
 993 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
 994 {
 995         u64 ret_end, pa_start, m_mask, m_match, m_end;
 996         struct mdesc_mblock *mblock;
 997         int _nid, i;
 998
 999         if (tlb_type != hypervisor)
1000                 return memblock_nid_range_sun4u(start, end, nid);
1001
1002         mblock = addr_to_mblock(start);
1003         if (!mblock) {
1004                 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1005                           start);
1006
1007                 _nid = 0;
1008                 ret_end = end;
1009                 goto done;
1010         }
1011
1012         pa_start = start + mblock->offset;
1013         m_match = 0;
1014         m_mask = 0;
1015
1016         for (_nid = 0; _nid < num_node_masks; _nid++) {
1017                 struct node_mem_mask *const m = &node_masks[_nid];
1018
1019                 if ((pa_start & m->mask) == m->match) {
1020                         m_match = m->match;
1021                         m_mask = m->mask;
1022                         break;
1023                 }
1024         }
1025
1026         if (num_node_masks == _nid) {
1027                 /* We could not find NUMA group, so default to 0, but lets
1028                  * search for latency group, so we could calculate the correct
1029                  * end address that we return
1030                  */
1031                 _nid = 0;
1032
1033                 for (i = 0; i < num_mlgroups; i++) {
1034                         struct mdesc_mlgroup *const m = &mlgroups[i];
1035
1036                         if ((pa_start & m->mask) == m->match) {
1037                                 m_match = m->match;
1038                                 m_mask = m->mask;
1039                                 break;
1040                         }
1041                 }
1042
1043                 if (i == num_mlgroups) {
1044                         WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1045                                   start);
1046
1047                         ret_end = end;
1048                         goto done;
1049                 }
1050         }
1051
1052         /*
1053          * Each latency group has match and mask, and each memory block has an
1054          * offset.  An address belongs to a latency group if its address matches
1055          * the following formula: ((addr + offset) & mask) == match
1056          * It is, however, slow to check every single page if it matches a
1057          * particular latency group. As optimization we calculate end value by
1058          * using bit arithmetics.
1059          */
1060         m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1061         m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1062         ret_end = m_end > end ? end : m_end;
1063
1064 done:
1065         *nid = _nid;
1066         return ret_end;
1067 }
1068 #endif
1069
1070 /* This must be invoked after performing all of the necessary
1071  * memblock_set_node() calls for 'nid'.  We need to be able to get
1072  * correct data from get_pfn_range_for_nid().
1073  */
1074 static void __init allocate_node_data(int nid)
1075 {
1076         struct pglist_data *p;
1077         unsigned long start_pfn, end_pfn;
1078
1079 #ifdef CONFIG_NUMA
1080         alloc_node_data(nid);
1081
1082         NODE_DATA(nid)->node_id = nid;
1083 #endif
1084
1085         p = NODE_DATA(nid);
1086
1087         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1088         p->node_start_pfn = start_pfn;
1089         p->node_spanned_pages = end_pfn - start_pfn;
1090 }
1091
1092 static void init_node_masks_nonnuma(void)
1093 {
1094 #ifdef CONFIG_NUMA
1095         int i;
1096 #endif
1097
1098         numadbg("Initializing tables for non-numa.\n");
1099
1100         node_masks[0].mask = 0;
1101         node_masks[0].match = 0;
1102         num_node_masks = 1;
1103
1104 #ifdef CONFIG_NUMA
1105         for (i = 0; i < NR_CPUS; i++)
1106                 numa_cpu_lookup_table[i] = 0;
1107
1108         cpumask_setall(&numa_cpumask_lookup_table[0]);
1109 #endif
1110 }
1111
1112 #ifdef CONFIG_NUMA
1113
1114 EXPORT_SYMBOL(numa_cpu_lookup_table);
1115 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1116
1117 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1118                                    u32 cfg_handle)
1119 {
1120         u64 arc;
1121
1122         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1123                 u64 target = mdesc_arc_target(md, arc);
1124                 const u64 *val;
1125
1126                 val = mdesc_get_property(md, target,
1127                                          "cfg-handle", NULL);
1128                 if (val && *val == cfg_handle)
1129                         return 0;
1130         }
1131         return -ENODEV;
1132 }
1133
1134 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1135                                     u32 cfg_handle)
1136 {
1137         u64 arc, candidate, best_latency = ~(u64)0;
1138
1139         candidate = MDESC_NODE_NULL;
1140         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1141                 u64 target = mdesc_arc_target(md, arc);
1142                 const char *name = mdesc_node_name(md, target);
1143                 const u64 *val;
1144
1145                 if (strcmp(name, "pio-latency-group"))
1146                         continue;
1147
1148                 val = mdesc_get_property(md, target, "latency", NULL);
1149                 if (!val)
1150                         continue;
1151
1152                 if (*val < best_latency) {
1153                         candidate = target;
1154                         best_latency = *val;
1155                 }
1156         }
1157
1158         if (candidate == MDESC_NODE_NULL)
1159                 return -ENODEV;
1160
1161         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1162 }
1163
1164 int of_node_to_nid(struct device_node *dp)
1165 {
1166         const struct linux_prom64_registers *regs;
1167         struct mdesc_handle *md;
1168         u32 cfg_handle;
1169         int count, nid;
1170         u64 grp;
1171
1172         /* This is the right thing to do on currently supported
1173          * SUN4U NUMA platforms as well, as the PCI controller does
1174          * not sit behind any particular memory controller.
1175          */
1176         if (!mlgroups)
1177                 return -1;
1178
1179         regs = of_get_property(dp, "reg", NULL);
1180         if (!regs)
1181                 return -1;
1182
1183         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1184
1185         md = mdesc_grab();
1186
1187         count = 0;
1188         nid = NUMA_NO_NODE;
1189         mdesc_for_each_node_by_name(md, grp, "group") {
1190                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1191                         nid = count;
1192                         break;
1193                 }
1194                 count++;
1195         }
1196
1197         mdesc_release(md);
1198
1199         return nid;
1200 }
1201
1202 static void __init add_node_ranges(void)
1203 {
1204         phys_addr_t start, end;
1205         unsigned long prev_max;
1206         u64 i;
1207
1208 memblock_resized:
1209         prev_max = memblock.memory.max;
1210
1211         for_each_mem_range(i, &start, &end) {
1212                 while (start < end) {
1213                         unsigned long this_end;
1214                         int nid;
1215
1216                         this_end = memblock_nid_range(start, end, &nid);
1217
1218                         numadbg("Setting memblock NUMA node nid[%d] "
1219                                 "start[%llx] end[%lx]\n",
1220                                 nid, start, this_end);
1221
1222                         memblock_set_node(start, this_end - start,
1223                                           &memblock.memory, nid);
1224                         if (memblock.memory.max != prev_max)
1225                                 goto memblock_resized;
1226                         start = this_end;
1227                 }
1228         }
1229 }
1230
1231 static int __init grab_mlgroups(struct mdesc_handle *md)
1232 {
1233         unsigned long paddr;
1234         int count = 0;
1235         u64 node;
1236
1237         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1238                 count++;
1239         if (!count)
1240                 return -ENOENT;
1241
1242         paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1243                                     SMP_CACHE_BYTES);
1244         if (!paddr)
1245                 return -ENOMEM;
1246
1247         mlgroups = __va(paddr);
1248         num_mlgroups = count;
1249
1250         count = 0;
1251         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1252                 struct mdesc_mlgroup *m = &mlgroups[count++];
1253                 const u64 *val;
1254
1255                 m->node = node;
1256
1257                 val = mdesc_get_property(md, node, "latency", NULL);
1258                 m->latency = *val;
1259                 val = mdesc_get_property(md, node, "address-match", NULL);
1260                 m->match = *val;
1261                 val = mdesc_get_property(md, node, "address-mask", NULL);
1262                 m->mask = *val;
1263
1264                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1265                         "match[%llx] mask[%llx]\n",
1266                         count - 1, m->node, m->latency, m->match, m->mask);
1267         }
1268
1269         return 0;
1270 }
1271
1272 static int __init grab_mblocks(struct mdesc_handle *md)
1273 {
1274         unsigned long paddr;
1275         int count = 0;
1276         u64 node;
1277
1278         mdesc_for_each_node_by_name(md, node, "mblock")
1279                 count++;
1280         if (!count)
1281                 return -ENOENT;
1282
1283         paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1284                                     SMP_CACHE_BYTES);
1285         if (!paddr)
1286                 return -ENOMEM;
1287
1288         mblocks = __va(paddr);
1289         num_mblocks = count;
1290
1291         count = 0;
1292         mdesc_for_each_node_by_name(md, node, "mblock") {
1293                 struct mdesc_mblock *m = &mblocks[count++];
1294                 const u64 *val;
1295
1296                 val = mdesc_get_property(md, node, "base", NULL);
1297                 m->base = *val;
1298                 val = mdesc_get_property(md, node, "size", NULL);
1299                 m->size = *val;
1300                 val = mdesc_get_property(md, node,
1301                                          "address-congruence-offset", NULL);
1302
1303                 /* The address-congruence-offset property is optional.
1304                  * Explicity zero it be identifty this.
1305                  */
1306                 if (val)
1307                         m->offset = *val;
1308                 else
1309                         m->offset = 0UL;
1310
1311                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1312                         count - 1, m->base, m->size, m->offset);
1313         }
1314
1315         return 0;
1316 }
1317
1318 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1319                                                u64 grp, cpumask_t *mask)
1320 {
1321         u64 arc;
1322
1323         cpumask_clear(mask);
1324
1325         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1326                 u64 target = mdesc_arc_target(md, arc);
1327                 const char *name = mdesc_node_name(md, target);
1328                 const u64 *id;
1329
1330                 if (strcmp(name, "cpu"))
1331                         continue;
1332                 id = mdesc_get_property(md, target, "id", NULL);
1333                 if (*id < nr_cpu_ids)
1334                         cpumask_set_cpu(*id, mask);
1335         }
1336 }
1337
1338 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1339 {
1340         int i;
1341
1342         for (i = 0; i < num_mlgroups; i++) {
1343                 struct mdesc_mlgroup *m = &mlgroups[i];
1344                 if (m->node == node)
1345                         return m;
1346         }
1347         return NULL;
1348 }
1349
1350 int __node_distance(int from, int to)
1351 {
1352         if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1353                 pr_warn("Returning default NUMA distance value for %d->%d\n",
1354                         from, to);
1355                 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1356         }
1357         return numa_latency[from][to];
1358 }
1359 EXPORT_SYMBOL(__node_distance);
1360
1361 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1362 {
1363         int i;
1364
1365         for (i = 0; i < MAX_NUMNODES; i++) {
1366                 struct node_mem_mask *n = &node_masks[i];
1367
1368                 if ((grp->mask == n->mask) && (grp->match == n->match))
1369                         break;
1370         }
1371         return i;
1372 }
1373
1374 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1375                                                  u64 grp, int index)
1376 {
1377         u64 arc;
1378
1379         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1380                 int tnode;
1381                 u64 target = mdesc_arc_target(md, arc);
1382                 struct mdesc_mlgroup *m = find_mlgroup(target);
1383
1384                 if (!m)
1385                         continue;
1386                 tnode = find_best_numa_node_for_mlgroup(m);
1387                 if (tnode == MAX_NUMNODES)
1388                         continue;
1389                 numa_latency[index][tnode] = m->latency;
1390         }
1391 }
1392
1393 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1394                                       int index)
1395 {
1396         struct mdesc_mlgroup *candidate = NULL;
1397         u64 arc, best_latency = ~(u64)0;
1398         struct node_mem_mask *n;
1399
1400         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1401                 u64 target = mdesc_arc_target(md, arc);
1402                 struct mdesc_mlgroup *m = find_mlgroup(target);
1403                 if (!m)
1404                         continue;
1405                 if (m->latency < best_latency) {
1406                         candidate = m;
1407                         best_latency = m->latency;
1408                 }
1409         }
1410         if (!candidate)
1411                 return -ENOENT;
1412
1413         if (num_node_masks != index) {
1414                 printk(KERN_ERR "Inconsistent NUMA state, "
1415                        "index[%d] != num_node_masks[%d]\n",
1416                        index, num_node_masks);
1417                 return -EINVAL;
1418         }
1419
1420         n = &node_masks[num_node_masks++];
1421
1422         n->mask = candidate->mask;
1423         n->match = candidate->match;
1424
1425         numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1426                 index, n->mask, n->match, candidate->latency);
1427
1428         return 0;
1429 }
1430
1431 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1432                                          int index)
1433 {
1434         cpumask_t mask;
1435         int cpu;
1436
1437         numa_parse_mdesc_group_cpus(md, grp, &mask);
1438
1439         for_each_cpu(cpu, &mask)
1440                 numa_cpu_lookup_table[cpu] = index;
1441         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1442
1443         if (numa_debug) {
1444                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1445                 for_each_cpu(cpu, &mask)
1446                         printk("%d ", cpu);
1447                 printk("]\n");
1448         }
1449
1450         return numa_attach_mlgroup(md, grp, index);
1451 }
1452
1453 static int __init numa_parse_mdesc(void)
1454 {
1455         struct mdesc_handle *md = mdesc_grab();
1456         int i, j, err, count;
1457         u64 node;
1458
1459         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1460         if (node == MDESC_NODE_NULL) {
1461                 mdesc_release(md);
1462                 return -ENOENT;
1463         }
1464
1465         err = grab_mblocks(md);
1466         if (err < 0)
1467                 goto out;
1468
1469         err = grab_mlgroups(md);
1470         if (err < 0)
1471                 goto out;
1472
1473         count = 0;
1474         mdesc_for_each_node_by_name(md, node, "group") {
1475                 err = numa_parse_mdesc_group(md, node, count);
1476                 if (err < 0)
1477                         break;
1478                 count++;
1479         }
1480
1481         count = 0;
1482         mdesc_for_each_node_by_name(md, node, "group") {
1483                 find_numa_latencies_for_group(md, node, count);
1484                 count++;
1485         }
1486
1487         /* Normalize numa latency matrix according to ACPI SLIT spec. */
1488         for (i = 0; i < MAX_NUMNODES; i++) {
1489                 u64 self_latency = numa_latency[i][i];
1490
1491                 for (j = 0; j < MAX_NUMNODES; j++) {
1492                         numa_latency[i][j] =
1493                                 (numa_latency[i][j] * LOCAL_DISTANCE) /
1494                                 self_latency;
1495                 }
1496         }
1497
1498         add_node_ranges();
1499
1500         for (i = 0; i < num_node_masks; i++) {
1501                 allocate_node_data(i);
1502                 node_set_online(i);
1503         }
1504
1505         err = 0;
1506 out:
1507         mdesc_release(md);
1508         return err;
1509 }
1510
1511 static int __init numa_parse_jbus(void)
1512 {
1513         unsigned long cpu, index;
1514
1515         /* NUMA node id is encoded in bits 36 and higher, and there is
1516          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1517          */
1518         index = 0;
1519         for_each_present_cpu(cpu) {
1520                 numa_cpu_lookup_table[cpu] = index;
1521                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1522                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1523                 node_masks[index].match = cpu << 36UL;
1524
1525                 index++;
1526         }
1527         num_node_masks = index;
1528
1529         add_node_ranges();
1530
1531         for (index = 0; index < num_node_masks; index++) {
1532                 allocate_node_data(index);
1533                 node_set_online(index);
1534         }
1535
1536         return 0;
1537 }
1538
1539 static int __init numa_parse_sun4u(void)
1540 {
1541         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1542                 unsigned long ver;
1543
1544                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1545                 if ((ver >> 32UL) == __JALAPENO_ID ||
1546                     (ver >> 32UL) == __SERRANO_ID)
1547                         return numa_parse_jbus();
1548         }
1549         return -1;
1550 }
1551
1552 static int __init bootmem_init_numa(void)
1553 {
1554         int i, j;
1555         int err = -1;
1556
1557         numadbg("bootmem_init_numa()\n");
1558
1559         /* Some sane defaults for numa latency values */
1560         for (i = 0; i < MAX_NUMNODES; i++) {
1561                 for (j = 0; j < MAX_NUMNODES; j++)
1562                         numa_latency[i][j] = (i == j) ?
1563                                 LOCAL_DISTANCE : REMOTE_DISTANCE;
1564         }
1565
1566         if (numa_enabled) {
1567                 if (tlb_type == hypervisor)
1568                         err = numa_parse_mdesc();
1569                 else
1570                         err = numa_parse_sun4u();
1571         }
1572         return err;
1573 }
1574
1575 #else
1576
1577 static int bootmem_init_numa(void)
1578 {
1579         return -1;
1580 }
1581
1582 #endif
1583
1584 static void __init bootmem_init_nonnuma(void)
1585 {
1586         unsigned long top_of_ram = memblock_end_of_DRAM();
1587         unsigned long total_ram = memblock_phys_mem_size();
1588
1589         numadbg("bootmem_init_nonnuma()\n");
1590
1591         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1592                top_of_ram, total_ram);
1593         printk(KERN_INFO "Memory hole size: %ldMB\n",
1594                (top_of_ram - total_ram) >> 20);
1595
1596         init_node_masks_nonnuma();
1597         memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1598         allocate_node_data(0);
1599         node_set_online(0);
1600 }
1601
1602 static unsigned long __init bootmem_init(unsigned long phys_base)
1603 {
1604         unsigned long end_pfn;
1605
1606         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1607         max_pfn = max_low_pfn = end_pfn;
1608         min_low_pfn = (phys_base >> PAGE_SHIFT);
1609
1610         if (bootmem_init_numa() < 0)
1611                 bootmem_init_nonnuma();
1612
1613         /* Dump memblock with node info. */
1614         memblock_dump_all();
1615
1616         /* XXX cpu notifier XXX */
1617
1618         sparse_init();
1619
1620         return end_pfn;
1621 }
1622
1623 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1624 static int pall_ents __initdata;
1625
1626 static unsigned long max_phys_bits = 40;
1627
1628 bool kern_addr_valid(unsigned long addr)
1629 {
1630         pgd_t *pgd;
1631         p4d_t *p4d;
1632         pud_t *pud;
1633         pmd_t *pmd;
1634         pte_t *pte;
1635
1636         if ((long)addr < 0L) {
1637                 unsigned long pa = __pa(addr);
1638
1639                 if ((pa >> max_phys_bits) != 0UL)
1640                         return false;
1641
1642                 return pfn_valid(pa >> PAGE_SHIFT);
1643         }
1644
1645         if (addr >= (unsigned long) KERNBASE &&
1646             addr < (unsigned long)&_end)
1647                 return true;
1648
1649         pgd = pgd_offset_k(addr);
1650         if (pgd_none(*pgd))
1651                 return false;
1652
1653         p4d = p4d_offset(pgd, addr);
1654         if (p4d_none(*p4d))
1655                 return false;
1656
1657         pud = pud_offset(p4d, addr);
1658         if (pud_none(*pud))
1659                 return false;
1660
1661         if (pud_leaf(*pud))
1662                 return pfn_valid(pud_pfn(*pud));
1663
1664         pmd = pmd_offset(pud, addr);
1665         if (pmd_none(*pmd))
1666                 return false;
1667
1668         if (pmd_leaf(*pmd))
1669                 return pfn_valid(pmd_pfn(*pmd));
1670
1671         pte = pte_offset_kernel(pmd, addr);
1672         if (pte_none(*pte))
1673                 return false;
1674
1675         return pfn_valid(pte_pfn(*pte));
1676 }
1677
1678 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1679                                               unsigned long vend,
1680                                               pud_t *pud)
1681 {
1682         const unsigned long mask16gb = (1UL << 34) - 1UL;
1683         u64 pte_val = vstart;
1684
1685         /* Each PUD is 8GB */
1686         if ((vstart & mask16gb) ||
1687             (vend - vstart <= mask16gb)) {
1688                 pte_val ^= kern_linear_pte_xor[2];
1689                 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1690
1691                 return vstart + PUD_SIZE;
1692         }
1693
1694         pte_val ^= kern_linear_pte_xor[3];
1695         pte_val |= _PAGE_PUD_HUGE;
1696
1697         vend = vstart + mask16gb + 1UL;
1698         while (vstart < vend) {
1699                 pud_val(*pud) = pte_val;
1700
1701                 pte_val += PUD_SIZE;
1702                 vstart += PUD_SIZE;
1703                 pud++;
1704         }
1705         return vstart;
1706 }
1707
1708 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1709                                    bool guard)
1710 {
1711         if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1712                 return true;
1713
1714         return false;
1715 }
1716
1717 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1718                                               unsigned long vend,
1719                                               pmd_t *pmd)
1720 {
1721         const unsigned long mask256mb = (1UL << 28) - 1UL;
1722         const unsigned long mask2gb = (1UL << 31) - 1UL;
1723         u64 pte_val = vstart;
1724
1725         /* Each PMD is 8MB */
1726         if ((vstart & mask256mb) ||
1727             (vend - vstart <= mask256mb)) {
1728                 pte_val ^= kern_linear_pte_xor[0];
1729                 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1730
1731                 return vstart + PMD_SIZE;
1732         }
1733
1734         if ((vstart & mask2gb) ||
1735             (vend - vstart <= mask2gb)) {
1736                 pte_val ^= kern_linear_pte_xor[1];
1737                 pte_val |= _PAGE_PMD_HUGE;
1738                 vend = vstart + mask256mb + 1UL;
1739         } else {
1740                 pte_val ^= kern_linear_pte_xor[2];
1741                 pte_val |= _PAGE_PMD_HUGE;
1742                 vend = vstart + mask2gb + 1UL;
1743         }
1744
1745         while (vstart < vend) {
1746                 pmd_val(*pmd) = pte_val;
1747
1748                 pte_val += PMD_SIZE;
1749                 vstart += PMD_SIZE;
1750                 pmd++;
1751         }
1752
1753         return vstart;
1754 }
1755
1756 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1757                                    bool guard)
1758 {
1759         if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1760                 return true;
1761
1762         return false;
1763 }
1764
1765 static unsigned long __ref kernel_map_range(unsigned long pstart,
1766                                             unsigned long pend, pgprot_t prot,
1767                                             bool use_huge)
1768 {
1769         unsigned long vstart = PAGE_OFFSET + pstart;
1770         unsigned long vend = PAGE_OFFSET + pend;
1771         unsigned long alloc_bytes = 0UL;
1772
1773         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1774                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1775                             vstart, vend);
1776                 prom_halt();
1777         }
1778
1779         while (vstart < vend) {
1780                 unsigned long this_end, paddr = __pa(vstart);
1781                 pgd_t *pgd = pgd_offset_k(vstart);
1782                 p4d_t *p4d;
1783                 pud_t *pud;
1784                 pmd_t *pmd;
1785                 pte_t *pte;
1786
1787                 if (pgd_none(*pgd)) {
1788                         pud_t *new;
1789
1790                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1791                                                   PAGE_SIZE);
1792                         if (!new)
1793                                 goto err_alloc;
1794                         alloc_bytes += PAGE_SIZE;
1795                         pgd_populate(&init_mm, pgd, new);
1796                 }
1797
1798                 p4d = p4d_offset(pgd, vstart);
1799                 if (p4d_none(*p4d)) {
1800                         pud_t *new;
1801
1802                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1803                                                   PAGE_SIZE);
1804                         if (!new)
1805                                 goto err_alloc;
1806                         alloc_bytes += PAGE_SIZE;
1807                         p4d_populate(&init_mm, p4d, new);
1808                 }
1809
1810                 pud = pud_offset(p4d, vstart);
1811                 if (pud_none(*pud)) {
1812                         pmd_t *new;
1813
1814                         if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1815                                 vstart = kernel_map_hugepud(vstart, vend, pud);
1816                                 continue;
1817                         }
1818                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1819                                                   PAGE_SIZE);
1820                         if (!new)
1821                                 goto err_alloc;
1822                         alloc_bytes += PAGE_SIZE;
1823                         pud_populate(&init_mm, pud, new);
1824                 }
1825
1826                 pmd = pmd_offset(pud, vstart);
1827                 if (pmd_none(*pmd)) {
1828                         pte_t *new;
1829
1830                         if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1831                                 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1832                                 continue;
1833                         }
1834                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1835                                                   PAGE_SIZE);
1836                         if (!new)
1837                                 goto err_alloc;
1838                         alloc_bytes += PAGE_SIZE;
1839                         pmd_populate_kernel(&init_mm, pmd, new);
1840                 }
1841
1842                 pte = pte_offset_kernel(pmd, vstart);
1843                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1844                 if (this_end > vend)
1845                         this_end = vend;
1846
1847                 while (vstart < this_end) {
1848                         pte_val(*pte) = (paddr | pgprot_val(prot));
1849
1850                         vstart += PAGE_SIZE;
1851                         paddr += PAGE_SIZE;
1852                         pte++;
1853                 }
1854         }
1855
1856         return alloc_bytes;
1857
1858 err_alloc:
1859         panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1860               __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1861         return -ENOMEM;
1862 }
1863
1864 static void __init flush_all_kernel_tsbs(void)
1865 {
1866         int i;
1867
1868         for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1869                 struct tsb *ent = &swapper_tsb[i];
1870
1871                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1872         }
1873 #ifndef CONFIG_DEBUG_PAGEALLOC
1874         for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1875                 struct tsb *ent = &swapper_4m_tsb[i];
1876
1877                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1878         }
1879 #endif
1880 }
1881
1882 extern unsigned int kvmap_linear_patch[1];
1883
1884 static void __init kernel_physical_mapping_init(void)
1885 {
1886         unsigned long i, mem_alloced = 0UL;
1887         bool use_huge = true;
1888
1889 #ifdef CONFIG_DEBUG_PAGEALLOC
1890         use_huge = false;
1891 #endif
1892         for (i = 0; i < pall_ents; i++) {
1893                 unsigned long phys_start, phys_end;
1894
1895                 phys_start = pall[i].phys_addr;
1896                 phys_end = phys_start + pall[i].reg_size;
1897
1898                 mem_alloced += kernel_map_range(phys_start, phys_end,
1899                                                 PAGE_KERNEL, use_huge);
1900         }
1901
1902         printk("Allocated %ld bytes for kernel page tables.\n",
1903                mem_alloced);
1904
1905         kvmap_linear_patch[0] = 0x01000000; /* nop */
1906         flushi(&kvmap_linear_patch[0]);
1907
1908         flush_all_kernel_tsbs();
1909
1910         __flush_tlb_all();
1911 }
1912
1913 #ifdef CONFIG_DEBUG_PAGEALLOC
1914 void __kernel_map_pages(struct page *page, int numpages, int enable)
1915 {
1916         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1917         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1918
1919         kernel_map_range(phys_start, phys_end,
1920                          (enable ? PAGE_KERNEL : __pgprot(0)), false);
1921
1922         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1923                                PAGE_OFFSET + phys_end);
1924
1925         /* we should perform an IPI and flush all tlbs,
1926          * but that can deadlock->flush only current cpu.
1927          */
1928         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1929                                  PAGE_OFFSET + phys_end);
1930 }
1931 #endif
1932
1933 unsigned long __init find_ecache_flush_span(unsigned long size)
1934 {
1935         int i;
1936
1937         for (i = 0; i < pavail_ents; i++) {
1938                 if (pavail[i].reg_size >= size)
1939                         return pavail[i].phys_addr;
1940         }
1941
1942         return ~0UL;
1943 }
1944
1945 unsigned long PAGE_OFFSET;
1946 EXPORT_SYMBOL(PAGE_OFFSET);
1947
1948 unsigned long VMALLOC_END   = 0x0000010000000000UL;
1949 EXPORT_SYMBOL(VMALLOC_END);
1950
1951 unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
1952 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1953
1954 static void __init setup_page_offset(void)
1955 {
1956         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1957                 /* Cheetah/Panther support a full 64-bit virtual
1958                  * address, so we can use all that our page tables
1959                  * support.
1960                  */
1961                 sparc64_va_hole_top =    0xfff0000000000000UL;
1962                 sparc64_va_hole_bottom = 0x0010000000000000UL;
1963
1964                 max_phys_bits = 42;
1965         } else if (tlb_type == hypervisor) {
1966                 switch (sun4v_chip_type) {
1967                 case SUN4V_CHIP_NIAGARA1:
1968                 case SUN4V_CHIP_NIAGARA2:
1969                         /* T1 and T2 support 48-bit virtual addresses.  */
1970                         sparc64_va_hole_top =    0xffff800000000000UL;
1971                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1972
1973                         max_phys_bits = 39;
1974                         break;
1975                 case SUN4V_CHIP_NIAGARA3:
1976                         /* T3 supports 48-bit virtual addresses.  */
1977                         sparc64_va_hole_top =    0xffff800000000000UL;
1978                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1979
1980                         max_phys_bits = 43;
1981                         break;
1982                 case SUN4V_CHIP_NIAGARA4:
1983                 case SUN4V_CHIP_NIAGARA5:
1984                 case SUN4V_CHIP_SPARC64X:
1985                 case SUN4V_CHIP_SPARC_M6:
1986                         /* T4 and later support 52-bit virtual addresses.  */
1987                         sparc64_va_hole_top =    0xfff8000000000000UL;
1988                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1989                         max_phys_bits = 47;
1990                         break;
1991                 case SUN4V_CHIP_SPARC_M7:
1992                 case SUN4V_CHIP_SPARC_SN:
1993                         /* M7 and later support 52-bit virtual addresses.  */
1994                         sparc64_va_hole_top =    0xfff8000000000000UL;
1995                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1996                         max_phys_bits = 49;
1997                         break;
1998                 case SUN4V_CHIP_SPARC_M8:
1999                 default:
2000                         /* M8 and later support 54-bit virtual addresses.
2001                          * However, restricting M8 and above VA bits to 53
2002                          * as 4-level page table cannot support more than
2003                          * 53 VA bits.
2004                          */
2005                         sparc64_va_hole_top =    0xfff0000000000000UL;
2006                         sparc64_va_hole_bottom = 0x0010000000000000UL;
2007                         max_phys_bits = 51;
2008                         break;
2009                 }
2010         }
2011
2012         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2013                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2014                             max_phys_bits);
2015                 prom_halt();
2016         }
2017
2018         PAGE_OFFSET = sparc64_va_hole_top;
2019         VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2020                        (sparc64_va_hole_bottom >> 2));
2021
2022         pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2023                 PAGE_OFFSET, max_phys_bits);
2024         pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2025                 VMALLOC_START, VMALLOC_END);
2026         pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2027                 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2028 }
2029
2030 static void __init tsb_phys_patch(void)
2031 {
2032         struct tsb_ldquad_phys_patch_entry *pquad;
2033         struct tsb_phys_patch_entry *p;
2034
2035         pquad = &__tsb_ldquad_phys_patch;
2036         while (pquad < &__tsb_ldquad_phys_patch_end) {
2037                 unsigned long addr = pquad->addr;
2038
2039                 if (tlb_type == hypervisor)
2040                         *(unsigned int *) addr = pquad->sun4v_insn;
2041                 else
2042                         *(unsigned int *) addr = pquad->sun4u_insn;
2043                 wmb();
2044                 __asm__ __volatile__("flush     %0"
2045                                      : /* no outputs */
2046                                      : "r" (addr));
2047
2048                 pquad++;
2049         }
2050
2051         p = &__tsb_phys_patch;
2052         while (p < &__tsb_phys_patch_end) {
2053                 unsigned long addr = p->addr;
2054
2055                 *(unsigned int *) addr = p->insn;
2056                 wmb();
2057                 __asm__ __volatile__("flush     %0"
2058                                      : /* no outputs */
2059                                      : "r" (addr));
2060
2061                 p++;
2062         }
2063 }
2064
2065 /* Don't mark as init, we give this to the Hypervisor.  */
2066 #ifndef CONFIG_DEBUG_PAGEALLOC
2067 #define NUM_KTSB_DESCR  2
2068 #else
2069 #define NUM_KTSB_DESCR  1
2070 #endif
2071 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2072
2073 /* The swapper TSBs are loaded with a base sequence of:
2074  *
2075  *      sethi   %uhi(SYMBOL), REG1
2076  *      sethi   %hi(SYMBOL), REG2
2077  *      or      REG1, %ulo(SYMBOL), REG1
2078  *      or      REG2, %lo(SYMBOL), REG2
2079  *      sllx    REG1, 32, REG1
2080  *      or      REG1, REG2, REG1
2081  *
2082  * When we use physical addressing for the TSB accesses, we patch the
2083  * first four instructions in the above sequence.
2084  */
2085
2086 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2087 {
2088         unsigned long high_bits, low_bits;
2089
2090         high_bits = (pa >> 32) & 0xffffffff;
2091         low_bits = (pa >> 0) & 0xffffffff;
2092
2093         while (start < end) {
2094                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2095
2096                 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2097                 __asm__ __volatile__("flush     %0" : : "r" (ia));
2098
2099                 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2100                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
2101
2102                 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2103                 __asm__ __volatile__("flush     %0" : : "r" (ia + 2));
2104
2105                 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2106                 __asm__ __volatile__("flush     %0" : : "r" (ia + 3));
2107
2108                 start++;
2109         }
2110 }
2111
2112 static void ktsb_phys_patch(void)
2113 {
2114         extern unsigned int __swapper_tsb_phys_patch;
2115         extern unsigned int __swapper_tsb_phys_patch_end;
2116         unsigned long ktsb_pa;
2117
2118         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2119         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2120                             &__swapper_tsb_phys_patch_end, ktsb_pa);
2121 #ifndef CONFIG_DEBUG_PAGEALLOC
2122         {
2123         extern unsigned int __swapper_4m_tsb_phys_patch;
2124         extern unsigned int __swapper_4m_tsb_phys_patch_end;
2125         ktsb_pa = (kern_base +
2126                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2127         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2128                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2129         }
2130 #endif
2131 }
2132
2133 static void __init sun4v_ktsb_init(void)
2134 {
2135         unsigned long ktsb_pa;
2136
2137         /* First KTSB for PAGE_SIZE mappings.  */
2138         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2139
2140         switch (PAGE_SIZE) {
2141         case 8 * 1024:
2142         default:
2143                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2144                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2145                 break;
2146
2147         case 64 * 1024:
2148                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2149                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2150                 break;
2151
2152         case 512 * 1024:
2153                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2154                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2155                 break;
2156
2157         case 4 * 1024 * 1024:
2158                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2159                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2160                 break;
2161         }
2162
2163         ktsb_descr[0].assoc = 1;
2164         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2165         ktsb_descr[0].ctx_idx = 0;
2166         ktsb_descr[0].tsb_base = ktsb_pa;
2167         ktsb_descr[0].resv = 0;
2168
2169 #ifndef CONFIG_DEBUG_PAGEALLOC
2170         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
2171         ktsb_pa = (kern_base +
2172                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2173
2174         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2175         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2176                                     HV_PGSZ_MASK_256MB |
2177                                     HV_PGSZ_MASK_2GB |
2178                                     HV_PGSZ_MASK_16GB) &
2179                                    cpu_pgsz_mask);
2180         ktsb_descr[1].assoc = 1;
2181         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2182         ktsb_descr[1].ctx_idx = 0;
2183         ktsb_descr[1].tsb_base = ktsb_pa;
2184         ktsb_descr[1].resv = 0;
2185 #endif
2186 }
2187
2188 void sun4v_ktsb_register(void)
2189 {
2190         unsigned long pa, ret;
2191
2192         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2193
2194         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2195         if (ret != 0) {
2196                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2197                             "errors with %lx\n", pa, ret);
2198                 prom_halt();
2199         }
2200 }
2201
2202 static void __init sun4u_linear_pte_xor_finalize(void)
2203 {
2204 #ifndef CONFIG_DEBUG_PAGEALLOC
2205         /* This is where we would add Panther support for
2206          * 32MB and 256MB pages.
2207          */
2208 #endif
2209 }
2210
2211 static void __init sun4v_linear_pte_xor_finalize(void)
2212 {
2213         unsigned long pagecv_flag;
2214
2215         /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2216          * enables MCD error. Do not set bit 9 on M7 processor.
2217          */
2218         switch (sun4v_chip_type) {
2219         case SUN4V_CHIP_SPARC_M7:
2220         case SUN4V_CHIP_SPARC_M8:
2221         case SUN4V_CHIP_SPARC_SN:
2222                 pagecv_flag = 0x00;
2223                 break;
2224         default:
2225                 pagecv_flag = _PAGE_CV_4V;
2226                 break;
2227         }
2228 #ifndef CONFIG_DEBUG_PAGEALLOC
2229         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2230                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2231                         PAGE_OFFSET;
2232                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2233                                            _PAGE_P_4V | _PAGE_W_4V);
2234         } else {
2235                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2236         }
2237
2238         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2239                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2240                         PAGE_OFFSET;
2241                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2242                                            _PAGE_P_4V | _PAGE_W_4V);
2243         } else {
2244                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2245         }
2246
2247         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2248                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2249                         PAGE_OFFSET;
2250                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2251                                            _PAGE_P_4V | _PAGE_W_4V);
2252         } else {
2253                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2254         }
2255 #endif
2256 }
2257
2258 /* paging_init() sets up the page tables */
2259
2260 static unsigned long last_valid_pfn;
2261
2262 static void sun4u_pgprot_init(void);
2263 static void sun4v_pgprot_init(void);
2264
2265 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2266 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2267 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2268 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2269 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2270 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2271
2272 /* We need to exclude reserved regions. This exclusion will include
2273  * vmlinux and initrd. To be more precise the initrd size could be used to
2274  * compute a new lower limit because it is freed later during initialization.
2275  */
2276 static void __init reduce_memory(phys_addr_t limit_ram)
2277 {
2278         limit_ram += memblock_reserved_size();
2279         memblock_enforce_memory_limit(limit_ram);
2280 }
2281
2282 void __init paging_init(void)
2283 {
2284         unsigned long end_pfn, shift, phys_base;
2285         unsigned long real_end, i;
2286
2287         setup_page_offset();
2288
2289         /* These build time checkes make sure that the dcache_dirty_cpu()
2290          * folio->flags usage will work.
2291          *
2292          * When a page gets marked as dcache-dirty, we store the
2293          * cpu number starting at bit 32 in the folio->flags.  Also,
2294          * functions like clear_dcache_dirty_cpu use the cpu mask
2295          * in 13-bit signed-immediate instruction fields.
2296          */
2297
2298         /*
2299          * Page flags must not reach into upper 32 bits that are used
2300          * for the cpu number
2301          */
2302         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2303
2304         /*
2305          * The bit fields placed in the high range must not reach below
2306          * the 32 bit boundary. Otherwise we cannot place the cpu field
2307          * at the 32 bit boundary.
2308          */
2309         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2310                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2311
2312         BUILD_BUG_ON(NR_CPUS > 4096);
2313
2314         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2315         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2316
2317         /* Invalidate both kernel TSBs.  */
2318         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2319 #ifndef CONFIG_DEBUG_PAGEALLOC
2320         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2321 #endif
2322
2323         /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2324          * bit on M7 processor. This is a conflicting usage of the same
2325          * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2326          * Detection error on all pages and this will lead to problems
2327          * later. Kernel does not run with MCD enabled and hence rest
2328          * of the required steps to fully configure memory corruption
2329          * detection are not taken. We need to ensure TTE.mcde is not
2330          * set on M7 processor. Compute the value of cacheability
2331          * flag for use later taking this into consideration.
2332          */
2333         switch (sun4v_chip_type) {
2334         case SUN4V_CHIP_SPARC_M7:
2335         case SUN4V_CHIP_SPARC_M8:
2336         case SUN4V_CHIP_SPARC_SN:
2337                 page_cache4v_flag = _PAGE_CP_4V;
2338                 break;
2339         default:
2340                 page_cache4v_flag = _PAGE_CACHE_4V;
2341                 break;
2342         }
2343
2344         if (tlb_type == hypervisor)
2345                 sun4v_pgprot_init();
2346         else
2347                 sun4u_pgprot_init();
2348
2349         if (tlb_type == cheetah_plus ||
2350             tlb_type == hypervisor) {
2351                 tsb_phys_patch();
2352                 ktsb_phys_patch();
2353         }
2354
2355         if (tlb_type == hypervisor)
2356                 sun4v_patch_tlb_handlers();
2357
2358         /* Find available physical memory...
2359          *
2360          * Read it twice in order to work around a bug in openfirmware.
2361          * The call to grab this table itself can cause openfirmware to
2362          * allocate memory, which in turn can take away some space from
2363          * the list of available memory.  Reading it twice makes sure
2364          * we really do get the final value.
2365          */
2366         read_obp_translations();
2367         read_obp_memory("reg", &pall[0], &pall_ents);
2368         read_obp_memory("available", &pavail[0], &pavail_ents);
2369         read_obp_memory("available", &pavail[0], &pavail_ents);
2370
2371         phys_base = 0xffffffffffffffffUL;
2372         for (i = 0; i < pavail_ents; i++) {
2373                 phys_base = min(phys_base, pavail[i].phys_addr);
2374                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2375         }
2376
2377         memblock_reserve(kern_base, kern_size);
2378
2379         find_ramdisk(phys_base);
2380
2381         if (cmdline_memory_size)
2382                 reduce_memory(cmdline_memory_size);
2383
2384         memblock_allow_resize();
2385         memblock_dump_all();
2386
2387         set_bit(0, mmu_context_bmap);
2388
2389         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2390
2391         real_end = (unsigned long)_end;
2392         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2393         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2394                num_kernel_image_mappings);
2395
2396         /* Set kernel pgd to upper alias so physical page computations
2397          * work.
2398          */
2399         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2400
2401         memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2402
2403         inherit_prom_mappings();
2404
2405         /* Ok, we can use our TLB miss and window trap handlers safely.  */
2406         setup_tba();
2407
2408         __flush_tlb_all();
2409
2410         prom_build_devicetree();
2411         of_populate_present_mask();
2412 #ifndef CONFIG_SMP
2413         of_fill_in_cpu_data();
2414 #endif
2415
2416         if (tlb_type == hypervisor) {
2417                 sun4v_mdesc_init();
2418                 mdesc_populate_present_mask(cpu_all_mask);
2419 #ifndef CONFIG_SMP
2420                 mdesc_fill_in_cpu_data(cpu_all_mask);
2421 #endif
2422                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2423
2424                 sun4v_linear_pte_xor_finalize();
2425
2426                 sun4v_ktsb_init();
2427                 sun4v_ktsb_register();
2428         } else {
2429                 unsigned long impl, ver;
2430
2431                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2432                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2433
2434                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2435                 impl = ((ver >> 32) & 0xffff);
2436                 if (impl == PANTHER_IMPL)
2437                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2438                                           HV_PGSZ_MASK_256MB);
2439
2440                 sun4u_linear_pte_xor_finalize();
2441         }
2442
2443         /* Flush the TLBs and the 4M TSB so that the updated linear
2444          * pte XOR settings are realized for all mappings.
2445          */
2446         __flush_tlb_all();
2447 #ifndef CONFIG_DEBUG_PAGEALLOC
2448         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2449 #endif
2450         __flush_tlb_all();
2451
2452         /* Setup bootmem... */
2453         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2454
2455         kernel_physical_mapping_init();
2456
2457         {
2458                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2459
2460                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2461
2462                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2463
2464                 free_area_init(max_zone_pfns);
2465         }
2466
2467         printk("Booting Linux...\n");
2468 }
2469
2470 int page_in_phys_avail(unsigned long paddr)
2471 {
2472         int i;
2473
2474         paddr &= PAGE_MASK;
2475
2476         for (i = 0; i < pavail_ents; i++) {
2477                 unsigned long start, end;
2478
2479                 start = pavail[i].phys_addr;
2480                 end = start + pavail[i].reg_size;
2481
2482                 if (paddr >= start && paddr < end)
2483                         return 1;
2484         }
2485         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2486                 return 1;
2487 #ifdef CONFIG_BLK_DEV_INITRD
2488         if (paddr >= __pa(initrd_start) &&
2489             paddr < __pa(PAGE_ALIGN(initrd_end)))
2490                 return 1;
2491 #endif
2492
2493         return 0;
2494 }
2495
2496 static void __init register_page_bootmem_info(void)
2497 {
2498 #ifdef CONFIG_NUMA
2499         int i;
2500
2501         for_each_online_node(i)
2502                 if (NODE_DATA(i)->node_spanned_pages)
2503                         register_page_bootmem_info_node(NODE_DATA(i));
2504 #endif
2505 }
2506 void __init mem_init(void)
2507 {
2508         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2509
2510         memblock_free_all();
2511
2512         /*
2513          * Must be done after boot memory is put on freelist, because here we
2514          * might set fields in deferred struct pages that have not yet been
2515          * initialized, and memblock_free_all() initializes all the reserved
2516          * deferred pages for us.
2517          */
2518         register_page_bootmem_info();
2519
2520         /*
2521          * Set up the zero page, mark it reserved, so that page count
2522          * is not manipulated when freeing the page from user ptes.
2523          */
2524         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2525         if (mem_map_zero == NULL) {
2526                 prom_printf("paging_init: Cannot alloc zero page.\n");
2527                 prom_halt();
2528         }
2529         mark_page_reserved(mem_map_zero);
2530
2531
2532         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2533                 cheetah_ecache_flush_init();
2534 }
2535
2536 void free_initmem(void)
2537 {
2538         unsigned long addr, initend;
2539         int do_free = 1;
2540
2541         /* If the physical memory maps were trimmed by kernel command
2542          * line options, don't even try freeing this initmem stuff up.
2543          * The kernel image could have been in the trimmed out region
2544          * and if so the freeing below will free invalid page structs.
2545          */
2546         if (cmdline_memory_size)
2547                 do_free = 0;
2548
2549         /*
2550          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2551          */
2552         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2553         initend = (unsigned long)(__init_end) & PAGE_MASK;
2554         for (; addr < initend; addr += PAGE_SIZE) {
2555                 unsigned long page;
2556
2557                 page = (addr +
2558                         ((unsigned long) __va(kern_base)) -
2559                         ((unsigned long) KERNBASE));
2560                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2561
2562                 if (do_free)
2563                         free_reserved_page(virt_to_page(page));
2564         }
2565 }
2566
2567 pgprot_t PAGE_KERNEL __read_mostly;
2568 EXPORT_SYMBOL(PAGE_KERNEL);
2569
2570 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2571 pgprot_t PAGE_COPY __read_mostly;
2572
2573 pgprot_t PAGE_SHARED __read_mostly;
2574 EXPORT_SYMBOL(PAGE_SHARED);
2575
2576 unsigned long pg_iobits __read_mostly;
2577
2578 unsigned long _PAGE_IE __read_mostly;
2579 EXPORT_SYMBOL(_PAGE_IE);
2580
2581 unsigned long _PAGE_E __read_mostly;
2582 EXPORT_SYMBOL(_PAGE_E);
2583
2584 unsigned long _PAGE_CACHE __read_mostly;
2585 EXPORT_SYMBOL(_PAGE_CACHE);
2586
2587 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2588 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2589                                int node, struct vmem_altmap *altmap)
2590 {
2591         unsigned long pte_base;
2592
2593         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2594                     _PAGE_CP_4U | _PAGE_CV_4U |
2595                     _PAGE_P_4U | _PAGE_W_4U);
2596         if (tlb_type == hypervisor)
2597                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2598                             page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2599
2600         pte_base |= _PAGE_PMD_HUGE;
2601
2602         vstart = vstart & PMD_MASK;
2603         vend = ALIGN(vend, PMD_SIZE);
2604         for (; vstart < vend; vstart += PMD_SIZE) {
2605                 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2606                 unsigned long pte;
2607                 p4d_t *p4d;
2608                 pud_t *pud;
2609                 pmd_t *pmd;
2610
2611                 if (!pgd)
2612                         return -ENOMEM;
2613
2614                 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2615                 if (!p4d)
2616                         return -ENOMEM;
2617
2618                 pud = vmemmap_pud_populate(p4d, vstart, node);
2619                 if (!pud)
2620                         return -ENOMEM;
2621
2622                 pmd = pmd_offset(pud, vstart);
2623                 pte = pmd_val(*pmd);
2624                 if (!(pte & _PAGE_VALID)) {
2625                         void *block = vmemmap_alloc_block(PMD_SIZE, node);
2626
2627                         if (!block)
2628                                 return -ENOMEM;
2629
2630                         pmd_val(*pmd) = pte_base | __pa(block);
2631                 }
2632         }
2633
2634         return 0;
2635 }
2636 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2637
2638 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
2639 static pgprot_t protection_map[16] __ro_after_init;
2640
2641 static void prot_init_common(unsigned long page_none,
2642                              unsigned long page_shared,
2643                              unsigned long page_copy,
2644                              unsigned long page_readonly,
2645                              unsigned long page_exec_bit)
2646 {
2647         PAGE_COPY = __pgprot(page_copy);
2648         PAGE_SHARED = __pgprot(page_shared);
2649
2650         protection_map[0x0] = __pgprot(page_none);
2651         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2652         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2653         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2654         protection_map[0x4] = __pgprot(page_readonly);
2655         protection_map[0x5] = __pgprot(page_readonly);
2656         protection_map[0x6] = __pgprot(page_copy);
2657         protection_map[0x7] = __pgprot(page_copy);
2658         protection_map[0x8] = __pgprot(page_none);
2659         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2660         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2661         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2662         protection_map[0xc] = __pgprot(page_readonly);
2663         protection_map[0xd] = __pgprot(page_readonly);
2664         protection_map[0xe] = __pgprot(page_shared);
2665         protection_map[0xf] = __pgprot(page_shared);
2666 }
2667
2668 static void __init sun4u_pgprot_init(void)
2669 {
2670         unsigned long page_none, page_shared, page_copy, page_readonly;
2671         unsigned long page_exec_bit;
2672         int i;
2673
2674         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2675                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2676                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2677                                 _PAGE_EXEC_4U);
2678         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2679                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2680                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2681                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2682
2683         _PAGE_IE = _PAGE_IE_4U;
2684         _PAGE_E = _PAGE_E_4U;
2685         _PAGE_CACHE = _PAGE_CACHE_4U;
2686
2687         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2688                      __ACCESS_BITS_4U | _PAGE_E_4U);
2689
2690 #ifdef CONFIG_DEBUG_PAGEALLOC
2691         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2692 #else
2693         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2694                 PAGE_OFFSET;
2695 #endif
2696         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2697                                    _PAGE_P_4U | _PAGE_W_4U);
2698
2699         for (i = 1; i < 4; i++)
2700                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2701
2702         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2703                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2704                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2705
2706
2707         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2708         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2709                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2710         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2711                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2712         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2713                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2714
2715         page_exec_bit = _PAGE_EXEC_4U;
2716
2717         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2718                          page_exec_bit);
2719 }
2720
2721 static void __init sun4v_pgprot_init(void)
2722 {
2723         unsigned long page_none, page_shared, page_copy, page_readonly;
2724         unsigned long page_exec_bit;
2725         int i;
2726
2727         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2728                                 page_cache4v_flag | _PAGE_P_4V |
2729                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2730                                 _PAGE_EXEC_4V);
2731         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2732
2733         _PAGE_IE = _PAGE_IE_4V;
2734         _PAGE_E = _PAGE_E_4V;
2735         _PAGE_CACHE = page_cache4v_flag;
2736
2737 #ifdef CONFIG_DEBUG_PAGEALLOC
2738         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2739 #else
2740         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2741                 PAGE_OFFSET;
2742 #endif
2743         kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2744                                    _PAGE_W_4V);
2745
2746         for (i = 1; i < 4; i++)
2747                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2748
2749         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2750                      __ACCESS_BITS_4V | _PAGE_E_4V);
2751
2752         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2753                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2754                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2755                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2756
2757         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2758         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2759                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2760         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2761                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2762         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2763                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2764
2765         page_exec_bit = _PAGE_EXEC_4V;
2766
2767         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2768                          page_exec_bit);
2769 }
2770
2771 unsigned long pte_sz_bits(unsigned long sz)
2772 {
2773         if (tlb_type == hypervisor) {
2774                 switch (sz) {
2775                 case 8 * 1024:
2776                 default:
2777                         return _PAGE_SZ8K_4V;
2778                 case 64 * 1024:
2779                         return _PAGE_SZ64K_4V;
2780                 case 512 * 1024:
2781                         return _PAGE_SZ512K_4V;
2782                 case 4 * 1024 * 1024:
2783                         return _PAGE_SZ4MB_4V;
2784                 }
2785         } else {
2786                 switch (sz) {
2787                 case 8 * 1024:
2788                 default:
2789                         return _PAGE_SZ8K_4U;
2790                 case 64 * 1024:
2791                         return _PAGE_SZ64K_4U;
2792                 case 512 * 1024:
2793                         return _PAGE_SZ512K_4U;
2794                 case 4 * 1024 * 1024:
2795                         return _PAGE_SZ4MB_4U;
2796                 }
2797         }
2798 }
2799
2800 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2801 {
2802         pte_t pte;
2803
2804         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2805         pte_val(pte) |= (((unsigned long)space) << 32);
2806         pte_val(pte) |= pte_sz_bits(page_size);
2807
2808         return pte;
2809 }
2810
2811 static unsigned long kern_large_tte(unsigned long paddr)
2812 {
2813         unsigned long val;
2814
2815         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2816                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2817                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2818         if (tlb_type == hypervisor)
2819                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2820                        page_cache4v_flag | _PAGE_P_4V |
2821                        _PAGE_EXEC_4V | _PAGE_W_4V);
2822
2823         return val | paddr;
2824 }
2825
2826 /* If not locked, zap it. */
2827 void __flush_tlb_all(void)
2828 {
2829         unsigned long pstate;
2830         int i;
2831
2832         __asm__ __volatile__("flushw\n\t"
2833                              "rdpr      %%pstate, %0\n\t"
2834                              "wrpr      %0, %1, %%pstate"
2835                              : "=r" (pstate)
2836                              : "i" (PSTATE_IE));
2837         if (tlb_type == hypervisor) {
2838                 sun4v_mmu_demap_all();
2839         } else if (tlb_type == spitfire) {
2840                 for (i = 0; i < 64; i++) {
2841                         /* Spitfire Errata #32 workaround */
2842                         /* NOTE: Always runs on spitfire, so no
2843                          *       cheetah+ page size encodings.
2844                          */
2845                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2846                                              "flush     %%g6"
2847                                              : /* No outputs */
2848                                              : "r" (0),
2849                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2850
2851                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2852                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2853                                                      "membar #Sync"
2854                                                      : /* no outputs */
2855                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2856                                 spitfire_put_dtlb_data(i, 0x0UL);
2857                         }
2858
2859                         /* Spitfire Errata #32 workaround */
2860                         /* NOTE: Always runs on spitfire, so no
2861                          *       cheetah+ page size encodings.
2862                          */
2863                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2864                                              "flush     %%g6"
2865                                              : /* No outputs */
2866                                              : "r" (0),
2867                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2868
2869                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2870                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2871                                                      "membar #Sync"
2872                                                      : /* no outputs */
2873                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2874                                 spitfire_put_itlb_data(i, 0x0UL);
2875                         }
2876                 }
2877         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2878                 cheetah_flush_dtlb_all();
2879                 cheetah_flush_itlb_all();
2880         }
2881         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2882                              : : "r" (pstate));
2883 }
2884
2885 pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2886 {
2887         struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2888         pte_t *pte = NULL;
2889
2890         if (page)
2891                 pte = (pte_t *) page_address(page);
2892
2893         return pte;
2894 }
2895
2896 pgtable_t pte_alloc_one(struct mm_struct *mm)
2897 {
2898         struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL | __GFP_ZERO, 0);
2899
2900         if (!ptdesc)
2901                 return NULL;
2902         if (!pagetable_pte_ctor(ptdesc)) {
2903                 pagetable_free(ptdesc);
2904                 return NULL;
2905         }
2906         return ptdesc_address(ptdesc);
2907 }
2908
2909 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2910 {
2911         free_page((unsigned long)pte);
2912 }
2913
2914 static void __pte_free(pgtable_t pte)
2915 {
2916         struct ptdesc *ptdesc = virt_to_ptdesc(pte);
2917
2918         pagetable_pte_dtor(ptdesc);
2919         pagetable_free(ptdesc);
2920 }
2921
2922 void pte_free(struct mm_struct *mm, pgtable_t pte)
2923 {
2924         __pte_free(pte);
2925 }
2926
2927 void pgtable_free(void *table, bool is_page)
2928 {
2929         if (is_page)
2930                 __pte_free(table);
2931         else
2932                 kmem_cache_free(pgtable_cache, table);
2933 }
2934
2935 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2936 static void pte_free_now(struct rcu_head *head)
2937 {
2938         struct page *page;
2939
2940         page = container_of(head, struct page, rcu_head);
2941         __pte_free((pgtable_t)page_address(page));
2942 }
2943
2944 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable)
2945 {
2946         struct page *page;
2947
2948         page = virt_to_page(pgtable);
2949         call_rcu(&page->rcu_head, pte_free_now);
2950 }
2951
2952 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2953                           pmd_t *pmd)
2954 {
2955         unsigned long pte, flags;
2956         struct mm_struct *mm;
2957         pmd_t entry = *pmd;
2958
2959         if (!pmd_leaf(entry) || !pmd_young(entry))
2960                 return;
2961
2962         pte = pmd_val(entry);
2963
2964         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2965         if (!(pte & _PAGE_VALID))
2966                 return;
2967
2968         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2969         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2970
2971         mm = vma->vm_mm;
2972
2973         spin_lock_irqsave(&mm->context.lock, flags);
2974
2975         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2976                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2977                                         addr, pte);
2978
2979         spin_unlock_irqrestore(&mm->context.lock, flags);
2980 }
2981 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2982
2983 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2984 static void context_reload(void *__data)
2985 {
2986         struct mm_struct *mm = __data;
2987
2988         if (mm == current->mm)
2989                 load_secondary_context(mm);
2990 }
2991
2992 void hugetlb_setup(struct pt_regs *regs)
2993 {
2994         struct mm_struct *mm = current->mm;
2995         struct tsb_config *tp;
2996
2997         if (faulthandler_disabled() || !mm) {
2998                 const struct exception_table_entry *entry;
2999
3000                 entry = search_exception_tables(regs->tpc);
3001                 if (entry) {
3002                         regs->tpc = entry->fixup;
3003                         regs->tnpc = regs->tpc + 4;
3004                         return;
3005                 }
3006                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3007                 die_if_kernel("HugeTSB in atomic", regs);
3008         }
3009
3010         tp = &mm->context.tsb_block[MM_TSB_HUGE];
3011         if (likely(tp->tsb == NULL))
3012                 tsb_grow(mm, MM_TSB_HUGE, 0);
3013
3014         tsb_context_switch(mm);
3015         smp_tsb_sync(mm);
3016
3017         /* On UltraSPARC-III+ and later, configure the second half of
3018          * the Data-TLB for huge pages.
3019          */
3020         if (tlb_type == cheetah_plus) {
3021                 bool need_context_reload = false;
3022                 unsigned long ctx;
3023
3024                 spin_lock_irq(&ctx_alloc_lock);
3025                 ctx = mm->context.sparc64_ctx_val;
3026                 ctx &= ~CTX_PGSZ_MASK;
3027                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3028                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3029
3030                 if (ctx != mm->context.sparc64_ctx_val) {
3031                         /* When changing the page size fields, we
3032                          * must perform a context flush so that no
3033                          * stale entries match.  This flush must
3034                          * occur with the original context register
3035                          * settings.
3036                          */
3037                         do_flush_tlb_mm(mm);
3038
3039                         /* Reload the context register of all processors
3040                          * also executing in this address space.
3041                          */
3042                         mm->context.sparc64_ctx_val = ctx;
3043                         need_context_reload = true;
3044                 }
3045                 spin_unlock_irq(&ctx_alloc_lock);
3046
3047                 if (need_context_reload)
3048                         on_each_cpu(context_reload, mm, 0);
3049         }
3050 }
3051 #endif
3052
3053 static struct resource code_resource = {
3054         .name   = "Kernel code",
3055         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3056 };
3057
3058 static struct resource data_resource = {
3059         .name   = "Kernel data",
3060         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3061 };
3062
3063 static struct resource bss_resource = {
3064         .name   = "Kernel bss",
3065         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3066 };
3067
3068 static inline resource_size_t compute_kern_paddr(void *addr)
3069 {
3070         return (resource_size_t) (addr - KERNBASE + kern_base);
3071 }
3072
3073 static void __init kernel_lds_init(void)
3074 {
3075         code_resource.start = compute_kern_paddr(_text);
3076         code_resource.end   = compute_kern_paddr(_etext - 1);
3077         data_resource.start = compute_kern_paddr(_etext);
3078         data_resource.end   = compute_kern_paddr(_edata - 1);
3079         bss_resource.start  = compute_kern_paddr(__bss_start);
3080         bss_resource.end    = compute_kern_paddr(_end - 1);
3081 }
3082
3083 static int __init report_memory(void)
3084 {
3085         int i;
3086         struct resource *res;
3087
3088         kernel_lds_init();
3089
3090         for (i = 0; i < pavail_ents; i++) {
3091                 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3092
3093                 if (!res) {
3094                         pr_warn("Failed to allocate source.\n");
3095                         break;
3096                 }
3097
3098                 res->name = "System RAM";
3099                 res->start = pavail[i].phys_addr;
3100                 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3101                 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3102
3103                 if (insert_resource(&iomem_resource, res) < 0) {
3104                         pr_warn("Resource insertion failed.\n");
3105                         break;
3106                 }
3107
3108                 insert_resource(res, &code_resource);
3109                 insert_resource(res, &data_resource);
3110                 insert_resource(res, &bss_resource);
3111         }
3112
3113         return 0;
3114 }
3115 arch_initcall(report_memory);
3116
3117 #ifdef CONFIG_SMP
3118 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
3119 #else
3120 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
3121 #endif
3122
3123 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3124 {
3125         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3126                 if (start < LOW_OBP_ADDRESS) {
3127                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3128                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3129                 }
3130                 if (end > HI_OBP_ADDRESS) {
3131                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3132                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3133                 }
3134         } else {
3135                 flush_tsb_kernel_range(start, end);
3136                 do_flush_tlb_kernel_range(start, end);
3137         }
3138 }
3139
3140 void copy_user_highpage(struct page *to, struct page *from,
3141         unsigned long vaddr, struct vm_area_struct *vma)
3142 {
3143         char *vfrom, *vto;
3144
3145         vfrom = kmap_atomic(from);
3146         vto = kmap_atomic(to);
3147         copy_user_page(vto, vfrom, vaddr, to);
3148         kunmap_atomic(vto);
3149         kunmap_atomic(vfrom);
3150
3151         /* If this page has ADI enabled, copy over any ADI tags
3152          * as well
3153          */
3154         if (vma->vm_flags & VM_SPARC_ADI) {
3155                 unsigned long pfrom, pto, i, adi_tag;
3156
3157                 pfrom = page_to_phys(from);
3158                 pto = page_to_phys(to);
3159
3160                 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3161                         asm volatile("ldxa [%1] %2, %0\n\t"
3162                                         : "=r" (adi_tag)
3163                                         :  "r" (i), "i" (ASI_MCD_REAL));
3164                         asm volatile("stxa %0, [%1] %2\n\t"
3165                                         :
3166                                         : "r" (adi_tag), "r" (pto),
3167                                           "i" (ASI_MCD_REAL));
3168                         pto += adi_blksize();
3169                 }
3170                 asm volatile("membar #Sync\n\t");
3171         }
3172 }
3173 EXPORT_SYMBOL(copy_user_highpage);
3174
3175 void copy_highpage(struct page *to, struct page *from)
3176 {
3177         char *vfrom, *vto;
3178
3179         vfrom = kmap_atomic(from);
3180         vto = kmap_atomic(to);
3181         copy_page(vto, vfrom);
3182         kunmap_atomic(vto);
3183         kunmap_atomic(vfrom);
3184
3185         /* If this platform is ADI enabled, copy any ADI tags
3186          * as well
3187          */
3188         if (adi_capable()) {
3189                 unsigned long pfrom, pto, i, adi_tag;
3190
3191                 pfrom = page_to_phys(from);
3192                 pto = page_to_phys(to);
3193
3194                 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3195                         asm volatile("ldxa [%1] %2, %0\n\t"
3196                                         : "=r" (adi_tag)
3197                                         :  "r" (i), "i" (ASI_MCD_REAL));
3198                         asm volatile("stxa %0, [%1] %2\n\t"
3199                                         :
3200                                         : "r" (adi_tag), "r" (pto),
3201                                           "i" (ASI_MCD_REAL));
3202                         pto += adi_blksize();
3203                 }
3204                 asm volatile("membar #Sync\n\t");
3205         }
3206 }
3207 EXPORT_SYMBOL(copy_highpage);
3208
3209 pgprot_t vm_get_page_prot(unsigned long vm_flags)
3210 {
3211         unsigned long prot = pgprot_val(protection_map[vm_flags &
3212                                         (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]);
3213
3214         if (vm_flags & VM_SPARC_ADI)
3215                 prot |= _PAGE_MCD_4V;
3216
3217         return __pgprot(prot);
3218 }
3219 EXPORT_SYMBOL(vm_get_page_prot);