1 // SPDX-License-Identifier: GPL-2.0
3 * 'traps.c' handles hardware traps and faults after we have saved some
6 * SuperH version: Copyright (C) 1999 Niibe Yutaka
7 * Copyright (C) 2000 Philipp Rumpf
8 * Copyright (C) 2000 David Howells
9 * Copyright (C) 2002 - 2010 Paul Mundt
11 #include <linux/kernel.h>
12 #include <linux/ptrace.h>
13 #include <linux/hardirq.h>
14 #include <linux/init.h>
15 #include <linux/spinlock.h>
16 #include <linux/kallsyms.h>
18 #include <linux/bug.h>
19 #include <linux/debug_locks.h>
20 #include <linux/kdebug.h>
21 #include <linux/limits.h>
22 #include <linux/sysfs.h>
23 #include <linux/uaccess.h>
24 #include <linux/perf_event.h>
25 #include <linux/sched/task_stack.h>
27 #include <asm/alignment.h>
29 #include <asm/kprobes.h>
30 #include <asm/setup.h>
31 #include <asm/traps.h>
32 #include <asm/bl_bit.h>
35 # define TRAP_RESERVED_INST 4
36 # define TRAP_ILLEGAL_SLOT_INST 6
37 # define TRAP_ADDRESS_ERROR 9
38 # ifdef CONFIG_CPU_SH2A
40 # define TRAP_FPU_ERROR 13
41 # define TRAP_DIVZERO_ERROR 17
42 # define TRAP_DIVOVF_ERROR 18
45 #define TRAP_RESERVED_INST 12
46 #define TRAP_ILLEGAL_SLOT_INST 13
49 static inline void sign_extend(unsigned int count, unsigned char *dst)
51 #ifdef __LITTLE_ENDIAN__
52 if ((count == 1) && dst[0] & 0x80) {
57 if ((count == 2) && dst[1] & 0x80) {
62 if ((count == 1) && dst[3] & 0x80) {
67 if ((count == 2) && dst[2] & 0x80) {
74 static struct mem_access user_mem_access = {
79 static unsigned long copy_from_kernel_wrapper(void *dst, const void __user *src,
82 return copy_from_kernel_nofault(dst, (const void __force *)src, cnt);
85 static unsigned long copy_to_kernel_wrapper(void __user *dst, const void *src,
88 return copy_to_kernel_nofault((void __force *)dst, src, cnt);
91 static struct mem_access kernel_mem_access = {
92 copy_from_kernel_wrapper,
93 copy_to_kernel_wrapper,
97 * handle an instruction that does an unaligned memory access by emulating the
99 * - note that PC _may not_ point to the faulting instruction
100 * (if that instruction is in a branch delay slot)
101 * - return 0 if emulation okay, -EFAULT on existential error
103 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
104 struct mem_access *ma)
106 int ret, index, count;
107 unsigned long *rm, *rn;
108 unsigned char *src, *dst;
109 unsigned char __user *srcu, *dstu;
111 index = (instruction>>8)&15; /* 0x0F00 */
112 rn = ®s->regs[index];
114 index = (instruction>>4)&15; /* 0x00F0 */
115 rm = ®s->regs[index];
117 count = 1<<(instruction&3);
120 case 1: inc_unaligned_byte_access(); break;
121 case 2: inc_unaligned_word_access(); break;
122 case 4: inc_unaligned_dword_access(); break;
123 case 8: inc_unaligned_multi_access(); break;
127 switch (instruction>>12) {
128 case 0: /* mov.[bwl] to/from memory via r0+rn */
129 if (instruction & 8) {
131 srcu = (unsigned char __user *)*rm;
132 srcu += regs->regs[0];
133 dst = (unsigned char *)rn;
134 *(unsigned long *)dst = 0;
136 #if !defined(__LITTLE_ENDIAN__)
139 if (ma->from(dst, srcu, count))
142 sign_extend(count, dst);
145 src = (unsigned char *)rm;
146 #if !defined(__LITTLE_ENDIAN__)
149 dstu = (unsigned char __user *)*rn;
150 dstu += regs->regs[0];
152 if (ma->to(dstu, src, count))
158 case 1: /* mov.l Rm,@(disp,Rn) */
159 src = (unsigned char*) rm;
160 dstu = (unsigned char __user *)*rn;
161 dstu += (instruction&0x000F)<<2;
163 if (ma->to(dstu, src, 4))
168 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
171 src = (unsigned char*) rm;
172 dstu = (unsigned char __user *)*rn;
173 #if !defined(__LITTLE_ENDIAN__)
176 if (ma->to(dstu, src, count))
181 case 5: /* mov.l @(disp,Rm),Rn */
182 srcu = (unsigned char __user *)*rm;
183 srcu += (instruction & 0x000F) << 2;
184 dst = (unsigned char *)rn;
185 *(unsigned long *)dst = 0;
187 if (ma->from(dst, srcu, 4))
192 case 6: /* mov.[bwl] from memory, possibly with post-increment */
193 srcu = (unsigned char __user *)*rm;
196 dst = (unsigned char*) rn;
197 *(unsigned long*)dst = 0;
199 #if !defined(__LITTLE_ENDIAN__)
202 if (ma->from(dst, srcu, count))
204 sign_extend(count, dst);
209 switch ((instruction&0xFF00)>>8) {
210 case 0x81: /* mov.w R0,@(disp,Rn) */
211 src = (unsigned char *) ®s->regs[0];
212 #if !defined(__LITTLE_ENDIAN__)
215 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
216 dstu += (instruction & 0x000F) << 1;
218 if (ma->to(dstu, src, 2))
223 case 0x85: /* mov.w @(disp,Rm),R0 */
224 srcu = (unsigned char __user *)*rm;
225 srcu += (instruction & 0x000F) << 1;
226 dst = (unsigned char *) ®s->regs[0];
227 *(unsigned long *)dst = 0;
229 #if !defined(__LITTLE_ENDIAN__)
232 if (ma->from(dst, srcu, 2))
240 case 9: /* mov.w @(disp,PC),Rn */
241 srcu = (unsigned char __user *)regs->pc;
243 srcu += (instruction & 0x00FF) << 1;
244 dst = (unsigned char *)rn;
245 *(unsigned long *)dst = 0;
247 #if !defined(__LITTLE_ENDIAN__)
251 if (ma->from(dst, srcu, 2))
257 case 0xd: /* mov.l @(disp,PC),Rn */
258 srcu = (unsigned char __user *)(regs->pc & ~0x3);
260 srcu += (instruction & 0x00FF) << 2;
261 dst = (unsigned char *)rn;
262 *(unsigned long *)dst = 0;
264 if (ma->from(dst, srcu, 4))
272 /* Argh. Address not only misaligned but also non-existent.
273 * Raise an EFAULT and see if it's trapped
275 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
280 * emulate the instruction in the delay slot
281 * - fetches the instruction from PC+2
283 static inline int handle_delayslot(struct pt_regs *regs,
284 insn_size_t old_instruction,
285 struct mem_access *ma)
287 insn_size_t instruction;
288 void __user *addr = (void __user *)(regs->pc +
289 instruction_size(old_instruction));
291 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
292 /* the instruction-fetch faulted */
297 die("delay-slot-insn faulting in handle_unaligned_delayslot",
301 return handle_unaligned_ins(instruction, regs, ma);
305 * handle an instruction that does an unaligned memory access
306 * - have to be careful of branch delay-slot instructions that fault
308 * - if the branch would be taken PC points to the branch
309 * - if the branch would not be taken, PC points to delay-slot
311 * - PC always points to delayed branch
312 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
315 /* Macros to determine offset from current PC for branch instructions */
316 /* Explicit type coercion is used to force sign extension where needed */
317 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
318 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
320 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
321 struct mem_access *ma, int expected,
322 unsigned long address)
328 * XXX: We can't handle mixed 16/32-bit instructions yet
330 if (instruction_size(instruction) != 2)
333 index = (instruction>>8)&15; /* 0x0F00 */
334 rm = regs->regs[index];
337 * Log the unexpected fixups, and then pass them on to perf.
339 * We intentionally don't report the expected cases to perf as
340 * otherwise the trapped I/O case will skew the results too much
344 unaligned_fixups_notify(current, instruction, regs);
345 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
350 switch (instruction&0xF000) {
352 if (instruction==0x000B) {
354 ret = handle_delayslot(regs, instruction, ma);
358 else if ((instruction&0x00FF)==0x0023) {
360 ret = handle_delayslot(regs, instruction, ma);
364 else if ((instruction&0x00FF)==0x0003) {
366 ret = handle_delayslot(regs, instruction, ma);
368 regs->pr = regs->pc + 4;
373 /* mov.[bwl] to/from memory via r0+rn */
378 case 0x1000: /* mov.l Rm,@(disp,Rn) */
381 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
385 if ((instruction&0x00FF)==0x002B) {
387 ret = handle_delayslot(regs, instruction, ma);
391 else if ((instruction&0x00FF)==0x000B) {
393 ret = handle_delayslot(regs, instruction, ma);
395 regs->pr = regs->pc + 4;
400 /* mov.[bwl] to/from memory via r0+rn */
405 case 0x5000: /* mov.l @(disp,Rm),Rn */
408 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
411 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
412 switch (instruction&0x0F00) {
413 case 0x0100: /* mov.w R0,@(disp,Rm) */
415 case 0x0500: /* mov.w @(disp,Rm),R0 */
417 case 0x0B00: /* bf lab - no delayslot*/
420 case 0x0F00: /* bf/s lab */
421 ret = handle_delayslot(regs, instruction, ma);
423 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
424 if ((regs->sr & 0x00000001) != 0)
425 regs->pc += 4; /* next after slot */
428 regs->pc += SH_PC_8BIT_OFFSET(instruction);
431 case 0x0900: /* bt lab - no delayslot */
434 case 0x0D00: /* bt/s lab */
435 ret = handle_delayslot(regs, instruction, ma);
437 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
438 if ((regs->sr & 0x00000001) == 0)
439 regs->pc += 4; /* next after slot */
442 regs->pc += SH_PC_8BIT_OFFSET(instruction);
448 case 0x9000: /* mov.w @(disp,Rm),Rn */
451 case 0xA000: /* bra label */
452 ret = handle_delayslot(regs, instruction, ma);
454 regs->pc += SH_PC_12BIT_OFFSET(instruction);
457 case 0xB000: /* bsr label */
458 ret = handle_delayslot(regs, instruction, ma);
460 regs->pr = regs->pc + 4;
461 regs->pc += SH_PC_12BIT_OFFSET(instruction);
465 case 0xD000: /* mov.l @(disp,Rm),Rn */
470 /* handle non-delay-slot instruction */
472 ret = handle_unaligned_ins(instruction, regs, ma);
474 regs->pc += instruction_size(instruction);
479 * Handle various address error exceptions:
480 * - instruction address error:
482 * PC >= 0x80000000 in user mode
483 * - data address error (read and write)
484 * misaligned data access
485 * access to >= 0x80000000 is user mode
486 * Unfortuntaly we can't distinguish between instruction address error
487 * and data address errors caused by read accesses.
489 asmlinkage void do_address_error(struct pt_regs *regs,
490 unsigned long writeaccess,
491 unsigned long address)
493 unsigned long error_code = 0;
494 insn_size_t instruction;
497 /* Intentional ifdef */
498 #ifdef CONFIG_CPU_HAS_SR_RB
499 error_code = lookup_exception_vector();
502 if (user_mode(regs)) {
503 int si_code = BUS_ADRERR;
504 unsigned int user_action;
507 inc_unaligned_user_access();
509 if (copy_from_user(&instruction, (insn_size_t __user *)(regs->pc & ~1),
510 sizeof(instruction))) {
514 /* shout about userspace fixups */
515 unaligned_fixups_notify(current, instruction, regs);
517 user_action = unaligned_user_action();
518 if (user_action & UM_FIXUP)
520 if (user_action & UM_SIGNAL)
524 regs->pc += instruction_size(instruction);
529 /* bad PC is not something we can fix */
531 si_code = BUS_ADRALN;
535 tmp = handle_unaligned_access(instruction, regs,
542 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
543 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
546 force_sig_fault(SIGBUS, si_code, (void __user *)address);
548 inc_unaligned_kernel_access();
551 die("unaligned program counter", regs, error_code);
553 if (copy_from_kernel_nofault(&instruction, (void *)(regs->pc),
554 sizeof(instruction))) {
555 /* Argh. Fault on the instruction itself.
556 This should never happen non-SMP
558 die("insn faulting in do_address_error", regs, 0);
561 unaligned_fixups_notify(current, instruction, regs);
563 handle_unaligned_access(instruction, regs, &kernel_mem_access,
572 static int is_dsp_inst(struct pt_regs *regs)
574 unsigned short inst = 0;
577 * Safe guard if DSP mode is already enabled or we're lacking
578 * the DSP altogether.
580 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
583 get_user(inst, ((unsigned short *) regs->pc));
587 /* Check for any type of DSP or support instruction */
588 if ((inst == 0xf000) || (inst == 0x4000))
594 static inline int is_dsp_inst(struct pt_regs *regs) { return 0; }
595 #endif /* CONFIG_SH_DSP */
597 #ifdef CONFIG_CPU_SH2A
598 asmlinkage void do_divide_error(unsigned long r4)
603 case TRAP_DIVZERO_ERROR:
606 case TRAP_DIVOVF_ERROR:
610 /* Let gcc know unhandled cases don't make it past here */
613 force_sig_fault(SIGFPE, code, NULL);
617 asmlinkage void do_reserved_inst(void)
619 struct pt_regs *regs = current_pt_regs();
620 unsigned long error_code;
622 #ifdef CONFIG_SH_FPU_EMU
623 unsigned short inst = 0;
626 get_user(inst, (unsigned short __user *)regs->pc);
628 err = do_fpu_inst(inst, regs);
630 regs->pc += instruction_size(inst);
633 /* not a FPU inst. */
637 /* Check if it's a DSP instruction */
638 if (is_dsp_inst(regs)) {
639 /* Enable DSP mode, and restart instruction. */
642 current->thread.dsp_status.status |= SR_DSP;
647 error_code = lookup_exception_vector();
651 die_if_no_fixup("reserved instruction", regs, error_code);
654 #ifdef CONFIG_SH_FPU_EMU
655 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
658 * bfs: 8fxx: PC+=d*2+4;
659 * bts: 8dxx: PC+=d*2+4;
660 * bra: axxx: PC+=D*2+4;
661 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
662 * braf:0x23: PC+=Rn*2+4;
663 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
665 * jsr: 4x0b: PC=Rn after PR=PC+4;
668 if (((inst & 0xf000) == 0xb000) || /* bsr */
669 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
670 ((inst & 0xf0ff) == 0x400b)) /* jsr */
671 regs->pr = regs->pc + 4;
673 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
674 regs->pc += SH_PC_8BIT_OFFSET(inst);
678 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
679 regs->pc += SH_PC_12BIT_OFFSET(inst);
683 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
684 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
688 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
689 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
693 if ((inst & 0xffff) == 0x000b) { /* rts */
702 asmlinkage void do_illegal_slot_inst(void)
704 struct pt_regs *regs = current_pt_regs();
707 if (kprobe_handle_illslot(regs->pc) == 0)
710 #ifdef CONFIG_SH_FPU_EMU
711 get_user(inst, (unsigned short __user *)regs->pc + 1);
712 if (!do_fpu_inst(inst, regs)) {
713 get_user(inst, (unsigned short __user *)regs->pc);
714 if (!emulate_branch(inst, regs))
716 /* fault in branch.*/
718 /* not a FPU inst. */
721 inst = lookup_exception_vector();
725 die_if_no_fixup("illegal slot instruction", regs, inst);
728 asmlinkage void do_exception_error(void)
732 ex = lookup_exception_vector();
733 die_if_kernel("exception", current_pt_regs(), ex);
736 void per_cpu_trap_init(void)
738 extern void *vbr_base;
740 /* NOTE: The VBR value should be at P1
741 (or P2, virtural "fixed" address space).
742 It's definitely should not in physical address. */
744 asm volatile("ldc %0, vbr"
749 /* disable exception blocking now when the vbr has been setup */
753 void *set_exception_table_vec(unsigned int vec, void *handler)
755 extern void *exception_handling_table[];
758 old_handler = exception_handling_table[vec];
759 exception_handling_table[vec] = handler;
763 void __init trap_init(void)
765 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
766 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
768 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
769 defined(CONFIG_SH_FPU_EMU)
771 * For SH-4 lacking an FPU, treat floating point instructions as
772 * reserved. They'll be handled in the math-emu case, or faulted on
775 set_exception_table_evt(0x800, do_reserved_inst);
776 set_exception_table_evt(0x820, do_illegal_slot_inst);
777 #elif defined(CONFIG_SH_FPU)
778 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
779 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
782 #ifdef CONFIG_CPU_SH2
783 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
785 #ifdef CONFIG_CPU_SH2A
786 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
787 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
789 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
794 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);