arch/powerpc/kernel/sysfs.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 #include <linux/device.h>
   3 #include <linux/cpu.h>
   4 #include <linux/smp.h>
   5 #include <linux/percpu.h>
   6 #include <linux/init.h>
   7 #include <linux/sched.h>
   8 #include <linux/export.h>
   9 #include <linux/nodemask.h>
  10 #include <linux/cpumask.h>
  11 #include <linux/notifier.h>
  12 #include <linux/of.h>
  13
  14 #include <asm/current.h>
  15 #include <asm/processor.h>
  16 #include <asm/cputable.h>
  17 #include <asm/hvcall.h>
  18 #include <asm/machdep.h>
  19 #include <asm/smp.h>
  20 #include <asm/time.h>
  21 #include <asm/pmc.h>
  22 #include <asm/firmware.h>
  23 #include <asm/idle.h>
  24 #include <asm/svm.h>
  25
  26 #include "cacheinfo.h"
  27 #include "setup.h"
  28
  29 #ifdef CONFIG_PPC64
  30 #include <asm/paca.h>
  31 #include <asm/lppaca.h>
  32 #endif
  33
  34 static DEFINE_PER_CPU(struct cpu, cpu_devices);
  35
  36 #ifdef CONFIG_PPC64
  37
  38 /*
  39  * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle:
  40  * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in
  41  * 2014:
  42  *
  43  *  "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean
  44  *  up the kernel code."
  45  *
  46  * powerpc-utils stopped using it as of 1.3.8. At some point in the future this
  47  * code should be removed.
  48  */
  49
  50 static ssize_t store_smt_snooze_delay(struct device *dev,
  51                                       struct device_attribute *attr,
  52                                       const char *buf,
  53                                       size_t count)
  54 {
  55         pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",
  56                      current->comm, current->pid);
  57         return count;
  58 }
  59
  60 static ssize_t show_smt_snooze_delay(struct device *dev,
  61                                      struct device_attribute *attr,
  62                                      char *buf)
  63 {
  64         pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",
  65                      current->comm, current->pid);
  66         return sprintf(buf, "100\n");
  67 }
  68
  69 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
  70                    store_smt_snooze_delay);
  71
  72 static int __init setup_smt_snooze_delay(char *str)
  73 {
  74         if (!cpu_has_feature(CPU_FTR_SMT))
  75                 return 1;
  76
  77         pr_warn("smt-snooze-delay command line option has no effect\n");
  78         return 1;
  79 }
  80 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
  81
  82 #endif /* CONFIG_PPC64 */
  83
  84 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
  85 static void read_##NAME(void *val) \
  86 { \
  87         *(unsigned long *)val = mfspr(ADDRESS); \
  88 } \
  89 static void write_##NAME(void *val) \
  90 { \
  91         EXTRA; \
  92         mtspr(ADDRESS, *(unsigned long *)val);  \
  93 }
  94
  95 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
  96 static ssize_t show_##NAME(struct device *dev, \
  97                         struct device_attribute *attr, \
  98                         char *buf) \
  99 { \
 100         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 101         unsigned long val; \
 102         smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);    \
 103         return sprintf(buf, "%lx\n", val); \
 104 } \
 105 static ssize_t __used \
 106         store_##NAME(struct device *dev, struct device_attribute *attr, \
 107                         const char *buf, size_t count) \
 108 { \
 109         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 110         unsigned long val; \
 111         int ret = sscanf(buf, "%lx", &val); \
 112         if (ret != 1) \
 113                 return -EINVAL; \
 114         smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
 115         return count; \
 116 }
 117
 118 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
 119         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
 120         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 121 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
 122         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
 123         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 124
 125 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 126         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 127
 128 #ifdef CONFIG_PPC64
 129
 130 /*
 131  * This is the system wide DSCR register default value. Any
 132  * change to this default value through the sysfs interface
 133  * will update all per cpu DSCR default values across the
 134  * system stored in their respective PACA structures.
 135  */
 136 static unsigned long dscr_default;
 137
 138 /**
 139  * read_dscr() - Fetch the cpu specific DSCR default
 140  * @val:        Returned cpu specific DSCR default value
 141  *
 142  * This function returns the per cpu DSCR default value
 143  * for any cpu which is contained in its PACA structure.
 144  */
 145 static void read_dscr(void *val)
 146 {
 147         *(unsigned long *)val = get_paca()->dscr_default;
 148 }
 149
 150
 151 /**
 152  * write_dscr() - Update the cpu specific DSCR default
 153  * @val:        New cpu specific DSCR default value to update
 154  *
 155  * This function updates the per cpu DSCR default value
 156  * for any cpu which is contained in its PACA structure.
 157  */
 158 static void write_dscr(void *val)
 159 {
 160         get_paca()->dscr_default = *(unsigned long *)val;
 161         if (!current->thread.dscr_inherit) {
 162                 current->thread.dscr = *(unsigned long *)val;
 163                 mtspr(SPRN_DSCR, *(unsigned long *)val);
 164         }
 165 }
 166
 167 SYSFS_SPRSETUP_SHOW_STORE(dscr);
 168 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 169
 170 static void add_write_permission_dev_attr(struct device_attribute *attr)
 171 {
 172         attr->attr.mode |= 0200;
 173 }
 174
 175 /**
 176  * show_dscr_default() - Fetch the system wide DSCR default
 177  * @dev:        Device structure
 178  * @attr:       Device attribute structure
 179  * @buf:        Interface buffer
 180  *
 181  * This function returns the system wide DSCR default value.
 182  */
 183 static ssize_t show_dscr_default(struct device *dev,
 184                 struct device_attribute *attr, char *buf)
 185 {
 186         return sprintf(buf, "%lx\n", dscr_default);
 187 }
 188
 189 /**
 190  * store_dscr_default() - Update the system wide DSCR default
 191  * @dev:        Device structure
 192  * @attr:       Device attribute structure
 193  * @buf:        Interface buffer
 194  * @count:      Size of the update
 195  *
 196  * This function updates the system wide DSCR default value.
 197  */
 198 static ssize_t __used store_dscr_default(struct device *dev,
 199                 struct device_attribute *attr, const char *buf,
 200                 size_t count)
 201 {
 202         unsigned long val;
 203         int ret = 0;
 204
 205         ret = sscanf(buf, "%lx", &val);
 206         if (ret != 1)
 207                 return -EINVAL;
 208         dscr_default = val;
 209
 210         on_each_cpu(write_dscr, &val, 1);
 211
 212         return count;
 213 }
 214
 215 static DEVICE_ATTR(dscr_default, 0600,
 216                 show_dscr_default, store_dscr_default);
 217
 218 static void __init sysfs_create_dscr_default(void)
 219 {
 220         if (cpu_has_feature(CPU_FTR_DSCR)) {
 221                 struct device *dev_root;
 222                 int cpu;
 223
 224                 dscr_default = spr_default_dscr;
 225                 for_each_possible_cpu(cpu)
 226                         paca_ptrs[cpu]->dscr_default = dscr_default;
 227
 228                 dev_root = bus_get_dev_root(&cpu_subsys);
 229                 if (dev_root) {
 230                         device_create_file(dev_root, &dev_attr_dscr_default);
 231                         put_device(dev_root);
 232                 }
 233         }
 234 }
 235 #endif /* CONFIG_PPC64 */
 236
 237 #ifdef CONFIG_PPC_E500
 238 #define MAX_BIT                         63
 239
 240 static u64 pw20_wt;
 241 static u64 altivec_idle_wt;
 242
 243 static unsigned int get_idle_ticks_bit(u64 ns)
 244 {
 245         u64 cycle;
 246
 247         if (ns >= 10000)
 248                 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
 249         else
 250                 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
 251
 252         if (!cycle)
 253                 return 0;
 254
 255         return ilog2(cycle);
 256 }
 257
 258 static void do_show_pwrmgtcr0(void *val)
 259 {
 260         u32 *value = val;
 261
 262         *value = mfspr(SPRN_PWRMGTCR0);
 263 }
 264
 265 static ssize_t show_pw20_state(struct device *dev,
 266                                 struct device_attribute *attr, char *buf)
 267 {
 268         u32 value;
 269         unsigned int cpu = dev->id;
 270
 271         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 272
 273         value &= PWRMGTCR0_PW20_WAIT;
 274
 275         return sprintf(buf, "%u\n", value ? 1 : 0);
 276 }
 277
 278 static void do_store_pw20_state(void *val)
 279 {
 280         u32 *value = val;
 281         u32 pw20_state;
 282
 283         pw20_state = mfspr(SPRN_PWRMGTCR0);
 284
 285         if (*value)
 286                 pw20_state |= PWRMGTCR0_PW20_WAIT;
 287         else
 288                 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
 289
 290         mtspr(SPRN_PWRMGTCR0, pw20_state);
 291 }
 292
 293 static ssize_t store_pw20_state(struct device *dev,
 294                                 struct device_attribute *attr,
 295                                 const char *buf, size_t count)
 296 {
 297         u32 value;
 298         unsigned int cpu = dev->id;
 299
 300         if (kstrtou32(buf, 0, &value))
 301                 return -EINVAL;
 302
 303         if (value > 1)
 304                 return -EINVAL;
 305
 306         smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
 307
 308         return count;
 309 }
 310
 311 static ssize_t show_pw20_wait_time(struct device *dev,
 312                                 struct device_attribute *attr, char *buf)
 313 {
 314         u32 value;
 315         u64 tb_cycle = 1;
 316         u64 time;
 317
 318         unsigned int cpu = dev->id;
 319
 320         if (!pw20_wt) {
 321                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 322                 value = (value & PWRMGTCR0_PW20_ENT) >>
 323                                         PWRMGTCR0_PW20_ENT_SHIFT;
 324
 325                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 326                 /* convert ms to ns */
 327                 if (tb_ticks_per_usec > 1000) {
 328                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 329                 } else {
 330                         u32 rem_us;
 331
 332                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 333                                                 &rem_us);
 334                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 335                 }
 336         } else {
 337                 time = pw20_wt;
 338         }
 339
 340         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 341 }
 342
 343 static void set_pw20_wait_entry_bit(void *val)
 344 {
 345         u32 *value = val;
 346         u32 pw20_idle;
 347
 348         pw20_idle = mfspr(SPRN_PWRMGTCR0);
 349
 350         /* Set Automatic PW20 Core Idle Count */
 351         /* clear count */
 352         pw20_idle &= ~PWRMGTCR0_PW20_ENT;
 353
 354         /* set count */
 355         pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
 356
 357         mtspr(SPRN_PWRMGTCR0, pw20_idle);
 358 }
 359
 360 static ssize_t store_pw20_wait_time(struct device *dev,
 361                                 struct device_attribute *attr,
 362                                 const char *buf, size_t count)
 363 {
 364         u32 entry_bit;
 365         u64 value;
 366
 367         unsigned int cpu = dev->id;
 368
 369         if (kstrtou64(buf, 0, &value))
 370                 return -EINVAL;
 371
 372         if (!value)
 373                 return -EINVAL;
 374
 375         entry_bit = get_idle_ticks_bit(value);
 376         if (entry_bit > MAX_BIT)
 377                 return -EINVAL;
 378
 379         pw20_wt = value;
 380
 381         smp_call_function_single(cpu, set_pw20_wait_entry_bit,
 382                                 &entry_bit, 1);
 383
 384         return count;
 385 }
 386
 387 static ssize_t show_altivec_idle(struct device *dev,
 388                                 struct device_attribute *attr, char *buf)
 389 {
 390         u32 value;
 391         unsigned int cpu = dev->id;
 392
 393         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 394
 395         value &= PWRMGTCR0_AV_IDLE_PD_EN;
 396
 397         return sprintf(buf, "%u\n", value ? 1 : 0);
 398 }
 399
 400 static void do_store_altivec_idle(void *val)
 401 {
 402         u32 *value = val;
 403         u32 altivec_idle;
 404
 405         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 406
 407         if (*value)
 408                 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
 409         else
 410                 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
 411
 412         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 413 }
 414
 415 static ssize_t store_altivec_idle(struct device *dev,
 416                                 struct device_attribute *attr,
 417                                 const char *buf, size_t count)
 418 {
 419         u32 value;
 420         unsigned int cpu = dev->id;
 421
 422         if (kstrtou32(buf, 0, &value))
 423                 return -EINVAL;
 424
 425         if (value > 1)
 426                 return -EINVAL;
 427
 428         smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
 429
 430         return count;
 431 }
 432
 433 static ssize_t show_altivec_idle_wait_time(struct device *dev,
 434                                 struct device_attribute *attr, char *buf)
 435 {
 436         u32 value;
 437         u64 tb_cycle = 1;
 438         u64 time;
 439
 440         unsigned int cpu = dev->id;
 441
 442         if (!altivec_idle_wt) {
 443                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 444                 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
 445                                         PWRMGTCR0_AV_IDLE_CNT_SHIFT;
 446
 447                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 448                 /* convert ms to ns */
 449                 if (tb_ticks_per_usec > 1000) {
 450                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 451                 } else {
 452                         u32 rem_us;
 453
 454                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 455                                                 &rem_us);
 456                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 457                 }
 458         } else {
 459                 time = altivec_idle_wt;
 460         }
 461
 462         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 463 }
 464
 465 static void set_altivec_idle_wait_entry_bit(void *val)
 466 {
 467         u32 *value = val;
 468         u32 altivec_idle;
 469
 470         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 471
 472         /* Set Automatic AltiVec Idle Count */
 473         /* clear count */
 474         altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
 475
 476         /* set count */
 477         altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
 478
 479         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 480 }
 481
 482 static ssize_t store_altivec_idle_wait_time(struct device *dev,
 483                                 struct device_attribute *attr,
 484                                 const char *buf, size_t count)
 485 {
 486         u32 entry_bit;
 487         u64 value;
 488
 489         unsigned int cpu = dev->id;
 490
 491         if (kstrtou64(buf, 0, &value))
 492                 return -EINVAL;
 493
 494         if (!value)
 495                 return -EINVAL;
 496
 497         entry_bit = get_idle_ticks_bit(value);
 498         if (entry_bit > MAX_BIT)
 499                 return -EINVAL;
 500
 501         altivec_idle_wt = value;
 502
 503         smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
 504                                 &entry_bit, 1);
 505
 506         return count;
 507 }
 508
 509 /*
 510  * Enable/Disable interface:
 511  * 0, disable. 1, enable.
 512  */
 513 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
 514 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
 515
 516 /*
 517  * Set wait time interface:(Nanosecond)
 518  * Example: Base on TBfreq is 41MHZ.
 519  * 1~48(ns): TB[63]
 520  * 49~97(ns): TB[62]
 521  * 98~195(ns): TB[61]
 522  * 196~390(ns): TB[60]
 523  * 391~780(ns): TB[59]
 524  * 781~1560(ns): TB[58]
 525  * ...
 526  */
 527 static DEVICE_ATTR(pw20_wait_time, 0600,
 528                         show_pw20_wait_time,
 529                         store_pw20_wait_time);
 530 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
 531                         show_altivec_idle_wait_time,
 532                         store_altivec_idle_wait_time);
 533 #endif
 534
 535 /*
 536  * Enabling PMCs will slow partition context switch times so we only do
 537  * it the first time we write to the PMCs.
 538  */
 539
 540 static DEFINE_PER_CPU(char, pmcs_enabled);
 541
 542 void ppc_enable_pmcs(void)
 543 {
 544         ppc_set_pmu_inuse(1);
 545
 546         /* Only need to enable them once */
 547         if (__this_cpu_read(pmcs_enabled))
 548                 return;
 549
 550         __this_cpu_write(pmcs_enabled, 1);
 551
 552         if (ppc_md.enable_pmcs)
 553                 ppc_md.enable_pmcs();
 554 }
 555 EXPORT_SYMBOL(ppc_enable_pmcs);
 556
 557
 558
 559 /* Let's define all possible registers, we'll only hook up the ones
 560  * that are implemented on the current processor
 561  */
 562
 563 #ifdef CONFIG_PMU_SYSFS
 564 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
 565 #define HAS_PPC_PMC_CLASSIC     1
 566 #define HAS_PPC_PMC_IBM         1
 567 #endif
 568
 569 #ifdef CONFIG_PPC64
 570 #define HAS_PPC_PMC_PA6T        1
 571 #define HAS_PPC_PMC56          1
 572 #endif
 573
 574 #ifdef CONFIG_PPC_BOOK3S_32
 575 #define HAS_PPC_PMC_G4          1
 576 #endif
 577 #endif /* CONFIG_PMU_SYSFS */
 578
 579 #if defined(CONFIG_PPC64) && defined(CONFIG_DEBUG_MISC)
 580 #define HAS_PPC_PA6T
 581 #endif
 582 /*
 583  * SPRs which are not related to PMU.
 584  */
 585 #ifdef CONFIG_PPC64
 586 SYSFS_SPRSETUP(purr, SPRN_PURR);
 587 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
 588 SYSFS_SPRSETUP(pir, SPRN_PIR);
 589 SYSFS_SPRSETUP(tscr, SPRN_TSCR);
 590
 591 /*
 592   Lets only enable read for phyp resources and
 593   enable write when needed with a separate function.
 594   Lets be conservative and default to pseries.
 595 */
 596 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 597 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 598 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
 599 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
 600 #endif /* CONFIG_PPC64 */
 601
 602 #ifdef HAS_PPC_PMC_CLASSIC
 603 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
 604 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
 605 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
 606 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
 607 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
 608 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
 609 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
 610 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
 611 #endif
 612
 613 #ifdef HAS_PPC_PMC_G4
 614 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
 615 #endif
 616
 617 #ifdef HAS_PPC_PMC56
 618 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
 619 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 620
 621 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 622 SYSFS_PMCSETUP(mmcr3, SPRN_MMCR3);
 623
 624 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 625 static DEVICE_ATTR(mmcr3, 0600, show_mmcr3, store_mmcr3);
 626 #endif /* HAS_PPC_PMC56 */
 627
 628
 629
 630
 631 #ifdef HAS_PPC_PMC_PA6T
 632 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
 633 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
 634 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
 635 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
 636 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
 637 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
 638 #endif
 639
 640 #ifdef HAS_PPC_PA6T
 641 SYSFS_SPRSETUP(hid0, SPRN_HID0);
 642 SYSFS_SPRSETUP(hid1, SPRN_HID1);
 643 SYSFS_SPRSETUP(hid4, SPRN_HID4);
 644 SYSFS_SPRSETUP(hid5, SPRN_HID5);
 645 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
 646 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
 647 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
 648 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
 649 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
 650 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
 651 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
 652 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
 653 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
 654 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
 655 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
 656 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
 657 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
 658 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
 659 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
 660 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
 661 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
 662 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
 663 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
 664 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
 665 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
 666 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
 667 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
 668 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
 669 #endif /* HAS_PPC_PA6T */
 670
 671 #ifdef HAS_PPC_PMC_IBM
 672 static struct device_attribute ibm_common_attrs[] = {
 673         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 674         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 675 };
 676 #endif /* HAS_PPC_PMC_IBM */
 677
 678 #ifdef HAS_PPC_PMC_G4
 679 static struct device_attribute g4_common_attrs[] = {
 680         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 681         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 682         __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
 683 };
 684 #endif /* HAS_PPC_PMC_G4 */
 685
 686 #ifdef HAS_PPC_PMC_CLASSIC
 687 static struct device_attribute classic_pmc_attrs[] = {
 688         __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
 689         __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
 690         __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
 691         __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
 692         __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
 693         __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
 694 #ifdef HAS_PPC_PMC56
 695         __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
 696         __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
 697 #endif
 698 };
 699 #endif
 700
 701 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
 702 static struct device_attribute pa6t_attrs[] = {
 703 #ifdef HAS_PPC_PMC_PA6T
 704         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 705         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 706         __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
 707         __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
 708         __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
 709         __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
 710         __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
 711         __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
 712 #endif
 713 #ifdef HAS_PPC_PA6T
 714         __ATTR(hid0, 0600, show_hid0, store_hid0),
 715         __ATTR(hid1, 0600, show_hid1, store_hid1),
 716         __ATTR(hid4, 0600, show_hid4, store_hid4),
 717         __ATTR(hid5, 0600, show_hid5, store_hid5),
 718         __ATTR(ima0, 0600, show_ima0, store_ima0),
 719         __ATTR(ima1, 0600, show_ima1, store_ima1),
 720         __ATTR(ima2, 0600, show_ima2, store_ima2),
 721         __ATTR(ima3, 0600, show_ima3, store_ima3),
 722         __ATTR(ima4, 0600, show_ima4, store_ima4),
 723         __ATTR(ima5, 0600, show_ima5, store_ima5),
 724         __ATTR(ima6, 0600, show_ima6, store_ima6),
 725         __ATTR(ima7, 0600, show_ima7, store_ima7),
 726         __ATTR(ima8, 0600, show_ima8, store_ima8),
 727         __ATTR(ima9, 0600, show_ima9, store_ima9),
 728         __ATTR(imaat, 0600, show_imaat, store_imaat),
 729         __ATTR(btcr, 0600, show_btcr, store_btcr),
 730         __ATTR(pccr, 0600, show_pccr, store_pccr),
 731         __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
 732         __ATTR(der, 0600, show_der, store_der),
 733         __ATTR(mer, 0600, show_mer, store_mer),
 734         __ATTR(ber, 0600, show_ber, store_ber),
 735         __ATTR(ier, 0600, show_ier, store_ier),
 736         __ATTR(sier, 0600, show_sier, store_sier),
 737         __ATTR(siar, 0600, show_siar, store_siar),
 738         __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
 739         __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
 740         __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
 741         __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
 742 #endif /* HAS_PPC_PA6T */
 743 };
 744 #endif
 745
 746 #ifdef CONFIG_PPC_SVM
 747 static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf)
 748 {
 749         return sprintf(buf, "%u\n", is_secure_guest());
 750 }
 751 static DEVICE_ATTR(svm, 0444, show_svm, NULL);
 752
 753 static void __init create_svm_file(void)
 754 {
 755         struct device *dev_root = bus_get_dev_root(&cpu_subsys);
 756
 757         if (dev_root) {
 758                 device_create_file(dev_root, &dev_attr_svm);
 759                 put_device(dev_root);
 760         }
 761 }
 762 #else
 763 static void __init create_svm_file(void)
 764 {
 765 }
 766 #endif /* CONFIG_PPC_SVM */
 767
 768 #ifdef CONFIG_PPC_PSERIES
 769 static void read_idle_purr(void *val)
 770 {
 771         u64 *ret = val;
 772
 773         *ret = read_this_idle_purr();
 774 }
 775
 776 static ssize_t idle_purr_show(struct device *dev,
 777                               struct device_attribute *attr, char *buf)
 778 {
 779         struct cpu *cpu = container_of(dev, struct cpu, dev);
 780         u64 val;
 781
 782         smp_call_function_single(cpu->dev.id, read_idle_purr, &val, 1);
 783         return sprintf(buf, "%llx\n", val);
 784 }
 785 static DEVICE_ATTR(idle_purr, 0400, idle_purr_show, NULL);
 786
 787 static void create_idle_purr_file(struct device *s)
 788 {
 789         if (firmware_has_feature(FW_FEATURE_LPAR))
 790                 device_create_file(s, &dev_attr_idle_purr);
 791 }
 792
 793 static void remove_idle_purr_file(struct device *s)
 794 {
 795         if (firmware_has_feature(FW_FEATURE_LPAR))
 796                 device_remove_file(s, &dev_attr_idle_purr);
 797 }
 798
 799 static void read_idle_spurr(void *val)
 800 {
 801         u64 *ret = val;
 802
 803         *ret = read_this_idle_spurr();
 804 }
 805
 806 static ssize_t idle_spurr_show(struct device *dev,
 807                                struct device_attribute *attr, char *buf)
 808 {
 809         struct cpu *cpu = container_of(dev, struct cpu, dev);
 810         u64 val;
 811
 812         smp_call_function_single(cpu->dev.id, read_idle_spurr, &val, 1);
 813         return sprintf(buf, "%llx\n", val);
 814 }
 815 static DEVICE_ATTR(idle_spurr, 0400, idle_spurr_show, NULL);
 816
 817 static void create_idle_spurr_file(struct device *s)
 818 {
 819         if (firmware_has_feature(FW_FEATURE_LPAR))
 820                 device_create_file(s, &dev_attr_idle_spurr);
 821 }
 822
 823 static void remove_idle_spurr_file(struct device *s)
 824 {
 825         if (firmware_has_feature(FW_FEATURE_LPAR))
 826                 device_remove_file(s, &dev_attr_idle_spurr);
 827 }
 828
 829 #else /* CONFIG_PPC_PSERIES */
 830 #define create_idle_purr_file(s)
 831 #define remove_idle_purr_file(s)
 832 #define create_idle_spurr_file(s)
 833 #define remove_idle_spurr_file(s)
 834 #endif /* CONFIG_PPC_PSERIES */
 835
 836 static int register_cpu_online(unsigned int cpu)
 837 {
 838         struct cpu *c = &per_cpu(cpu_devices, cpu);
 839         struct device *s = &c->dev;
 840         struct device_attribute *attrs, *pmc_attrs;
 841         int i, nattrs;
 842
 843         /* For cpus present at boot a reference was already grabbed in register_cpu() */
 844         if (!s->of_node)
 845                 s->of_node = of_get_cpu_node(cpu, NULL);
 846
 847 #ifdef CONFIG_PPC64
 848         if (cpu_has_feature(CPU_FTR_SMT))
 849                 device_create_file(s, &dev_attr_smt_snooze_delay);
 850 #endif
 851
 852         /* PMC stuff */
 853         switch (cur_cpu_spec->pmc_type) {
 854 #ifdef HAS_PPC_PMC_IBM
 855         case PPC_PMC_IBM:
 856                 attrs = ibm_common_attrs;
 857                 nattrs = ARRAY_SIZE(ibm_common_attrs);
 858                 pmc_attrs = classic_pmc_attrs;
 859                 break;
 860 #endif /* HAS_PPC_PMC_IBM */
 861 #ifdef HAS_PPC_PMC_G4
 862         case PPC_PMC_G4:
 863                 attrs = g4_common_attrs;
 864                 nattrs = ARRAY_SIZE(g4_common_attrs);
 865                 pmc_attrs = classic_pmc_attrs;
 866                 break;
 867 #endif /* HAS_PPC_PMC_G4 */
 868 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
 869         case PPC_PMC_PA6T:
 870                 /* PA Semi starts counting at PMC0 */
 871                 attrs = pa6t_attrs;
 872                 nattrs = ARRAY_SIZE(pa6t_attrs);
 873                 pmc_attrs = NULL;
 874                 break;
 875 #endif
 876         default:
 877                 attrs = NULL;
 878                 nattrs = 0;
 879                 pmc_attrs = NULL;
 880         }
 881
 882         for (i = 0; i < nattrs; i++)
 883                 device_create_file(s, &attrs[i]);
 884
 885         if (pmc_attrs)
 886                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 887                         device_create_file(s, &pmc_attrs[i]);
 888
 889 #ifdef CONFIG_PPC64
 890 #ifdef  CONFIG_PMU_SYSFS
 891         if (cpu_has_feature(CPU_FTR_MMCRA))
 892                 device_create_file(s, &dev_attr_mmcra);
 893
 894         if (cpu_has_feature(CPU_FTR_ARCH_31))
 895                 device_create_file(s, &dev_attr_mmcr3);
 896 #endif /* CONFIG_PMU_SYSFS */
 897
 898         if (cpu_has_feature(CPU_FTR_PURR)) {
 899                 if (!firmware_has_feature(FW_FEATURE_LPAR))
 900                         add_write_permission_dev_attr(&dev_attr_purr);
 901                 device_create_file(s, &dev_attr_purr);
 902                 create_idle_purr_file(s);
 903         }
 904
 905         if (cpu_has_feature(CPU_FTR_SPURR)) {
 906                 device_create_file(s, &dev_attr_spurr);
 907                 create_idle_spurr_file(s);
 908         }
 909
 910         if (cpu_has_feature(CPU_FTR_DSCR))
 911                 device_create_file(s, &dev_attr_dscr);
 912
 913         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 914                 device_create_file(s, &dev_attr_pir);
 915
 916         if (cpu_has_feature(CPU_FTR_ARCH_206) &&
 917                 !firmware_has_feature(FW_FEATURE_LPAR))
 918                 device_create_file(s, &dev_attr_tscr);
 919 #endif /* CONFIG_PPC64 */
 920
 921 #ifdef CONFIG_PPC_E500
 922         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 923                 device_create_file(s, &dev_attr_pw20_state);
 924                 device_create_file(s, &dev_attr_pw20_wait_time);
 925
 926                 device_create_file(s, &dev_attr_altivec_idle);
 927                 device_create_file(s, &dev_attr_altivec_idle_wait_time);
 928         }
 929 #endif
 930         cacheinfo_cpu_online(cpu);
 931         return 0;
 932 }
 933
 934 #ifdef CONFIG_HOTPLUG_CPU
 935 static int unregister_cpu_online(unsigned int cpu)
 936 {
 937         struct cpu *c = &per_cpu(cpu_devices, cpu);
 938         struct device *s = &c->dev;
 939         struct device_attribute *attrs, *pmc_attrs;
 940         int i, nattrs;
 941
 942         if (WARN_RATELIMIT(!c->hotpluggable, "cpu %d can't be offlined\n", cpu))
 943                 return -EBUSY;
 944
 945 #ifdef CONFIG_PPC64
 946         if (cpu_has_feature(CPU_FTR_SMT))
 947                 device_remove_file(s, &dev_attr_smt_snooze_delay);
 948 #endif
 949
 950         /* PMC stuff */
 951         switch (cur_cpu_spec->pmc_type) {
 952 #ifdef HAS_PPC_PMC_IBM
 953         case PPC_PMC_IBM:
 954                 attrs = ibm_common_attrs;
 955                 nattrs = ARRAY_SIZE(ibm_common_attrs);
 956                 pmc_attrs = classic_pmc_attrs;
 957                 break;
 958 #endif /* HAS_PPC_PMC_IBM */
 959 #ifdef HAS_PPC_PMC_G4
 960         case PPC_PMC_G4:
 961                 attrs = g4_common_attrs;
 962                 nattrs = ARRAY_SIZE(g4_common_attrs);
 963                 pmc_attrs = classic_pmc_attrs;
 964                 break;
 965 #endif /* HAS_PPC_PMC_G4 */
 966 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
 967         case PPC_PMC_PA6T:
 968                 /* PA Semi starts counting at PMC0 */
 969                 attrs = pa6t_attrs;
 970                 nattrs = ARRAY_SIZE(pa6t_attrs);
 971                 pmc_attrs = NULL;
 972                 break;
 973 #endif
 974         default:
 975                 attrs = NULL;
 976                 nattrs = 0;
 977                 pmc_attrs = NULL;
 978         }
 979
 980         for (i = 0; i < nattrs; i++)
 981                 device_remove_file(s, &attrs[i]);
 982
 983         if (pmc_attrs)
 984                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 985                         device_remove_file(s, &pmc_attrs[i]);
 986
 987 #ifdef CONFIG_PPC64
 988 #ifdef CONFIG_PMU_SYSFS
 989         if (cpu_has_feature(CPU_FTR_MMCRA))
 990                 device_remove_file(s, &dev_attr_mmcra);
 991
 992         if (cpu_has_feature(CPU_FTR_ARCH_31))
 993                 device_remove_file(s, &dev_attr_mmcr3);
 994 #endif /* CONFIG_PMU_SYSFS */
 995
 996         if (cpu_has_feature(CPU_FTR_PURR)) {
 997                 device_remove_file(s, &dev_attr_purr);
 998                 remove_idle_purr_file(s);
 999         }
1000
1001         if (cpu_has_feature(CPU_FTR_SPURR)) {
1002                 device_remove_file(s, &dev_attr_spurr);
1003                 remove_idle_spurr_file(s);
1004         }
1005
1006         if (cpu_has_feature(CPU_FTR_DSCR))
1007                 device_remove_file(s, &dev_attr_dscr);
1008
1009         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
1010                 device_remove_file(s, &dev_attr_pir);
1011
1012         if (cpu_has_feature(CPU_FTR_ARCH_206) &&
1013                 !firmware_has_feature(FW_FEATURE_LPAR))
1014                 device_remove_file(s, &dev_attr_tscr);
1015 #endif /* CONFIG_PPC64 */
1016
1017 #ifdef CONFIG_PPC_E500
1018         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
1019                 device_remove_file(s, &dev_attr_pw20_state);
1020                 device_remove_file(s, &dev_attr_pw20_wait_time);
1021
1022                 device_remove_file(s, &dev_attr_altivec_idle);
1023                 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
1024         }
1025 #endif
1026         cacheinfo_cpu_offline(cpu);
1027         of_node_put(s->of_node);
1028         s->of_node = NULL;
1029         return 0;
1030 }
1031 #else /* !CONFIG_HOTPLUG_CPU */
1032 #define unregister_cpu_online NULL
1033 #endif
1034
1035 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
1036 ssize_t arch_cpu_probe(const char *buf, size_t count)
1037 {
1038         if (ppc_md.cpu_probe)
1039                 return ppc_md.cpu_probe(buf, count);
1040
1041         return -EINVAL;
1042 }
1043
1044 ssize_t arch_cpu_release(const char *buf, size_t count)
1045 {
1046         if (ppc_md.cpu_release)
1047                 return ppc_md.cpu_release(buf, count);
1048
1049         return -EINVAL;
1050 }
1051 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
1052
1053 static DEFINE_MUTEX(cpu_mutex);
1054
1055 int cpu_add_dev_attr(struct device_attribute *attr)
1056 {
1057         int cpu;
1058
1059         mutex_lock(&cpu_mutex);
1060
1061         for_each_possible_cpu(cpu) {
1062                 device_create_file(get_cpu_device(cpu), attr);
1063         }
1064
1065         mutex_unlock(&cpu_mutex);
1066         return 0;
1067 }
1068 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
1069
1070 int cpu_add_dev_attr_group(struct attribute_group *attrs)
1071 {
1072         int cpu;
1073         struct device *dev;
1074         int ret;
1075
1076         mutex_lock(&cpu_mutex);
1077
1078         for_each_possible_cpu(cpu) {
1079                 dev = get_cpu_device(cpu);
1080                 ret = sysfs_create_group(&dev->kobj, attrs);
1081                 WARN_ON(ret != 0);
1082         }
1083
1084         mutex_unlock(&cpu_mutex);
1085         return 0;
1086 }
1087 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
1088
1089
1090 void cpu_remove_dev_attr(struct device_attribute *attr)
1091 {
1092         int cpu;
1093
1094         mutex_lock(&cpu_mutex);
1095
1096         for_each_possible_cpu(cpu) {
1097                 device_remove_file(get_cpu_device(cpu), attr);
1098         }
1099
1100         mutex_unlock(&cpu_mutex);
1101 }
1102 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
1103
1104 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
1105 {
1106         int cpu;
1107         struct device *dev;
1108
1109         mutex_lock(&cpu_mutex);
1110
1111         for_each_possible_cpu(cpu) {
1112                 dev = get_cpu_device(cpu);
1113                 sysfs_remove_group(&dev->kobj, attrs);
1114         }
1115
1116         mutex_unlock(&cpu_mutex);
1117 }
1118 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
1119
1120
1121 /* NUMA stuff */
1122
1123 #ifdef CONFIG_NUMA
1124 int sysfs_add_device_to_node(struct device *dev, int nid)
1125 {
1126         struct node *node = node_devices[nid];
1127         return sysfs_create_link(&node->dev.kobj, &dev->kobj,
1128                         kobject_name(&dev->kobj));
1129 }
1130 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1131
1132 void sysfs_remove_device_from_node(struct device *dev, int nid)
1133 {
1134         struct node *node = node_devices[nid];
1135         sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1136 }
1137 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1138 #endif
1139
1140 /* Only valid if CPU is present. */
1141 static ssize_t show_physical_id(struct device *dev,
1142                                 struct device_attribute *attr, char *buf)
1143 {
1144         struct cpu *cpu = container_of(dev, struct cpu, dev);
1145
1146         return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1147 }
1148 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1149
1150 static int __init topology_init(void)
1151 {
1152         int cpu, r;
1153
1154         for_each_possible_cpu(cpu) {
1155                 struct cpu *c = &per_cpu(cpu_devices, cpu);
1156
1157 #ifdef CONFIG_HOTPLUG_CPU
1158                 /*
1159                  * For now, we just see if the system supports making
1160                  * the RTAS calls for CPU hotplug.  But, there may be a
1161                  * more comprehensive way to do this for an individual
1162                  * CPU.  For instance, the boot cpu might never be valid
1163                  * for hotplugging.
1164                  */
1165                 if (smp_ops && smp_ops->cpu_offline_self)
1166                         c->hotpluggable = 1;
1167 #endif
1168
1169                 if (cpu_online(cpu) || c->hotpluggable) {
1170                         register_cpu(c, cpu);
1171
1172                         device_create_file(&c->dev, &dev_attr_physical_id);
1173                 }
1174         }
1175         r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1176                               register_cpu_online, unregister_cpu_online);
1177         WARN_ON(r < 0);
1178 #ifdef CONFIG_PPC64
1179         sysfs_create_dscr_default();
1180 #endif /* CONFIG_PPC64 */
1181
1182         create_svm_file();
1183
1184         return 0;
1185 }
1186 subsys_initcall(topology_init);