drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "amdgpu_dm_psr.h"
  27 #include "dc.h"
  28 #include "dm_helpers.h"
  29 #include "amdgpu_dm.h"
  30 #include "modules/power/power_helpers.h"
  31
  32 static bool link_supports_psrsu(struct dc_link *link)
  33 {
  34         struct dc *dc = link->ctx->dc;
  35
  36         if (!dc->caps.dmcub_support)
  37                 return false;
  38
  39         if (dc->ctx->dce_version < DCN_VERSION_3_1)
  40                 return false;
  41
  42         if (!is_psr_su_specific_panel(link))
  43                 return false;
  44
  45         if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
  46             !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
  47                 return false;
  48
  49         if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&
  50             !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
  51                 return false;
  52
  53         return true;
  54 }
  55
  56 /*
  57  * amdgpu_dm_set_psr_caps() - set link psr capabilities
  58  * @link: link
  59  *
  60  */
  61 void amdgpu_dm_set_psr_caps(struct dc_link *link)
  62 {
  63         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
  64                 return;
  65
  66         if (link->type == dc_connection_none)
  67                 return;
  68
  69         if (link->dpcd_caps.psr_info.psr_version == 0) {
  70                 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
  71                 link->psr_settings.psr_feature_enabled = false;
  72
  73         } else {
  74                 if (link_supports_psrsu(link))
  75                         link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
  76                 else
  77                         link->psr_settings.psr_version = DC_PSR_VERSION_1;
  78
  79                 link->psr_settings.psr_feature_enabled = true;
  80         }
  81
  82         DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d\n",
  83                 link->psr_settings.psr_feature_enabled,
  84                 link->psr_settings.psr_version,
  85                 link->dpcd_caps.psr_info.psr_version);
  86
  87 }
  88
  89 /*
  90  * amdgpu_dm_link_setup_psr() - configure psr link
  91  * @stream: stream state
  92  *
  93  * Return: true if success
  94  */
  95 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
  96 {
  97         struct dc_link *link = NULL;
  98         struct psr_config psr_config = {0};
  99         struct psr_context psr_context = {0};
 100         bool ret = false;
 101
 102         if (stream == NULL)
 103                 return false;
 104
 105         link = stream->link;
 106
 107         if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
 108                 psr_config.psr_version = link->psr_settings.psr_version;
 109                 psr_config.psr_frame_capture_indication_req = 0;
 110                 psr_config.psr_rfb_setup_time = 0x37;
 111                 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
 112                 psr_config.allow_smu_optimizations = 0x0;
 113
 114                 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
 115
 116         }
 117         DRM_DEBUG_DRIVER("PSR link: %d\n",      link->psr_settings.psr_feature_enabled);
 118
 119         return ret;
 120 }
 121
 122 /*
 123  * amdgpu_dm_psr_enable() - enable psr f/w
 124  * @stream: stream state
 125  *
 126  * Return: true if success
 127  */
 128 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
 129 {
 130         struct dc_link *link = stream->link;
 131         unsigned int vsync_rate_hz = 0;
 132         struct dc_static_screen_params params = {0};
 133         /* Calculate number of static frames before generating interrupt to
 134          * enter PSR.
 135          */
 136         // Init fail safe of 2 frames static
 137         unsigned int num_frames_static = 2;
 138         unsigned int power_opt = 0;
 139         bool psr_enable = true;
 140
 141         DRM_DEBUG_DRIVER("Enabling psr...\n");
 142
 143         vsync_rate_hz = div64_u64(div64_u64((
 144                         stream->timing.pix_clk_100hz * 100),
 145                         stream->timing.v_total),
 146                         stream->timing.h_total);
 147
 148         /* Round up
 149          * Calculate number of frames such that at least 30 ms of time has
 150          * passed.
 151          */
 152         if (vsync_rate_hz != 0) {
 153                 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
 154                 num_frames_static = (30000 / frame_time_microsec) + 1;
 155         }
 156
 157         params.triggers.cursor_update = true;
 158         params.triggers.overlay_update = true;
 159         params.triggers.surface_update = true;
 160         params.num_frames = num_frames_static;
 161
 162         dc_stream_set_static_screen_params(link->ctx->dc,
 163                                            &stream, 1,
 164                                            &params);
 165
 166         power_opt |= psr_power_opt_z10_static_screen;
 167
 168         return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
 169 }
 170
 171 /*
 172  * amdgpu_dm_psr_disable() - disable psr f/w
 173  * @stream:  stream state
 174  *
 175  * Return: true if success
 176  */
 177 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
 178 {
 179         unsigned int power_opt = 0;
 180         bool psr_enable = false;
 181
 182         DRM_DEBUG_DRIVER("Disabling psr...\n");
 183
 184         return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);
 185 }
 186
 187 /*
 188  * amdgpu_dm_psr_disable() - disable psr f/w
 189  * if psr is enabled on any stream
 190  *
 191  * Return: true if success
 192  */
 193 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
 194 {
 195         DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
 196         return dc_set_psr_allow_active(dm->dc, false);
 197 }
 198