drivers/gpu/drm/i915/display/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <[email protected]>
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_mipi_dsi.h>
  32
  33 #include "i915_drv.h"
  34 #include "intel_atomic.h"
  35 #include "intel_backlight.h"
  36 #include "intel_connector.h"
  37 #include "intel_crtc.h"
  38 #include "intel_de.h"
  39 #include "intel_display_types.h"
  40 #include "intel_dsi.h"
  41 #include "intel_dsi_vbt.h"
  42 #include "intel_fifo_underrun.h"
  43 #include "intel_panel.h"
  44 #include "skl_scaler.h"
  45 #include "vlv_dsi.h"
  46 #include "vlv_dsi_pll.h"
  47 #include "vlv_dsi_regs.h"
  48 #include "vlv_sideband.h"
  49
  50 /* return pixels in terms of txbyteclkhs */
  51 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  52                        u16 burst_mode_ratio)
  53 {
  54         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  55                                          8 * 100), lane_count);
  56 }
  57
  58 /* return pixels equvalent to txbyteclkhs */
  59 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  60                         u16 burst_mode_ratio)
  61 {
  62         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  63                                                 (bpp * burst_mode_ratio));
  64 }
  65
  66 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  67 {
  68         /* It just so happens the VBT matches register contents. */
  69         switch (fmt) {
  70         case VID_MODE_FORMAT_RGB888:
  71                 return MIPI_DSI_FMT_RGB888;
  72         case VID_MODE_FORMAT_RGB666:
  73                 return MIPI_DSI_FMT_RGB666;
  74         case VID_MODE_FORMAT_RGB666_PACKED:
  75                 return MIPI_DSI_FMT_RGB666_PACKED;
  76         case VID_MODE_FORMAT_RGB565:
  77                 return MIPI_DSI_FMT_RGB565;
  78         default:
  79                 MISSING_CASE(fmt);
  80                 return MIPI_DSI_FMT_RGB666;
  81         }
  82 }
  83
  84 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  85 {
  86         struct drm_encoder *encoder = &intel_dsi->base.base;
  87         struct drm_device *dev = encoder->dev;
  88         struct drm_i915_private *dev_priv = to_i915(dev);
  89         u32 mask;
  90
  91         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  92                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  93
  94         if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
  95                                   mask, 100))
  96                 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
  97 }
  98
  99 static void write_data(struct drm_i915_private *dev_priv,
 100                        i915_reg_t reg,
 101                        const u8 *data, u32 len)
 102 {
 103         u32 i, j;
 104
 105         for (i = 0; i < len; i += 4) {
 106                 u32 val = 0;
 107
 108                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 109                         val |= *data++ << 8 * j;
 110
 111                 intel_de_write(dev_priv, reg, val);
 112         }
 113 }
 114
 115 static void read_data(struct drm_i915_private *dev_priv,
 116                       i915_reg_t reg,
 117                       u8 *data, u32 len)
 118 {
 119         u32 i, j;
 120
 121         for (i = 0; i < len; i += 4) {
 122                 u32 val = intel_de_read(dev_priv, reg);
 123
 124                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 125                         *data++ = val >> 8 * j;
 126         }
 127 }
 128
 129 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 130                                        const struct mipi_dsi_msg *msg)
 131 {
 132         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 133         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 134         struct drm_i915_private *dev_priv = to_i915(dev);
 135         enum port port = intel_dsi_host->port;
 136         struct mipi_dsi_packet packet;
 137         ssize_t ret;
 138         const u8 *header, *data;
 139         i915_reg_t data_reg, ctrl_reg;
 140         u32 data_mask, ctrl_mask;
 141
 142         ret = mipi_dsi_create_packet(&packet, msg);
 143         if (ret < 0)
 144                 return ret;
 145
 146         header = packet.header;
 147         data = packet.payload;
 148
 149         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 150                 data_reg = MIPI_LP_GEN_DATA(port);
 151                 data_mask = LP_DATA_FIFO_FULL;
 152                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 153                 ctrl_mask = LP_CTRL_FIFO_FULL;
 154         } else {
 155                 data_reg = MIPI_HS_GEN_DATA(port);
 156                 data_mask = HS_DATA_FIFO_FULL;
 157                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 158                 ctrl_mask = HS_CTRL_FIFO_FULL;
 159         }
 160
 161         /* note: this is never true for reads */
 162         if (packet.payload_length) {
 163                 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 164                                             data_mask, 50))
 165                         drm_err(&dev_priv->drm,
 166                                 "Timeout waiting for HS/LP DATA FIFO !full\n");
 167
 168                 write_data(dev_priv, data_reg, packet.payload,
 169                            packet.payload_length);
 170         }
 171
 172         if (msg->rx_len) {
 173                 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
 174                                GEN_READ_DATA_AVAIL);
 175         }
 176
 177         if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 178                                     ctrl_mask, 50)) {
 179                 drm_err(&dev_priv->drm,
 180                         "Timeout waiting for HS/LP CTRL FIFO !full\n");
 181         }
 182
 183         intel_de_write(dev_priv, ctrl_reg,
 184                        header[2] << 16 | header[1] << 8 | header[0]);
 185
 186         /* ->rx_len is set only for reads */
 187         if (msg->rx_len) {
 188                 data_mask = GEN_READ_DATA_AVAIL;
 189                 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
 190                                           data_mask, 50))
 191                         drm_err(&dev_priv->drm,
 192                                 "Timeout waiting for read data.\n");
 193
 194                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 195         }
 196
 197         /* XXX: fix for reads and writes */
 198         return 4 + packet.payload_length;
 199 }
 200
 201 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 202                                  struct mipi_dsi_device *dsi)
 203 {
 204         return 0;
 205 }
 206
 207 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 208                                  struct mipi_dsi_device *dsi)
 209 {
 210         return 0;
 211 }
 212
 213 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 214         .attach = intel_dsi_host_attach,
 215         .detach = intel_dsi_host_detach,
 216         .transfer = intel_dsi_host_transfer,
 217 };
 218
 219 /*
 220  * send a video mode command
 221  *
 222  * XXX: commands with data in MIPI_DPI_DATA?
 223  */
 224 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 225                         enum port port)
 226 {
 227         struct drm_encoder *encoder = &intel_dsi->base.base;
 228         struct drm_device *dev = encoder->dev;
 229         struct drm_i915_private *dev_priv = to_i915(dev);
 230         u32 mask;
 231
 232         /* XXX: pipe, hs */
 233         if (hs)
 234                 cmd &= ~DPI_LP_MODE;
 235         else
 236                 cmd |= DPI_LP_MODE;
 237
 238         /* clear bit */
 239         intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 240
 241         /* XXX: old code skips write if control unchanged */
 242         if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
 243                 drm_dbg_kms(&dev_priv->drm,
 244                             "Same special packet %02x twice in a row.\n", cmd);
 245
 246         intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
 247
 248         mask = SPL_PKT_SENT_INTERRUPT;
 249         if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
 250                 drm_err(&dev_priv->drm,
 251                         "Video mode command 0x%08x send failed.\n", cmd);
 252
 253         return 0;
 254 }
 255
 256 static void band_gap_reset(struct drm_i915_private *dev_priv)
 257 {
 258         vlv_flisdsi_get(dev_priv);
 259
 260         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 261         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 262         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 263         udelay(150);
 264         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 265         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 266
 267         vlv_flisdsi_put(dev_priv);
 268 }
 269
 270 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 271                                     struct intel_crtc_state *pipe_config,
 272                                     struct drm_connector_state *conn_state)
 273 {
 274         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 275         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 276                                                    base);
 277         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 278         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 279         int ret;
 280
 281         drm_dbg_kms(&dev_priv->drm, "\n");
 282         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 283
 284         ret = intel_panel_compute_config(intel_connector, adjusted_mode);
 285         if (ret)
 286                 return ret;
 287
 288         ret = intel_panel_fitting(pipe_config, conn_state);
 289         if (ret)
 290                 return ret;
 291
 292         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 293                 return -EINVAL;
 294
 295         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 296         adjusted_mode->flags = 0;
 297
 298         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 299                 pipe_config->pipe_bpp = 24;
 300         else
 301                 pipe_config->pipe_bpp = 18;
 302
 303         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 304                 /* Enable Frame time stamp based scanline reporting */
 305                 pipe_config->mode_flags |=
 306                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 307
 308                 /* Dual link goes to DSI transcoder A. */
 309                 if (intel_dsi->ports == BIT(PORT_C))
 310                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 311                 else
 312                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 313
 314                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 315                 if (ret)
 316                         return -EINVAL;
 317         } else {
 318                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 319                 if (ret)
 320                         return -EINVAL;
 321         }
 322
 323         pipe_config->clock_set = true;
 324
 325         return 0;
 326 }
 327
 328 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 329 {
 330         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 331         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 332         enum port port;
 333         u32 tmp;
 334         bool cold_boot = false;
 335
 336         /* Set the MIPI mode
 337          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 338          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 339          */
 340         for_each_dsi_port(port, intel_dsi->ports) {
 341                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 342                 intel_de_write(dev_priv, MIPI_CTRL(port),
 343                                tmp | GLK_MIPIIO_ENABLE);
 344         }
 345
 346         /* Put the IO into reset */
 347         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 348         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 349         intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
 350
 351         /* Program LP Wake */
 352         for_each_dsi_port(port, intel_dsi->ports) {
 353                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 354                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
 355                         tmp &= ~GLK_LP_WAKE;
 356                 else
 357                         tmp |= GLK_LP_WAKE;
 358                 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
 359         }
 360
 361         /* Wait for Pwr ACK */
 362         for_each_dsi_port(port, intel_dsi->ports) {
 363                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 364                                           GLK_MIPIIO_PORT_POWERED, 20))
 365                         drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
 366         }
 367
 368         /* Check for cold boot scenario */
 369         for_each_dsi_port(port, intel_dsi->ports) {
 370                 cold_boot |=
 371                         !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
 372         }
 373
 374         return cold_boot;
 375 }
 376
 377 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 378 {
 379         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 380         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 381         enum port port;
 382         u32 val;
 383
 384         /* Wait for MIPI PHY status bit to set */
 385         for_each_dsi_port(port, intel_dsi->ports) {
 386                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 387                                           GLK_PHY_STATUS_PORT_READY, 20))
 388                         drm_err(&dev_priv->drm, "PHY is not ON\n");
 389         }
 390
 391         /* Get IO out of reset */
 392         val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 393         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
 394                        val | GLK_MIPIIO_RESET_RELEASED);
 395
 396         /* Get IO out of Low power state*/
 397         for_each_dsi_port(port, intel_dsi->ports) {
 398                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 399                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 400                         val &= ~ULPS_STATE_MASK;
 401                         val |= DEVICE_READY;
 402                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 403                         usleep_range(10, 15);
 404                 } else {
 405                         /* Enter ULPS */
 406                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 407                         val &= ~ULPS_STATE_MASK;
 408                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 409                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 410
 411                         /* Wait for ULPS active */
 412                         if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 413                                                     GLK_ULPS_NOT_ACTIVE, 20))
 414                                 drm_err(&dev_priv->drm, "ULPS not active\n");
 415
 416                         /* Exit ULPS */
 417                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 418                         val &= ~ULPS_STATE_MASK;
 419                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 420                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 421
 422                         /* Enter Normal Mode */
 423                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 424                         val &= ~ULPS_STATE_MASK;
 425                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 426                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 427
 428                         val = intel_de_read(dev_priv, MIPI_CTRL(port));
 429                         val &= ~GLK_LP_WAKE;
 430                         intel_de_write(dev_priv, MIPI_CTRL(port), val);
 431                 }
 432         }
 433
 434         /* Wait for Stop state */
 435         for_each_dsi_port(port, intel_dsi->ports) {
 436                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 437                                           GLK_DATA_LANE_STOP_STATE, 20))
 438                         drm_err(&dev_priv->drm,
 439                                 "Date lane not in STOP state\n");
 440         }
 441
 442         /* Wait for AFE LATCH */
 443         for_each_dsi_port(port, intel_dsi->ports) {
 444                 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
 445                                           AFE_LATCHOUT, 20))
 446                         drm_err(&dev_priv->drm,
 447                                 "D-PHY not entering LP-11 state\n");
 448         }
 449 }
 450
 451 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 452 {
 453         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 454         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 455         enum port port;
 456         u32 val;
 457
 458         drm_dbg_kms(&dev_priv->drm, "\n");
 459
 460         /* Enable MIPI PHY transparent latch */
 461         for_each_dsi_port(port, intel_dsi->ports) {
 462                 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
 463                 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port),
 464                                val | LP_OUTPUT_HOLD);
 465                 usleep_range(2000, 2500);
 466         }
 467
 468         /* Clear ULPS and set device ready */
 469         for_each_dsi_port(port, intel_dsi->ports) {
 470                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 471                 val &= ~ULPS_STATE_MASK;
 472                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 473                 usleep_range(2000, 2500);
 474                 val |= DEVICE_READY;
 475                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 476         }
 477 }
 478
 479 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 480 {
 481         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 482         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 483         enum port port;
 484         u32 val;
 485
 486         drm_dbg_kms(&dev_priv->drm, "\n");
 487
 488         vlv_flisdsi_get(dev_priv);
 489         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 490          * needed everytime after power gate */
 491         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 492         vlv_flisdsi_put(dev_priv);
 493
 494         /* bandgap reset is needed after everytime we do power gate */
 495         band_gap_reset(dev_priv);
 496
 497         for_each_dsi_port(port, intel_dsi->ports) {
 498
 499                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 500                                ULPS_STATE_ENTER);
 501                 usleep_range(2500, 3000);
 502
 503                 /* Enable MIPI PHY transparent latch
 504                  * Common bit for both MIPI Port A & MIPI Port C
 505                  * No similar bit in MIPI Port C reg
 506                  */
 507                 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A));
 508                 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A),
 509                                val | LP_OUTPUT_HOLD);
 510                 usleep_range(1000, 1500);
 511
 512                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 513                                ULPS_STATE_EXIT);
 514                 usleep_range(2500, 3000);
 515
 516                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 517                                DEVICE_READY);
 518                 usleep_range(2500, 3000);
 519         }
 520 }
 521
 522 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 523 {
 524         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 525
 526         if (IS_GEMINILAKE(dev_priv))
 527                 glk_dsi_device_ready(encoder);
 528         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 529                 bxt_dsi_device_ready(encoder);
 530         else
 531                 vlv_dsi_device_ready(encoder);
 532 }
 533
 534 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 535 {
 536         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 537         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 538         enum port port;
 539         u32 val;
 540
 541         /* Enter ULPS */
 542         for_each_dsi_port(port, intel_dsi->ports) {
 543                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 544                 val &= ~ULPS_STATE_MASK;
 545                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 546                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 547         }
 548
 549         /* Wait for MIPI PHY status bit to unset */
 550         for_each_dsi_port(port, intel_dsi->ports) {
 551                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 552                                             GLK_PHY_STATUS_PORT_READY, 20))
 553                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 554         }
 555
 556         /* Wait for Pwr ACK bit to unset */
 557         for_each_dsi_port(port, intel_dsi->ports) {
 558                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 559                                             GLK_MIPIIO_PORT_POWERED, 20))
 560                         drm_err(&dev_priv->drm,
 561                                 "MIPI IO Port is not powergated\n");
 562         }
 563 }
 564
 565 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 566 {
 567         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 568         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 569         enum port port;
 570         u32 tmp;
 571
 572         /* Put the IO into reset */
 573         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 574         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 575         intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
 576
 577         /* Wait for MIPI PHY status bit to unset */
 578         for_each_dsi_port(port, intel_dsi->ports) {
 579                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 580                                             GLK_PHY_STATUS_PORT_READY, 20))
 581                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 582         }
 583
 584         /* Clear MIPI mode */
 585         for_each_dsi_port(port, intel_dsi->ports) {
 586                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 587                 tmp &= ~GLK_MIPIIO_ENABLE;
 588                 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
 589         }
 590 }
 591
 592 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 593 {
 594         glk_dsi_enter_low_power_mode(encoder);
 595         glk_dsi_disable_mipi_io(encoder);
 596 }
 597
 598 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 599 {
 600         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 601         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 602         enum port port;
 603
 604         drm_dbg_kms(&dev_priv->drm, "\n");
 605         for_each_dsi_port(port, intel_dsi->ports) {
 606                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 607                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 608                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 609                 u32 val;
 610
 611                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 612                                DEVICE_READY | ULPS_STATE_ENTER);
 613                 usleep_range(2000, 2500);
 614
 615                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 616                                DEVICE_READY | ULPS_STATE_EXIT);
 617                 usleep_range(2000, 2500);
 618
 619                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 620                                DEVICE_READY | ULPS_STATE_ENTER);
 621                 usleep_range(2000, 2500);
 622
 623                 /*
 624                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 625                  * Port A only. MIPI Port C has no similar bit for checking.
 626                  */
 627                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
 628                     intel_de_wait_for_clear(dev_priv, port_ctrl,
 629                                             AFE_LATCHOUT, 30))
 630                         drm_err(&dev_priv->drm, "DSI LP not going Low\n");
 631
 632                 /* Disable MIPI PHY transparent latch */
 633                 val = intel_de_read(dev_priv, port_ctrl);
 634                 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD);
 635                 usleep_range(1000, 1500);
 636
 637                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
 638                 usleep_range(2000, 2500);
 639         }
 640 }
 641
 642 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 643                                   const struct intel_crtc_state *crtc_state)
 644 {
 645         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 646         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 647         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 648         enum port port;
 649
 650         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 651                 u32 temp;
 652                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 653                         for_each_dsi_port(port, intel_dsi->ports) {
 654                                 temp = intel_de_read(dev_priv,
 655                                                      MIPI_CTRL(port));
 656                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 657                                         intel_dsi->pixel_overlap <<
 658                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 659                                 intel_de_write(dev_priv, MIPI_CTRL(port),
 660                                                temp);
 661                         }
 662                 } else {
 663                         temp = intel_de_read(dev_priv, VLV_CHICKEN_3);
 664                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 665                                         intel_dsi->pixel_overlap <<
 666                                         PIXEL_OVERLAP_CNT_SHIFT;
 667                         intel_de_write(dev_priv, VLV_CHICKEN_3, temp);
 668                 }
 669         }
 670
 671         for_each_dsi_port(port, intel_dsi->ports) {
 672                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 673                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 674                 u32 temp;
 675
 676                 temp = intel_de_read(dev_priv, port_ctrl);
 677
 678                 temp &= ~LANE_CONFIGURATION_MASK;
 679                 temp &= ~DUAL_LINK_MODE_MASK;
 680
 681                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 682                         temp |= (intel_dsi->dual_link - 1)
 683                                                 << DUAL_LINK_MODE_SHIFT;
 684                         if (IS_BROXTON(dev_priv))
 685                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 686                         else
 687                                 temp |= crtc->pipe ?
 688                                         LANE_CONFIGURATION_DUAL_LINK_B :
 689                                         LANE_CONFIGURATION_DUAL_LINK_A;
 690                 }
 691
 692                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 693                         temp |= DITHERING_ENABLE;
 694
 695                 /* assert ip_tg_enable signal */
 696                 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
 697                 intel_de_posting_read(dev_priv, port_ctrl);
 698         }
 699 }
 700
 701 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 702 {
 703         struct drm_device *dev = encoder->base.dev;
 704         struct drm_i915_private *dev_priv = to_i915(dev);
 705         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 706         enum port port;
 707
 708         for_each_dsi_port(port, intel_dsi->ports) {
 709                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 710                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 711                 u32 temp;
 712
 713                 /* de-assert ip_tg_enable signal */
 714                 temp = intel_de_read(dev_priv, port_ctrl);
 715                 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE);
 716                 intel_de_posting_read(dev_priv, port_ctrl);
 717         }
 718 }
 719
 720 static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
 721 {
 722         ktime_t panel_power_on_time;
 723         s64 panel_power_off_duration;
 724
 725         panel_power_on_time = ktime_get_boottime();
 726         panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
 727                                                   intel_dsi->panel_power_off_time);
 728
 729         if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
 730                 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration);
 731 }
 732
 733 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 734                               const struct intel_crtc_state *pipe_config);
 735 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 736
 737 /*
 738  * Panel enable/disable sequences from the VBT spec.
 739  *
 740  * Note the spec has AssertReset / DeassertReset swapped from their
 741  * usual naming. We use the normal names to avoid confusion (so below
 742  * they are swapped compared to the spec).
 743  *
 744  * Steps starting with MIPI refer to VBT sequences, note that for v2
 745  * VBTs several steps which have a VBT in v2 are expected to be handled
 746  * directly by the driver, by directly driving gpios for example.
 747  *
 748  * v2 video mode seq         v3 video mode seq         command mode seq
 749  * - power on                - MIPIPanelPowerOn        - power on
 750  * - wait t1+t2                                        - wait t1+t2
 751  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 752  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 753  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 754  *                                                     - MIPITearOn
 755  *                                                     - MIPIDisplayOn
 756  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 757  * - MIPIDisplayOn           - MIPIDisplayOn
 758  * - wait t5                                           - wait t5
 759  * - backlight on            - MIPIBacklightOn         - backlight on
 760  * ...                       ...                       ... issue mem cmds ...
 761  * - backlight off           - MIPIBacklightOff        - backlight off
 762  * - wait t6                                           - wait t6
 763  * - MIPIDisplayOff
 764  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 765  *                                                     - MIPITearOff
 766  *                           - MIPIDisplayOff          - MIPIDisplayOff
 767  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 768  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 769  * - wait t3                                           - wait t3
 770  * - power off               - MIPIPanelPowerOff       - power off
 771  * - wait t4                                           - wait t4
 772  */
 773
 774 /*
 775  * DSI port enable has to be done before pipe and plane enable, so we do it in
 776  * the pre_enable hook instead of the enable hook.
 777  */
 778 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 779                                  struct intel_encoder *encoder,
 780                                  const struct intel_crtc_state *pipe_config,
 781                                  const struct drm_connector_state *conn_state)
 782 {
 783         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 784         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 785         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 786         enum pipe pipe = crtc->pipe;
 787         enum port port;
 788         u32 val;
 789         bool glk_cold_boot = false;
 790
 791         drm_dbg_kms(&dev_priv->drm, "\n");
 792
 793         intel_dsi_wait_panel_power_cycle(intel_dsi);
 794
 795         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 796
 797         /*
 798          * The BIOS may leave the PLL in a wonky state where it doesn't
 799          * lock. It needs to be fully powered down to fix it.
 800          */
 801         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 802                 bxt_dsi_pll_disable(encoder);
 803                 bxt_dsi_pll_enable(encoder, pipe_config);
 804         } else {
 805                 vlv_dsi_pll_disable(encoder);
 806                 vlv_dsi_pll_enable(encoder, pipe_config);
 807         }
 808
 809         if (IS_BROXTON(dev_priv)) {
 810                 /* Add MIPI IO reset programming for modeset */
 811                 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
 812                 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
 813                                val | MIPIO_RST_CTRL);
 814
 815                 /* Power up DSI regulator */
 816                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 817                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 818         }
 819
 820         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 821                 u32 val;
 822
 823                 /* Disable DPOunit clock gating, can stall pipe */
 824                 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
 825                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 826                 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 827         }
 828
 829         if (!IS_GEMINILAKE(dev_priv))
 830                 intel_dsi_prepare(encoder, pipe_config);
 831
 832         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 833
 834         /*
 835          * Give the panel time to power-on and then deassert its reset.
 836          * Depending on the VBT MIPI sequences version the deassert-seq
 837          * may contain the necessary delay, intel_dsi_msleep() will skip
 838          * the delay in that case. If there is no deassert-seq, then an
 839          * unconditional msleep is used to give the panel time to power-on.
 840          */
 841         if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
 842                 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 843                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 844         } else {
 845                 msleep(intel_dsi->panel_on_delay);
 846         }
 847
 848         if (IS_GEMINILAKE(dev_priv)) {
 849                 glk_cold_boot = glk_dsi_enable_io(encoder);
 850
 851                 /* Prepare port in cold boot(s3/s4) scenario */
 852                 if (glk_cold_boot)
 853                         intel_dsi_prepare(encoder, pipe_config);
 854         }
 855
 856         /* Put device in ready state (LP-11) */
 857         intel_dsi_device_ready(encoder);
 858
 859         /* Prepare port in normal boot scenario */
 860         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 861                 intel_dsi_prepare(encoder, pipe_config);
 862
 863         /* Send initialization commands in LP mode */
 864         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 865
 866         /*
 867          * Enable port in pre-enable phase itself because as per hw team
 868          * recommendation, port should be enabled before plane & pipe
 869          */
 870         if (is_cmd_mode(intel_dsi)) {
 871                 for_each_dsi_port(port, intel_dsi->ports)
 872                         intel_de_write(dev_priv,
 873                                        MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 874                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 875                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 876         } else {
 877                 msleep(20); /* XXX */
 878                 for_each_dsi_port(port, intel_dsi->ports)
 879                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 880                 intel_dsi_msleep(intel_dsi, 100);
 881
 882                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 883
 884                 intel_dsi_port_enable(encoder, pipe_config);
 885         }
 886
 887         intel_backlight_enable(pipe_config, conn_state);
 888         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 889 }
 890
 891 static void bxt_dsi_enable(struct intel_atomic_state *state,
 892                            struct intel_encoder *encoder,
 893                            const struct intel_crtc_state *crtc_state,
 894                            const struct drm_connector_state *conn_state)
 895 {
 896         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
 897
 898         intel_crtc_vblank_on(crtc_state);
 899 }
 900
 901 /*
 902  * DSI port disable has to be done after pipe and plane disable, so we do it in
 903  * the post_disable hook.
 904  */
 905 static void intel_dsi_disable(struct intel_atomic_state *state,
 906                               struct intel_encoder *encoder,
 907                               const struct intel_crtc_state *old_crtc_state,
 908                               const struct drm_connector_state *old_conn_state)
 909 {
 910         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 911         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 912         enum port port;
 913
 914         drm_dbg_kms(&i915->drm, "\n");
 915
 916         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 917         intel_backlight_disable(old_conn_state);
 918
 919         /*
 920          * According to the spec we should send SHUTDOWN before
 921          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 922          * has shown that the v3 sequence works for v2 VBTs too
 923          */
 924         if (is_vid_mode(intel_dsi)) {
 925                 /* Send Shutdown command to the panel in LP mode */
 926                 for_each_dsi_port(port, intel_dsi->ports)
 927                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 928                 msleep(10);
 929         }
 930 }
 931
 932 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 933 {
 934         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 935
 936         if (IS_GEMINILAKE(dev_priv))
 937                 glk_dsi_clear_device_ready(encoder);
 938         else
 939                 vlv_dsi_clear_device_ready(encoder);
 940 }
 941
 942 static void intel_dsi_post_disable(struct intel_atomic_state *state,
 943                                    struct intel_encoder *encoder,
 944                                    const struct intel_crtc_state *old_crtc_state,
 945                                    const struct drm_connector_state *old_conn_state)
 946 {
 947         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 948         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 949         enum port port;
 950         u32 val;
 951
 952         drm_dbg_kms(&dev_priv->drm, "\n");
 953
 954         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 955                 intel_crtc_vblank_off(old_crtc_state);
 956
 957                 skl_scaler_disable(old_crtc_state);
 958         }
 959
 960         if (is_vid_mode(intel_dsi)) {
 961                 for_each_dsi_port(port, intel_dsi->ports)
 962                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 963
 964                 intel_dsi_port_disable(encoder);
 965                 usleep_range(2000, 5000);
 966         }
 967
 968         intel_dsi_unprepare(encoder);
 969
 970         /*
 971          * if disable packets are sent before sending shutdown packet then in
 972          * some next enable sequence send turn on packet error is observed
 973          */
 974         if (is_cmd_mode(intel_dsi))
 975                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 976         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 977
 978         /* Transition to LP-00 */
 979         intel_dsi_clear_device_ready(encoder);
 980
 981         if (IS_BROXTON(dev_priv)) {
 982                 /* Power down DSI regulator to save power */
 983                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 984                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
 985                                HS_IO_CTRL_SELECT);
 986
 987                 /* Add MIPI IO reset programming for modeset */
 988                 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
 989                 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
 990                                val & ~MIPIO_RST_CTRL);
 991         }
 992
 993         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 994                 bxt_dsi_pll_disable(encoder);
 995         } else {
 996                 u32 val;
 997
 998                 vlv_dsi_pll_disable(encoder);
 999
1000                 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
1001                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
1002                 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
1003         }
1004
1005         /* Assert reset */
1006         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1007
1008         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
1009         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1010
1011         intel_dsi->panel_power_off_time = ktime_get_boottime();
1012 }
1013
1014 static void intel_dsi_shutdown(struct intel_encoder *encoder)
1015 {
1016         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1017
1018         intel_dsi_wait_panel_power_cycle(intel_dsi);
1019 }
1020
1021 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1022                                    enum pipe *pipe)
1023 {
1024         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1025         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1026         intel_wakeref_t wakeref;
1027         enum port port;
1028         bool active = false;
1029
1030         drm_dbg_kms(&dev_priv->drm, "\n");
1031
1032         wakeref = intel_display_power_get_if_enabled(dev_priv,
1033                                                      encoder->power_domain);
1034         if (!wakeref)
1035                 return false;
1036
1037         /*
1038          * On Broxton the PLL needs to be enabled with a valid divider
1039          * configuration, otherwise accessing DSI registers will hang the
1040          * machine. See BSpec North Display Engine registers/MIPI[BXT].
1041          */
1042         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1043             !bxt_dsi_pll_is_enabled(dev_priv))
1044                 goto out_put_power;
1045
1046         /* XXX: this only works for one DSI output */
1047         for_each_dsi_port(port, intel_dsi->ports) {
1048                 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
1049                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1050                 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
1051
1052                 /*
1053                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1054                  * bit in port C control register does not get set. As a
1055                  * workaround, check pipe B conf instead.
1056                  */
1057                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1058                     port == PORT_C)
1059                         enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1060
1061                 /* Try command mode if video mode not enabled */
1062                 if (!enabled) {
1063                         u32 tmp = intel_de_read(dev_priv,
1064                                                 MIPI_DSI_FUNC_PRG(port));
1065                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1066                 }
1067
1068                 if (!enabled)
1069                         continue;
1070
1071                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
1072                         continue;
1073
1074                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1075                         u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1076                         tmp &= BXT_PIPE_SELECT_MASK;
1077                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1078
1079                         if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
1080                                 continue;
1081
1082                         *pipe = tmp;
1083                 } else {
1084                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1085                 }
1086
1087                 active = true;
1088                 break;
1089         }
1090
1091 out_put_power:
1092         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1093
1094         return active;
1095 }
1096
1097 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1098                                     struct intel_crtc_state *pipe_config)
1099 {
1100         struct drm_device *dev = encoder->base.dev;
1101         struct drm_i915_private *dev_priv = to_i915(dev);
1102         struct drm_display_mode *adjusted_mode =
1103                                         &pipe_config->hw.adjusted_mode;
1104         struct drm_display_mode *adjusted_mode_sw;
1105         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1106         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1107         unsigned int lane_count = intel_dsi->lane_count;
1108         unsigned int bpp, fmt;
1109         enum port port;
1110         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1111         u16 hfp_sw, hsync_sw, hbp_sw;
1112         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1113                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1114
1115         /* FIXME: hw readout should not depend on SW state */
1116         adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1117
1118         /*
1119          * Atleast one port is active as encoder->get_config called only if
1120          * encoder->get_hw_state() returns true.
1121          */
1122         for_each_dsi_port(port, intel_dsi->ports) {
1123                 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1124                         break;
1125         }
1126
1127         fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1128         bpp = mipi_dsi_pixel_format_to_bpp(
1129                         pixel_format_from_register_bits(fmt));
1130
1131         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1132
1133         /* Enable Frame time stamo based scanline reporting */
1134         pipe_config->mode_flags |=
1135                 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1136
1137         /* In terms of pixels */
1138         adjusted_mode->crtc_hdisplay =
1139                                 intel_de_read(dev_priv,
1140                                               BXT_MIPI_TRANS_HACTIVE(port));
1141         adjusted_mode->crtc_vdisplay =
1142                                 intel_de_read(dev_priv,
1143                                               BXT_MIPI_TRANS_VACTIVE(port));
1144         adjusted_mode->crtc_vtotal =
1145                                 intel_de_read(dev_priv,
1146                                               BXT_MIPI_TRANS_VTOTAL(port));
1147
1148         hactive = adjusted_mode->crtc_hdisplay;
1149         hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1150
1151         /*
1152          * Meaningful for video mode non-burst sync pulse mode only,
1153          * can be zero for non-burst sync events and burst modes
1154          */
1155         hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1156         hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1157
1158         /* harizontal values are in terms of high speed byte clock */
1159         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1160                                                 intel_dsi->burst_mode_ratio);
1161         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1162                                                 intel_dsi->burst_mode_ratio);
1163         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1164                                                 intel_dsi->burst_mode_ratio);
1165
1166         if (intel_dsi->dual_link) {
1167                 hfp *= 2;
1168                 hsync *= 2;
1169                 hbp *= 2;
1170         }
1171
1172         /* vertical values are in terms of lines */
1173         vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1174         vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1175         vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port));
1176
1177         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1178         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1179         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1180         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1181         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1182
1183         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1184         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1185         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1186         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1187
1188         /*
1189          * In BXT DSI there is no regs programmed with few horizontal timings
1190          * in Pixels but txbyteclkhs.. So retrieval process adds some
1191          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1192          * Actually here for the given adjusted_mode, we are calculating the
1193          * value programmed to the port and then back to the horizontal timing
1194          * param in pixels. This is the expected value, including roundup errors
1195          * And if that is same as retrieved value from port, then
1196          * (HW state) adjusted_mode's horizontal timings are corrected to
1197          * match with SW state to nullify the errors.
1198          */
1199         /* Calculating the value programmed to the Port register */
1200         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1201                                         adjusted_mode_sw->crtc_hdisplay;
1202         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1203                                         adjusted_mode_sw->crtc_hsync_start;
1204         hbp_sw = adjusted_mode_sw->crtc_htotal -
1205                                         adjusted_mode_sw->crtc_hsync_end;
1206
1207         if (intel_dsi->dual_link) {
1208                 hfp_sw /= 2;
1209                 hsync_sw /= 2;
1210                 hbp_sw /= 2;
1211         }
1212
1213         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1214                                                 intel_dsi->burst_mode_ratio);
1215         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1216                             intel_dsi->burst_mode_ratio);
1217         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1218                                                 intel_dsi->burst_mode_ratio);
1219
1220         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1221         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1222                                                 intel_dsi->burst_mode_ratio);
1223         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1224                                                 intel_dsi->burst_mode_ratio);
1225         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1226                                                 intel_dsi->burst_mode_ratio);
1227
1228         if (intel_dsi->dual_link) {
1229                 hfp_sw *= 2;
1230                 hsync_sw *= 2;
1231                 hbp_sw *= 2;
1232         }
1233
1234         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1235                                                         hsync_sw + hbp_sw;
1236         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1237         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1238         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1239         crtc_hblank_end_sw = crtc_htotal_sw;
1240
1241         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1242                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1243
1244         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1245                 adjusted_mode->crtc_hsync_start =
1246                                         adjusted_mode_sw->crtc_hsync_start;
1247
1248         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1249                 adjusted_mode->crtc_hsync_end =
1250                                         adjusted_mode_sw->crtc_hsync_end;
1251
1252         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1253                 adjusted_mode->crtc_hblank_start =
1254                                         adjusted_mode_sw->crtc_hblank_start;
1255
1256         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1257                 adjusted_mode->crtc_hblank_end =
1258                                         adjusted_mode_sw->crtc_hblank_end;
1259 }
1260
1261 static void intel_dsi_get_config(struct intel_encoder *encoder,
1262                                  struct intel_crtc_state *pipe_config)
1263 {
1264         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1265         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1266         u32 pclk;
1267
1268         drm_dbg_kms(&dev_priv->drm, "\n");
1269
1270         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1271
1272         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1273                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1274                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1275         } else {
1276                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1277         }
1278
1279         if (intel_dsi->dual_link)
1280                 pclk *= 2;
1281
1282         if (pclk) {
1283                 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1284                 pipe_config->port_clock = pclk;
1285         }
1286 }
1287
1288 /* return txclkesc cycles in terms of divider and duration in us */
1289 static u16 txclkesc(u32 divider, unsigned int us)
1290 {
1291         switch (divider) {
1292         case ESCAPE_CLOCK_DIVIDER_1:
1293         default:
1294                 return 20 * us;
1295         case ESCAPE_CLOCK_DIVIDER_2:
1296                 return 10 * us;
1297         case ESCAPE_CLOCK_DIVIDER_4:
1298                 return 5 * us;
1299         }
1300 }
1301
1302 static void set_dsi_timings(struct drm_encoder *encoder,
1303                             const struct drm_display_mode *adjusted_mode)
1304 {
1305         struct drm_device *dev = encoder->dev;
1306         struct drm_i915_private *dev_priv = to_i915(dev);
1307         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1308         enum port port;
1309         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1310         unsigned int lane_count = intel_dsi->lane_count;
1311
1312         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1313
1314         hactive = adjusted_mode->crtc_hdisplay;
1315         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1316         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1317         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1318
1319         if (intel_dsi->dual_link) {
1320                 hactive /= 2;
1321                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1322                         hactive += intel_dsi->pixel_overlap;
1323                 hfp /= 2;
1324                 hsync /= 2;
1325                 hbp /= 2;
1326         }
1327
1328         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1329         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1330         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1331
1332         /* horizontal values are in terms of high speed byte clock */
1333         hactive = txbyteclkhs(hactive, bpp, lane_count,
1334                               intel_dsi->burst_mode_ratio);
1335         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1336         hsync = txbyteclkhs(hsync, bpp, lane_count,
1337                             intel_dsi->burst_mode_ratio);
1338         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1339
1340         for_each_dsi_port(port, intel_dsi->ports) {
1341                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1342                         /*
1343                          * Program hdisplay and vdisplay on MIPI transcoder.
1344                          * This is different from calculated hactive and
1345                          * vactive, as they are calculated per channel basis,
1346                          * whereas these values should be based on resolution.
1347                          */
1348                         intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1349                                        adjusted_mode->crtc_hdisplay);
1350                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1351                                        adjusted_mode->crtc_vdisplay);
1352                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1353                                        adjusted_mode->crtc_vtotal);
1354                 }
1355
1356                 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1357                                hactive);
1358                 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1359
1360                 /* meaningful for video mode non-burst sync pulse mode only,
1361                  * can be zero for non-burst sync events and burst modes */
1362                 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1363                                hsync);
1364                 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1365
1366                 /* vertical values are in terms of lines */
1367                 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1368                 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1369                                vsync);
1370                 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1371         }
1372 }
1373
1374 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1375 {
1376         switch (fmt) {
1377         case MIPI_DSI_FMT_RGB888:
1378                 return VID_MODE_FORMAT_RGB888;
1379         case MIPI_DSI_FMT_RGB666:
1380                 return VID_MODE_FORMAT_RGB666;
1381         case MIPI_DSI_FMT_RGB666_PACKED:
1382                 return VID_MODE_FORMAT_RGB666_PACKED;
1383         case MIPI_DSI_FMT_RGB565:
1384                 return VID_MODE_FORMAT_RGB565;
1385         default:
1386                 MISSING_CASE(fmt);
1387                 return VID_MODE_FORMAT_RGB666;
1388         }
1389 }
1390
1391 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1392                               const struct intel_crtc_state *pipe_config)
1393 {
1394         struct drm_encoder *encoder = &intel_encoder->base;
1395         struct drm_device *dev = encoder->dev;
1396         struct drm_i915_private *dev_priv = to_i915(dev);
1397         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1398         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1399         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1400         enum port port;
1401         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1402         u32 val, tmp;
1403         u16 mode_hdisplay;
1404
1405         drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe));
1406
1407         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1408
1409         if (intel_dsi->dual_link) {
1410                 mode_hdisplay /= 2;
1411                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1412                         mode_hdisplay += intel_dsi->pixel_overlap;
1413         }
1414
1415         for_each_dsi_port(port, intel_dsi->ports) {
1416                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1417                         /*
1418                          * escape clock divider, 20MHz, shared for A and C.
1419                          * device ready must be off when doing this! txclkesc?
1420                          */
1421                         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1422                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1423                         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1424                                        tmp | ESCAPE_CLOCK_DIVIDER_1);
1425
1426                         /* read request priority is per pipe */
1427                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1428                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1429                         intel_de_write(dev_priv, MIPI_CTRL(port),
1430                                        tmp | READ_REQUEST_PRIORITY_HIGH);
1431                 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1432                         enum pipe pipe = crtc->pipe;
1433
1434                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1435                         tmp &= ~BXT_PIPE_SELECT_MASK;
1436
1437                         tmp |= BXT_PIPE_SELECT(pipe);
1438                         intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
1439                 }
1440
1441                 /* XXX: why here, why like this? handling in irq handler?! */
1442                 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1443                 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1444
1445                 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1446                                intel_dsi->dphy_reg);
1447
1448                 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1449                                adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1450         }
1451
1452         set_dsi_timings(encoder, adjusted_mode);
1453
1454         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1455         if (is_cmd_mode(intel_dsi)) {
1456                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1457                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1458         } else {
1459                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1460                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1461         }
1462
1463         tmp = 0;
1464         if (intel_dsi->eotp_pkt == 0)
1465                 tmp |= EOT_DISABLE;
1466         if (intel_dsi->clock_stop)
1467                 tmp |= CLOCKSTOP;
1468
1469         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1470                 tmp |= BXT_DPHY_DEFEATURE_EN;
1471                 if (!is_cmd_mode(intel_dsi))
1472                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1473         }
1474
1475         for_each_dsi_port(port, intel_dsi->ports) {
1476                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1477
1478                 /* timeouts for recovery. one frame IIUC. if counter expires,
1479                  * EOT and stop state. */
1480
1481                 /*
1482                  * In burst mode, value greater than one DPI line Time in byte
1483                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1484                  * said value is recommended.
1485                  *
1486                  * In non-burst mode, Value greater than one DPI frame time in
1487                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1488                  * said value is recommended.
1489                  *
1490                  * In DBI only mode, value greater than one DBI frame time in
1491                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1492                  * said value is recommended.
1493                  */
1494
1495                 if (is_vid_mode(intel_dsi) &&
1496                         intel_dsi->video_mode == BURST_MODE) {
1497                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1498                                        txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1499                 } else {
1500                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1501                                        txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1502                 }
1503                 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1504                                intel_dsi->lp_rx_timeout);
1505                 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1506                                intel_dsi->turn_arnd_val);
1507                 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1508                                intel_dsi->rst_timer_val);
1509
1510                 /* dphy stuff */
1511
1512                 /* in terms of low power clock */
1513                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1514                                txclkesc(intel_dsi->escape_clk_div, 100));
1515
1516                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1517                     !intel_dsi->dual_link) {
1518                         /*
1519                          * BXT spec says write MIPI_INIT_COUNT for
1520                          * both the ports, even if only one is
1521                          * getting used. So write the other port
1522                          * if not in dual link mode.
1523                          */
1524                         intel_de_write(dev_priv,
1525                                        MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1526                                        intel_dsi->init_count);
1527                 }
1528
1529                 /* recovery disables */
1530                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1531
1532                 /* in terms of low power clock */
1533                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1534                                intel_dsi->init_count);
1535
1536                 /* in terms of txbyteclkhs. actual high to low switch +
1537                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1538                  *
1539                  * XXX: write MIPI_STOP_STATE_STALL?
1540                  */
1541                 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1542                                intel_dsi->hs_to_lp_count);
1543
1544                 /* XXX: low power clock equivalence in terms of byte clock.
1545                  * the number of byte clocks occupied in one low power clock.
1546                  * based on txbyteclkhs and txclkesc.
1547                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1548                  * ) / 105.???
1549                  */
1550                 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1551                                intel_dsi->lp_byte_clk);
1552
1553                 if (IS_GEMINILAKE(dev_priv)) {
1554                         intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1555                                        intel_dsi->lp_byte_clk);
1556                         /* Shadow of DPHY reg */
1557                         intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1558                                        intel_dsi->dphy_reg);
1559                 }
1560
1561                 /* the bw essential for transmitting 16 long packets containing
1562                  * 252 bytes meant for dcs write memory command is programmed in
1563                  * this register in terms of byte clocks. based on dsi transfer
1564                  * rate and the number of lanes configured the time taken to
1565                  * transmit 16 long packets in a dsi stream varies. */
1566                 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1567                                intel_dsi->bw_timer);
1568
1569                 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1570                                intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1571
1572                 if (is_vid_mode(intel_dsi)) {
1573                         u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1574
1575                         /*
1576                          * Some panels might have resolution which is not a
1577                          * multiple of 64 like 1366 x 768. Enable RANDOM
1578                          * resolution support for such panels by default.
1579                          */
1580                         fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1581
1582                         switch (intel_dsi->video_mode) {
1583                         default:
1584                                 MISSING_CASE(intel_dsi->video_mode);
1585                                 fallthrough;
1586                         case NON_BURST_SYNC_EVENTS:
1587                                 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1588                                 break;
1589                         case NON_BURST_SYNC_PULSE:
1590                                 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1591                                 break;
1592                         case BURST_MODE:
1593                                 fmt |= VIDEO_MODE_BURST;
1594                                 break;
1595                         }
1596
1597                         intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt);
1598                 }
1599         }
1600 }
1601
1602 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1603 {
1604         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1605         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1606         enum port port;
1607         u32 val;
1608
1609         if (IS_GEMINILAKE(dev_priv))
1610                 return;
1611
1612         for_each_dsi_port(port, intel_dsi->ports) {
1613                 /* Panel commands can be sent when clock is in LP11 */
1614                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1615
1616                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1617                         bxt_dsi_reset_clocks(encoder, port);
1618                 else
1619                         vlv_dsi_reset_clocks(encoder, port);
1620                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1621
1622                 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port));
1623                 val &= ~VID_MODE_FORMAT_MASK;
1624                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1625
1626                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1627         }
1628 }
1629
1630 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1631 {
1632         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1633
1634         intel_dsi_vbt_gpio_cleanup(intel_dsi);
1635         intel_encoder_destroy(encoder);
1636 }
1637
1638 static const struct drm_encoder_funcs intel_dsi_funcs = {
1639         .destroy = intel_dsi_encoder_destroy,
1640 };
1641
1642 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1643         .get_modes = intel_dsi_get_modes,
1644         .mode_valid = intel_dsi_mode_valid,
1645         .atomic_check = intel_digital_connector_atomic_check,
1646 };
1647
1648 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1649         .detect = intel_panel_detect,
1650         .late_register = intel_connector_register,
1651         .early_unregister = intel_connector_unregister,
1652         .destroy = intel_connector_destroy,
1653         .fill_modes = drm_helper_probe_single_connector_modes,
1654         .atomic_get_property = intel_digital_connector_atomic_get_property,
1655         .atomic_set_property = intel_digital_connector_atomic_set_property,
1656         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1657         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1658 };
1659
1660 static void vlv_dsi_add_properties(struct intel_connector *connector)
1661 {
1662         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1663         const struct drm_display_mode *fixed_mode =
1664                 intel_panel_preferred_fixed_mode(connector);
1665         u32 allowed_scalers;
1666
1667         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1668         if (!HAS_GMCH(dev_priv))
1669                 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1670
1671         drm_connector_attach_scaling_mode_property(&connector->base,
1672                                                    allowed_scalers);
1673
1674         connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1675
1676         drm_connector_set_panel_orientation_with_quirk(&connector->base,
1677                                                        intel_dsi_get_panel_orientation(connector),
1678                                                        fixed_mode->hdisplay,
1679                                                        fixed_mode->vdisplay);
1680 }
1681
1682 #define NS_KHZ_RATIO            1000000
1683
1684 #define PREPARE_CNT_MAX         0x3F
1685 #define EXIT_ZERO_CNT_MAX       0x3F
1686 #define CLK_ZERO_CNT_MAX        0xFF
1687 #define TRAIL_CNT_MAX           0x1F
1688
1689 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1690 {
1691         struct drm_device *dev = intel_dsi->base.base.dev;
1692         struct drm_i915_private *dev_priv = to_i915(dev);
1693         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1694         u32 tlpx_ns, extra_byte_count, tlpx_ui;
1695         u32 ui_num, ui_den;
1696         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1697         u32 ths_prepare_ns, tclk_trail_ns;
1698         u32 tclk_prepare_clkzero, ths_prepare_hszero;
1699         u32 lp_to_hs_switch, hs_to_lp_switch;
1700         u32 mul;
1701
1702         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1703
1704         switch (intel_dsi->lane_count) {
1705         case 1:
1706         case 2:
1707                 extra_byte_count = 2;
1708                 break;
1709         case 3:
1710                 extra_byte_count = 4;
1711                 break;
1712         case 4:
1713         default:
1714                 extra_byte_count = 3;
1715                 break;
1716         }
1717
1718         /* in Kbps */
1719         ui_num = NS_KHZ_RATIO;
1720         ui_den = intel_dsi_bitrate(intel_dsi);
1721
1722         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1723         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1724
1725         /*
1726          * B060
1727          * LP byte clock = TLPX/ (8UI)
1728          */
1729         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1730
1731         /* DDR clock period = 2 * UI
1732          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1733          * UI(nsec) = 10^6 / bitrate
1734          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1735          * DDR clock count  = ns_value / DDR clock period
1736          *
1737          * For GEMINILAKE dphy_param_reg will be programmed in terms of
1738          * HS byte clock count for other platform in HS ddr clock count
1739          */
1740         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1741         ths_prepare_ns = max(mipi_config->ths_prepare,
1742                              mipi_config->tclk_prepare);
1743
1744         /* prepare count */
1745         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1746
1747         if (prepare_cnt > PREPARE_CNT_MAX) {
1748                 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1749                             prepare_cnt);
1750                 prepare_cnt = PREPARE_CNT_MAX;
1751         }
1752
1753         /* exit zero count */
1754         exit_zero_cnt = DIV_ROUND_UP(
1755                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1756                                 ui_num * mul
1757                                 );
1758
1759         /*
1760          * Exit zero is unified val ths_zero and ths_exit
1761          * minimum value for ths_exit = 110ns
1762          * min (exit_zero_cnt * 2) = 110/UI
1763          * exit_zero_cnt = 55/UI
1764          */
1765         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1766                 exit_zero_cnt += 1;
1767
1768         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1769                 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1770                             exit_zero_cnt);
1771                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1772         }
1773
1774         /* clk zero count */
1775         clk_zero_cnt = DIV_ROUND_UP(
1776                                 (tclk_prepare_clkzero - ths_prepare_ns)
1777                                 * ui_den, ui_num * mul);
1778
1779         if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1780                 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1781                             clk_zero_cnt);
1782                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1783         }
1784
1785         /* trail count */
1786         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1787         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1788
1789         if (trail_cnt > TRAIL_CNT_MAX) {
1790                 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1791                             trail_cnt);
1792                 trail_cnt = TRAIL_CNT_MAX;
1793         }
1794
1795         /* B080 */
1796         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1797                                                 clk_zero_cnt << 8 | prepare_cnt;
1798
1799         /*
1800          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1801          *                                      mul + 10UI + Extra Byte Count
1802          *
1803          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1804          * Extra Byte Count is calculated according to number of lanes.
1805          * High Low Switch Count is the Max of LP to HS and
1806          * HS to LP switch count
1807          *
1808          */
1809         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1810
1811         /* B044 */
1812         /* FIXME:
1813          * The comment above does not match with the code */
1814         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1815                                                 exit_zero_cnt * mul + 10, 8);
1816
1817         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1818
1819         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1820         intel_dsi->hs_to_lp_count += extra_byte_count;
1821
1822         /* B088 */
1823         /* LP -> HS for clock lanes
1824          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1825          *                                              extra byte count
1826          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1827          *                                      2(in UI) + extra byte count
1828          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1829          *                                      8 + extra byte count
1830          */
1831         intel_dsi->clk_lp_to_hs_count =
1832                 DIV_ROUND_UP(
1833                         4 * tlpx_ui + prepare_cnt * 2 +
1834                         clk_zero_cnt * 2,
1835                         8);
1836
1837         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1838
1839         /* HS->LP for Clock Lanes
1840          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1841          *                                              Extra byte count
1842          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1843          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1844          *                                              Extra byte count
1845          */
1846         intel_dsi->clk_hs_to_lp_count =
1847                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1848                         8);
1849         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1850
1851         intel_dsi_log_params(intel_dsi);
1852 }
1853
1854 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1855 {
1856         struct drm_device *dev = &dev_priv->drm;
1857         struct intel_dsi *intel_dsi;
1858         struct intel_encoder *intel_encoder;
1859         struct drm_encoder *encoder;
1860         struct intel_connector *intel_connector;
1861         struct drm_connector *connector;
1862         struct drm_display_mode *current_mode;
1863         enum port port;
1864         enum pipe pipe;
1865
1866         drm_dbg_kms(&dev_priv->drm, "\n");
1867
1868         /* There is no detection method for MIPI so rely on VBT */
1869         if (!intel_bios_is_dsi_present(dev_priv, &port))
1870                 return;
1871
1872         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1873                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1874         else
1875                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1876
1877         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1878         if (!intel_dsi)
1879                 return;
1880
1881         intel_connector = intel_connector_alloc();
1882         if (!intel_connector) {
1883                 kfree(intel_dsi);
1884                 return;
1885         }
1886
1887         intel_encoder = &intel_dsi->base;
1888         encoder = &intel_encoder->base;
1889         intel_dsi->attached_connector = intel_connector;
1890
1891         connector = &intel_connector->base;
1892
1893         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1894                          "DSI %c", port_name(port));
1895
1896         intel_encoder->compute_config = intel_dsi_compute_config;
1897         intel_encoder->pre_enable = intel_dsi_pre_enable;
1898         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1899                 intel_encoder->enable = bxt_dsi_enable;
1900         intel_encoder->disable = intel_dsi_disable;
1901         intel_encoder->post_disable = intel_dsi_post_disable;
1902         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1903         intel_encoder->get_config = intel_dsi_get_config;
1904         intel_encoder->update_pipe = intel_backlight_update;
1905         intel_encoder->shutdown = intel_dsi_shutdown;
1906
1907         intel_connector->get_hw_state = intel_connector_get_hw_state;
1908
1909         intel_encoder->port = port;
1910         intel_encoder->type = INTEL_OUTPUT_DSI;
1911         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1912         intel_encoder->cloneable = 0;
1913
1914         /*
1915          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1916          * port C. BXT isn't limited like this.
1917          */
1918         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1919                 intel_encoder->pipe_mask = ~0;
1920         else if (port == PORT_A)
1921                 intel_encoder->pipe_mask = BIT(PIPE_A);
1922         else
1923                 intel_encoder->pipe_mask = BIT(PIPE_B);
1924
1925         intel_dsi->panel_power_off_time = ktime_get_boottime();
1926
1927         if (dev_priv->vbt.dsi.config->dual_link)
1928                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1929         else
1930                 intel_dsi->ports = BIT(port);
1931
1932         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1933         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1934
1935         /* Create a DSI host (and a device) for each port. */
1936         for_each_dsi_port(port, intel_dsi->ports) {
1937                 struct intel_dsi_host *host;
1938
1939                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1940                                            port);
1941                 if (!host)
1942                         goto err;
1943
1944                 intel_dsi->dsi_hosts[port] = host;
1945         }
1946
1947         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1948                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1949                 goto err;
1950         }
1951
1952         /* Use clock read-back from current hw-state for fastboot */
1953         current_mode = intel_encoder_current_mode(intel_encoder);
1954         if (current_mode) {
1955                 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1956                             intel_dsi->pclk, current_mode->clock);
1957                 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1958                                             current_mode->clock)) {
1959                         drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1960                         intel_dsi->pclk = current_mode->clock;
1961                 }
1962
1963                 kfree(current_mode);
1964         }
1965
1966         vlv_dphy_param_init(intel_dsi);
1967
1968         intel_dsi_vbt_gpio_init(intel_dsi,
1969                                 intel_dsi_get_hw_state(intel_encoder, &pipe));
1970
1971         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1972                            DRM_MODE_CONNECTOR_DSI);
1973
1974         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1975
1976         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1977         connector->interlace_allowed = false;
1978         connector->doublescan_allowed = false;
1979
1980         intel_connector_attach_encoder(intel_connector, intel_encoder);
1981
1982         mutex_lock(&dev->mode_config.mutex);
1983         intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
1984         mutex_unlock(&dev->mode_config.mutex);
1985
1986         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
1987                 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1988                 goto err_cleanup_connector;
1989         }
1990
1991         intel_panel_init(intel_connector);
1992
1993         intel_backlight_setup(intel_connector, INVALID_PIPE);
1994
1995         vlv_dsi_add_properties(intel_connector);
1996
1997         return;
1998
1999 err_cleanup_connector:
2000         drm_connector_cleanup(&intel_connector->base);
2001 err:
2002         drm_encoder_cleanup(&intel_encoder->base);
2003         kfree(intel_dsi);
2004         kfree(intel_connector);
2005 }