drivers/gpu/drm/i915/display/intel_pps.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include "g4x_dp.h"
   7 #include "i915_drv.h"
   8 #include "intel_de.h"
   9 #include "intel_display_power_well.h"
  10 #include "intel_display_types.h"
  11 #include "intel_dp.h"
  12 #include "intel_dpll.h"
  13 #include "intel_lvds.h"
  14 #include "intel_pps.h"
  15
  16 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
  17                                       enum pipe pipe);
  18
  19 static void pps_init_delays(struct intel_dp *intel_dp);
  20 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
  21
  22 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
  23 {
  24         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  25         intel_wakeref_t wakeref;
  26
  27         /*
  28          * See intel_pps_reset_all() why we need a power domain reference here.
  29          */
  30         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
  31         mutex_lock(&dev_priv->pps_mutex);
  32
  33         return wakeref;
  34 }
  35
  36 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
  37                                  intel_wakeref_t wakeref)
  38 {
  39         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  40
  41         mutex_unlock(&dev_priv->pps_mutex);
  42         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
  43
  44         return 0;
  45 }
  46
  47 static void
  48 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
  49 {
  50         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  51         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  52         enum pipe pipe = intel_dp->pps.pps_pipe;
  53         bool pll_enabled, release_cl_override = false;
  54         enum dpio_phy phy = DPIO_PHY(pipe);
  55         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
  56         u32 DP;
  57
  58         if (drm_WARN(&dev_priv->drm,
  59                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
  60                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
  61                      pipe_name(pipe), dig_port->base.base.base.id,
  62                      dig_port->base.base.name))
  63                 return;
  64
  65         drm_dbg_kms(&dev_priv->drm,
  66                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
  67                     pipe_name(pipe), dig_port->base.base.base.id,
  68                     dig_port->base.base.name);
  69
  70         /* Preserve the BIOS-computed detected bit. This is
  71          * supposed to be read-only.
  72          */
  73         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
  74         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  75         DP |= DP_PORT_WIDTH(1);
  76         DP |= DP_LINK_TRAIN_PAT_1;
  77
  78         if (IS_CHERRYVIEW(dev_priv))
  79                 DP |= DP_PIPE_SEL_CHV(pipe);
  80         else
  81                 DP |= DP_PIPE_SEL(pipe);
  82
  83         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
  84
  85         /*
  86          * The DPLL for the pipe must be enabled for this to work.
  87          * So enable temporarily it if it's not already enabled.
  88          */
  89         if (!pll_enabled) {
  90                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
  91                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
  92
  93                 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
  94                         drm_err(&dev_priv->drm,
  95                                 "Failed to force on pll for pipe %c!\n",
  96                                 pipe_name(pipe));
  97                         return;
  98                 }
  99         }
 100
 101         /*
 102          * Similar magic as in intel_dp_enable_port().
 103          * We _must_ do this port enable + disable trick
 104          * to make this power sequencer lock onto the port.
 105          * Otherwise even VDD force bit won't work.
 106          */
 107         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 108         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 109
 110         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 111         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 112
 113         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 114         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 115
 116         if (!pll_enabled) {
 117                 vlv_force_pll_off(dev_priv, pipe);
 118
 119                 if (release_cl_override)
 120                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 121         }
 122 }
 123
 124 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 125 {
 126         struct intel_encoder *encoder;
 127         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 128
 129         /*
 130          * We don't have power sequencer currently.
 131          * Pick one that's not used by other ports.
 132          */
 133         for_each_intel_dp(&dev_priv->drm, encoder) {
 134                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 135
 136                 if (encoder->type == INTEL_OUTPUT_EDP) {
 137                         drm_WARN_ON(&dev_priv->drm,
 138                                     intel_dp->pps.active_pipe != INVALID_PIPE &&
 139                                     intel_dp->pps.active_pipe !=
 140                                     intel_dp->pps.pps_pipe);
 141
 142                         if (intel_dp->pps.pps_pipe != INVALID_PIPE)
 143                                 pipes &= ~(1 << intel_dp->pps.pps_pipe);
 144                 } else {
 145                         drm_WARN_ON(&dev_priv->drm,
 146                                     intel_dp->pps.pps_pipe != INVALID_PIPE);
 147
 148                         if (intel_dp->pps.active_pipe != INVALID_PIPE)
 149                                 pipes &= ~(1 << intel_dp->pps.active_pipe);
 150                 }
 151         }
 152
 153         if (pipes == 0)
 154                 return INVALID_PIPE;
 155
 156         return ffs(pipes) - 1;
 157 }
 158
 159 static enum pipe
 160 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 161 {
 162         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 163         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 164         enum pipe pipe;
 165
 166         lockdep_assert_held(&dev_priv->pps_mutex);
 167
 168         /* We should never land here with regular DP ports */
 169         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 170
 171         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
 172                     intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
 173
 174         if (intel_dp->pps.pps_pipe != INVALID_PIPE)
 175                 return intel_dp->pps.pps_pipe;
 176
 177         pipe = vlv_find_free_pps(dev_priv);
 178
 179         /*
 180          * Didn't find one. This should not happen since there
 181          * are two power sequencers and up to two eDP ports.
 182          */
 183         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
 184                 pipe = PIPE_A;
 185
 186         vlv_steal_power_sequencer(dev_priv, pipe);
 187         intel_dp->pps.pps_pipe = pipe;
 188
 189         drm_dbg_kms(&dev_priv->drm,
 190                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 191                     pipe_name(intel_dp->pps.pps_pipe),
 192                     dig_port->base.base.base.id,
 193                     dig_port->base.base.name);
 194
 195         /* init power sequencer on this pipe and port */
 196         pps_init_delays(intel_dp);
 197         pps_init_registers(intel_dp, true);
 198
 199         /*
 200          * Even vdd force doesn't work until we've made
 201          * the power sequencer lock in on the port.
 202          */
 203         vlv_power_sequencer_kick(intel_dp);
 204
 205         return intel_dp->pps.pps_pipe;
 206 }
 207
 208 static int
 209 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 210 {
 211         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 212         int backlight_controller = dev_priv->vbt.backlight.controller;
 213
 214         lockdep_assert_held(&dev_priv->pps_mutex);
 215
 216         /* We should never land here with regular DP ports */
 217         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 218
 219         if (!intel_dp->pps.pps_reset)
 220                 return backlight_controller;
 221
 222         intel_dp->pps.pps_reset = false;
 223
 224         /*
 225          * Only the HW needs to be reprogrammed, the SW state is fixed and
 226          * has been setup during connector init.
 227          */
 228         pps_init_registers(intel_dp, false);
 229
 230         return backlight_controller;
 231 }
 232
 233 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 234                                enum pipe pipe);
 235
 236 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 237                                enum pipe pipe)
 238 {
 239         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
 240 }
 241
 242 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 243                                 enum pipe pipe)
 244 {
 245         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 246 }
 247
 248 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 249                          enum pipe pipe)
 250 {
 251         return true;
 252 }
 253
 254 static enum pipe
 255 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 256                      enum port port,
 257                      vlv_pipe_check pipe_check)
 258 {
 259         enum pipe pipe;
 260
 261         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 262                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
 263                         PANEL_PORT_SELECT_MASK;
 264
 265                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 266                         continue;
 267
 268                 if (!pipe_check(dev_priv, pipe))
 269                         continue;
 270
 271                 return pipe;
 272         }
 273
 274         return INVALID_PIPE;
 275 }
 276
 277 static void
 278 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 279 {
 280         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 281         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 282         enum port port = dig_port->base.port;
 283
 284         lockdep_assert_held(&dev_priv->pps_mutex);
 285
 286         /* try to find a pipe with this port selected */
 287         /* first pick one where the panel is on */
 288         intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 289                                                       vlv_pipe_has_pp_on);
 290         /* didn't find one? pick one where vdd is on */
 291         if (intel_dp->pps.pps_pipe == INVALID_PIPE)
 292                 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 293                                                               vlv_pipe_has_vdd_on);
 294         /* didn't find one? pick one with just the correct port */
 295         if (intel_dp->pps.pps_pipe == INVALID_PIPE)
 296                 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 297                                                               vlv_pipe_any);
 298
 299         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 300         if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
 301                 drm_dbg_kms(&dev_priv->drm,
 302                             "no initial power sequencer for [ENCODER:%d:%s]\n",
 303                             dig_port->base.base.base.id,
 304                             dig_port->base.base.name);
 305                 return;
 306         }
 307
 308         drm_dbg_kms(&dev_priv->drm,
 309                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
 310                     dig_port->base.base.base.id,
 311                     dig_port->base.base.name,
 312                     pipe_name(intel_dp->pps.pps_pipe));
 313 }
 314
 315 void intel_pps_reset_all(struct drm_i915_private *dev_priv)
 316 {
 317         struct intel_encoder *encoder;
 318
 319         if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv)))
 320                 return;
 321
 322         if (!HAS_DISPLAY(dev_priv))
 323                 return;
 324
 325         /*
 326          * We can't grab pps_mutex here due to deadlock with power_domain
 327          * mutex when power_domain functions are called while holding pps_mutex.
 328          * That also means that in order to use pps_pipe the code needs to
 329          * hold both a power domain reference and pps_mutex, and the power domain
 330          * reference get/put must be done while _not_ holding pps_mutex.
 331          * pps_{lock,unlock}() do these steps in the correct order, so one
 332          * should use them always.
 333          */
 334
 335         for_each_intel_dp(&dev_priv->drm, encoder) {
 336                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 337
 338                 drm_WARN_ON(&dev_priv->drm,
 339                             intel_dp->pps.active_pipe != INVALID_PIPE);
 340
 341                 if (encoder->type != INTEL_OUTPUT_EDP)
 342                         continue;
 343
 344                 if (DISPLAY_VER(dev_priv) >= 9)
 345                         intel_dp->pps.pps_reset = true;
 346                 else
 347                         intel_dp->pps.pps_pipe = INVALID_PIPE;
 348         }
 349 }
 350
 351 struct pps_registers {
 352         i915_reg_t pp_ctrl;
 353         i915_reg_t pp_stat;
 354         i915_reg_t pp_on;
 355         i915_reg_t pp_off;
 356         i915_reg_t pp_div;
 357 };
 358
 359 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 360                                     struct pps_registers *regs)
 361 {
 362         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 363         int pps_idx = 0;
 364
 365         memset(regs, 0, sizeof(*regs));
 366
 367         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 368                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 369         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 370                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 371
 372         regs->pp_ctrl = PP_CONTROL(pps_idx);
 373         regs->pp_stat = PP_STATUS(pps_idx);
 374         regs->pp_on = PP_ON_DELAYS(pps_idx);
 375         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 376
 377         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 378         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
 379             INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 380                 regs->pp_div = INVALID_MMIO_REG;
 381         else
 382                 regs->pp_div = PP_DIVISOR(pps_idx);
 383 }
 384
 385 static i915_reg_t
 386 _pp_ctrl_reg(struct intel_dp *intel_dp)
 387 {
 388         struct pps_registers regs;
 389
 390         intel_pps_get_registers(intel_dp, &regs);
 391
 392         return regs.pp_ctrl;
 393 }
 394
 395 static i915_reg_t
 396 _pp_stat_reg(struct intel_dp *intel_dp)
 397 {
 398         struct pps_registers regs;
 399
 400         intel_pps_get_registers(intel_dp, &regs);
 401
 402         return regs.pp_stat;
 403 }
 404
 405 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 406 {
 407         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 408
 409         lockdep_assert_held(&dev_priv->pps_mutex);
 410
 411         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 412             intel_dp->pps.pps_pipe == INVALID_PIPE)
 413                 return false;
 414
 415         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
 416 }
 417
 418 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 419 {
 420         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 421
 422         lockdep_assert_held(&dev_priv->pps_mutex);
 423
 424         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 425             intel_dp->pps.pps_pipe == INVALID_PIPE)
 426                 return false;
 427
 428         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 429 }
 430
 431 void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
 432 {
 433         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 434
 435         if (!intel_dp_is_edp(intel_dp))
 436                 return;
 437
 438         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 439                 drm_WARN(&dev_priv->drm, 1,
 440                          "eDP powered off while attempting aux channel communication.\n");
 441                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
 442                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
 443                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
 444         }
 445 }
 446
 447 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 448 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 449
 450 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
 451 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
 452
 453 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 454 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 455
 456 static void intel_pps_verify_state(struct intel_dp *intel_dp);
 457
 458 static void wait_panel_status(struct intel_dp *intel_dp,
 459                                        u32 mask,
 460                                        u32 value)
 461 {
 462         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 463         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 464
 465         lockdep_assert_held(&dev_priv->pps_mutex);
 466
 467         intel_pps_verify_state(intel_dp);
 468
 469         pp_stat_reg = _pp_stat_reg(intel_dp);
 470         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 471
 472         drm_dbg_kms(&dev_priv->drm,
 473                     "mask %08x value %08x status %08x control %08x\n",
 474                     mask, value,
 475                     intel_de_read(dev_priv, pp_stat_reg),
 476                     intel_de_read(dev_priv, pp_ctrl_reg));
 477
 478         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
 479                                        mask, value, 5000))
 480                 drm_err(&dev_priv->drm,
 481                         "Panel status timeout: status %08x control %08x\n",
 482                         intel_de_read(dev_priv, pp_stat_reg),
 483                         intel_de_read(dev_priv, pp_ctrl_reg));
 484
 485         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
 486 }
 487
 488 static void wait_panel_on(struct intel_dp *intel_dp)
 489 {
 490         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 491
 492         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
 493         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 494 }
 495
 496 static void wait_panel_off(struct intel_dp *intel_dp)
 497 {
 498         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 499
 500         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
 501         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 502 }
 503
 504 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
 505 {
 506         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 507         ktime_t panel_power_on_time;
 508         s64 panel_power_off_duration;
 509
 510         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
 511
 512         /* take the difference of currrent time and panel power off time
 513          * and then make panel wait for t11_t12 if needed. */
 514         panel_power_on_time = ktime_get_boottime();
 515         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
 516
 517         /* When we disable the VDD override bit last we have to do the manual
 518          * wait. */
 519         if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
 520                 wait_remaining_ms_from_jiffies(jiffies,
 521                                        intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
 522
 523         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 524 }
 525
 526 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
 527 {
 528         intel_wakeref_t wakeref;
 529
 530         if (!intel_dp_is_edp(intel_dp))
 531                 return;
 532
 533         with_intel_pps_lock(intel_dp, wakeref)
 534                 wait_panel_power_cycle(intel_dp);
 535 }
 536
 537 static void wait_backlight_on(struct intel_dp *intel_dp)
 538 {
 539         wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
 540                                        intel_dp->pps.backlight_on_delay);
 541 }
 542
 543 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
 544 {
 545         wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
 546                                        intel_dp->pps.backlight_off_delay);
 547 }
 548
 549 /* Read the current pp_control value, unlocking the register if it
 550  * is locked
 551  */
 552
 553 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
 554 {
 555         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 556         u32 control;
 557
 558         lockdep_assert_held(&dev_priv->pps_mutex);
 559
 560         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
 561         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
 562                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
 563                 control &= ~PANEL_UNLOCK_MASK;
 564                 control |= PANEL_UNLOCK_REGS;
 565         }
 566         return control;
 567 }
 568
 569 /*
 570  * Must be paired with intel_pps_vdd_off_unlocked().
 571  * Must hold pps_mutex around the whole on/off sequence.
 572  * Can be nested with intel_pps_vdd_{on,off}() calls.
 573  */
 574 bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
 575 {
 576         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 577         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 578         u32 pp;
 579         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 580         bool need_to_disable = !intel_dp->pps.want_panel_vdd;
 581
 582         lockdep_assert_held(&dev_priv->pps_mutex);
 583
 584         if (!intel_dp_is_edp(intel_dp))
 585                 return false;
 586
 587         cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
 588         intel_dp->pps.want_panel_vdd = true;
 589
 590         if (edp_have_panel_vdd(intel_dp))
 591                 return need_to_disable;
 592
 593         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
 594         intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
 595                                                             intel_aux_power_domain(dig_port));
 596
 597         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
 598                     dig_port->base.base.base.id,
 599                     dig_port->base.base.name);
 600
 601         if (!edp_have_panel_power(intel_dp))
 602                 wait_panel_power_cycle(intel_dp);
 603
 604         pp = ilk_get_pp_control(intel_dp);
 605         pp |= EDP_FORCE_VDD;
 606
 607         pp_stat_reg = _pp_stat_reg(intel_dp);
 608         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 609
 610         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 611         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 612         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 613                     intel_de_read(dev_priv, pp_stat_reg),
 614                     intel_de_read(dev_priv, pp_ctrl_reg));
 615         /*
 616          * If the panel wasn't on, delay before accessing aux channel
 617          */
 618         if (!edp_have_panel_power(intel_dp)) {
 619                 drm_dbg_kms(&dev_priv->drm,
 620                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
 621                             dig_port->base.base.base.id,
 622                             dig_port->base.base.name);
 623                 msleep(intel_dp->pps.panel_power_up_delay);
 624         }
 625
 626         return need_to_disable;
 627 }
 628
 629 /*
 630  * Must be paired with intel_pps_off().
 631  * Nested calls to these functions are not allowed since
 632  * we drop the lock. Caller must use some higher level
 633  * locking to prevent nested calls from other threads.
 634  */
 635 void intel_pps_vdd_on(struct intel_dp *intel_dp)
 636 {
 637         intel_wakeref_t wakeref;
 638         bool vdd;
 639
 640         if (!intel_dp_is_edp(intel_dp))
 641                 return;
 642
 643         vdd = false;
 644         with_intel_pps_lock(intel_dp, wakeref)
 645                 vdd = intel_pps_vdd_on_unlocked(intel_dp);
 646         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
 647                         dp_to_dig_port(intel_dp)->base.base.base.id,
 648                         dp_to_dig_port(intel_dp)->base.base.name);
 649 }
 650
 651 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
 652 {
 653         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 654         struct intel_digital_port *dig_port =
 655                 dp_to_dig_port(intel_dp);
 656         u32 pp;
 657         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 658
 659         lockdep_assert_held(&dev_priv->pps_mutex);
 660
 661         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
 662
 663         if (!edp_have_panel_vdd(intel_dp))
 664                 return;
 665
 666         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
 667                     dig_port->base.base.base.id,
 668                     dig_port->base.base.name);
 669
 670         pp = ilk_get_pp_control(intel_dp);
 671         pp &= ~EDP_FORCE_VDD;
 672
 673         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 674         pp_stat_reg = _pp_stat_reg(intel_dp);
 675
 676         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 677         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 678
 679         /* Make sure sequencer is idle before allowing subsequent activity */
 680         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 681                     intel_de_read(dev_priv, pp_stat_reg),
 682                     intel_de_read(dev_priv, pp_ctrl_reg));
 683
 684         if ((pp & PANEL_POWER_ON) == 0)
 685                 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
 686
 687         intel_display_power_put(dev_priv,
 688                                 intel_aux_power_domain(dig_port),
 689                                 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
 690 }
 691
 692 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
 693 {
 694         intel_wakeref_t wakeref;
 695
 696         if (!intel_dp_is_edp(intel_dp))
 697                 return;
 698
 699         cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
 700         /*
 701          * vdd might still be enabled due to the delayed vdd off.
 702          * Make sure vdd is actually turned off here.
 703          */
 704         with_intel_pps_lock(intel_dp, wakeref)
 705                 intel_pps_vdd_off_sync_unlocked(intel_dp);
 706 }
 707
 708 static void edp_panel_vdd_work(struct work_struct *__work)
 709 {
 710         struct intel_pps *pps = container_of(to_delayed_work(__work),
 711                                              struct intel_pps, panel_vdd_work);
 712         struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
 713         intel_wakeref_t wakeref;
 714
 715         with_intel_pps_lock(intel_dp, wakeref) {
 716                 if (!intel_dp->pps.want_panel_vdd)
 717                         intel_pps_vdd_off_sync_unlocked(intel_dp);
 718         }
 719 }
 720
 721 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
 722 {
 723         unsigned long delay;
 724
 725         /*
 726          * Queue the timer to fire a long time from now (relative to the power
 727          * down delay) to keep the panel power up across a sequence of
 728          * operations.
 729          */
 730         delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
 731         schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);
 732 }
 733
 734 /*
 735  * Must be paired with edp_panel_vdd_on().
 736  * Must hold pps_mutex around the whole on/off sequence.
 737  * Can be nested with intel_pps_vdd_{on,off}() calls.
 738  */
 739 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
 740 {
 741         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 742
 743         lockdep_assert_held(&dev_priv->pps_mutex);
 744
 745         if (!intel_dp_is_edp(intel_dp))
 746                 return;
 747
 748         I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
 749                         dp_to_dig_port(intel_dp)->base.base.base.id,
 750                         dp_to_dig_port(intel_dp)->base.base.name);
 751
 752         intel_dp->pps.want_panel_vdd = false;
 753
 754         if (sync)
 755                 intel_pps_vdd_off_sync_unlocked(intel_dp);
 756         else
 757                 edp_panel_vdd_schedule_off(intel_dp);
 758 }
 759
 760 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
 761 {
 762         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 763         u32 pp;
 764         i915_reg_t pp_ctrl_reg;
 765
 766         lockdep_assert_held(&dev_priv->pps_mutex);
 767
 768         if (!intel_dp_is_edp(intel_dp))
 769                 return;
 770
 771         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
 772                     dp_to_dig_port(intel_dp)->base.base.base.id,
 773                     dp_to_dig_port(intel_dp)->base.base.name);
 774
 775         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
 776                      "[ENCODER:%d:%s] panel power already on\n",
 777                      dp_to_dig_port(intel_dp)->base.base.base.id,
 778                      dp_to_dig_port(intel_dp)->base.base.name))
 779                 return;
 780
 781         wait_panel_power_cycle(intel_dp);
 782
 783         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 784         pp = ilk_get_pp_control(intel_dp);
 785         if (IS_IRONLAKE(dev_priv)) {
 786                 /* ILK workaround: disable reset around power sequence */
 787                 pp &= ~PANEL_POWER_RESET;
 788                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 789                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 790         }
 791
 792         pp |= PANEL_POWER_ON;
 793         if (!IS_IRONLAKE(dev_priv))
 794                 pp |= PANEL_POWER_RESET;
 795
 796         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 797         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 798
 799         wait_panel_on(intel_dp);
 800         intel_dp->pps.last_power_on = jiffies;
 801
 802         if (IS_IRONLAKE(dev_priv)) {
 803                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 804                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 805                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 806         }
 807 }
 808
 809 void intel_pps_on(struct intel_dp *intel_dp)
 810 {
 811         intel_wakeref_t wakeref;
 812
 813         if (!intel_dp_is_edp(intel_dp))
 814                 return;
 815
 816         with_intel_pps_lock(intel_dp, wakeref)
 817                 intel_pps_on_unlocked(intel_dp);
 818 }
 819
 820 void intel_pps_off_unlocked(struct intel_dp *intel_dp)
 821 {
 822         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 823         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 824         u32 pp;
 825         i915_reg_t pp_ctrl_reg;
 826
 827         lockdep_assert_held(&dev_priv->pps_mutex);
 828
 829         if (!intel_dp_is_edp(intel_dp))
 830                 return;
 831
 832         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
 833                     dig_port->base.base.base.id, dig_port->base.base.name);
 834
 835         drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
 836                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
 837                  dig_port->base.base.base.id, dig_port->base.base.name);
 838
 839         pp = ilk_get_pp_control(intel_dp);
 840         /* We need to switch off panel power _and_ force vdd, for otherwise some
 841          * panels get very unhappy and cease to work. */
 842         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
 843                 EDP_BLC_ENABLE);
 844
 845         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 846
 847         intel_dp->pps.want_panel_vdd = false;
 848
 849         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 850         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 851
 852         wait_panel_off(intel_dp);
 853         intel_dp->pps.panel_power_off_time = ktime_get_boottime();
 854
 855         /* We got a reference when we enabled the VDD. */
 856         intel_display_power_put(dev_priv,
 857                                 intel_aux_power_domain(dig_port),
 858                                 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
 859 }
 860
 861 void intel_pps_off(struct intel_dp *intel_dp)
 862 {
 863         intel_wakeref_t wakeref;
 864
 865         if (!intel_dp_is_edp(intel_dp))
 866                 return;
 867
 868         with_intel_pps_lock(intel_dp, wakeref)
 869                 intel_pps_off_unlocked(intel_dp);
 870 }
 871
 872 /* Enable backlight in the panel power control. */
 873 void intel_pps_backlight_on(struct intel_dp *intel_dp)
 874 {
 875         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 876         intel_wakeref_t wakeref;
 877
 878         /*
 879          * If we enable the backlight right away following a panel power
 880          * on, we may see slight flicker as the panel syncs with the eDP
 881          * link.  So delay a bit to make sure the image is solid before
 882          * allowing it to appear.
 883          */
 884         wait_backlight_on(intel_dp);
 885
 886         with_intel_pps_lock(intel_dp, wakeref) {
 887                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 888                 u32 pp;
 889
 890                 pp = ilk_get_pp_control(intel_dp);
 891                 pp |= EDP_BLC_ENABLE;
 892
 893                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 894                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 895         }
 896 }
 897
 898 /* Disable backlight in the panel power control. */
 899 void intel_pps_backlight_off(struct intel_dp *intel_dp)
 900 {
 901         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 902         intel_wakeref_t wakeref;
 903
 904         if (!intel_dp_is_edp(intel_dp))
 905                 return;
 906
 907         with_intel_pps_lock(intel_dp, wakeref) {
 908                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 909                 u32 pp;
 910
 911                 pp = ilk_get_pp_control(intel_dp);
 912                 pp &= ~EDP_BLC_ENABLE;
 913
 914                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 915                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 916         }
 917
 918         intel_dp->pps.last_backlight_off = jiffies;
 919         edp_wait_backlight_off(intel_dp);
 920 }
 921
 922 /*
 923  * Hook for controlling the panel power control backlight through the bl_power
 924  * sysfs attribute. Take care to handle multiple calls.
 925  */
 926 void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
 927 {
 928         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 929         struct intel_dp *intel_dp = intel_attached_dp(connector);
 930         intel_wakeref_t wakeref;
 931         bool is_enabled;
 932
 933         is_enabled = false;
 934         with_intel_pps_lock(intel_dp, wakeref)
 935                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
 936         if (is_enabled == enable)
 937                 return;
 938
 939         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
 940                     enable ? "enable" : "disable");
 941
 942         if (enable)
 943                 intel_pps_backlight_on(intel_dp);
 944         else
 945                 intel_pps_backlight_off(intel_dp);
 946 }
 947
 948 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
 949 {
 950         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 951         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 952         enum pipe pipe = intel_dp->pps.pps_pipe;
 953         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
 954
 955         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
 956
 957         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
 958                 return;
 959
 960         intel_pps_vdd_off_sync_unlocked(intel_dp);
 961
 962         /*
 963          * VLV seems to get confused when multiple power sequencers
 964          * have the same port selected (even if only one has power/vdd
 965          * enabled). The failure manifests as vlv_wait_port_ready() failing
 966          * CHV on the other hand doesn't seem to mind having the same port
 967          * selected in multiple power sequencers, but let's clear the
 968          * port select always when logically disconnecting a power sequencer
 969          * from a port.
 970          */
 971         drm_dbg_kms(&dev_priv->drm,
 972                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
 973                     pipe_name(pipe), dig_port->base.base.base.id,
 974                     dig_port->base.base.name);
 975         intel_de_write(dev_priv, pp_on_reg, 0);
 976         intel_de_posting_read(dev_priv, pp_on_reg);
 977
 978         intel_dp->pps.pps_pipe = INVALID_PIPE;
 979 }
 980
 981 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 982                                       enum pipe pipe)
 983 {
 984         struct intel_encoder *encoder;
 985
 986         lockdep_assert_held(&dev_priv->pps_mutex);
 987
 988         for_each_intel_dp(&dev_priv->drm, encoder) {
 989                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 990
 991                 drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
 992                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
 993                          pipe_name(pipe), encoder->base.base.id,
 994                          encoder->base.name);
 995
 996                 if (intel_dp->pps.pps_pipe != pipe)
 997                         continue;
 998
 999                 drm_dbg_kms(&dev_priv->drm,
1000                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
1001                             pipe_name(pipe), encoder->base.base.id,
1002                             encoder->base.name);
1003
1004                 /* make sure vdd is off before we steal it */
1005                 vlv_detach_power_sequencer(intel_dp);
1006         }
1007 }
1008
1009 void vlv_pps_init(struct intel_encoder *encoder,
1010                   const struct intel_crtc_state *crtc_state)
1011 {
1012         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1013         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1014         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1015
1016         lockdep_assert_held(&dev_priv->pps_mutex);
1017
1018         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
1019
1020         if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
1021             intel_dp->pps.pps_pipe != crtc->pipe) {
1022                 /*
1023                  * If another power sequencer was being used on this
1024                  * port previously make sure to turn off vdd there while
1025                  * we still have control of it.
1026                  */
1027                 vlv_detach_power_sequencer(intel_dp);
1028         }
1029
1030         /*
1031          * We may be stealing the power
1032          * sequencer from another port.
1033          */
1034         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
1035
1036         intel_dp->pps.active_pipe = crtc->pipe;
1037
1038         if (!intel_dp_is_edp(intel_dp))
1039                 return;
1040
1041         /* now it's all ours */
1042         intel_dp->pps.pps_pipe = crtc->pipe;
1043
1044         drm_dbg_kms(&dev_priv->drm,
1045                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
1046                     pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,
1047                     encoder->base.name);
1048
1049         /* init power sequencer on this pipe and port */
1050         pps_init_delays(intel_dp);
1051         pps_init_registers(intel_dp, true);
1052 }
1053
1054 static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
1055 {
1056         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1057         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1058
1059         lockdep_assert_held(&dev_priv->pps_mutex);
1060
1061         if (!edp_have_panel_vdd(intel_dp))
1062                 return;
1063
1064         /*
1065          * The VDD bit needs a power domain reference, so if the bit is
1066          * already enabled when we boot or resume, grab this reference and
1067          * schedule a vdd off, so we don't hold on to the reference
1068          * indefinitely.
1069          */
1070         drm_dbg_kms(&dev_priv->drm,
1071                     "VDD left on by BIOS, adjusting state tracking\n");
1072         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
1073         intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
1074                                                             intel_aux_power_domain(dig_port));
1075
1076         edp_panel_vdd_schedule_off(intel_dp);
1077 }
1078
1079 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
1080 {
1081         intel_wakeref_t wakeref;
1082         bool have_power = false;
1083
1084         with_intel_pps_lock(intel_dp, wakeref) {
1085                 have_power = edp_have_panel_power(intel_dp) ||
1086                              edp_have_panel_vdd(intel_dp);
1087         }
1088
1089         return have_power;
1090 }
1091
1092 static void pps_init_timestamps(struct intel_dp *intel_dp)
1093 {
1094         intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1095         intel_dp->pps.last_power_on = jiffies;
1096         intel_dp->pps.last_backlight_off = jiffies;
1097 }
1098
1099 static void
1100 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
1101 {
1102         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1103         u32 pp_on, pp_off, pp_ctl;
1104         struct pps_registers regs;
1105
1106         intel_pps_get_registers(intel_dp, &regs);
1107
1108         pp_ctl = ilk_get_pp_control(intel_dp);
1109
1110         /* Ensure PPS is unlocked */
1111         if (!HAS_DDI(dev_priv))
1112                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1113
1114         pp_on = intel_de_read(dev_priv, regs.pp_on);
1115         pp_off = intel_de_read(dev_priv, regs.pp_off);
1116
1117         /* Pull timing values out of registers */
1118         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1119         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1120         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1121         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1122
1123         if (i915_mmio_reg_valid(regs.pp_div)) {
1124                 u32 pp_div;
1125
1126                 pp_div = intel_de_read(dev_priv, regs.pp_div);
1127
1128                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
1129         } else {
1130                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
1131         }
1132 }
1133
1134 static void
1135 intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
1136                      const struct edp_power_seq *seq)
1137 {
1138         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1139
1140         drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1141                     state_name,
1142                     seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
1143 }
1144
1145 static void
1146 intel_pps_verify_state(struct intel_dp *intel_dp)
1147 {
1148         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1149         struct edp_power_seq hw;
1150         struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
1151
1152         intel_pps_readout_hw_state(intel_dp, &hw);
1153
1154         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
1155             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
1156                 drm_err(&i915->drm, "PPS state mismatch\n");
1157                 intel_pps_dump_state(intel_dp, "sw", sw);
1158                 intel_pps_dump_state(intel_dp, "hw", &hw);
1159         }
1160 }
1161
1162 static void pps_init_delays(struct intel_dp *intel_dp)
1163 {
1164         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1165         struct edp_power_seq cur, vbt, spec,
1166                 *final = &intel_dp->pps.pps_delays;
1167
1168         lockdep_assert_held(&dev_priv->pps_mutex);
1169
1170         /* already initialized? */
1171         if (final->t11_t12 != 0)
1172                 return;
1173
1174         intel_pps_readout_hw_state(intel_dp, &cur);
1175
1176         intel_pps_dump_state(intel_dp, "cur", &cur);
1177
1178         vbt = dev_priv->vbt.edp.pps;
1179         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
1180          * of 500ms appears to be too short. Ocassionally the panel
1181          * just fails to power back on. Increasing the delay to 800ms
1182          * seems sufficient to avoid this problem.
1183          */
1184         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
1185                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
1186                 drm_dbg_kms(&dev_priv->drm,
1187                             "Increasing T12 panel delay as per the quirk to %d\n",
1188                             vbt.t11_t12);
1189         }
1190         /* T11_T12 delay is special and actually in units of 100ms, but zero
1191          * based in the hw (so we need to add 100 ms). But the sw vbt
1192          * table multiplies it with 1000 to make it in units of 100usec,
1193          * too. */
1194         vbt.t11_t12 += 100 * 10;
1195
1196         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
1197          * our hw here, which are all in 100usec. */
1198         spec.t1_t3 = 210 * 10;
1199         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
1200         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
1201         spec.t10 = 500 * 10;
1202         /* This one is special and actually in units of 100ms, but zero
1203          * based in the hw (so we need to add 100 ms). But the sw vbt
1204          * table multiplies it with 1000 to make it in units of 100usec,
1205          * too. */
1206         spec.t11_t12 = (510 + 100) * 10;
1207
1208         intel_pps_dump_state(intel_dp, "vbt", &vbt);
1209
1210         /* Use the max of the register settings and vbt. If both are
1211          * unset, fall back to the spec limits. */
1212 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
1213                                        spec.field : \
1214                                        max(cur.field, vbt.field))
1215         assign_final(t1_t3);
1216         assign_final(t8);
1217         assign_final(t9);
1218         assign_final(t10);
1219         assign_final(t11_t12);
1220 #undef assign_final
1221
1222 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
1223         intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
1224         intel_dp->pps.backlight_on_delay = get_delay(t8);
1225         intel_dp->pps.backlight_off_delay = get_delay(t9);
1226         intel_dp->pps.panel_power_down_delay = get_delay(t10);
1227         intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
1228 #undef get_delay
1229
1230         drm_dbg_kms(&dev_priv->drm,
1231                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1232                     intel_dp->pps.panel_power_up_delay,
1233                     intel_dp->pps.panel_power_down_delay,
1234                     intel_dp->pps.panel_power_cycle_delay);
1235
1236         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
1237                     intel_dp->pps.backlight_on_delay,
1238                     intel_dp->pps.backlight_off_delay);
1239
1240         /*
1241          * We override the HW backlight delays to 1 because we do manual waits
1242          * on them. For T8, even BSpec recommends doing it. For T9, if we
1243          * don't do this, we'll end up waiting for the backlight off delay
1244          * twice: once when we do the manual sleep, and once when we disable
1245          * the panel and wait for the PP_STATUS bit to become zero.
1246          */
1247         final->t8 = 1;
1248         final->t9 = 1;
1249
1250         /*
1251          * HW has only a 100msec granularity for t11_t12 so round it up
1252          * accordingly.
1253          */
1254         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
1255 }
1256
1257 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)
1258 {
1259         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1260         u32 pp_on, pp_off, port_sel = 0;
1261         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
1262         struct pps_registers regs;
1263         enum port port = dp_to_dig_port(intel_dp)->base.port;
1264         const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
1265
1266         lockdep_assert_held(&dev_priv->pps_mutex);
1267
1268         intel_pps_get_registers(intel_dp, &regs);
1269
1270         /*
1271          * On some VLV machines the BIOS can leave the VDD
1272          * enabled even on power sequencers which aren't
1273          * hooked up to any port. This would mess up the
1274          * power domain tracking the first time we pick
1275          * one of these power sequencers for use since
1276          * intel_pps_vdd_on_unlocked() would notice that the VDD was
1277          * already on and therefore wouldn't grab the power
1278          * domain reference. Disable VDD first to avoid this.
1279          * This also avoids spuriously turning the VDD on as
1280          * soon as the new power sequencer gets initialized.
1281          */
1282         if (force_disable_vdd) {
1283                 u32 pp = ilk_get_pp_control(intel_dp);
1284
1285                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
1286                          "Panel power already on\n");
1287
1288                 if (pp & EDP_FORCE_VDD)
1289                         drm_dbg_kms(&dev_priv->drm,
1290                                     "VDD already on, disabling first\n");
1291
1292                 pp &= ~EDP_FORCE_VDD;
1293
1294                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
1295         }
1296
1297         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
1298                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
1299         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
1300                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
1301
1302         /* Haswell doesn't have any port selection bits for the panel
1303          * power sequencer any more. */
1304         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1305                 port_sel = PANEL_PORT_SELECT_VLV(port);
1306         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1307                 switch (port) {
1308                 case PORT_A:
1309                         port_sel = PANEL_PORT_SELECT_DPA;
1310                         break;
1311                 case PORT_C:
1312                         port_sel = PANEL_PORT_SELECT_DPC;
1313                         break;
1314                 case PORT_D:
1315                         port_sel = PANEL_PORT_SELECT_DPD;
1316                         break;
1317                 default:
1318                         MISSING_CASE(port);
1319                         break;
1320                 }
1321         }
1322
1323         pp_on |= port_sel;
1324
1325         intel_de_write(dev_priv, regs.pp_on, pp_on);
1326         intel_de_write(dev_priv, regs.pp_off, pp_off);
1327
1328         /*
1329          * Compute the divisor for the pp clock, simply match the Bspec formula.
1330          */
1331         if (i915_mmio_reg_valid(regs.pp_div)) {
1332                 intel_de_write(dev_priv, regs.pp_div,
1333                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
1334         } else {
1335                 u32 pp_ctl;
1336
1337                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
1338                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
1339                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
1340                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1341         }
1342
1343         drm_dbg_kms(&dev_priv->drm,
1344                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1345                     intel_de_read(dev_priv, regs.pp_on),
1346                     intel_de_read(dev_priv, regs.pp_off),
1347                     i915_mmio_reg_valid(regs.pp_div) ?
1348                     intel_de_read(dev_priv, regs.pp_div) :
1349                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1350 }
1351
1352 void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1353 {
1354         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1355         intel_wakeref_t wakeref;
1356
1357         if (!intel_dp_is_edp(intel_dp))
1358                 return;
1359
1360         with_intel_pps_lock(intel_dp, wakeref) {
1361                 /*
1362                  * Reinit the power sequencer also on the resume path, in case
1363                  * BIOS did something nasty with it.
1364                  */
1365                 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1366                         vlv_initial_power_sequencer_setup(intel_dp);
1367
1368                 pps_init_delays(intel_dp);
1369                 pps_init_registers(intel_dp, false);
1370
1371                 intel_pps_vdd_sanitize(intel_dp);
1372         }
1373 }
1374
1375 void intel_pps_init(struct intel_dp *intel_dp)
1376 {
1377         INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
1378
1379         pps_init_timestamps(intel_dp);
1380
1381         intel_pps_encoder_reset(intel_dp);
1382 }
1383
1384 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
1385 {
1386         int pps_num;
1387         int pps_idx;
1388
1389         if (!HAS_DISPLAY(dev_priv) || HAS_DDI(dev_priv))
1390                 return;
1391         /*
1392          * This w/a is needed at least on CPT/PPT, but to be sure apply it
1393          * everywhere where registers can be write protected.
1394          */
1395         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1396                 pps_num = 2;
1397         else
1398                 pps_num = 1;
1399
1400         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
1401                 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
1402
1403                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
1404                 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
1405         }
1406 }
1407
1408 void intel_pps_setup(struct drm_i915_private *i915)
1409 {
1410         if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1411                 i915->pps_mmio_base = PCH_PPS_BASE;
1412         else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1413                 i915->pps_mmio_base = VLV_PPS_BASE;
1414         else
1415                 i915->pps_mmio_base = PPS_BASE;
1416 }
1417
1418 void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1419 {
1420         i915_reg_t pp_reg;
1421         u32 val;
1422         enum pipe panel_pipe = INVALID_PIPE;
1423         bool locked = true;
1424
1425         if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1426                 return;
1427
1428         if (HAS_PCH_SPLIT(dev_priv)) {
1429                 u32 port_sel;
1430
1431                 pp_reg = PP_CONTROL(0);
1432                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1433
1434                 switch (port_sel) {
1435                 case PANEL_PORT_SELECT_LVDS:
1436                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1437                         break;
1438                 case PANEL_PORT_SELECT_DPA:
1439                         g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1440                         break;
1441                 case PANEL_PORT_SELECT_DPC:
1442                         g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1443                         break;
1444                 case PANEL_PORT_SELECT_DPD:
1445                         g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1446                         break;
1447                 default:
1448                         MISSING_CASE(port_sel);
1449                         break;
1450                 }
1451         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1452                 /* presumably write lock depends on pipe, not port select */
1453                 pp_reg = PP_CONTROL(pipe);
1454                 panel_pipe = pipe;
1455         } else {
1456                 u32 port_sel;
1457
1458                 pp_reg = PP_CONTROL(0);
1459                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1460
1461                 drm_WARN_ON(&dev_priv->drm,
1462                             port_sel != PANEL_PORT_SELECT_LVDS);
1463                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1464         }
1465
1466         val = intel_de_read(dev_priv, pp_reg);
1467         if (!(val & PANEL_POWER_ON) ||
1468             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1469                 locked = false;
1470
1471         I915_STATE_WARN(panel_pipe == pipe && locked,
1472                         "panel assertion failure, pipe %c regs locked\n",
1473                         pipe_name(pipe));
1474 }