drivers/gpu/drm/i915/display/intel_display_power_map.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "i915_reg.h"
   8
   9 #include "vlv_sideband_reg.h"
  10
  11 #include "intel_display_power_map.h"
  12 #include "intel_display_power_well.h"
  13
  14 #define __LIST_INLINE_ELEMS(__elem_type, ...) \
  15         ((__elem_type[]) { __VA_ARGS__ })
  16
  17 #define __LIST(__elems) { \
  18         .list = __elems, \
  19         .count = ARRAY_SIZE(__elems), \
  20 }
  21
  22 #define I915_PW_DOMAINS(...) \
  23         (const struct i915_power_domain_list) \
  24                 __LIST(__LIST_INLINE_ELEMS(const enum intel_display_power_domain, __VA_ARGS__))
  25
  26 #define I915_DECL_PW_DOMAINS(__name, ...) \
  27         static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__)
  28
  29 /* Zero-length list assigns all power domains, a NULL list assigns none. */
  30 #define I915_PW_DOMAINS_NONE    NULL
  31 #define I915_PW_DOMAINS_ALL     /* zero-length list */
  32
  33 #define I915_PW_INSTANCES(...) \
  34         (const struct i915_power_well_instance_list) \
  35                 __LIST(__LIST_INLINE_ELEMS(const struct i915_power_well_instance, __VA_ARGS__))
  36
  37 #define I915_PW(_name, _domain_list, ...) \
  38         { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
  39
  40
  41 struct i915_power_well_desc_list {
  42         const struct i915_power_well_desc *list;
  43         u8 count;
  44 };
  45
  46 #define I915_PW_DESCRIPTORS(x) __LIST(x)
  47
  48
  49 I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
  50
  51 static const struct i915_power_well_desc i9xx_power_wells_always_on[] = {
  52         {
  53                 .instances = &I915_PW_INSTANCES(
  54                         I915_PW("always-on", &i9xx_pwdoms_always_on),
  55                 ),
  56                 .ops = &i9xx_always_on_power_well_ops,
  57                 .always_on = true,
  58         },
  59 };
  60
  61 static const struct i915_power_well_desc_list i9xx_power_wells[] = {
  62         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
  63 };
  64
  65 I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
  66         POWER_DOMAIN_PIPE_A,
  67         POWER_DOMAIN_PIPE_B,
  68         POWER_DOMAIN_PIPE_PANEL_FITTER_A,
  69         POWER_DOMAIN_PIPE_PANEL_FITTER_B,
  70         POWER_DOMAIN_TRANSCODER_A,
  71         POWER_DOMAIN_TRANSCODER_B,
  72         POWER_DOMAIN_INIT);
  73
  74 static const struct i915_power_well_desc i830_power_wells_main[] = {
  75         {
  76                 .instances = &I915_PW_INSTANCES(
  77                         I915_PW("pipes", &i830_pwdoms_pipes),
  78                 ),
  79                 .ops = &i830_pipes_power_well_ops,
  80         },
  81 };
  82
  83 static const struct i915_power_well_desc_list i830_power_wells[] = {
  84         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
  85         I915_PW_DESCRIPTORS(i830_power_wells_main),
  86 };
  87
  88 I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
  89         POWER_DOMAIN_PIPE_B,
  90         POWER_DOMAIN_PIPE_C,
  91         POWER_DOMAIN_PIPE_PANEL_FITTER_A,
  92         POWER_DOMAIN_PIPE_PANEL_FITTER_B,
  93         POWER_DOMAIN_PIPE_PANEL_FITTER_C,
  94         POWER_DOMAIN_TRANSCODER_A,
  95         POWER_DOMAIN_TRANSCODER_B,
  96         POWER_DOMAIN_TRANSCODER_C,
  97         POWER_DOMAIN_PORT_DDI_LANES_B,
  98         POWER_DOMAIN_PORT_DDI_LANES_C,
  99         POWER_DOMAIN_PORT_DDI_LANES_D,
 100         POWER_DOMAIN_PORT_CRT, /* DDI E */
 101         POWER_DOMAIN_VGA,
 102         POWER_DOMAIN_AUDIO_MMIO,
 103         POWER_DOMAIN_AUDIO_PLAYBACK,
 104         POWER_DOMAIN_INIT);
 105
 106 static const struct i915_power_well_desc hsw_power_wells_main[] = {
 107         {
 108                 .instances = &I915_PW_INSTANCES(
 109                         I915_PW("display", &hsw_pwdoms_display,
 110                                 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
 111                                 .id = HSW_DISP_PW_GLOBAL),
 112                 ),
 113                 .ops = &hsw_power_well_ops,
 114                 .has_vga = true,
 115         },
 116 };
 117
 118 static const struct i915_power_well_desc_list hsw_power_wells[] = {
 119         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 120         I915_PW_DESCRIPTORS(hsw_power_wells_main),
 121 };
 122
 123 I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
 124         POWER_DOMAIN_PIPE_B,
 125         POWER_DOMAIN_PIPE_C,
 126         POWER_DOMAIN_PIPE_PANEL_FITTER_B,
 127         POWER_DOMAIN_PIPE_PANEL_FITTER_C,
 128         POWER_DOMAIN_TRANSCODER_A,
 129         POWER_DOMAIN_TRANSCODER_B,
 130         POWER_DOMAIN_TRANSCODER_C,
 131         POWER_DOMAIN_PORT_DDI_LANES_B,
 132         POWER_DOMAIN_PORT_DDI_LANES_C,
 133         POWER_DOMAIN_PORT_DDI_LANES_D,
 134         POWER_DOMAIN_PORT_CRT, /* DDI E */
 135         POWER_DOMAIN_VGA,
 136         POWER_DOMAIN_AUDIO_MMIO,
 137         POWER_DOMAIN_AUDIO_PLAYBACK,
 138         POWER_DOMAIN_INIT);
 139
 140 static const struct i915_power_well_desc bdw_power_wells_main[] = {
 141         {
 142                 .instances = &I915_PW_INSTANCES(
 143                         I915_PW("display", &bdw_pwdoms_display,
 144                                 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
 145                                 .id = HSW_DISP_PW_GLOBAL),
 146                 ),
 147                 .ops = &hsw_power_well_ops,
 148                 .has_vga = true,
 149                 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
 150         },
 151 };
 152
 153 static const struct i915_power_well_desc_list bdw_power_wells[] = {
 154         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 155         I915_PW_DESCRIPTORS(bdw_power_wells_main),
 156 };
 157
 158 I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
 159         POWER_DOMAIN_DISPLAY_CORE,
 160         POWER_DOMAIN_PIPE_A,
 161         POWER_DOMAIN_PIPE_B,
 162         POWER_DOMAIN_PIPE_PANEL_FITTER_A,
 163         POWER_DOMAIN_PIPE_PANEL_FITTER_B,
 164         POWER_DOMAIN_TRANSCODER_A,
 165         POWER_DOMAIN_TRANSCODER_B,
 166         POWER_DOMAIN_PORT_DDI_LANES_B,
 167         POWER_DOMAIN_PORT_DDI_LANES_C,
 168         POWER_DOMAIN_PORT_DSI,
 169         POWER_DOMAIN_PORT_CRT,
 170         POWER_DOMAIN_VGA,
 171         POWER_DOMAIN_AUDIO_MMIO,
 172         POWER_DOMAIN_AUDIO_PLAYBACK,
 173         POWER_DOMAIN_AUX_B,
 174         POWER_DOMAIN_AUX_C,
 175         POWER_DOMAIN_GMBUS,
 176         POWER_DOMAIN_INIT);
 177
 178 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
 179         POWER_DOMAIN_PORT_DDI_LANES_B,
 180         POWER_DOMAIN_PORT_DDI_LANES_C,
 181         POWER_DOMAIN_PORT_CRT,
 182         POWER_DOMAIN_AUX_B,
 183         POWER_DOMAIN_AUX_C,
 184         POWER_DOMAIN_INIT);
 185
 186 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
 187         POWER_DOMAIN_PORT_DDI_LANES_B,
 188         POWER_DOMAIN_PORT_DDI_LANES_C,
 189         POWER_DOMAIN_AUX_B,
 190         POWER_DOMAIN_AUX_C,
 191         POWER_DOMAIN_INIT);
 192
 193 static const struct i915_power_well_desc vlv_power_wells_main[] = {
 194         {
 195                 .instances = &I915_PW_INSTANCES(
 196                         I915_PW("display", &vlv_pwdoms_display,
 197                                 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
 198                                 .id = VLV_DISP_PW_DISP2D),
 199                 ),
 200                 .ops = &vlv_display_power_well_ops,
 201         }, {
 202                 .instances = &I915_PW_INSTANCES(
 203                         I915_PW("dpio-tx-b-01", &vlv_pwdoms_dpio_tx_bc_lanes,
 204                                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
 205                         I915_PW("dpio-tx-b-23", &vlv_pwdoms_dpio_tx_bc_lanes,
 206                                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
 207                         I915_PW("dpio-tx-c-01", &vlv_pwdoms_dpio_tx_bc_lanes,
 208                                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
 209                         I915_PW("dpio-tx-c-23", &vlv_pwdoms_dpio_tx_bc_lanes,
 210                                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
 211                 ),
 212                 .ops = &vlv_dpio_power_well_ops,
 213         }, {
 214                 .instances = &I915_PW_INSTANCES(
 215                         I915_PW("dpio-common", &vlv_pwdoms_dpio_cmn_bc,
 216                                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
 217                                 .id = VLV_DISP_PW_DPIO_CMN_BC),
 218                 ),
 219                 .ops = &vlv_dpio_cmn_power_well_ops,
 220         },
 221 };
 222
 223 static const struct i915_power_well_desc_list vlv_power_wells[] = {
 224         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 225         I915_PW_DESCRIPTORS(vlv_power_wells_main),
 226 };
 227
 228 I915_DECL_PW_DOMAINS(chv_pwdoms_display,
 229         POWER_DOMAIN_DISPLAY_CORE,
 230         POWER_DOMAIN_PIPE_A,
 231         POWER_DOMAIN_PIPE_B,
 232         POWER_DOMAIN_PIPE_C,
 233         POWER_DOMAIN_PIPE_PANEL_FITTER_A,
 234         POWER_DOMAIN_PIPE_PANEL_FITTER_B,
 235         POWER_DOMAIN_PIPE_PANEL_FITTER_C,
 236         POWER_DOMAIN_TRANSCODER_A,
 237         POWER_DOMAIN_TRANSCODER_B,
 238         POWER_DOMAIN_TRANSCODER_C,
 239         POWER_DOMAIN_PORT_DDI_LANES_B,
 240         POWER_DOMAIN_PORT_DDI_LANES_C,
 241         POWER_DOMAIN_PORT_DDI_LANES_D,
 242         POWER_DOMAIN_PORT_DSI,
 243         POWER_DOMAIN_VGA,
 244         POWER_DOMAIN_AUDIO_MMIO,
 245         POWER_DOMAIN_AUDIO_PLAYBACK,
 246         POWER_DOMAIN_AUX_B,
 247         POWER_DOMAIN_AUX_C,
 248         POWER_DOMAIN_AUX_D,
 249         POWER_DOMAIN_GMBUS,
 250         POWER_DOMAIN_INIT);
 251
 252 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
 253         POWER_DOMAIN_PORT_DDI_LANES_B,
 254         POWER_DOMAIN_PORT_DDI_LANES_C,
 255         POWER_DOMAIN_AUX_B,
 256         POWER_DOMAIN_AUX_C,
 257         POWER_DOMAIN_INIT);
 258
 259 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
 260         POWER_DOMAIN_PORT_DDI_LANES_D,
 261         POWER_DOMAIN_AUX_D,
 262         POWER_DOMAIN_INIT);
 263
 264 static const struct i915_power_well_desc chv_power_wells_main[] = {
 265         {
 266                 /*
 267                  * Pipe A power well is the new disp2d well. Pipe B and C
 268                  * power wells don't actually exist. Pipe A power well is
 269                  * required for any pipe to work.
 270                  */
 271                 .instances = &I915_PW_INSTANCES(
 272                         I915_PW("display", &chv_pwdoms_display),
 273                 ),
 274                 .ops = &chv_pipe_power_well_ops,
 275         }, {
 276                 .instances = &I915_PW_INSTANCES(
 277                         I915_PW("dpio-common-bc", &chv_pwdoms_dpio_cmn_bc,
 278                                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
 279                                 .id = VLV_DISP_PW_DPIO_CMN_BC),
 280                         I915_PW("dpio-common-d", &chv_pwdoms_dpio_cmn_d,
 281                                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
 282                                 .id = CHV_DISP_PW_DPIO_CMN_D),
 283                 ),
 284                 .ops = &chv_dpio_cmn_power_well_ops,
 285         },
 286 };
 287
 288 static const struct i915_power_well_desc_list chv_power_wells[] = {
 289         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 290         I915_PW_DESCRIPTORS(chv_power_wells_main),
 291 };
 292
 293 #define SKL_PW_2_POWER_DOMAINS \
 294         POWER_DOMAIN_PIPE_B, \
 295         POWER_DOMAIN_PIPE_C, \
 296         POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
 297         POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
 298         POWER_DOMAIN_TRANSCODER_A, \
 299         POWER_DOMAIN_TRANSCODER_B, \
 300         POWER_DOMAIN_TRANSCODER_C, \
 301         POWER_DOMAIN_PORT_DDI_LANES_B, \
 302         POWER_DOMAIN_PORT_DDI_LANES_C, \
 303         POWER_DOMAIN_PORT_DDI_LANES_D, \
 304         POWER_DOMAIN_PORT_DDI_LANES_E, \
 305         POWER_DOMAIN_VGA, \
 306         POWER_DOMAIN_AUDIO_MMIO, \
 307         POWER_DOMAIN_AUDIO_PLAYBACK, \
 308         POWER_DOMAIN_AUX_B, \
 309         POWER_DOMAIN_AUX_C, \
 310         POWER_DOMAIN_AUX_D
 311
 312 I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
 313         SKL_PW_2_POWER_DOMAINS,
 314         POWER_DOMAIN_INIT);
 315
 316 I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
 317         SKL_PW_2_POWER_DOMAINS,
 318         POWER_DOMAIN_AUX_A,
 319         POWER_DOMAIN_MODESET,
 320         POWER_DOMAIN_GT_IRQ,
 321         POWER_DOMAIN_INIT);
 322
 323 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
 324         POWER_DOMAIN_PORT_DDI_IO_A,
 325         POWER_DOMAIN_PORT_DDI_IO_E,
 326         POWER_DOMAIN_INIT);
 327
 328 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
 329         POWER_DOMAIN_PORT_DDI_IO_B,
 330         POWER_DOMAIN_INIT);
 331
 332 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
 333         POWER_DOMAIN_PORT_DDI_IO_C,
 334         POWER_DOMAIN_INIT);
 335
 336 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
 337         POWER_DOMAIN_PORT_DDI_IO_D,
 338         POWER_DOMAIN_INIT);
 339
 340 static const struct i915_power_well_desc skl_power_wells_pw_1[] = {
 341         {
 342                 /* Handled by the DMC firmware */
 343                 .instances = &I915_PW_INSTANCES(
 344                         I915_PW("PW_1", I915_PW_DOMAINS_NONE,
 345                                 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
 346                                 .id = SKL_DISP_PW_1),
 347                 ),
 348                 .ops = &hsw_power_well_ops,
 349                 .always_on = true,
 350                 .has_fuses = true,
 351         },
 352 };
 353
 354 static const struct i915_power_well_desc skl_power_wells_main[] = {
 355         {
 356                 /* Handled by the DMC firmware */
 357                 .instances = &I915_PW_INSTANCES(
 358                         I915_PW("MISC_IO", I915_PW_DOMAINS_NONE,
 359                                 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
 360                                 .id = SKL_DISP_PW_MISC_IO),
 361                 ),
 362                 .ops = &hsw_power_well_ops,
 363                 .always_on = true,
 364         }, {
 365                 .instances = &I915_PW_INSTANCES(
 366                         I915_PW("DC_off", &skl_pwdoms_dc_off,
 367                                 .id = SKL_DISP_DC_OFF),
 368                 ),
 369                 .ops = &gen9_dc_off_power_well_ops,
 370         }, {
 371                 .instances = &I915_PW_INSTANCES(
 372                         I915_PW("PW_2", &skl_pwdoms_pw_2,
 373                                 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
 374                                 .id = SKL_DISP_PW_2),
 375                 ),
 376                 .ops = &hsw_power_well_ops,
 377                 .has_vga = true,
 378                 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
 379                 .has_fuses = true,
 380         }, {
 381                 .instances = &I915_PW_INSTANCES(
 382                         I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E),
 383                         I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
 384                         I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
 385                         I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D),
 386                 ),
 387                 .ops = &hsw_power_well_ops,
 388         },
 389 };
 390
 391 static const struct i915_power_well_desc_list skl_power_wells[] = {
 392         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 393         I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
 394         I915_PW_DESCRIPTORS(skl_power_wells_main),
 395 };
 396
 397 #define BXT_PW_2_POWER_DOMAINS \
 398         POWER_DOMAIN_PIPE_B, \
 399         POWER_DOMAIN_PIPE_C, \
 400         POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
 401         POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
 402         POWER_DOMAIN_TRANSCODER_A, \
 403         POWER_DOMAIN_TRANSCODER_B, \
 404         POWER_DOMAIN_TRANSCODER_C, \
 405         POWER_DOMAIN_PORT_DDI_LANES_B, \
 406         POWER_DOMAIN_PORT_DDI_LANES_C, \
 407         POWER_DOMAIN_VGA, \
 408         POWER_DOMAIN_AUDIO_MMIO, \
 409         POWER_DOMAIN_AUDIO_PLAYBACK, \
 410         POWER_DOMAIN_AUX_B, \
 411         POWER_DOMAIN_AUX_C
 412
 413 I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
 414         BXT_PW_2_POWER_DOMAINS,
 415         POWER_DOMAIN_INIT);
 416
 417 I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
 418         BXT_PW_2_POWER_DOMAINS,
 419         POWER_DOMAIN_AUX_A,
 420         POWER_DOMAIN_GMBUS,
 421         POWER_DOMAIN_MODESET,
 422         POWER_DOMAIN_GT_IRQ,
 423         POWER_DOMAIN_INIT);
 424
 425 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
 426         POWER_DOMAIN_PORT_DDI_LANES_A,
 427         POWER_DOMAIN_AUX_A,
 428         POWER_DOMAIN_INIT);
 429
 430 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
 431         POWER_DOMAIN_PORT_DDI_LANES_B,
 432         POWER_DOMAIN_PORT_DDI_LANES_C,
 433         POWER_DOMAIN_AUX_B,
 434         POWER_DOMAIN_AUX_C,
 435         POWER_DOMAIN_INIT);
 436
 437 static const struct i915_power_well_desc bxt_power_wells_main[] = {
 438         {
 439                 .instances = &I915_PW_INSTANCES(
 440                         I915_PW("DC_off", &bxt_pwdoms_dc_off,
 441                                 .id = SKL_DISP_DC_OFF),
 442                 ),
 443                 .ops = &gen9_dc_off_power_well_ops,
 444         }, {
 445                 .instances = &I915_PW_INSTANCES(
 446                         I915_PW("PW_2", &bxt_pwdoms_pw_2,
 447                                 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
 448                                 .id = SKL_DISP_PW_2),
 449                 ),
 450                 .ops = &hsw_power_well_ops,
 451                 .has_vga = true,
 452                 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
 453                 .has_fuses = true,
 454         }, {
 455                 .instances = &I915_PW_INSTANCES(
 456                         I915_PW("dpio-common-a", &bxt_pwdoms_dpio_cmn_a,
 457                                 .bxt.phy = DPIO_PHY1,
 458                                 .id = BXT_DISP_PW_DPIO_CMN_A),
 459                         I915_PW("dpio-common-bc", &bxt_pwdoms_dpio_cmn_bc,
 460                                 .bxt.phy = DPIO_PHY0,
 461                                 .id = VLV_DISP_PW_DPIO_CMN_BC),
 462                 ),
 463                 .ops = &bxt_dpio_cmn_power_well_ops,
 464         },
 465 };
 466
 467 static const struct i915_power_well_desc_list bxt_power_wells[] = {
 468         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 469         I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
 470         I915_PW_DESCRIPTORS(bxt_power_wells_main),
 471 };
 472
 473 #define GLK_PW_2_POWER_DOMAINS \
 474         POWER_DOMAIN_PIPE_B, \
 475         POWER_DOMAIN_PIPE_C, \
 476         POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
 477         POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
 478         POWER_DOMAIN_TRANSCODER_A, \
 479         POWER_DOMAIN_TRANSCODER_B, \
 480         POWER_DOMAIN_TRANSCODER_C, \
 481         POWER_DOMAIN_PORT_DDI_LANES_B, \
 482         POWER_DOMAIN_PORT_DDI_LANES_C, \
 483         POWER_DOMAIN_VGA, \
 484         POWER_DOMAIN_AUDIO_MMIO, \
 485         POWER_DOMAIN_AUDIO_PLAYBACK, \
 486         POWER_DOMAIN_AUX_B, \
 487         POWER_DOMAIN_AUX_C
 488
 489 I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
 490         GLK_PW_2_POWER_DOMAINS,
 491         POWER_DOMAIN_INIT);
 492
 493 I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
 494         GLK_PW_2_POWER_DOMAINS,
 495         POWER_DOMAIN_AUX_A,
 496         POWER_DOMAIN_GMBUS,
 497         POWER_DOMAIN_MODESET,
 498         POWER_DOMAIN_GT_IRQ,
 499         POWER_DOMAIN_INIT);
 500
 501 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a,       POWER_DOMAIN_PORT_DDI_IO_A);
 502 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b,       POWER_DOMAIN_PORT_DDI_IO_B);
 503 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c,       POWER_DOMAIN_PORT_DDI_IO_C);
 504
 505 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
 506         POWER_DOMAIN_PORT_DDI_LANES_A,
 507         POWER_DOMAIN_AUX_A,
 508         POWER_DOMAIN_INIT);
 509
 510 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
 511         POWER_DOMAIN_PORT_DDI_LANES_B,
 512         POWER_DOMAIN_AUX_B,
 513         POWER_DOMAIN_INIT);
 514
 515 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
 516         POWER_DOMAIN_PORT_DDI_LANES_C,
 517         POWER_DOMAIN_AUX_C,
 518         POWER_DOMAIN_INIT);
 519
 520 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
 521         POWER_DOMAIN_AUX_A,
 522         POWER_DOMAIN_AUX_IO_A,
 523         POWER_DOMAIN_INIT);
 524
 525 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
 526         POWER_DOMAIN_AUX_B,
 527         POWER_DOMAIN_INIT);
 528
 529 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
 530         POWER_DOMAIN_AUX_C,
 531         POWER_DOMAIN_INIT);
 532
 533 static const struct i915_power_well_desc glk_power_wells_main[] = {
 534         {
 535                 .instances = &I915_PW_INSTANCES(
 536                         I915_PW("DC_off", &glk_pwdoms_dc_off,
 537                                 .id = SKL_DISP_DC_OFF),
 538                 ),
 539                 .ops = &gen9_dc_off_power_well_ops,
 540         }, {
 541                 .instances = &I915_PW_INSTANCES(
 542                         I915_PW("PW_2", &glk_pwdoms_pw_2,
 543                                 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
 544                                 .id = SKL_DISP_PW_2),
 545                 ),
 546                 .ops = &hsw_power_well_ops,
 547                 .has_vga = true,
 548                 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
 549                 .has_fuses = true,
 550         }, {
 551                 .instances = &I915_PW_INSTANCES(
 552                         I915_PW("dpio-common-a", &glk_pwdoms_dpio_cmn_a,
 553                                 .bxt.phy = DPIO_PHY1,
 554                                 .id = BXT_DISP_PW_DPIO_CMN_A),
 555                         I915_PW("dpio-common-b", &glk_pwdoms_dpio_cmn_b,
 556                                 .bxt.phy = DPIO_PHY0,
 557                                 .id = VLV_DISP_PW_DPIO_CMN_BC),
 558                         I915_PW("dpio-common-c", &glk_pwdoms_dpio_cmn_c,
 559                                 .bxt.phy = DPIO_PHY2,
 560                                 .id = GLK_DISP_PW_DPIO_CMN_C),
 561                 ),
 562                 .ops = &bxt_dpio_cmn_power_well_ops,
 563         }, {
 564                 .instances = &I915_PW_INSTANCES(
 565                         I915_PW("AUX_A", &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A),
 566                         I915_PW("AUX_B", &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B),
 567                         I915_PW("AUX_C", &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C),
 568                         I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A),
 569                         I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
 570                         I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
 571                 ),
 572                 .ops = &hsw_power_well_ops,
 573         },
 574 };
 575
 576 static const struct i915_power_well_desc_list glk_power_wells[] = {
 577         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 578         I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
 579         I915_PW_DESCRIPTORS(glk_power_wells_main),
 580 };
 581
 582 /*
 583  * ICL PW_0/PG_0 domains (HW/DMC control):
 584  * - PCI
 585  * - clocks except port PLL
 586  * - central power except FBC
 587  * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
 588  * ICL PW_1/PG_1 domains (HW/DMC control):
 589  * - DBUF function
 590  * - PIPE_A and its planes, except VGA
 591  * - transcoder EDP + PSR
 592  * - transcoder DSI
 593  * - DDI_A
 594  * - FBC
 595  */
 596 #define ICL_PW_4_POWER_DOMAINS \
 597         POWER_DOMAIN_PIPE_C, \
 598         POWER_DOMAIN_PIPE_PANEL_FITTER_C
 599
 600 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
 601         ICL_PW_4_POWER_DOMAINS,
 602         POWER_DOMAIN_INIT);
 603         /* VDSC/joining */
 604
 605 #define ICL_PW_3_POWER_DOMAINS \
 606         ICL_PW_4_POWER_DOMAINS, \
 607         POWER_DOMAIN_PIPE_B, \
 608         POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
 609         POWER_DOMAIN_TRANSCODER_A, \
 610         POWER_DOMAIN_TRANSCODER_B, \
 611         POWER_DOMAIN_TRANSCODER_C, \
 612         POWER_DOMAIN_PORT_DDI_LANES_B, \
 613         POWER_DOMAIN_PORT_DDI_LANES_C, \
 614         POWER_DOMAIN_PORT_DDI_LANES_D, \
 615         POWER_DOMAIN_PORT_DDI_LANES_E, \
 616         POWER_DOMAIN_PORT_DDI_LANES_F, \
 617         POWER_DOMAIN_VGA, \
 618         POWER_DOMAIN_AUDIO_MMIO, \
 619         POWER_DOMAIN_AUDIO_PLAYBACK, \
 620         POWER_DOMAIN_AUX_B, \
 621         POWER_DOMAIN_AUX_C, \
 622         POWER_DOMAIN_AUX_D, \
 623         POWER_DOMAIN_AUX_E, \
 624         POWER_DOMAIN_AUX_F, \
 625         POWER_DOMAIN_AUX_TBT1, \
 626         POWER_DOMAIN_AUX_TBT2, \
 627         POWER_DOMAIN_AUX_TBT3, \
 628         POWER_DOMAIN_AUX_TBT4
 629
 630 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
 631         ICL_PW_3_POWER_DOMAINS,
 632         POWER_DOMAIN_INIT);
 633         /*
 634          * - transcoder WD
 635          * - KVMR (HW control)
 636          */
 637
 638 #define ICL_PW_2_POWER_DOMAINS \
 639         ICL_PW_3_POWER_DOMAINS, \
 640         POWER_DOMAIN_TRANSCODER_VDSC_PW2
 641
 642 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
 643         ICL_PW_2_POWER_DOMAINS,
 644         POWER_DOMAIN_INIT);
 645         /*
 646          * - KVMR (HW control)
 647          */
 648
 649 I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
 650         ICL_PW_2_POWER_DOMAINS,
 651         POWER_DOMAIN_AUX_A,
 652         POWER_DOMAIN_MODESET,
 653         POWER_DOMAIN_DC_OFF,
 654         POWER_DOMAIN_INIT);
 655
 656 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d,       POWER_DOMAIN_PORT_DDI_IO_D);
 657 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e,       POWER_DOMAIN_PORT_DDI_IO_E);
 658 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,       POWER_DOMAIN_PORT_DDI_IO_F);
 659
 660 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
 661         POWER_DOMAIN_AUX_A,
 662         POWER_DOMAIN_AUX_IO_A);
 663 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,          POWER_DOMAIN_AUX_B);
 664 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,          POWER_DOMAIN_AUX_C);
 665 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,          POWER_DOMAIN_AUX_D);
 666 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,          POWER_DOMAIN_AUX_E);
 667 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,          POWER_DOMAIN_AUX_F);
 668 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,       POWER_DOMAIN_AUX_TBT1);
 669 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,       POWER_DOMAIN_AUX_TBT2);
 670 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,       POWER_DOMAIN_AUX_TBT3);
 671 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4,       POWER_DOMAIN_AUX_TBT4);
 672
 673 static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
 674         {
 675                 /* Handled by the DMC firmware */
 676                 .instances = &I915_PW_INSTANCES(
 677                         I915_PW("PW_1", I915_PW_DOMAINS_NONE,
 678                                 .hsw.idx = ICL_PW_CTL_IDX_PW_1,
 679                                 .id = SKL_DISP_PW_1),
 680                 ),
 681                 .ops = &hsw_power_well_ops,
 682                 .always_on = true,
 683                 .has_fuses = true,
 684         },
 685 };
 686
 687 static const struct i915_power_well_desc icl_power_wells_main[] = {
 688         {
 689                 .instances = &I915_PW_INSTANCES(
 690                         I915_PW("DC_off", &icl_pwdoms_dc_off,
 691                                 .id = SKL_DISP_DC_OFF),
 692                 ),
 693                 .ops = &gen9_dc_off_power_well_ops,
 694         }, {
 695                 .instances = &I915_PW_INSTANCES(
 696                         I915_PW("PW_2", &icl_pwdoms_pw_2,
 697                                 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
 698                                 .id = SKL_DISP_PW_2),
 699                 ),
 700                 .ops = &hsw_power_well_ops,
 701                 .has_fuses = true,
 702         }, {
 703                 .instances = &I915_PW_INSTANCES(
 704                         I915_PW("PW_3", &icl_pwdoms_pw_3,
 705                                 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
 706                                 .id = ICL_DISP_PW_3),
 707                 ),
 708                 .ops = &hsw_power_well_ops,
 709                 .has_vga = true,
 710                 .irq_pipe_mask = BIT(PIPE_B),
 711                 .has_fuses = true,
 712         }, {
 713                 .instances = &I915_PW_INSTANCES(
 714                         I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
 715                         I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
 716                         I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
 717                         I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D),
 718                         I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E),
 719                         I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F),
 720                 ),
 721                 .ops = &icl_ddi_power_well_ops,
 722         }, {
 723                 .instances = &I915_PW_INSTANCES(
 724                         I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
 725                         I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
 726                         I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
 727                         I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D),
 728                         I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E),
 729                         I915_PW("AUX_F", &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F),
 730                 ),
 731                 .ops = &icl_aux_power_well_ops,
 732         }, {
 733                 .instances = &I915_PW_INSTANCES(
 734                         I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1),
 735                         I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2),
 736                         I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3),
 737                         I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4),
 738                 ),
 739                 .ops = &icl_aux_power_well_ops,
 740                 .is_tc_tbt = true,
 741         }, {
 742                 .instances = &I915_PW_INSTANCES(
 743                         I915_PW("PW_4", &icl_pwdoms_pw_4,
 744                                 .hsw.idx = ICL_PW_CTL_IDX_PW_4),
 745                 ),
 746                 .ops = &hsw_power_well_ops,
 747                 .irq_pipe_mask = BIT(PIPE_C),
 748                 .has_fuses = true,
 749         },
 750 };
 751
 752 static const struct i915_power_well_desc_list icl_power_wells[] = {
 753         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 754         I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
 755         I915_PW_DESCRIPTORS(icl_power_wells_main),
 756 };
 757
 758 #define TGL_PW_5_POWER_DOMAINS \
 759         POWER_DOMAIN_PIPE_D, \
 760         POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
 761         POWER_DOMAIN_TRANSCODER_D
 762
 763 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
 764         TGL_PW_5_POWER_DOMAINS,
 765         POWER_DOMAIN_INIT);
 766
 767 #define TGL_PW_4_POWER_DOMAINS \
 768         TGL_PW_5_POWER_DOMAINS, \
 769         POWER_DOMAIN_PIPE_C, \
 770         POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
 771         POWER_DOMAIN_TRANSCODER_C
 772
 773 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
 774         TGL_PW_4_POWER_DOMAINS,
 775         POWER_DOMAIN_INIT);
 776
 777 #define TGL_PW_3_POWER_DOMAINS \
 778         TGL_PW_4_POWER_DOMAINS, \
 779         POWER_DOMAIN_PIPE_B, \
 780         POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
 781         POWER_DOMAIN_TRANSCODER_B, \
 782         POWER_DOMAIN_PORT_DDI_LANES_TC1, \
 783         POWER_DOMAIN_PORT_DDI_LANES_TC2, \
 784         POWER_DOMAIN_PORT_DDI_LANES_TC3, \
 785         POWER_DOMAIN_PORT_DDI_LANES_TC4, \
 786         POWER_DOMAIN_PORT_DDI_LANES_TC5, \
 787         POWER_DOMAIN_PORT_DDI_LANES_TC6, \
 788         POWER_DOMAIN_VGA, \
 789         POWER_DOMAIN_AUDIO_MMIO, \
 790         POWER_DOMAIN_AUDIO_PLAYBACK, \
 791         POWER_DOMAIN_AUX_USBC1, \
 792         POWER_DOMAIN_AUX_USBC2, \
 793         POWER_DOMAIN_AUX_USBC3, \
 794         POWER_DOMAIN_AUX_USBC4, \
 795         POWER_DOMAIN_AUX_USBC5, \
 796         POWER_DOMAIN_AUX_USBC6, \
 797         POWER_DOMAIN_AUX_TBT1, \
 798         POWER_DOMAIN_AUX_TBT2, \
 799         POWER_DOMAIN_AUX_TBT3, \
 800         POWER_DOMAIN_AUX_TBT4, \
 801         POWER_DOMAIN_AUX_TBT5, \
 802         POWER_DOMAIN_AUX_TBT6
 803
 804 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
 805         TGL_PW_3_POWER_DOMAINS,
 806         POWER_DOMAIN_INIT);
 807
 808 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
 809         TGL_PW_3_POWER_DOMAINS,
 810         POWER_DOMAIN_TRANSCODER_VDSC_PW2,
 811         POWER_DOMAIN_INIT);
 812
 813 I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
 814         TGL_PW_3_POWER_DOMAINS,
 815         POWER_DOMAIN_AUX_A,
 816         POWER_DOMAIN_AUX_B,
 817         POWER_DOMAIN_AUX_C,
 818         POWER_DOMAIN_MODESET,
 819         POWER_DOMAIN_INIT);
 820
 821 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1,     POWER_DOMAIN_PORT_DDI_IO_TC1);
 822 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2,     POWER_DOMAIN_PORT_DDI_IO_TC2);
 823 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3,     POWER_DOMAIN_PORT_DDI_IO_TC3);
 824 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4,     POWER_DOMAIN_PORT_DDI_IO_TC4);
 825 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5,     POWER_DOMAIN_PORT_DDI_IO_TC5);
 826 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6,     POWER_DOMAIN_PORT_DDI_IO_TC6);
 827
 828 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1,      POWER_DOMAIN_AUX_USBC1);
 829 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2,      POWER_DOMAIN_AUX_USBC2);
 830 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3,      POWER_DOMAIN_AUX_USBC3);
 831 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4,      POWER_DOMAIN_AUX_USBC4);
 832 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5,      POWER_DOMAIN_AUX_USBC5);
 833 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6,      POWER_DOMAIN_AUX_USBC6);
 834
 835 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5,       POWER_DOMAIN_AUX_TBT5);
 836 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6,       POWER_DOMAIN_AUX_TBT6);
 837
 838 I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
 839         POWER_DOMAIN_AUX_USBC1,
 840         POWER_DOMAIN_AUX_USBC2,
 841         POWER_DOMAIN_AUX_USBC3,
 842         POWER_DOMAIN_AUX_USBC4,
 843         POWER_DOMAIN_AUX_USBC5,
 844         POWER_DOMAIN_AUX_USBC6,
 845         POWER_DOMAIN_AUX_TBT1,
 846         POWER_DOMAIN_AUX_TBT2,
 847         POWER_DOMAIN_AUX_TBT3,
 848         POWER_DOMAIN_AUX_TBT4,
 849         POWER_DOMAIN_AUX_TBT5,
 850         POWER_DOMAIN_AUX_TBT6,
 851         POWER_DOMAIN_TC_COLD_OFF);
 852
 853 static const struct i915_power_well_desc tgl_power_wells_main[] = {
 854         {
 855                 .instances = &I915_PW_INSTANCES(
 856                         I915_PW("DC_off", &tgl_pwdoms_dc_off,
 857                                 .id = SKL_DISP_DC_OFF),
 858                 ),
 859                 .ops = &gen9_dc_off_power_well_ops,
 860         }, {
 861                 .instances = &I915_PW_INSTANCES(
 862                         I915_PW("PW_2", &tgl_pwdoms_pw_2,
 863                                 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
 864                                 .id = SKL_DISP_PW_2),
 865                 ),
 866                 .ops = &hsw_power_well_ops,
 867                 .has_fuses = true,
 868         }, {
 869                 .instances = &I915_PW_INSTANCES(
 870                         I915_PW("PW_3", &tgl_pwdoms_pw_3,
 871                                 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
 872                                 .id = ICL_DISP_PW_3),
 873                 ),
 874                 .ops = &hsw_power_well_ops,
 875                 .has_vga = true,
 876                 .irq_pipe_mask = BIT(PIPE_B),
 877                 .has_fuses = true,
 878         }, {
 879                 .instances = &I915_PW_INSTANCES(
 880                         I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
 881                         I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
 882                         I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
 883                         I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
 884                         I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
 885                         I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
 886                         I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
 887                         I915_PW("DDI_IO_TC5", &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5),
 888                         I915_PW("DDI_IO_TC6", &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6),
 889                 ),
 890                 .ops = &icl_ddi_power_well_ops,
 891         }, {
 892                 .instances = &I915_PW_INSTANCES(
 893                         I915_PW("PW_4", &tgl_pwdoms_pw_4,
 894                                 .hsw.idx = ICL_PW_CTL_IDX_PW_4),
 895                 ),
 896                 .ops = &hsw_power_well_ops,
 897                 .has_fuses = true,
 898                 .irq_pipe_mask = BIT(PIPE_C),
 899         }, {
 900                 .instances = &I915_PW_INSTANCES(
 901                         I915_PW("PW_5", &tgl_pwdoms_pw_5,
 902                                 .hsw.idx = TGL_PW_CTL_IDX_PW_5),
 903                 ),
 904                 .ops = &hsw_power_well_ops,
 905                 .has_fuses = true,
 906                 .irq_pipe_mask = BIT(PIPE_D),
 907         },
 908 };
 909
 910 static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = {
 911         {
 912                 .instances = &I915_PW_INSTANCES(
 913                         I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off,
 914                                 .id = TGL_DISP_PW_TC_COLD_OFF),
 915                 ),
 916                 .ops = &tgl_tc_cold_off_ops,
 917         },
 918 };
 919
 920 static const struct i915_power_well_desc tgl_power_wells_aux[] = {
 921         {
 922                 .instances = &I915_PW_INSTANCES(
 923                         I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
 924                         I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
 925                         I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
 926                         I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
 927                         I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
 928                         I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
 929                         I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
 930                         I915_PW("AUX_USBC5", &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5),
 931                         I915_PW("AUX_USBC6", &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6),
 932                 ),
 933                 .ops = &icl_aux_power_well_ops,
 934         }, {
 935                 .instances = &I915_PW_INSTANCES(
 936                         I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
 937                         I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
 938                         I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
 939                         I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
 940                         I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5),
 941                         I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6),
 942                 ),
 943                 .ops = &icl_aux_power_well_ops,
 944                 .is_tc_tbt = true,
 945         },
 946 };
 947
 948 static const struct i915_power_well_desc_list tgl_power_wells[] = {
 949         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 950         I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
 951         I915_PW_DESCRIPTORS(tgl_power_wells_main),
 952         I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off),
 953         I915_PW_DESCRIPTORS(tgl_power_wells_aux),
 954 };
 955
 956 static const struct i915_power_well_desc_list adls_power_wells[] = {
 957         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
 958         I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
 959         I915_PW_DESCRIPTORS(tgl_power_wells_main),
 960         I915_PW_DESCRIPTORS(tgl_power_wells_aux),
 961 };
 962
 963 #define RKL_PW_4_POWER_DOMAINS \
 964         POWER_DOMAIN_PIPE_C, \
 965         POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
 966         POWER_DOMAIN_TRANSCODER_C
 967
 968 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
 969         RKL_PW_4_POWER_DOMAINS,
 970         POWER_DOMAIN_INIT);
 971
 972 #define RKL_PW_3_POWER_DOMAINS \
 973         RKL_PW_4_POWER_DOMAINS, \
 974         POWER_DOMAIN_PIPE_B, \
 975         POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
 976         POWER_DOMAIN_TRANSCODER_B, \
 977         POWER_DOMAIN_PORT_DDI_LANES_TC1, \
 978         POWER_DOMAIN_PORT_DDI_LANES_TC2, \
 979         POWER_DOMAIN_VGA, \
 980         POWER_DOMAIN_AUDIO_MMIO, \
 981         POWER_DOMAIN_AUDIO_PLAYBACK, \
 982         POWER_DOMAIN_AUX_USBC1, \
 983         POWER_DOMAIN_AUX_USBC2
 984
 985 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
 986         RKL_PW_3_POWER_DOMAINS,
 987         POWER_DOMAIN_INIT);
 988
 989 /*
 990  * There is no PW_2/PG_2 on RKL.
 991  *
 992  * RKL PW_1/PG_1 domains (under HW/DMC control):
 993  * - DBUF function (note: registers are in PW0)
 994  * - PIPE_A and its planes and VDSC/joining, except VGA
 995  * - transcoder A
 996  * - DDI_A and DDI_B
 997  * - FBC
 998  *
 999  * RKL PW_0/PG_0 domains (under HW/DMC control):
1000  * - PCI
1001  * - clocks except port PLL
1002  * - shared functions:
1003  *     * interrupts except pipe interrupts
1004  *     * MBus except PIPE_MBUS_DBOX_CTL
1005  *     * DBUF registers
1006  * - central power except FBC
1007  * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
1008  */
1009
1010 I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
1011         RKL_PW_3_POWER_DOMAINS,
1012         POWER_DOMAIN_AUX_A,
1013         POWER_DOMAIN_AUX_B,
1014         POWER_DOMAIN_MODESET,
1015         POWER_DOMAIN_INIT);
1016
1017 static const struct i915_power_well_desc rkl_power_wells_main[] = {
1018         {
1019                 .instances = &I915_PW_INSTANCES(
1020                         I915_PW("DC_off", &rkl_pwdoms_dc_off,
1021                                 .id = SKL_DISP_DC_OFF),
1022                 ),
1023                 .ops = &gen9_dc_off_power_well_ops,
1024         }, {
1025                 .instances = &I915_PW_INSTANCES(
1026                         I915_PW("PW_3", &rkl_pwdoms_pw_3,
1027                                 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
1028                                 .id = ICL_DISP_PW_3),
1029                 ),
1030                 .ops = &hsw_power_well_ops,
1031                 .irq_pipe_mask = BIT(PIPE_B),
1032                 .has_vga = true,
1033                 .has_fuses = true,
1034         }, {
1035                 .instances = &I915_PW_INSTANCES(
1036                         I915_PW("PW_4", &rkl_pwdoms_pw_4,
1037                                 .hsw.idx = ICL_PW_CTL_IDX_PW_4),
1038                 ),
1039                 .ops = &hsw_power_well_ops,
1040                 .has_fuses = true,
1041                 .irq_pipe_mask = BIT(PIPE_C),
1042         },
1043 };
1044
1045 static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = {
1046         {
1047                 .instances = &I915_PW_INSTANCES(
1048                         I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
1049                         I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
1050                         I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
1051                         I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
1052                 ),
1053                 .ops = &icl_ddi_power_well_ops,
1054         }, {
1055                 .instances = &I915_PW_INSTANCES(
1056                         I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
1057                         I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
1058                         I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
1059                         I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
1060                 ),
1061                 .ops = &icl_aux_power_well_ops,
1062         },
1063 };
1064
1065 static const struct i915_power_well_desc_list rkl_power_wells[] = {
1066         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1067         I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1068         I915_PW_DESCRIPTORS(rkl_power_wells_main),
1069         I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
1070 };
1071
1072 /*
1073  * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
1074  */
1075 #define DG1_PW_3_POWER_DOMAINS \
1076         TGL_PW_4_POWER_DOMAINS, \
1077         POWER_DOMAIN_PIPE_B, \
1078         POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
1079         POWER_DOMAIN_TRANSCODER_B, \
1080         POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1081         POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1082         POWER_DOMAIN_VGA, \
1083         POWER_DOMAIN_AUDIO_PLAYBACK, \
1084         POWER_DOMAIN_AUX_USBC1, \
1085         POWER_DOMAIN_AUX_USBC2
1086
1087 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
1088         DG1_PW_3_POWER_DOMAINS,
1089         POWER_DOMAIN_INIT);
1090
1091 I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
1092         DG1_PW_3_POWER_DOMAINS,
1093         POWER_DOMAIN_AUDIO_MMIO,
1094         POWER_DOMAIN_AUX_A,
1095         POWER_DOMAIN_AUX_B,
1096         POWER_DOMAIN_MODESET,
1097         POWER_DOMAIN_INIT);
1098
1099 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
1100         DG1_PW_3_POWER_DOMAINS,
1101         POWER_DOMAIN_TRANSCODER_VDSC_PW2,
1102         POWER_DOMAIN_INIT);
1103
1104 static const struct i915_power_well_desc dg1_power_wells_main[] = {
1105         {
1106                 .instances = &I915_PW_INSTANCES(
1107                         I915_PW("DC_off", &dg1_pwdoms_dc_off,
1108                                 .id = SKL_DISP_DC_OFF),
1109                 ),
1110                 .ops = &gen9_dc_off_power_well_ops,
1111         }, {
1112                 .instances = &I915_PW_INSTANCES(
1113                         I915_PW("PW_2", &dg1_pwdoms_pw_2,
1114                                 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
1115                                 .id = SKL_DISP_PW_2),
1116                 ),
1117                 .ops = &hsw_power_well_ops,
1118                 .has_fuses = true,
1119         }, {
1120                 .instances = &I915_PW_INSTANCES(
1121                         I915_PW("PW_3", &dg1_pwdoms_pw_3,
1122                                 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
1123                                 .id = ICL_DISP_PW_3),
1124                 ),
1125                 .ops = &hsw_power_well_ops,
1126                 .irq_pipe_mask = BIT(PIPE_B),
1127                 .has_vga = true,
1128                 .has_fuses = true,
1129         }, {
1130                 .instances = &I915_PW_INSTANCES(
1131                         I915_PW("PW_4", &tgl_pwdoms_pw_4,
1132                                 .hsw.idx = ICL_PW_CTL_IDX_PW_4),
1133                 ),
1134                 .ops = &hsw_power_well_ops,
1135                 .has_fuses = true,
1136                 .irq_pipe_mask = BIT(PIPE_C),
1137         }, {
1138                 .instances = &I915_PW_INSTANCES(
1139                         I915_PW("PW_5", &tgl_pwdoms_pw_5,
1140                                 .hsw.idx = TGL_PW_CTL_IDX_PW_5),
1141                 ),
1142                 .ops = &hsw_power_well_ops,
1143                 .has_fuses = true,
1144                 .irq_pipe_mask = BIT(PIPE_D),
1145         },
1146 };
1147
1148 static const struct i915_power_well_desc_list dg1_power_wells[] = {
1149         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1150         I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1151         I915_PW_DESCRIPTORS(dg1_power_wells_main),
1152         I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
1153 };
1154
1155 /*
1156  * XE_LPD Power Domains
1157  *
1158  * Previous platforms required that PG(n-1) be enabled before PG(n).  That
1159  * dependency chain turns into a dependency tree on XE_LPD:
1160  *
1161  *       PG0
1162  *        |
1163  *     --PG1--
1164  *    /       \
1165  *  PGA     --PG2--
1166  *         /   |   \
1167  *       PGB  PGC  PGD
1168  *
1169  * Power wells must be enabled from top to bottom and disabled from bottom
1170  * to top.  This allows pipes to be power gated independently.
1171  */
1172
1173 #define XELPD_PW_D_POWER_DOMAINS \
1174         POWER_DOMAIN_PIPE_D, \
1175         POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
1176         POWER_DOMAIN_TRANSCODER_D
1177
1178 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
1179         XELPD_PW_D_POWER_DOMAINS,
1180         POWER_DOMAIN_INIT);
1181
1182 #define XELPD_PW_C_POWER_DOMAINS \
1183         POWER_DOMAIN_PIPE_C, \
1184         POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
1185         POWER_DOMAIN_TRANSCODER_C
1186
1187 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
1188         XELPD_PW_C_POWER_DOMAINS,
1189         POWER_DOMAIN_INIT);
1190
1191 #define XELPD_PW_B_POWER_DOMAINS \
1192         POWER_DOMAIN_PIPE_B, \
1193         POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
1194         POWER_DOMAIN_TRANSCODER_B
1195
1196 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
1197         XELPD_PW_B_POWER_DOMAINS,
1198         POWER_DOMAIN_INIT);
1199
1200 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
1201         POWER_DOMAIN_PIPE_A,
1202         POWER_DOMAIN_PIPE_PANEL_FITTER_A,
1203         POWER_DOMAIN_INIT);
1204
1205 #define XELPD_PW_2_POWER_DOMAINS \
1206         XELPD_PW_B_POWER_DOMAINS, \
1207         XELPD_PW_C_POWER_DOMAINS, \
1208         XELPD_PW_D_POWER_DOMAINS, \
1209         POWER_DOMAIN_PORT_DDI_LANES_C, \
1210         POWER_DOMAIN_PORT_DDI_LANES_D, \
1211         POWER_DOMAIN_PORT_DDI_LANES_E, \
1212         POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1213         POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1214         POWER_DOMAIN_PORT_DDI_LANES_TC3, \
1215         POWER_DOMAIN_PORT_DDI_LANES_TC4, \
1216         POWER_DOMAIN_VGA, \
1217         POWER_DOMAIN_AUDIO_PLAYBACK, \
1218         POWER_DOMAIN_AUX_C, \
1219         POWER_DOMAIN_AUX_D, \
1220         POWER_DOMAIN_AUX_E, \
1221         POWER_DOMAIN_AUX_USBC1, \
1222         POWER_DOMAIN_AUX_USBC2, \
1223         POWER_DOMAIN_AUX_USBC3, \
1224         POWER_DOMAIN_AUX_USBC4, \
1225         POWER_DOMAIN_AUX_TBT1, \
1226         POWER_DOMAIN_AUX_TBT2, \
1227         POWER_DOMAIN_AUX_TBT3, \
1228         POWER_DOMAIN_AUX_TBT4
1229
1230 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
1231         XELPD_PW_2_POWER_DOMAINS,
1232         POWER_DOMAIN_INIT);
1233
1234 /*
1235  * XELPD PW_1/PG_1 domains (under HW/DMC control):
1236  *  - DBUF function (registers are in PW0)
1237  *  - Transcoder A
1238  *  - DDI_A and DDI_B
1239  *
1240  * XELPD PW_0/PW_1 domains (under HW/DMC control):
1241  *  - PCI
1242  *  - Clocks except port PLL
1243  *  - Shared functions:
1244  *     * interrupts except pipe interrupts
1245  *     * MBus except PIPE_MBUS_DBOX_CTL
1246  *     * DBUF registers
1247  *  - Central power except FBC
1248  *  - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
1249  */
1250
1251 I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
1252         XELPD_PW_2_POWER_DOMAINS,
1253         POWER_DOMAIN_PORT_DSI,
1254         POWER_DOMAIN_AUDIO_MMIO,
1255         POWER_DOMAIN_AUX_A,
1256         POWER_DOMAIN_AUX_B,
1257         POWER_DOMAIN_MODESET,
1258         POWER_DOMAIN_INIT);
1259
1260 static const struct i915_power_well_desc xelpd_power_wells_main[] = {
1261         {
1262                 .instances = &I915_PW_INSTANCES(
1263                         I915_PW("DC_off", &xelpd_pwdoms_dc_off,
1264                                 .id = SKL_DISP_DC_OFF),
1265                 ),
1266                 .ops = &gen9_dc_off_power_well_ops,
1267         }, {
1268                 .instances = &I915_PW_INSTANCES(
1269                         I915_PW("PW_2", &xelpd_pwdoms_pw_2,
1270                                 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
1271                                 .id = SKL_DISP_PW_2),
1272                 ),
1273                 .ops = &hsw_power_well_ops,
1274                 .has_vga = true,
1275                 .has_fuses = true,
1276         }, {
1277                 .instances = &I915_PW_INSTANCES(
1278                         I915_PW("PW_A", &xelpd_pwdoms_pw_a,
1279                                 .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
1280                 ),
1281                 .ops = &hsw_power_well_ops,
1282                 .irq_pipe_mask = BIT(PIPE_A),
1283                 .has_fuses = true,
1284         }, {
1285                 .instances = &I915_PW_INSTANCES(
1286                         I915_PW("PW_B", &xelpd_pwdoms_pw_b,
1287                                 .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
1288                 ),
1289                 .ops = &hsw_power_well_ops,
1290                 .irq_pipe_mask = BIT(PIPE_B),
1291                 .has_fuses = true,
1292         }, {
1293                 .instances = &I915_PW_INSTANCES(
1294                         I915_PW("PW_C", &xelpd_pwdoms_pw_c,
1295                                 .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
1296                 ),
1297                 .ops = &hsw_power_well_ops,
1298                 .irq_pipe_mask = BIT(PIPE_C),
1299                 .has_fuses = true,
1300         }, {
1301                 .instances = &I915_PW_INSTANCES(
1302                         I915_PW("PW_D", &xelpd_pwdoms_pw_d,
1303                                 .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
1304                 ),
1305                 .ops = &hsw_power_well_ops,
1306                 .irq_pipe_mask = BIT(PIPE_D),
1307                 .has_fuses = true,
1308         }, {
1309                 .instances = &I915_PW_INSTANCES(
1310                         I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
1311                         I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
1312                         I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
1313                         I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
1314                         I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
1315                         I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
1316                         I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
1317                         I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
1318                         I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
1319                 ),
1320                 .ops = &icl_ddi_power_well_ops,
1321         }, {
1322                 .instances = &I915_PW_INSTANCES(
1323                         I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
1324                         I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
1325                         I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
1326                         I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
1327                         I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
1328                         I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
1329                         I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
1330                         I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
1331                         I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
1332                 ),
1333                 .ops = &icl_aux_power_well_ops,
1334                 .fixed_enable_delay = true,
1335         }, {
1336                 .instances = &I915_PW_INSTANCES(
1337                         I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
1338                         I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
1339                         I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
1340                         I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
1341                 ),
1342                 .ops = &icl_aux_power_well_ops,
1343                 .is_tc_tbt = true,
1344         },
1345 };
1346
1347 static const struct i915_power_well_desc_list xelpd_power_wells[] = {
1348         I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1349         I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1350         I915_PW_DESCRIPTORS(xelpd_power_wells_main),
1351 };
1352
1353 static void init_power_well_domains(const struct i915_power_well_instance *inst,
1354                                     struct i915_power_well *power_well)
1355 {
1356         int j;
1357
1358         if (!inst->domain_list)
1359                 return;
1360
1361         if (inst->domain_list->count == 0) {
1362                 bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
1363
1364                 return;
1365         }
1366
1367         for (j = 0; j < inst->domain_list->count; j++)
1368                 set_bit(inst->domain_list->list[j], power_well->domains.bits);
1369 }
1370
1371 #define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \
1372         for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \
1373                 for ((_inst) = (_desc)->instances->list; \
1374                      (_inst) - (_desc)->instances->list < (_desc)->instances->count; \
1375                      (_inst)++)
1376
1377 #define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \
1378         for ((_descs) = (_desc_list); \
1379              (_descs) - (_desc_list) < (_desc_count); \
1380              (_descs)++) \
1381                 for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \
1382                                                           (_desc), (_inst))
1383
1384 static int
1385 __set_power_wells(struct i915_power_domains *power_domains,
1386                   const struct i915_power_well_desc_list *power_well_descs,
1387                   int power_well_descs_sz)
1388 {
1389         struct drm_i915_private *i915 = container_of(power_domains,
1390                                                      struct drm_i915_private,
1391                                                      power_domains);
1392         u64 power_well_ids = 0;
1393         const struct i915_power_well_desc_list *desc_list;
1394         const struct i915_power_well_desc *desc;
1395         const struct i915_power_well_instance *inst;
1396         int power_well_count = 0;
1397         int plt_idx = 0;
1398
1399         for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
1400                 power_well_count++;
1401
1402         power_domains->power_well_count = power_well_count;
1403         power_domains->power_wells =
1404                                 kcalloc(power_well_count,
1405                                         sizeof(*power_domains->power_wells),
1406                                         GFP_KERNEL);
1407         if (!power_domains->power_wells)
1408                 return -ENOMEM;
1409
1410         for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {
1411                 struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
1412                 enum i915_power_well_id id = inst->id;
1413
1414                 pw->desc = desc;
1415                 drm_WARN_ON(&i915->drm,
1416                             overflows_type(inst - desc->instances->list, pw->instance_idx));
1417                 pw->instance_idx = inst - desc->instances->list;
1418
1419                 init_power_well_domains(inst, pw);
1420
1421                 plt_idx++;
1422
1423                 if (id == DISP_PW_ID_NONE)
1424                         continue;
1425
1426                 drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
1427                 drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
1428                 power_well_ids |= BIT_ULL(id);
1429         }
1430
1431         return 0;
1432 }
1433
1434 #define set_power_wells(power_domains, __power_well_descs) \
1435         __set_power_wells(power_domains, __power_well_descs, \
1436                           ARRAY_SIZE(__power_well_descs))
1437
1438 /**
1439  * intel_display_power_map_init - initialize power domain -> power well mappings
1440  * @power_domains: power domain state
1441  *
1442  * Creates all the power wells for the current platform, initializes the
1443  * dynamic state for them and initializes the mapping of each power well to
1444  * all the power domains the power well belongs to.
1445  */
1446 int intel_display_power_map_init(struct i915_power_domains *power_domains)
1447 {
1448         struct drm_i915_private *i915 = container_of(power_domains,
1449                                                      struct drm_i915_private,
1450                                                      power_domains);
1451         /*
1452          * The enabling order will be from lower to higher indexed wells,
1453          * the disabling order is reversed.
1454          */
1455         if (!HAS_DISPLAY(i915)) {
1456                 power_domains->power_well_count = 0;
1457                 return 0;
1458         }
1459
1460         if (DISPLAY_VER(i915) >= 13)
1461                 return set_power_wells(power_domains, xelpd_power_wells);
1462         else if (IS_DG1(i915))
1463                 return set_power_wells(power_domains, dg1_power_wells);
1464         else if (IS_ALDERLAKE_S(i915))
1465                 return set_power_wells(power_domains, adls_power_wells);
1466         else if (IS_ROCKETLAKE(i915))
1467                 return set_power_wells(power_domains, rkl_power_wells);
1468         else if (DISPLAY_VER(i915) == 12)
1469                 return set_power_wells(power_domains, tgl_power_wells);
1470         else if (DISPLAY_VER(i915) == 11)
1471                 return set_power_wells(power_domains, icl_power_wells);
1472         else if (IS_GEMINILAKE(i915))
1473                 return set_power_wells(power_domains, glk_power_wells);
1474         else if (IS_BROXTON(i915))
1475                 return set_power_wells(power_domains, bxt_power_wells);
1476         else if (DISPLAY_VER(i915) == 9)
1477                 return set_power_wells(power_domains, skl_power_wells);
1478         else if (IS_CHERRYVIEW(i915))
1479                 return set_power_wells(power_domains, chv_power_wells);
1480         else if (IS_BROADWELL(i915))
1481                 return set_power_wells(power_domains, bdw_power_wells);
1482         else if (IS_HASWELL(i915))
1483                 return set_power_wells(power_domains, hsw_power_wells);
1484         else if (IS_VALLEYVIEW(i915))
1485                 return set_power_wells(power_domains, vlv_power_wells);
1486         else if (IS_I830(i915))
1487                 return set_power_wells(power_domains, i830_power_wells);
1488         else
1489                 return set_power_wells(power_domains, i9xx_power_wells);
1490 }
1491
1492 /**
1493  * intel_display_power_map_cleanup - clean up power domain -> power well mappings
1494  * @power_domains: power domain state
1495  *
1496  * Cleans up all the state that was initialized by intel_display_power_map_init().
1497  */
1498 void intel_display_power_map_cleanup(struct i915_power_domains *power_domains)
1499 {
1500         kfree(power_domains->power_wells);
1501 }