drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <[email protected]>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Jesse Barnes <[email protected]>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include <drm/intel_lpe_audio.h>
  42 #include "i915_drv.h"
  43
  44 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  45 {
  46         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  47 }
  48
  49 static void
  50 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  51 {
  52         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  53         struct drm_i915_private *dev_priv = to_i915(dev);
  54         u32 enabled_bits;
  55
  56         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  57
  58         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  59              "HDMI port enabled, expecting disabled\n");
  60 }
  61
  62 static void
  63 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  64                                      enum transcoder cpu_transcoder)
  65 {
  66         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  67              TRANS_DDI_FUNC_ENABLE,
  68              "HDMI transcoder function enabled, expecting disabled\n");
  69 }
  70
  71 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  72 {
  73         struct intel_digital_port *intel_dig_port =
  74                 container_of(encoder, struct intel_digital_port, base.base);
  75         return &intel_dig_port->hdmi;
  76 }
  77
  78 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  79 {
  80         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  81 }
  82
  83 static u32 g4x_infoframe_index(unsigned int type)
  84 {
  85         switch (type) {
  86         case HDMI_INFOFRAME_TYPE_AVI:
  87                 return VIDEO_DIP_SELECT_AVI;
  88         case HDMI_INFOFRAME_TYPE_SPD:
  89                 return VIDEO_DIP_SELECT_SPD;
  90         case HDMI_INFOFRAME_TYPE_VENDOR:
  91                 return VIDEO_DIP_SELECT_VENDOR;
  92         default:
  93                 MISSING_CASE(type);
  94                 return 0;
  95         }
  96 }
  97
  98 static u32 g4x_infoframe_enable(unsigned int type)
  99 {
 100         switch (type) {
 101         case HDMI_INFOFRAME_TYPE_AVI:
 102                 return VIDEO_DIP_ENABLE_AVI;
 103         case HDMI_INFOFRAME_TYPE_SPD:
 104                 return VIDEO_DIP_ENABLE_SPD;
 105         case HDMI_INFOFRAME_TYPE_VENDOR:
 106                 return VIDEO_DIP_ENABLE_VENDOR;
 107         default:
 108                 MISSING_CASE(type);
 109                 return 0;
 110         }
 111 }
 112
 113 static u32 hsw_infoframe_enable(unsigned int type)
 114 {
 115         switch (type) {
 116         case DP_SDP_VSC:
 117                 return VIDEO_DIP_ENABLE_VSC_HSW;
 118         case HDMI_INFOFRAME_TYPE_AVI:
 119                 return VIDEO_DIP_ENABLE_AVI_HSW;
 120         case HDMI_INFOFRAME_TYPE_SPD:
 121                 return VIDEO_DIP_ENABLE_SPD_HSW;
 122         case HDMI_INFOFRAME_TYPE_VENDOR:
 123                 return VIDEO_DIP_ENABLE_VS_HSW;
 124         default:
 125                 MISSING_CASE(type);
 126                 return 0;
 127         }
 128 }
 129
 130 static i915_reg_t
 131 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 132                  enum transcoder cpu_transcoder,
 133                  unsigned int type,
 134                  int i)
 135 {
 136         switch (type) {
 137         case DP_SDP_VSC:
 138                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 139         case HDMI_INFOFRAME_TYPE_AVI:
 140                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 141         case HDMI_INFOFRAME_TYPE_SPD:
 142                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 143         case HDMI_INFOFRAME_TYPE_VENDOR:
 144                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 145         default:
 146                 MISSING_CASE(type);
 147                 return INVALID_MMIO_REG;
 148         }
 149 }
 150
 151 static void g4x_write_infoframe(struct drm_encoder *encoder,
 152                                 const struct intel_crtc_state *crtc_state,
 153                                 unsigned int type,
 154                                 const void *frame, ssize_t len)
 155 {
 156         const u32 *data = frame;
 157         struct drm_device *dev = encoder->dev;
 158         struct drm_i915_private *dev_priv = to_i915(dev);
 159         u32 val = I915_READ(VIDEO_DIP_CTL);
 160         int i;
 161
 162         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 163
 164         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 165         val |= g4x_infoframe_index(type);
 166
 167         val &= ~g4x_infoframe_enable(type);
 168
 169         I915_WRITE(VIDEO_DIP_CTL, val);
 170
 171         mmiowb();
 172         for (i = 0; i < len; i += 4) {
 173                 I915_WRITE(VIDEO_DIP_DATA, *data);
 174                 data++;
 175         }
 176         /* Write every possible data byte to force correct ECC calculation. */
 177         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 178                 I915_WRITE(VIDEO_DIP_DATA, 0);
 179         mmiowb();
 180
 181         val |= g4x_infoframe_enable(type);
 182         val &= ~VIDEO_DIP_FREQ_MASK;
 183         val |= VIDEO_DIP_FREQ_VSYNC;
 184
 185         I915_WRITE(VIDEO_DIP_CTL, val);
 186         POSTING_READ(VIDEO_DIP_CTL);
 187 }
 188
 189 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 190                                   const struct intel_crtc_state *pipe_config)
 191 {
 192         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 193         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 194         u32 val = I915_READ(VIDEO_DIP_CTL);
 195
 196         if ((val & VIDEO_DIP_ENABLE) == 0)
 197                 return false;
 198
 199         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 200                 return false;
 201
 202         return val & (VIDEO_DIP_ENABLE_AVI |
 203                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 204 }
 205
 206 static void ibx_write_infoframe(struct drm_encoder *encoder,
 207                                 const struct intel_crtc_state *crtc_state,
 208                                 unsigned int type,
 209                                 const void *frame, ssize_t len)
 210 {
 211         const u32 *data = frame;
 212         struct drm_device *dev = encoder->dev;
 213         struct drm_i915_private *dev_priv = to_i915(dev);
 214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 215         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 216         u32 val = I915_READ(reg);
 217         int i;
 218
 219         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 220
 221         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 222         val |= g4x_infoframe_index(type);
 223
 224         val &= ~g4x_infoframe_enable(type);
 225
 226         I915_WRITE(reg, val);
 227
 228         mmiowb();
 229         for (i = 0; i < len; i += 4) {
 230                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 231                 data++;
 232         }
 233         /* Write every possible data byte to force correct ECC calculation. */
 234         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 235                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 236         mmiowb();
 237
 238         val |= g4x_infoframe_enable(type);
 239         val &= ~VIDEO_DIP_FREQ_MASK;
 240         val |= VIDEO_DIP_FREQ_VSYNC;
 241
 242         I915_WRITE(reg, val);
 243         POSTING_READ(reg);
 244 }
 245
 246 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 247                                   const struct intel_crtc_state *pipe_config)
 248 {
 249         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 250         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 251         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 252         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 253         u32 val = I915_READ(reg);
 254
 255         if ((val & VIDEO_DIP_ENABLE) == 0)
 256                 return false;
 257
 258         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 259                 return false;
 260
 261         return val & (VIDEO_DIP_ENABLE_AVI |
 262                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 263                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 264 }
 265
 266 static void cpt_write_infoframe(struct drm_encoder *encoder,
 267                                 const struct intel_crtc_state *crtc_state,
 268                                 unsigned int type,
 269                                 const void *frame, ssize_t len)
 270 {
 271         const u32 *data = frame;
 272         struct drm_device *dev = encoder->dev;
 273         struct drm_i915_private *dev_priv = to_i915(dev);
 274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 275         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 276         u32 val = I915_READ(reg);
 277         int i;
 278
 279         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 280
 281         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 282         val |= g4x_infoframe_index(type);
 283
 284         /* The DIP control register spec says that we need to update the AVI
 285          * infoframe without clearing its enable bit */
 286         if (type != HDMI_INFOFRAME_TYPE_AVI)
 287                 val &= ~g4x_infoframe_enable(type);
 288
 289         I915_WRITE(reg, val);
 290
 291         mmiowb();
 292         for (i = 0; i < len; i += 4) {
 293                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 294                 data++;
 295         }
 296         /* Write every possible data byte to force correct ECC calculation. */
 297         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 298                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 299         mmiowb();
 300
 301         val |= g4x_infoframe_enable(type);
 302         val &= ~VIDEO_DIP_FREQ_MASK;
 303         val |= VIDEO_DIP_FREQ_VSYNC;
 304
 305         I915_WRITE(reg, val);
 306         POSTING_READ(reg);
 307 }
 308
 309 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 310                                   const struct intel_crtc_state *pipe_config)
 311 {
 312         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 313         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 314         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 315
 316         if ((val & VIDEO_DIP_ENABLE) == 0)
 317                 return false;
 318
 319         return val & (VIDEO_DIP_ENABLE_AVI |
 320                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 321                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 322 }
 323
 324 static void vlv_write_infoframe(struct drm_encoder *encoder,
 325                                 const struct intel_crtc_state *crtc_state,
 326                                 unsigned int type,
 327                                 const void *frame, ssize_t len)
 328 {
 329         const u32 *data = frame;
 330         struct drm_device *dev = encoder->dev;
 331         struct drm_i915_private *dev_priv = to_i915(dev);
 332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 333         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 334         u32 val = I915_READ(reg);
 335         int i;
 336
 337         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 338
 339         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 340         val |= g4x_infoframe_index(type);
 341
 342         val &= ~g4x_infoframe_enable(type);
 343
 344         I915_WRITE(reg, val);
 345
 346         mmiowb();
 347         for (i = 0; i < len; i += 4) {
 348                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 349                 data++;
 350         }
 351         /* Write every possible data byte to force correct ECC calculation. */
 352         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 353                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 354         mmiowb();
 355
 356         val |= g4x_infoframe_enable(type);
 357         val &= ~VIDEO_DIP_FREQ_MASK;
 358         val |= VIDEO_DIP_FREQ_VSYNC;
 359
 360         I915_WRITE(reg, val);
 361         POSTING_READ(reg);
 362 }
 363
 364 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 365                                   const struct intel_crtc_state *pipe_config)
 366 {
 367         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 368         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 369         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 370         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 371
 372         if ((val & VIDEO_DIP_ENABLE) == 0)
 373                 return false;
 374
 375         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 376                 return false;
 377
 378         return val & (VIDEO_DIP_ENABLE_AVI |
 379                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 380                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 381 }
 382
 383 static void hsw_write_infoframe(struct drm_encoder *encoder,
 384                                 const struct intel_crtc_state *crtc_state,
 385                                 unsigned int type,
 386                                 const void *frame, ssize_t len)
 387 {
 388         const u32 *data = frame;
 389         struct drm_device *dev = encoder->dev;
 390         struct drm_i915_private *dev_priv = to_i915(dev);
 391         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 392         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 393         int data_size = type == DP_SDP_VSC ?
 394                 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
 395         int i;
 396         u32 val = I915_READ(ctl_reg);
 397
 398         val &= ~hsw_infoframe_enable(type);
 399         I915_WRITE(ctl_reg, val);
 400
 401         mmiowb();
 402         for (i = 0; i < len; i += 4) {
 403                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 404                                             type, i >> 2), *data);
 405                 data++;
 406         }
 407         /* Write every possible data byte to force correct ECC calculation. */
 408         for (; i < data_size; i += 4)
 409                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 410                                             type, i >> 2), 0);
 411         mmiowb();
 412
 413         val |= hsw_infoframe_enable(type);
 414         I915_WRITE(ctl_reg, val);
 415         POSTING_READ(ctl_reg);
 416 }
 417
 418 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 419                                   const struct intel_crtc_state *pipe_config)
 420 {
 421         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 422         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 423
 424         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 425                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 426                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 427 }
 428
 429 /*
 430  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 431  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 432  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 433  * used for both technologies.
 434  *
 435  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 436  * DW1:       DB3       | DB2 | DB1 | DB0
 437  * DW2:       DB7       | DB6 | DB5 | DB4
 438  * DW3: ...
 439  *
 440  * (HB is Header Byte, DB is Data Byte)
 441  *
 442  * The hdmi pack() functions don't know about that hardware specific hole so we
 443  * trick them by giving an offset into the buffer and moving back the header
 444  * bytes by one.
 445  */
 446 static void intel_write_infoframe(struct drm_encoder *encoder,
 447                                   const struct intel_crtc_state *crtc_state,
 448                                   union hdmi_infoframe *frame)
 449 {
 450         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 451         u8 buffer[VIDEO_DIP_DATA_SIZE];
 452         ssize_t len;
 453
 454         /* see comment above for the reason for this offset */
 455         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 456         if (len < 0)
 457                 return;
 458
 459         /* Insert the 'hole' (see big comment above) at position 3 */
 460         buffer[0] = buffer[1];
 461         buffer[1] = buffer[2];
 462         buffer[2] = buffer[3];
 463         buffer[3] = 0;
 464         len++;
 465
 466         intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
 467 }
 468
 469 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 470                                          const struct intel_crtc_state *crtc_state,
 471                                          const struct drm_connector_state *conn_state)
 472 {
 473         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 474         const struct drm_display_mode *adjusted_mode =
 475                 &crtc_state->base.adjusted_mode;
 476         struct drm_connector *connector = &intel_hdmi->attached_connector->base;
 477         bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported ||
 478            connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
 479         union hdmi_infoframe frame;
 480         int ret;
 481
 482         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 483                                                        adjusted_mode,
 484                                                        is_hdmi2_sink);
 485         if (ret < 0) {
 486                 DRM_ERROR("couldn't fill AVI infoframe\n");
 487                 return;
 488         }
 489
 490         if (crtc_state->ycbcr420)
 491                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
 492         else
 493                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 494
 495         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 496                                            crtc_state->limited_color_range ?
 497                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 498                                            HDMI_QUANTIZATION_RANGE_FULL,
 499                                            intel_hdmi->rgb_quant_range_selectable,
 500                                            is_hdmi2_sink);
 501
 502         drm_hdmi_avi_infoframe_content_type(&frame.avi,
 503                                             conn_state);
 504
 505         /* TODO: handle pixel repetition for YCBCR420 outputs */
 506         intel_write_infoframe(encoder, crtc_state, &frame);
 507 }
 508
 509 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
 510                                          const struct intel_crtc_state *crtc_state)
 511 {
 512         union hdmi_infoframe frame;
 513         int ret;
 514
 515         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 516         if (ret < 0) {
 517                 DRM_ERROR("couldn't fill SPD infoframe\n");
 518                 return;
 519         }
 520
 521         frame.spd.sdi = HDMI_SPD_SDI_PC;
 522
 523         intel_write_infoframe(encoder, crtc_state, &frame);
 524 }
 525
 526 static void
 527 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 528                               const struct intel_crtc_state *crtc_state,
 529                               const struct drm_connector_state *conn_state)
 530 {
 531         union hdmi_infoframe frame;
 532         int ret;
 533
 534         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 535                                                           conn_state->connector,
 536                                                           &crtc_state->base.adjusted_mode);
 537         if (ret < 0)
 538                 return;
 539
 540         intel_write_infoframe(encoder, crtc_state, &frame);
 541 }
 542
 543 static void g4x_set_infoframes(struct drm_encoder *encoder,
 544                                bool enable,
 545                                const struct intel_crtc_state *crtc_state,
 546                                const struct drm_connector_state *conn_state)
 547 {
 548         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 549         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 550         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 551         i915_reg_t reg = VIDEO_DIP_CTL;
 552         u32 val = I915_READ(reg);
 553         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 554
 555         assert_hdmi_port_disabled(intel_hdmi);
 556
 557         /* If the registers were not initialized yet, they might be zeroes,
 558          * which means we're selecting the AVI DIP and we're setting its
 559          * frequency to once. This seems to really confuse the HW and make
 560          * things stop working (the register spec says the AVI always needs to
 561          * be sent every VSync). So here we avoid writing to the register more
 562          * than we need and also explicitly select the AVI DIP and explicitly
 563          * set its frequency to every VSync. Avoiding to write it twice seems to
 564          * be enough to solve the problem, but being defensive shouldn't hurt us
 565          * either. */
 566         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 567
 568         if (!enable) {
 569                 if (!(val & VIDEO_DIP_ENABLE))
 570                         return;
 571                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 572                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 573                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 574                         return;
 575                 }
 576                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 577                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 578                 I915_WRITE(reg, val);
 579                 POSTING_READ(reg);
 580                 return;
 581         }
 582
 583         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 584                 if (val & VIDEO_DIP_ENABLE) {
 585                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 586                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 587                         return;
 588                 }
 589                 val &= ~VIDEO_DIP_PORT_MASK;
 590                 val |= port;
 591         }
 592
 593         val |= VIDEO_DIP_ENABLE;
 594         val &= ~(VIDEO_DIP_ENABLE_AVI |
 595                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 596
 597         I915_WRITE(reg, val);
 598         POSTING_READ(reg);
 599
 600         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 601         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 602         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 603 }
 604
 605 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 606 {
 607         struct drm_connector *connector = conn_state->connector;
 608
 609         /*
 610          * HDMI cloning is only supported on g4x which doesn't
 611          * support deep color or GCP infoframes anyway so no
 612          * need to worry about multiple HDMI sinks here.
 613          */
 614
 615         return connector->display_info.bpc > 8;
 616 }
 617
 618 /*
 619  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 620  *
 621  * From HDMI specification 1.4a:
 622  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 623  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 624  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 625  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 626  *   phase of 0
 627  */
 628 static bool gcp_default_phase_possible(int pipe_bpp,
 629                                        const struct drm_display_mode *mode)
 630 {
 631         unsigned int pixels_per_group;
 632
 633         switch (pipe_bpp) {
 634         case 30:
 635                 /* 4 pixels in 5 clocks */
 636                 pixels_per_group = 4;
 637                 break;
 638         case 36:
 639                 /* 2 pixels in 3 clocks */
 640                 pixels_per_group = 2;
 641                 break;
 642         case 48:
 643                 /* 1 pixel in 2 clocks */
 644                 pixels_per_group = 1;
 645                 break;
 646         default:
 647                 /* phase information not relevant for 8bpc */
 648                 return false;
 649         }
 650
 651         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 652                 mode->crtc_htotal % pixels_per_group == 0 &&
 653                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 654                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 655                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 656                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 657                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 658                  mode->crtc_htotal/2 % pixels_per_group == 0);
 659 }
 660
 661 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
 662                                          const struct intel_crtc_state *crtc_state,
 663                                          const struct drm_connector_state *conn_state)
 664 {
 665         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 666         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 667         i915_reg_t reg;
 668         u32 val = 0;
 669
 670         if (HAS_DDI(dev_priv))
 671                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 672         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 673                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 674         else if (HAS_PCH_SPLIT(dev_priv))
 675                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 676         else
 677                 return false;
 678
 679         /* Indicate color depth whenever the sink supports deep color */
 680         if (hdmi_sink_is_deep_color(conn_state))
 681                 val |= GCP_COLOR_INDICATION;
 682
 683         /* Enable default_phase whenever the display mode is suitably aligned */
 684         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 685                                        &crtc_state->base.adjusted_mode))
 686                 val |= GCP_DEFAULT_PHASE_ENABLE;
 687
 688         I915_WRITE(reg, val);
 689
 690         return val != 0;
 691 }
 692
 693 static void ibx_set_infoframes(struct drm_encoder *encoder,
 694                                bool enable,
 695                                const struct intel_crtc_state *crtc_state,
 696                                const struct drm_connector_state *conn_state)
 697 {
 698         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 700         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 701         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 702         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 703         u32 val = I915_READ(reg);
 704         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 705
 706         assert_hdmi_port_disabled(intel_hdmi);
 707
 708         /* See the big comment in g4x_set_infoframes() */
 709         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 710
 711         if (!enable) {
 712                 if (!(val & VIDEO_DIP_ENABLE))
 713                         return;
 714                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 715                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 716                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 717                 I915_WRITE(reg, val);
 718                 POSTING_READ(reg);
 719                 return;
 720         }
 721
 722         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 723                 WARN(val & VIDEO_DIP_ENABLE,
 724                      "DIP already enabled on port %c\n",
 725                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 726                 val &= ~VIDEO_DIP_PORT_MASK;
 727                 val |= port;
 728         }
 729
 730         val |= VIDEO_DIP_ENABLE;
 731         val &= ~(VIDEO_DIP_ENABLE_AVI |
 732                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 733                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 734
 735         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 736                 val |= VIDEO_DIP_ENABLE_GCP;
 737
 738         I915_WRITE(reg, val);
 739         POSTING_READ(reg);
 740
 741         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 742         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 743         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 744 }
 745
 746 static void cpt_set_infoframes(struct drm_encoder *encoder,
 747                                bool enable,
 748                                const struct intel_crtc_state *crtc_state,
 749                                const struct drm_connector_state *conn_state)
 750 {
 751         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 753         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 754         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 755         u32 val = I915_READ(reg);
 756
 757         assert_hdmi_port_disabled(intel_hdmi);
 758
 759         /* See the big comment in g4x_set_infoframes() */
 760         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 761
 762         if (!enable) {
 763                 if (!(val & VIDEO_DIP_ENABLE))
 764                         return;
 765                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 766                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 767                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 768                 I915_WRITE(reg, val);
 769                 POSTING_READ(reg);
 770                 return;
 771         }
 772
 773         /* Set both together, unset both together: see the spec. */
 774         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 775         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 776                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 777
 778         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 779                 val |= VIDEO_DIP_ENABLE_GCP;
 780
 781         I915_WRITE(reg, val);
 782         POSTING_READ(reg);
 783
 784         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 785         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 786         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 787 }
 788
 789 static void vlv_set_infoframes(struct drm_encoder *encoder,
 790                                bool enable,
 791                                const struct intel_crtc_state *crtc_state,
 792                                const struct drm_connector_state *conn_state)
 793 {
 794         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 795         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 797         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 798         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 799         u32 val = I915_READ(reg);
 800         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 801
 802         assert_hdmi_port_disabled(intel_hdmi);
 803
 804         /* See the big comment in g4x_set_infoframes() */
 805         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 806
 807         if (!enable) {
 808                 if (!(val & VIDEO_DIP_ENABLE))
 809                         return;
 810                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 811                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 812                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 813                 I915_WRITE(reg, val);
 814                 POSTING_READ(reg);
 815                 return;
 816         }
 817
 818         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 819                 WARN(val & VIDEO_DIP_ENABLE,
 820                      "DIP already enabled on port %c\n",
 821                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 822                 val &= ~VIDEO_DIP_PORT_MASK;
 823                 val |= port;
 824         }
 825
 826         val |= VIDEO_DIP_ENABLE;
 827         val &= ~(VIDEO_DIP_ENABLE_AVI |
 828                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 829                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 830
 831         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 832                 val |= VIDEO_DIP_ENABLE_GCP;
 833
 834         I915_WRITE(reg, val);
 835         POSTING_READ(reg);
 836
 837         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 838         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 839         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 840 }
 841
 842 static void hsw_set_infoframes(struct drm_encoder *encoder,
 843                                bool enable,
 844                                const struct intel_crtc_state *crtc_state,
 845                                const struct drm_connector_state *conn_state)
 846 {
 847         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 848         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 849         u32 val = I915_READ(reg);
 850
 851         assert_hdmi_transcoder_func_disabled(dev_priv,
 852                                              crtc_state->cpu_transcoder);
 853
 854         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 855                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 856                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 857
 858         if (!enable) {
 859                 I915_WRITE(reg, val);
 860                 POSTING_READ(reg);
 861                 return;
 862         }
 863
 864         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 865                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 866
 867         I915_WRITE(reg, val);
 868         POSTING_READ(reg);
 869
 870         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 871         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 872         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 873 }
 874
 875 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 876 {
 877         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 878         struct i2c_adapter *adapter =
 879                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 880
 881         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 882                 return;
 883
 884         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 885                       enable ? "Enabling" : "Disabling");
 886
 887         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 888                                          adapter, enable);
 889 }
 890
 891 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
 892                                 unsigned int offset, void *buffer, size_t size)
 893 {
 894         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 895         struct drm_i915_private *dev_priv =
 896                 intel_dig_port->base.base.dev->dev_private;
 897         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 898                                                               hdmi->ddc_bus);
 899         int ret;
 900         u8 start = offset & 0xff;
 901         struct i2c_msg msgs[] = {
 902                 {
 903                         .addr = DRM_HDCP_DDC_ADDR,
 904                         .flags = 0,
 905                         .len = 1,
 906                         .buf = &start,
 907                 },
 908                 {
 909                         .addr = DRM_HDCP_DDC_ADDR,
 910                         .flags = I2C_M_RD,
 911                         .len = size,
 912                         .buf = buffer
 913                 }
 914         };
 915         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
 916         if (ret == ARRAY_SIZE(msgs))
 917                 return 0;
 918         return ret >= 0 ? -EIO : ret;
 919 }
 920
 921 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
 922                                  unsigned int offset, void *buffer, size_t size)
 923 {
 924         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 925         struct drm_i915_private *dev_priv =
 926                 intel_dig_port->base.base.dev->dev_private;
 927         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 928                                                               hdmi->ddc_bus);
 929         int ret;
 930         u8 *write_buf;
 931         struct i2c_msg msg;
 932
 933         write_buf = kzalloc(size + 1, GFP_KERNEL);
 934         if (!write_buf)
 935                 return -ENOMEM;
 936
 937         write_buf[0] = offset & 0xff;
 938         memcpy(&write_buf[1], buffer, size);
 939
 940         msg.addr = DRM_HDCP_DDC_ADDR;
 941         msg.flags = 0,
 942         msg.len = size + 1,
 943         msg.buf = write_buf;
 944
 945         ret = i2c_transfer(adapter, &msg, 1);
 946         if (ret == 1)
 947                 ret = 0;
 948         else if (ret >= 0)
 949                 ret = -EIO;
 950
 951         kfree(write_buf);
 952         return ret;
 953 }
 954
 955 static
 956 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
 957                                   u8 *an)
 958 {
 959         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 960         struct drm_i915_private *dev_priv =
 961                 intel_dig_port->base.base.dev->dev_private;
 962         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 963                                                               hdmi->ddc_bus);
 964         int ret;
 965
 966         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
 967                                     DRM_HDCP_AN_LEN);
 968         if (ret) {
 969                 DRM_ERROR("Write An over DDC failed (%d)\n", ret);
 970                 return ret;
 971         }
 972
 973         ret = intel_gmbus_output_aksv(adapter);
 974         if (ret < 0) {
 975                 DRM_ERROR("Failed to output aksv (%d)\n", ret);
 976                 return ret;
 977         }
 978         return 0;
 979 }
 980
 981 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
 982                                      u8 *bksv)
 983 {
 984         int ret;
 985         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
 986                                    DRM_HDCP_KSV_LEN);
 987         if (ret)
 988                 DRM_ERROR("Read Bksv over DDC failed (%d)\n", ret);
 989         return ret;
 990 }
 991
 992 static
 993 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
 994                                  u8 *bstatus)
 995 {
 996         int ret;
 997         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
 998                                    bstatus, DRM_HDCP_BSTATUS_LEN);
 999         if (ret)
1000                 DRM_ERROR("Read bstatus over DDC failed (%d)\n", ret);
1001         return ret;
1002 }
1003
1004 static
1005 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1006                                      bool *repeater_present)
1007 {
1008         int ret;
1009         u8 val;
1010
1011         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1012         if (ret) {
1013                 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
1014                 return ret;
1015         }
1016         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1017         return 0;
1018 }
1019
1020 static
1021 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1022                                   u8 *ri_prime)
1023 {
1024         int ret;
1025         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1026                                    ri_prime, DRM_HDCP_RI_LEN);
1027         if (ret)
1028                 DRM_ERROR("Read Ri' over DDC failed (%d)\n", ret);
1029         return ret;
1030 }
1031
1032 static
1033 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1034                                    bool *ksv_ready)
1035 {
1036         int ret;
1037         u8 val;
1038
1039         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1040         if (ret) {
1041                 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
1042                 return ret;
1043         }
1044         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1045         return 0;
1046 }
1047
1048 static
1049 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1050                                   int num_downstream, u8 *ksv_fifo)
1051 {
1052         int ret;
1053         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1054                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1055         if (ret) {
1056                 DRM_ERROR("Read ksv fifo over DDC failed (%d)\n", ret);
1057                 return ret;
1058         }
1059         return 0;
1060 }
1061
1062 static
1063 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1064                                       int i, u32 *part)
1065 {
1066         int ret;
1067
1068         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1069                 return -EINVAL;
1070
1071         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1072                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1073         if (ret)
1074                 DRM_ERROR("Read V'[%d] over DDC failed (%d)\n", i, ret);
1075         return ret;
1076 }
1077
1078 static
1079 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1080                                       bool enable)
1081 {
1082         int ret;
1083
1084         if (!enable)
1085                 usleep_range(6, 60); /* Bspec says >= 6us */
1086
1087         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1088         if (ret) {
1089                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1090                           enable ? "Enable" : "Disable", ret);
1091                 return ret;
1092         }
1093         return 0;
1094 }
1095
1096 static
1097 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1098 {
1099         struct drm_i915_private *dev_priv =
1100                 intel_dig_port->base.base.dev->dev_private;
1101         enum port port = intel_dig_port->base.port;
1102         int ret;
1103         union {
1104                 u32 reg;
1105                 u8 shim[DRM_HDCP_RI_LEN];
1106         } ri;
1107
1108         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1109         if (ret)
1110                 return false;
1111
1112         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1113
1114         /* Wait for Ri prime match */
1115         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1116                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1117                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1118                           I915_READ(PORT_HDCP_STATUS(port)));
1119                 return false;
1120         }
1121         return true;
1122 }
1123
1124 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1125         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1126         .read_bksv = intel_hdmi_hdcp_read_bksv,
1127         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1128         .repeater_present = intel_hdmi_hdcp_repeater_present,
1129         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1130         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1131         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1132         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1133         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1134         .check_link = intel_hdmi_hdcp_check_link,
1135 };
1136
1137 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1138                                const struct intel_crtc_state *crtc_state)
1139 {
1140         struct drm_device *dev = encoder->base.dev;
1141         struct drm_i915_private *dev_priv = to_i915(dev);
1142         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1143         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1144         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1145         u32 hdmi_val;
1146
1147         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1148
1149         hdmi_val = SDVO_ENCODING_HDMI;
1150         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1151                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1152         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1153                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1154         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1155                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1156
1157         if (crtc_state->pipe_bpp > 24)
1158                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1159         else
1160                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1161
1162         if (crtc_state->has_hdmi_sink)
1163                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1164
1165         if (HAS_PCH_CPT(dev_priv))
1166                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1167         else if (IS_CHERRYVIEW(dev_priv))
1168                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1169         else
1170                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1171
1172         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1173         POSTING_READ(intel_hdmi->hdmi_reg);
1174 }
1175
1176 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1177                                     enum pipe *pipe)
1178 {
1179         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1180         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1181         bool ret;
1182
1183         if (!intel_display_power_get_if_enabled(dev_priv,
1184                                                 encoder->power_domain))
1185                 return false;
1186
1187         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1188
1189         intel_display_power_put(dev_priv, encoder->power_domain);
1190
1191         return ret;
1192 }
1193
1194 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1195                                   struct intel_crtc_state *pipe_config)
1196 {
1197         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1198         struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1199         struct drm_device *dev = encoder->base.dev;
1200         struct drm_i915_private *dev_priv = to_i915(dev);
1201         u32 tmp, flags = 0;
1202         int dotclock;
1203
1204         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1205
1206         tmp = I915_READ(intel_hdmi->hdmi_reg);
1207
1208         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1209                 flags |= DRM_MODE_FLAG_PHSYNC;
1210         else
1211                 flags |= DRM_MODE_FLAG_NHSYNC;
1212
1213         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1214                 flags |= DRM_MODE_FLAG_PVSYNC;
1215         else
1216                 flags |= DRM_MODE_FLAG_NVSYNC;
1217
1218         if (tmp & HDMI_MODE_SELECT_HDMI)
1219                 pipe_config->has_hdmi_sink = true;
1220
1221         if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
1222                 pipe_config->has_infoframe = true;
1223
1224         if (tmp & SDVO_AUDIO_ENABLE)
1225                 pipe_config->has_audio = true;
1226
1227         if (!HAS_PCH_SPLIT(dev_priv) &&
1228             tmp & HDMI_COLOR_RANGE_16_235)
1229                 pipe_config->limited_color_range = true;
1230
1231         pipe_config->base.adjusted_mode.flags |= flags;
1232
1233         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1234                 dotclock = pipe_config->port_clock * 2 / 3;
1235         else
1236                 dotclock = pipe_config->port_clock;
1237
1238         if (pipe_config->pixel_multiplier)
1239                 dotclock /= pipe_config->pixel_multiplier;
1240
1241         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1242
1243         pipe_config->lane_count = 4;
1244 }
1245
1246 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1247                                     const struct intel_crtc_state *pipe_config,
1248                                     const struct drm_connector_state *conn_state)
1249 {
1250         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1251
1252         WARN_ON(!pipe_config->has_hdmi_sink);
1253         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1254                          pipe_name(crtc->pipe));
1255         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1256 }
1257
1258 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1259                             const struct intel_crtc_state *pipe_config,
1260                             const struct drm_connector_state *conn_state)
1261 {
1262         struct drm_device *dev = encoder->base.dev;
1263         struct drm_i915_private *dev_priv = to_i915(dev);
1264         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1265         u32 temp;
1266
1267         temp = I915_READ(intel_hdmi->hdmi_reg);
1268
1269         temp |= SDVO_ENABLE;
1270         if (pipe_config->has_audio)
1271                 temp |= SDVO_AUDIO_ENABLE;
1272
1273         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1274         POSTING_READ(intel_hdmi->hdmi_reg);
1275
1276         if (pipe_config->has_audio)
1277                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1278 }
1279
1280 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1281                             const struct intel_crtc_state *pipe_config,
1282                             const struct drm_connector_state *conn_state)
1283 {
1284         struct drm_device *dev = encoder->base.dev;
1285         struct drm_i915_private *dev_priv = to_i915(dev);
1286         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1287         u32 temp;
1288
1289         temp = I915_READ(intel_hdmi->hdmi_reg);
1290
1291         temp |= SDVO_ENABLE;
1292         if (pipe_config->has_audio)
1293                 temp |= SDVO_AUDIO_ENABLE;
1294
1295         /*
1296          * HW workaround, need to write this twice for issue
1297          * that may result in first write getting masked.
1298          */
1299         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1300         POSTING_READ(intel_hdmi->hdmi_reg);
1301         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1302         POSTING_READ(intel_hdmi->hdmi_reg);
1303
1304         /*
1305          * HW workaround, need to toggle enable bit off and on
1306          * for 12bpc with pixel repeat.
1307          *
1308          * FIXME: BSpec says this should be done at the end of
1309          * of the modeset sequence, so not sure if this isn't too soon.
1310          */
1311         if (pipe_config->pipe_bpp > 24 &&
1312             pipe_config->pixel_multiplier > 1) {
1313                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1314                 POSTING_READ(intel_hdmi->hdmi_reg);
1315
1316                 /*
1317                  * HW workaround, need to write this twice for issue
1318                  * that may result in first write getting masked.
1319                  */
1320                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1321                 POSTING_READ(intel_hdmi->hdmi_reg);
1322                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1323                 POSTING_READ(intel_hdmi->hdmi_reg);
1324         }
1325
1326         if (pipe_config->has_audio)
1327                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1328 }
1329
1330 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1331                             const struct intel_crtc_state *pipe_config,
1332                             const struct drm_connector_state *conn_state)
1333 {
1334         struct drm_device *dev = encoder->base.dev;
1335         struct drm_i915_private *dev_priv = to_i915(dev);
1336         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1337         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1338         enum pipe pipe = crtc->pipe;
1339         u32 temp;
1340
1341         temp = I915_READ(intel_hdmi->hdmi_reg);
1342
1343         temp |= SDVO_ENABLE;
1344         if (pipe_config->has_audio)
1345                 temp |= SDVO_AUDIO_ENABLE;
1346
1347         /*
1348          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1349          *
1350          * The procedure for 12bpc is as follows:
1351          * 1. disable HDMI clock gating
1352          * 2. enable HDMI with 8bpc
1353          * 3. enable HDMI with 12bpc
1354          * 4. enable HDMI clock gating
1355          */
1356
1357         if (pipe_config->pipe_bpp > 24) {
1358                 I915_WRITE(TRANS_CHICKEN1(pipe),
1359                            I915_READ(TRANS_CHICKEN1(pipe)) |
1360                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1361
1362                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1363                 temp |= SDVO_COLOR_FORMAT_8bpc;
1364         }
1365
1366         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1367         POSTING_READ(intel_hdmi->hdmi_reg);
1368
1369         if (pipe_config->pipe_bpp > 24) {
1370                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1371                 temp |= HDMI_COLOR_FORMAT_12bpc;
1372
1373                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1374                 POSTING_READ(intel_hdmi->hdmi_reg);
1375
1376                 I915_WRITE(TRANS_CHICKEN1(pipe),
1377                            I915_READ(TRANS_CHICKEN1(pipe)) &
1378                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1379         }
1380
1381         if (pipe_config->has_audio)
1382                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1383 }
1384
1385 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1386                             const struct intel_crtc_state *pipe_config,
1387                             const struct drm_connector_state *conn_state)
1388 {
1389 }
1390
1391 static void intel_disable_hdmi(struct intel_encoder *encoder,
1392                                const struct intel_crtc_state *old_crtc_state,
1393                                const struct drm_connector_state *old_conn_state)
1394 {
1395         struct drm_device *dev = encoder->base.dev;
1396         struct drm_i915_private *dev_priv = to_i915(dev);
1397         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1398         struct intel_digital_port *intel_dig_port =
1399                 hdmi_to_dig_port(intel_hdmi);
1400         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1401         u32 temp;
1402
1403         temp = I915_READ(intel_hdmi->hdmi_reg);
1404
1405         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1406         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1407         POSTING_READ(intel_hdmi->hdmi_reg);
1408
1409         /*
1410          * HW workaround for IBX, we need to move the port
1411          * to transcoder A after disabling it to allow the
1412          * matching DP port to be enabled on transcoder A.
1413          */
1414         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1415                 /*
1416                  * We get CPU/PCH FIFO underruns on the other pipe when
1417                  * doing the workaround. Sweep them under the rug.
1418                  */
1419                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1420                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1421
1422                 temp &= ~SDVO_PIPE_SEL_MASK;
1423                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1424                 /*
1425                  * HW workaround, need to write this twice for issue
1426                  * that may result in first write getting masked.
1427                  */
1428                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1429                 POSTING_READ(intel_hdmi->hdmi_reg);
1430                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1431                 POSTING_READ(intel_hdmi->hdmi_reg);
1432
1433                 temp &= ~SDVO_ENABLE;
1434                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1435                 POSTING_READ(intel_hdmi->hdmi_reg);
1436
1437                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1438                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1439                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1440         }
1441
1442         intel_dig_port->set_infoframes(&encoder->base, false,
1443                                        old_crtc_state, old_conn_state);
1444
1445         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1446 }
1447
1448 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1449                              const struct intel_crtc_state *old_crtc_state,
1450                              const struct drm_connector_state *old_conn_state)
1451 {
1452         if (old_crtc_state->has_audio)
1453                 intel_audio_codec_disable(encoder,
1454                                           old_crtc_state, old_conn_state);
1455
1456         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1457 }
1458
1459 static void pch_disable_hdmi(struct intel_encoder *encoder,
1460                              const struct intel_crtc_state *old_crtc_state,
1461                              const struct drm_connector_state *old_conn_state)
1462 {
1463         if (old_crtc_state->has_audio)
1464                 intel_audio_codec_disable(encoder,
1465                                           old_crtc_state, old_conn_state);
1466 }
1467
1468 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1469                                   const struct intel_crtc_state *old_crtc_state,
1470                                   const struct drm_connector_state *old_conn_state)
1471 {
1472         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1473 }
1474
1475 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1476 {
1477         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1478         const struct ddi_vbt_port_info *info =
1479                 &dev_priv->vbt.ddi_port_info[encoder->port];
1480         int max_tmds_clock;
1481
1482         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1483                 max_tmds_clock = 594000;
1484         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1485                 max_tmds_clock = 300000;
1486         else if (INTEL_GEN(dev_priv) >= 5)
1487                 max_tmds_clock = 225000;
1488         else
1489                 max_tmds_clock = 165000;
1490
1491         if (info->max_tmds_clock)
1492                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1493
1494         return max_tmds_clock;
1495 }
1496
1497 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1498                                  bool respect_downstream_limits,
1499                                  bool force_dvi)
1500 {
1501         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1502         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1503
1504         if (respect_downstream_limits) {
1505                 struct intel_connector *connector = hdmi->attached_connector;
1506                 const struct drm_display_info *info = &connector->base.display_info;
1507
1508                 if (hdmi->dp_dual_mode.max_tmds_clock)
1509                         max_tmds_clock = min(max_tmds_clock,
1510                                              hdmi->dp_dual_mode.max_tmds_clock);
1511
1512                 if (info->max_tmds_clock)
1513                         max_tmds_clock = min(max_tmds_clock,
1514                                              info->max_tmds_clock);
1515                 else if (!hdmi->has_hdmi_sink || force_dvi)
1516                         max_tmds_clock = min(max_tmds_clock, 165000);
1517         }
1518
1519         return max_tmds_clock;
1520 }
1521
1522 static enum drm_mode_status
1523 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1524                       int clock, bool respect_downstream_limits,
1525                       bool force_dvi)
1526 {
1527         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1528
1529         if (clock < 25000)
1530                 return MODE_CLOCK_LOW;
1531         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1532                 return MODE_CLOCK_HIGH;
1533
1534         /* BXT DPLL can't generate 223-240 MHz */
1535         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1536                 return MODE_CLOCK_RANGE;
1537
1538         /* CHV DPLL can't generate 216-240 MHz */
1539         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1540                 return MODE_CLOCK_RANGE;
1541
1542         return MODE_OK;
1543 }
1544
1545 static enum drm_mode_status
1546 intel_hdmi_mode_valid(struct drm_connector *connector,
1547                       struct drm_display_mode *mode)
1548 {
1549         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1550         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1551         struct drm_i915_private *dev_priv = to_i915(dev);
1552         enum drm_mode_status status;
1553         int clock;
1554         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1555         bool force_dvi =
1556                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1557
1558         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1559                 return MODE_NO_DBLESCAN;
1560
1561         clock = mode->clock;
1562
1563         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1564                 clock *= 2;
1565
1566         if (clock > max_dotclk)
1567                 return MODE_CLOCK_HIGH;
1568
1569         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1570                 clock *= 2;
1571
1572         if (drm_mode_is_420_only(&connector->display_info, mode))
1573                 clock /= 2;
1574
1575         /* check if we can do 8bpc */
1576         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1577
1578         if (hdmi->has_hdmi_sink && !force_dvi) {
1579                 /* if we can't do 8bpc we may still be able to do 12bpc */
1580                 if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
1581                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1582                                                        true, force_dvi);
1583
1584                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1585                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1586                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1587                                                        true, force_dvi);
1588         }
1589
1590         return status;
1591 }
1592
1593 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1594                                      int bpc)
1595 {
1596         struct drm_i915_private *dev_priv =
1597                 to_i915(crtc_state->base.crtc->dev);
1598         struct drm_atomic_state *state = crtc_state->base.state;
1599         struct drm_connector_state *connector_state;
1600         struct drm_connector *connector;
1601         int i;
1602
1603         if (HAS_GMCH_DISPLAY(dev_priv))
1604                 return false;
1605
1606         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1607                 return false;
1608
1609         if (crtc_state->pipe_bpp <= 8*3)
1610                 return false;
1611
1612         if (!crtc_state->has_hdmi_sink)
1613                 return false;
1614
1615         /*
1616          * HDMI deep color affects the clocks, so it's only possible
1617          * when not cloning with other encoder types.
1618          */
1619         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1620                 return false;
1621
1622         for_each_new_connector_in_state(state, connector, connector_state, i) {
1623                 const struct drm_display_info *info = &connector->display_info;
1624
1625                 if (connector_state->crtc != crtc_state->base.crtc)
1626                         continue;
1627
1628                 if (crtc_state->ycbcr420) {
1629                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1630
1631                         if (bpc == 12 && !(hdmi->y420_dc_modes &
1632                                            DRM_EDID_YCBCR420_DC_36))
1633                                 return false;
1634                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
1635                                                 DRM_EDID_YCBCR420_DC_30))
1636                                 return false;
1637                 } else {
1638                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1639                                            DRM_EDID_HDMI_DC_36))
1640                                 return false;
1641                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1642                                                 DRM_EDID_HDMI_DC_30))
1643                                 return false;
1644                 }
1645         }
1646
1647         /* Display WA #1139: glk */
1648         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1649             crtc_state->base.adjusted_mode.htotal > 5460)
1650                 return false;
1651
1652         return true;
1653 }
1654
1655 static bool
1656 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1657                            struct intel_crtc_state *config,
1658                            int *clock_12bpc, int *clock_10bpc,
1659                            int *clock_8bpc)
1660 {
1661         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1662
1663         if (!connector->ycbcr_420_allowed) {
1664                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1665                 return false;
1666         }
1667
1668         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1669         config->port_clock /= 2;
1670         *clock_12bpc /= 2;
1671         *clock_10bpc /= 2;
1672         *clock_8bpc /= 2;
1673         config->ycbcr420 = true;
1674
1675         /* YCBCR 420 output conversion needs a scaler */
1676         if (skl_update_scaler_crtc(config)) {
1677                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1678                 return false;
1679         }
1680
1681         intel_pch_panel_fitting(intel_crtc, config,
1682                                 DRM_MODE_SCALE_FULLSCREEN);
1683
1684         return true;
1685 }
1686
1687 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1688                                struct intel_crtc_state *pipe_config,
1689                                struct drm_connector_state *conn_state)
1690 {
1691         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1692         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1693         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1694         struct drm_connector *connector = conn_state->connector;
1695         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1696         struct intel_digital_connector_state *intel_conn_state =
1697                 to_intel_digital_connector_state(conn_state);
1698         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1699         int clock_10bpc = clock_8bpc * 5 / 4;
1700         int clock_12bpc = clock_8bpc * 3 / 2;
1701         int desired_bpp;
1702         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1703
1704         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1705                 return false;
1706
1707         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1708
1709         if (pipe_config->has_hdmi_sink)
1710                 pipe_config->has_infoframe = true;
1711
1712         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1713                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1714                 pipe_config->limited_color_range =
1715                         pipe_config->has_hdmi_sink &&
1716                         drm_default_rgb_quant_range(adjusted_mode) ==
1717                         HDMI_QUANTIZATION_RANGE_LIMITED;
1718         } else {
1719                 pipe_config->limited_color_range =
1720                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1721         }
1722
1723         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1724                 pipe_config->pixel_multiplier = 2;
1725                 clock_8bpc *= 2;
1726                 clock_10bpc *= 2;
1727                 clock_12bpc *= 2;
1728         }
1729
1730         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1731                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1732                                                 &clock_12bpc, &clock_10bpc,
1733                                                 &clock_8bpc)) {
1734                         DRM_ERROR("Can't support YCBCR420 output\n");
1735                         return false;
1736                 }
1737         }
1738
1739         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1740                 pipe_config->has_pch_encoder = true;
1741
1742         if (pipe_config->has_hdmi_sink) {
1743                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1744                         pipe_config->has_audio = intel_hdmi->has_audio;
1745                 else
1746                         pipe_config->has_audio =
1747                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1748         }
1749
1750         /*
1751          * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1752          * to check that the higher clock still fits within limits.
1753          */
1754         if (hdmi_deep_color_possible(pipe_config, 12) &&
1755             hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1756                                   true, force_dvi) == MODE_OK) {
1757                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1758                 desired_bpp = 12*3;
1759
1760                 /* Need to adjust the port link by 1.5x for 12bpc. */
1761                 pipe_config->port_clock = clock_12bpc;
1762         } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1763                    hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1764                                          true, force_dvi) == MODE_OK) {
1765                 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1766                 desired_bpp = 10 * 3;
1767
1768                 /* Need to adjust the port link by 1.25x for 10bpc. */
1769                 pipe_config->port_clock = clock_10bpc;
1770         } else {
1771                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1772                 desired_bpp = 8*3;
1773
1774                 pipe_config->port_clock = clock_8bpc;
1775         }
1776
1777         if (!pipe_config->bw_constrained) {
1778                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1779                 pipe_config->pipe_bpp = desired_bpp;
1780         }
1781
1782         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1783                                   false, force_dvi) != MODE_OK) {
1784                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1785                 return false;
1786         }
1787
1788         /* Set user selected PAR to incoming mode's member */
1789         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1790
1791         pipe_config->lane_count = 4;
1792
1793         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1794                                            IS_GEMINILAKE(dev_priv))) {
1795                 if (scdc->scrambling.low_rates)
1796                         pipe_config->hdmi_scrambling = true;
1797
1798                 if (pipe_config->port_clock > 340000) {
1799                         pipe_config->hdmi_scrambling = true;
1800                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1801                 }
1802         }
1803
1804         return true;
1805 }
1806
1807 static void
1808 intel_hdmi_unset_edid(struct drm_connector *connector)
1809 {
1810         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1811
1812         intel_hdmi->has_hdmi_sink = false;
1813         intel_hdmi->has_audio = false;
1814         intel_hdmi->rgb_quant_range_selectable = false;
1815
1816         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1817         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1818
1819         kfree(to_intel_connector(connector)->detect_edid);
1820         to_intel_connector(connector)->detect_edid = NULL;
1821 }
1822
1823 static void
1824 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1825 {
1826         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1827         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1828         enum port port = hdmi_to_dig_port(hdmi)->base.port;
1829         struct i2c_adapter *adapter =
1830                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1831         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1832
1833         /*
1834          * Type 1 DVI adaptors are not required to implement any
1835          * registers, so we can't always detect their presence.
1836          * Ideally we should be able to check the state of the
1837          * CONFIG1 pin, but no such luck on our hardware.
1838          *
1839          * The only method left to us is to check the VBT to see
1840          * if the port is a dual mode capable DP port. But let's
1841          * only do that when we sucesfully read the EDID, to avoid
1842          * confusing log messages about DP dual mode adaptors when
1843          * there's nothing connected to the port.
1844          */
1845         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1846                 /* An overridden EDID imply that we want this port for testing.
1847                  * Make sure not to set limits for that port.
1848                  */
1849                 if (has_edid && !connector->override_edid &&
1850                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1851                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1852                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1853                 } else {
1854                         type = DRM_DP_DUAL_MODE_NONE;
1855                 }
1856         }
1857
1858         if (type == DRM_DP_DUAL_MODE_NONE)
1859                 return;
1860
1861         hdmi->dp_dual_mode.type = type;
1862         hdmi->dp_dual_mode.max_tmds_clock =
1863                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1864
1865         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1866                       drm_dp_get_dual_mode_type_name(type),
1867                       hdmi->dp_dual_mode.max_tmds_clock);
1868 }
1869
1870 static bool
1871 intel_hdmi_set_edid(struct drm_connector *connector)
1872 {
1873         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1874         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1875         struct edid *edid;
1876         bool connected = false;
1877         struct i2c_adapter *i2c;
1878
1879         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1880
1881         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1882
1883         edid = drm_get_edid(connector, i2c);
1884
1885         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1886                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1887                 intel_gmbus_force_bit(i2c, true);
1888                 edid = drm_get_edid(connector, i2c);
1889                 intel_gmbus_force_bit(i2c, false);
1890         }
1891
1892         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1893
1894         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1895
1896         to_intel_connector(connector)->detect_edid = edid;
1897         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1898                 intel_hdmi->rgb_quant_range_selectable =
1899                         drm_rgb_quant_range_selectable(edid);
1900
1901                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1902                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1903
1904                 connected = true;
1905         }
1906
1907         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
1908
1909         return connected;
1910 }
1911
1912 static enum drm_connector_status
1913 intel_hdmi_detect(struct drm_connector *connector, bool force)
1914 {
1915         enum drm_connector_status status = connector_status_disconnected;
1916         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1917         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1918         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
1919
1920         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1921                       connector->base.id, connector->name);
1922
1923         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1924
1925         if (IS_ICELAKE(dev_priv) &&
1926             !intel_digital_port_connected(encoder))
1927                 goto out;
1928
1929         intel_hdmi_unset_edid(connector);
1930
1931         if (intel_hdmi_set_edid(connector))
1932                 status = connector_status_connected;
1933
1934 out:
1935         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1936
1937         if (status != connector_status_connected)
1938                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
1939
1940         return status;
1941 }
1942
1943 static void
1944 intel_hdmi_force(struct drm_connector *connector)
1945 {
1946         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1947                       connector->base.id, connector->name);
1948
1949         intel_hdmi_unset_edid(connector);
1950
1951         if (connector->status != connector_status_connected)
1952                 return;
1953
1954         intel_hdmi_set_edid(connector);
1955 }
1956
1957 static int intel_hdmi_get_modes(struct drm_connector *connector)
1958 {
1959         struct edid *edid;
1960
1961         edid = to_intel_connector(connector)->detect_edid;
1962         if (edid == NULL)
1963                 return 0;
1964
1965         return intel_connector_update_modes(connector, edid);
1966 }
1967
1968 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1969                                   const struct intel_crtc_state *pipe_config,
1970                                   const struct drm_connector_state *conn_state)
1971 {
1972         struct intel_digital_port *intel_dig_port =
1973                 enc_to_dig_port(&encoder->base);
1974
1975         intel_hdmi_prepare(encoder, pipe_config);
1976
1977         intel_dig_port->set_infoframes(&encoder->base,
1978                                        pipe_config->has_infoframe,
1979                                        pipe_config, conn_state);
1980 }
1981
1982 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1983                                 const struct intel_crtc_state *pipe_config,
1984                                 const struct drm_connector_state *conn_state)
1985 {
1986         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1987         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1988
1989         vlv_phy_pre_encoder_enable(encoder, pipe_config);
1990
1991         /* HDMI 1.0V-2dB */
1992         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1993                                  0x2b247878);
1994
1995         dport->set_infoframes(&encoder->base,
1996                               pipe_config->has_infoframe,
1997                               pipe_config, conn_state);
1998
1999         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2000
2001         vlv_wait_port_ready(dev_priv, dport, 0x0);
2002 }
2003
2004 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2005                                     const struct intel_crtc_state *pipe_config,
2006                                     const struct drm_connector_state *conn_state)
2007 {
2008         intel_hdmi_prepare(encoder, pipe_config);
2009
2010         vlv_phy_pre_pll_enable(encoder, pipe_config);
2011 }
2012
2013 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2014                                     const struct intel_crtc_state *pipe_config,
2015                                     const struct drm_connector_state *conn_state)
2016 {
2017         intel_hdmi_prepare(encoder, pipe_config);
2018
2019         chv_phy_pre_pll_enable(encoder, pipe_config);
2020 }
2021
2022 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2023                                       const struct intel_crtc_state *old_crtc_state,
2024                                       const struct drm_connector_state *old_conn_state)
2025 {
2026         chv_phy_post_pll_disable(encoder, old_crtc_state);
2027 }
2028
2029 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2030                                   const struct intel_crtc_state *old_crtc_state,
2031                                   const struct drm_connector_state *old_conn_state)
2032 {
2033         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2034         vlv_phy_reset_lanes(encoder, old_crtc_state);
2035 }
2036
2037 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2038                                   const struct intel_crtc_state *old_crtc_state,
2039                                   const struct drm_connector_state *old_conn_state)
2040 {
2041         struct drm_device *dev = encoder->base.dev;
2042         struct drm_i915_private *dev_priv = to_i915(dev);
2043
2044         mutex_lock(&dev_priv->sb_lock);
2045
2046         /* Assert data lane reset */
2047         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2048
2049         mutex_unlock(&dev_priv->sb_lock);
2050 }
2051
2052 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2053                                 const struct intel_crtc_state *pipe_config,
2054                                 const struct drm_connector_state *conn_state)
2055 {
2056         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2057         struct drm_device *dev = encoder->base.dev;
2058         struct drm_i915_private *dev_priv = to_i915(dev);
2059
2060         chv_phy_pre_encoder_enable(encoder, pipe_config);
2061
2062         /* FIXME: Program the support xxx V-dB */
2063         /* Use 800mV-0dB */
2064         chv_set_phy_signal_level(encoder, 128, 102, false);
2065
2066         dport->set_infoframes(&encoder->base,
2067                               pipe_config->has_infoframe,
2068                               pipe_config, conn_state);
2069
2070         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2071
2072         vlv_wait_port_ready(dev_priv, dport, 0x0);
2073
2074         /* Second common lane will stay alive on its own now */
2075         chv_phy_release_cl2_override(encoder);
2076 }
2077
2078 static void intel_hdmi_destroy(struct drm_connector *connector)
2079 {
2080         if (intel_attached_hdmi(connector)->cec_notifier)
2081                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2082         kfree(to_intel_connector(connector)->detect_edid);
2083         drm_connector_cleanup(connector);
2084         kfree(connector);
2085 }
2086
2087 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2088         .detect = intel_hdmi_detect,
2089         .force = intel_hdmi_force,
2090         .fill_modes = drm_helper_probe_single_connector_modes,
2091         .atomic_get_property = intel_digital_connector_atomic_get_property,
2092         .atomic_set_property = intel_digital_connector_atomic_set_property,
2093         .late_register = intel_connector_register,
2094         .early_unregister = intel_connector_unregister,
2095         .destroy = intel_hdmi_destroy,
2096         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2097         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2098 };
2099
2100 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2101         .get_modes = intel_hdmi_get_modes,
2102         .mode_valid = intel_hdmi_mode_valid,
2103         .atomic_check = intel_digital_connector_atomic_check,
2104 };
2105
2106 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2107         .destroy = intel_encoder_destroy,
2108 };
2109
2110 static void
2111 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2112 {
2113         intel_attach_force_audio_property(connector);
2114         intel_attach_broadcast_rgb_property(connector);
2115         intel_attach_aspect_ratio_property(connector);
2116         drm_connector_attach_content_type_property(connector);
2117         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2118 }
2119
2120 /*
2121  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2122  * @encoder: intel_encoder
2123  * @connector: drm_connector
2124  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2125  *  or reset the high tmds clock ratio for scrambling
2126  * @scrambling: bool to Indicate if the function needs to set or reset
2127  *  sink scrambling
2128  *
2129  * This function handles scrambling on HDMI 2.0 capable sinks.
2130  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2131  * it enables scrambling. This should be called before enabling the HDMI
2132  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2133  * detect a scrambled clock within 100 ms.
2134  *
2135  * Returns:
2136  * True on success, false on failure.
2137  */
2138 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2139                                        struct drm_connector *connector,
2140                                        bool high_tmds_clock_ratio,
2141                                        bool scrambling)
2142 {
2143         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2144         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2145         struct drm_scrambling *sink_scrambling =
2146                 &connector->display_info.hdmi.scdc.scrambling;
2147         struct i2c_adapter *adapter =
2148                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2149
2150         if (!sink_scrambling->supported)
2151                 return true;
2152
2153         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2154                       connector->base.id, connector->name,
2155                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2156
2157         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2158         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2159                                                   high_tmds_clock_ratio) &&
2160                 drm_scdc_set_scrambling(adapter, scrambling);
2161 }
2162
2163 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2164 {
2165         u8 ddc_pin;
2166
2167         switch (port) {
2168         case PORT_B:
2169                 ddc_pin = GMBUS_PIN_DPB;
2170                 break;
2171         case PORT_C:
2172                 ddc_pin = GMBUS_PIN_DPC;
2173                 break;
2174         case PORT_D:
2175                 ddc_pin = GMBUS_PIN_DPD_CHV;
2176                 break;
2177         default:
2178                 MISSING_CASE(port);
2179                 ddc_pin = GMBUS_PIN_DPB;
2180                 break;
2181         }
2182         return ddc_pin;
2183 }
2184
2185 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2186 {
2187         u8 ddc_pin;
2188
2189         switch (port) {
2190         case PORT_B:
2191                 ddc_pin = GMBUS_PIN_1_BXT;
2192                 break;
2193         case PORT_C:
2194                 ddc_pin = GMBUS_PIN_2_BXT;
2195                 break;
2196         default:
2197                 MISSING_CASE(port);
2198                 ddc_pin = GMBUS_PIN_1_BXT;
2199                 break;
2200         }
2201         return ddc_pin;
2202 }
2203
2204 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2205                               enum port port)
2206 {
2207         u8 ddc_pin;
2208
2209         switch (port) {
2210         case PORT_B:
2211                 ddc_pin = GMBUS_PIN_1_BXT;
2212                 break;
2213         case PORT_C:
2214                 ddc_pin = GMBUS_PIN_2_BXT;
2215                 break;
2216         case PORT_D:
2217                 ddc_pin = GMBUS_PIN_4_CNP;
2218                 break;
2219         case PORT_F:
2220                 ddc_pin = GMBUS_PIN_3_BXT;
2221                 break;
2222         default:
2223                 MISSING_CASE(port);
2224                 ddc_pin = GMBUS_PIN_1_BXT;
2225                 break;
2226         }
2227         return ddc_pin;
2228 }
2229
2230 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2231 {
2232         u8 ddc_pin;
2233
2234         switch (port) {
2235         case PORT_A:
2236                 ddc_pin = GMBUS_PIN_1_BXT;
2237                 break;
2238         case PORT_B:
2239                 ddc_pin = GMBUS_PIN_2_BXT;
2240                 break;
2241         case PORT_C:
2242                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2243                 break;
2244         case PORT_D:
2245                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2246                 break;
2247         case PORT_E:
2248                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2249                 break;
2250         case PORT_F:
2251                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2252                 break;
2253         default:
2254                 MISSING_CASE(port);
2255                 ddc_pin = GMBUS_PIN_2_BXT;
2256                 break;
2257         }
2258         return ddc_pin;
2259 }
2260
2261 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2262                               enum port port)
2263 {
2264         u8 ddc_pin;
2265
2266         switch (port) {
2267         case PORT_B:
2268                 ddc_pin = GMBUS_PIN_DPB;
2269                 break;
2270         case PORT_C:
2271                 ddc_pin = GMBUS_PIN_DPC;
2272                 break;
2273         case PORT_D:
2274                 ddc_pin = GMBUS_PIN_DPD;
2275                 break;
2276         default:
2277                 MISSING_CASE(port);
2278                 ddc_pin = GMBUS_PIN_DPB;
2279                 break;
2280         }
2281         return ddc_pin;
2282 }
2283
2284 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2285                              enum port port)
2286 {
2287         const struct ddi_vbt_port_info *info =
2288                 &dev_priv->vbt.ddi_port_info[port];
2289         u8 ddc_pin;
2290
2291         if (info->alternate_ddc_pin) {
2292                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2293                               info->alternate_ddc_pin, port_name(port));
2294                 return info->alternate_ddc_pin;
2295         }
2296
2297         if (IS_CHERRYVIEW(dev_priv))
2298                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2299         else if (IS_GEN9_LP(dev_priv))
2300                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2301         else if (HAS_PCH_CNP(dev_priv))
2302                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2303         else if (HAS_PCH_ICP(dev_priv))
2304                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2305         else
2306                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2307
2308         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2309                       ddc_pin, port_name(port));
2310
2311         return ddc_pin;
2312 }
2313
2314 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2315 {
2316         struct drm_i915_private *dev_priv =
2317                 to_i915(intel_dig_port->base.base.dev);
2318
2319         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2320                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2321                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2322                 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2323         } else if (IS_G4X(dev_priv)) {
2324                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2325                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2326                 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2327         } else if (HAS_DDI(dev_priv)) {
2328                 intel_dig_port->write_infoframe = hsw_write_infoframe;
2329                 intel_dig_port->set_infoframes = hsw_set_infoframes;
2330                 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
2331         } else if (HAS_PCH_IBX(dev_priv)) {
2332                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2333                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2334                 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2335         } else {
2336                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2337                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2338                 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2339         }
2340 }
2341
2342 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2343                                struct intel_connector *intel_connector)
2344 {
2345         struct drm_connector *connector = &intel_connector->base;
2346         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2347         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2348         struct drm_device *dev = intel_encoder->base.dev;
2349         struct drm_i915_private *dev_priv = to_i915(dev);
2350         enum port port = intel_encoder->port;
2351
2352         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2353                       port_name(port));
2354
2355         if (WARN(intel_dig_port->max_lanes < 4,
2356                  "Not enough lanes (%d) for HDMI on port %c\n",
2357                  intel_dig_port->max_lanes, port_name(port)))
2358                 return;
2359
2360         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2361                            DRM_MODE_CONNECTOR_HDMIA);
2362         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2363
2364         connector->interlace_allowed = 1;
2365         connector->doublescan_allowed = 0;
2366         connector->stereo_allowed = 1;
2367
2368         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2369                 connector->ycbcr_420_allowed = true;
2370
2371         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2372
2373         if (WARN_ON(port == PORT_A))
2374                 return;
2375         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2376
2377         if (HAS_DDI(dev_priv))
2378                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2379         else
2380                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2381
2382         intel_hdmi_add_properties(intel_hdmi, connector);
2383
2384         if (is_hdcp_supported(dev_priv, port)) {
2385                 int ret = intel_hdcp_init(intel_connector,
2386                                           &intel_hdmi_hdcp_shim);
2387                 if (ret)
2388                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2389         }
2390
2391         intel_connector_attach_encoder(intel_connector, intel_encoder);
2392         intel_hdmi->attached_connector = intel_connector;
2393
2394         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2395          * 0xd.  Failure to do so will result in spurious interrupts being
2396          * generated on the port when a cable is not attached.
2397          */
2398         if (IS_G45(dev_priv)) {
2399                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2400                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2401         }
2402
2403         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2404                                                          port_identifier(port));
2405         if (!intel_hdmi->cec_notifier)
2406                 DRM_DEBUG_KMS("CEC notifier get failed\n");
2407 }
2408
2409 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2410                      i915_reg_t hdmi_reg, enum port port)
2411 {
2412         struct intel_digital_port *intel_dig_port;
2413         struct intel_encoder *intel_encoder;
2414         struct intel_connector *intel_connector;
2415
2416         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2417         if (!intel_dig_port)
2418                 return;
2419
2420         intel_connector = intel_connector_alloc();
2421         if (!intel_connector) {
2422                 kfree(intel_dig_port);
2423                 return;
2424         }
2425
2426         intel_encoder = &intel_dig_port->base;
2427
2428         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2429                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2430                          "HDMI %c", port_name(port));
2431
2432         intel_encoder->hotplug = intel_encoder_hotplug;
2433         intel_encoder->compute_config = intel_hdmi_compute_config;
2434         if (HAS_PCH_SPLIT(dev_priv)) {
2435                 intel_encoder->disable = pch_disable_hdmi;
2436                 intel_encoder->post_disable = pch_post_disable_hdmi;
2437         } else {
2438                 intel_encoder->disable = g4x_disable_hdmi;
2439         }
2440         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2441         intel_encoder->get_config = intel_hdmi_get_config;
2442         if (IS_CHERRYVIEW(dev_priv)) {
2443                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2444                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2445                 intel_encoder->enable = vlv_enable_hdmi;
2446                 intel_encoder->post_disable = chv_hdmi_post_disable;
2447                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2448         } else if (IS_VALLEYVIEW(dev_priv)) {
2449                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2450                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2451                 intel_encoder->enable = vlv_enable_hdmi;
2452                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2453         } else {
2454                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2455                 if (HAS_PCH_CPT(dev_priv))
2456                         intel_encoder->enable = cpt_enable_hdmi;
2457                 else if (HAS_PCH_IBX(dev_priv))
2458                         intel_encoder->enable = ibx_enable_hdmi;
2459                 else
2460                         intel_encoder->enable = g4x_enable_hdmi;
2461         }
2462
2463         intel_encoder->type = INTEL_OUTPUT_HDMI;
2464         intel_encoder->power_domain = intel_port_to_power_domain(port);
2465         intel_encoder->port = port;
2466         if (IS_CHERRYVIEW(dev_priv)) {
2467                 if (port == PORT_D)
2468                         intel_encoder->crtc_mask = 1 << 2;
2469                 else
2470                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2471         } else {
2472                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2473         }
2474         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2475         /*
2476          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2477          * to work on real hardware. And since g4x can send infoframes to
2478          * only one port anyway, nothing is lost by allowing it.
2479          */
2480         if (IS_G4X(dev_priv))
2481                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2482
2483         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2484         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2485         intel_dig_port->max_lanes = 4;
2486
2487         intel_infoframe_init(intel_dig_port);
2488
2489         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2490 }