include/linux/mfd/stm32-timers.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) STMicroelectronics 2016
   4  * Author: Benjamin Gaignard <[email protected]>
   5  */
   6
   7 #ifndef _LINUX_STM32_GPTIMER_H_
   8 #define _LINUX_STM32_GPTIMER_H_
   9
  10 #include <linux/clk.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/regmap.h>
  14
  15 #define TIM_CR1         0x00                    /* Control Register 1                   */
  16 #define TIM_CR2         0x04                    /* Control Register 2                   */
  17 #define TIM_SMCR        0x08                    /* Slave mode control reg               */
  18 #define TIM_DIER        0x0C                    /* DMA/interrupt register               */
  19 #define TIM_SR          0x10                    /* Status register                      */
  20 #define TIM_EGR         0x14                    /* Event Generation Reg                 */
  21 #define TIM_CCMR1       0x18                    /* Capt/Comp 1 Mode Reg                 */
  22 #define TIM_CCMR2       0x1C                    /* Capt/Comp 2 Mode Reg                 */
  23 #define TIM_CCER        0x20                    /* Capt/Comp Enable Reg                 */
  24 #define TIM_CNT         0x24                    /* Counter                              */
  25 #define TIM_PSC         0x28                    /* Prescaler                            */
  26 #define TIM_ARR         0x2c                    /* Auto-Reload Register                 */
  27 #define TIM_CCRx(x)     (0x34 + 4 * ((x) - 1))  /* Capt/Comp Register x (x ∈ {1, .. 4})       */
  28 #define TIM_CCR1        TIM_CCRx(1)             /* Capt/Comp Register 1                 */
  29 #define TIM_CCR2        TIM_CCRx(2)             /* Capt/Comp Register 2                 */
  30 #define TIM_CCR3        TIM_CCRx(3)             /* Capt/Comp Register 3                 */
  31 #define TIM_CCR4        TIM_CCRx(4)             /* Capt/Comp Register 4                 */
  32 #define TIM_BDTR        0x44                    /* Break and Dead-Time Reg              */
  33 #define TIM_DCR         0x48                    /* DMA control register                 */
  34 #define TIM_DMAR        0x4C                    /* DMA register for transfer            */
  35 #define TIM_TISEL       0x68                    /* Input Selection                      */
  36
  37 #define TIM_CR1_CEN             BIT(0)                                  /* Counter Enable                               */
  38 #define TIM_CR1_DIR             BIT(4)                                  /* Counter Direction                            */
  39 #define TIM_CR1_ARPE            BIT(7)                                  /* Auto-reload Preload Ena                      */
  40 #define TIM_CR2_MMS             (BIT(4) | BIT(5) | BIT(6))              /* Master mode selection                        */
  41 #define TIM_CR2_MMS2            GENMASK(23, 20)                         /* Master mode selection 2                      */
  42 #define TIM_SMCR_SMS            (BIT(0) | BIT(1) | BIT(2))              /* Slave mode selection                         */
  43 #define TIM_SMCR_TS             (BIT(4) | BIT(5) | BIT(6))              /* Trigger selection                            */
  44 #define TIM_DIER_UIE            BIT(0)                                  /* Update interrupt                             */
  45 #define TIM_DIER_CCxIE(x)       BIT(1 + ((x) - 1))                      /* CCx Interrupt Enable (x ∈ {1, .. 4})               */
  46 #define TIM_DIER_CC1IE          TIM_DIER_CCxIE(1)                       /* CC1 Interrupt Enable                         */
  47 #define TIM_DIER_CC2IE          TIM_DIER_CCxIE(2)                       /* CC2 Interrupt Enable                         */
  48 #define TIM_DIER_CC3IE          TIM_DIER_CCxIE(3)                       /* CC3 Interrupt Enable                         */
  49 #define TIM_DIER_CC4IE          TIM_DIER_CCxIE(4)                       /* CC4 Interrupt Enable                         */
  50 #define TIM_DIER_UDE            BIT(8)                                  /* Update DMA request Enable                    */
  51 #define TIM_DIER_CCxDE(x)       BIT(9 + ((x) - 1))                      /* CCx DMA request Enable (x ∈ {1, .. 4})     */
  52 #define TIM_DIER_CC1DE          TIM_DIER_CCxDE(1)                       /* CC1 DMA request Enable                       */
  53 #define TIM_DIER_CC2DE          TIM_DIER_CCxDE(2)                       /* CC2 DMA request Enable                       */
  54 #define TIM_DIER_CC3DE          TIM_DIER_CCxDE(3)                       /* CC3 DMA request Enable                       */
  55 #define TIM_DIER_CC4DE          TIM_DIER_CCxDE(4)                       /* CC4 DMA request Enable                       */
  56 #define TIM_DIER_COMDE          BIT(13)                                 /* COM DMA request Enable                       */
  57 #define TIM_DIER_TDE            BIT(14)                                 /* Trigger DMA request Enable                   */
  58 #define TIM_SR_UIF              BIT(0)                                  /* Update interrupt flag                        */
  59 #define TIM_SR_CC_IF(x)         BIT((x) + 1)                            /* CC1, CC2, CC3, CC4 interrupt flag            */
  60 #define TIM_EGR_UG              BIT(0)                                  /* Update Generation                            */
  61 #define TIM_CCMR_PE             BIT(3)                                  /* Channel Preload Enable                       */
  62 #define TIM_CCMR_M1             (BIT(6) | BIT(5))                       /* Channel PWM Mode 1                           */
  63 #define TIM_CCMR_CC1S           (BIT(0) | BIT(1))                       /* Capture/compare 1 sel                        */
  64 #define TIM_CCMR_IC1PSC         GENMASK(3, 2)                           /* Input capture 1 prescaler                    */
  65 #define TIM_CCMR_CC2S           (BIT(8) | BIT(9))                       /* Capture/compare 2 sel                        */
  66 #define TIM_CCMR_IC2PSC         GENMASK(11, 10)                         /* Input capture 2 prescaler                    */
  67 #define TIM_CCMR_CC1S_TI1       BIT(0)                                  /* IC1/IC3 selects TI1/TI3                      */
  68 #define TIM_CCMR_CC1S_TI2       BIT(1)                                  /* IC1/IC3 selects TI2/TI4                      */
  69 #define TIM_CCMR_CC2S_TI2       BIT(8)                                  /* IC2/IC4 selects TI2/TI4                      */
  70 #define TIM_CCMR_CC2S_TI1       BIT(9)                                  /* IC2/IC4 selects TI1/TI3                      */
  71 #define TIM_CCMR_CC3S           (BIT(0) | BIT(1))                       /* Capture/compare 3 sel                        */
  72 #define TIM_CCMR_CC4S           (BIT(8) | BIT(9))                       /* Capture/compare 4 sel                        */
  73 #define TIM_CCMR_CC3S_TI3       BIT(0)                                  /* IC3 selects TI3                              */
  74 #define TIM_CCMR_CC4S_TI4       BIT(8)                                  /* IC4 selects TI4                              */
  75 #define TIM_CCER_CCxE(x)        BIT(0 + 4 * ((x) - 1))                  /* Capt/Comp x  out Ena (x ∈ {1, .. 4})               */
  76 #define TIM_CCER_CCxP(x)        BIT(1 + 4 * ((x) - 1))                  /* Capt/Comp x  Polarity (x ∈ {1, .. 4})      */
  77 #define TIM_CCER_CCxNE(x)       BIT(2 + 4 * ((x) - 1))                  /* Capt/Comp xN out Ena (x ∈ {1, .. 4})               */
  78 #define TIM_CCER_CCxNP(x)       BIT(3 + 4 * ((x) - 1))                  /* Capt/Comp xN Polarity (x ∈ {1, .. 4})      */
  79 #define TIM_CCER_CC1E           TIM_CCER_CCxE(1)                        /* Capt/Comp 1  out Ena                         */
  80 #define TIM_CCER_CC1P           TIM_CCER_CCxP(1)                        /* Capt/Comp 1  Polarity                        */
  81 #define TIM_CCER_CC1NE          TIM_CCER_CCxNE(1)                       /* Capt/Comp 1N out Ena                         */
  82 #define TIM_CCER_CC1NP          TIM_CCER_CCxNP(1)                       /* Capt/Comp 1N Polarity                        */
  83 #define TIM_CCER_CC2E           TIM_CCER_CCxE(2)                        /* Capt/Comp 2  out Ena                         */
  84 #define TIM_CCER_CC2P           TIM_CCER_CCxP(2)                        /* Capt/Comp 2  Polarity                        */
  85 #define TIM_CCER_CC2NE          TIM_CCER_CCxNE(2)                       /* Capt/Comp 2N out Ena                         */
  86 #define TIM_CCER_CC2NP          TIM_CCER_CCxNP(2)                       /* Capt/Comp 2N Polarity                        */
  87 #define TIM_CCER_CC3E           TIM_CCER_CCxE(3)                        /* Capt/Comp 3  out Ena                         */
  88 #define TIM_CCER_CC3P           TIM_CCER_CCxP(3)                        /* Capt/Comp 3  Polarity                        */
  89 #define TIM_CCER_CC3NE          TIM_CCER_CCxNE(3)                       /* Capt/Comp 3N out Ena                         */
  90 #define TIM_CCER_CC3NP          TIM_CCER_CCxNP(3)                       /* Capt/Comp 3N Polarity                        */
  91 #define TIM_CCER_CC4E           TIM_CCER_CCxE(4)                        /* Capt/Comp 4  out Ena                         */
  92 #define TIM_CCER_CC4P           TIM_CCER_CCxP(4)                        /* Capt/Comp 4  Polarity                        */
  93 #define TIM_CCER_CC4NE          TIM_CCER_CCxNE(4)                       /* Capt/Comp 4N out Ena                         */
  94 #define TIM_CCER_CC4NP          TIM_CCER_CCxNP(4)                       /* Capt/Comp 4N Polarity                        */
  95 #define TIM_CCER_CCXE           (BIT(0) | BIT(4) | BIT(8) | BIT(12))
  96 #define TIM_BDTR_BKE(x)         BIT(12 + (x) * 12)                      /* Break input enable                           */
  97 #define TIM_BDTR_BKP(x)         BIT(13 + (x) * 12)                      /* Break input polarity                         */
  98 #define TIM_BDTR_AOE            BIT(14)                                 /* Automatic Output Enable                      */
  99 #define TIM_BDTR_MOE            BIT(15)                                 /* Main Output Enable                           */
 100 #define TIM_BDTR_BKF(x)         (0xf << (16 + (x) * 4))
 101 #define TIM_DCR_DBA             GENMASK(4, 0)                           /* DMA base addr                                */
 102 #define TIM_DCR_DBL             GENMASK(12, 8)                          /* DMA burst len                                */
 103
 104 #define MAX_TIM_PSC                             0xFFFF
 105 #define MAX_TIM_ICPSC                           0x3
 106 #define TIM_CR2_MMS_SHIFT                       4
 107 #define TIM_CR2_MMS2_SHIFT                      20
 108 #define TIM_SMCR_SMS_SLAVE_MODE_DISABLED        0 /* counts on internal clock when CEN=1 */
 109 #define TIM_SMCR_SMS_ENCODER_MODE_1             1 /* counts TI1FP1 edges, depending on TI2FP2 level */
 110 #define TIM_SMCR_SMS_ENCODER_MODE_2             2 /* counts TI2FP2 edges, depending on TI1FP1 level */
 111 #define TIM_SMCR_SMS_ENCODER_MODE_3             3 /* counts on both TI1FP1 and TI2FP2 edges */
 112 #define TIM_SMCR_TS_SHIFT                       4
 113 #define TIM_BDTR_BKF_MASK                       0xF
 114 #define TIM_BDTR_BKF_SHIFT(x)                   (16 + (x) * 4)
 115
 116 enum stm32_timers_dmas {
 117         STM32_TIMERS_DMA_CH1,
 118         STM32_TIMERS_DMA_CH2,
 119         STM32_TIMERS_DMA_CH3,
 120         STM32_TIMERS_DMA_CH4,
 121         STM32_TIMERS_DMA_UP,
 122         STM32_TIMERS_DMA_TRIG,
 123         STM32_TIMERS_DMA_COM,
 124         STM32_TIMERS_MAX_DMAS,
 125 };
 126
 127 /* STM32 Timer may have either a unique global interrupt or 4 interrupt lines */
 128 enum stm32_timers_irqs {
 129         STM32_TIMERS_IRQ_GLOBAL_BRK, /* global or brk IRQ */
 130         STM32_TIMERS_IRQ_UP,
 131         STM32_TIMERS_IRQ_TRG_COM,
 132         STM32_TIMERS_IRQ_CC,
 133         STM32_TIMERS_MAX_IRQS,
 134 };
 135
 136 /**
 137  * struct stm32_timers_dma - STM32 timer DMA handling.
 138  * @completion:         end of DMA transfer completion
 139  * @phys_base:          control registers physical base address
 140  * @lock:               protect DMA access
 141  * @chan:               DMA channel in use
 142  * @chans:              DMA channels available for this timer instance
 143  */
 144 struct stm32_timers_dma {
 145         struct completion completion;
 146         phys_addr_t phys_base;
 147         struct mutex lock;
 148         struct dma_chan *chan;
 149         struct dma_chan *chans[STM32_TIMERS_MAX_DMAS];
 150 };
 151
 152 struct stm32_timers {
 153         struct clk *clk;
 154         struct regmap *regmap;
 155         u32 max_arr;
 156         struct stm32_timers_dma dma; /* Only to be used by the parent */
 157         unsigned int nr_irqs;
 158         int irq[STM32_TIMERS_MAX_IRQS];
 159 };
 160
 161 #if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS)
 162 int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
 163                                 enum stm32_timers_dmas id, u32 reg,
 164                                 unsigned int num_reg, unsigned int bursts,
 165                                 unsigned long tmo_ms);
 166 #else
 167 static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
 168                                               enum stm32_timers_dmas id,
 169                                               u32 reg,
 170                                               unsigned int num_reg,
 171                                               unsigned int bursts,
 172                                               unsigned long tmo_ms)
 173 {
 174         return -ENODEV;
 175 }
 176 #endif
 177 #endif