include/linux/soc/mediatek/mtk-mmsys.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #ifndef __MTK_MMSYS_H
   7 #define __MTK_MMSYS_H
   8
   9 #include <linux/mailbox_controller.h>
  10 #include <linux/mailbox/mtk-cmdq-mailbox.h>
  11 #include <linux/soc/mediatek/mtk-cmdq.h>
  12
  13 enum mtk_ddp_comp_id;
  14 struct device;
  15
  16 enum mtk_dpi_out_format_con {
  17         MTK_DPI_RGB888_SDR_CON,
  18         MTK_DPI_RGB888_DDR_CON,
  19         MTK_DPI_RGB565_SDR_CON,
  20         MTK_DPI_RGB565_DDR_CON
  21 };
  22
  23 enum mtk_ddp_comp_id {
  24         DDP_COMPONENT_AAL0,
  25         DDP_COMPONENT_AAL1,
  26         DDP_COMPONENT_BLS,
  27         DDP_COMPONENT_CCORR,
  28         DDP_COMPONENT_COLOR0,
  29         DDP_COMPONENT_COLOR1,
  30         DDP_COMPONENT_DITHER,
  31         DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
  32         DDP_COMPONENT_DITHER1,
  33         DDP_COMPONENT_DP_INTF0,
  34         DDP_COMPONENT_DP_INTF1,
  35         DDP_COMPONENT_DPI0,
  36         DDP_COMPONENT_DPI1,
  37         DDP_COMPONENT_DSC0,
  38         DDP_COMPONENT_DSC1,
  39         DDP_COMPONENT_DSI0,
  40         DDP_COMPONENT_DSI1,
  41         DDP_COMPONENT_DSI2,
  42         DDP_COMPONENT_DSI3,
  43         DDP_COMPONENT_ETHDR_MIXER,
  44         DDP_COMPONENT_GAMMA,
  45         DDP_COMPONENT_MDP_RDMA0,
  46         DDP_COMPONENT_MDP_RDMA1,
  47         DDP_COMPONENT_MDP_RDMA2,
  48         DDP_COMPONENT_MDP_RDMA3,
  49         DDP_COMPONENT_MDP_RDMA4,
  50         DDP_COMPONENT_MDP_RDMA5,
  51         DDP_COMPONENT_MDP_RDMA6,
  52         DDP_COMPONENT_MDP_RDMA7,
  53         DDP_COMPONENT_MERGE0,
  54         DDP_COMPONENT_MERGE1,
  55         DDP_COMPONENT_MERGE2,
  56         DDP_COMPONENT_MERGE3,
  57         DDP_COMPONENT_MERGE4,
  58         DDP_COMPONENT_MERGE5,
  59         DDP_COMPONENT_OD0,
  60         DDP_COMPONENT_OD1,
  61         DDP_COMPONENT_OVL0,
  62         DDP_COMPONENT_OVL_2L0,
  63         DDP_COMPONENT_OVL_2L1,
  64         DDP_COMPONENT_OVL_2L2,
  65         DDP_COMPONENT_OVL1,
  66         DDP_COMPONENT_POSTMASK0,
  67         DDP_COMPONENT_PWM0,
  68         DDP_COMPONENT_PWM1,
  69         DDP_COMPONENT_PWM2,
  70         DDP_COMPONENT_RDMA0,
  71         DDP_COMPONENT_RDMA1,
  72         DDP_COMPONENT_RDMA2,
  73         DDP_COMPONENT_RDMA4,
  74         DDP_COMPONENT_UFOE,
  75         DDP_COMPONENT_WDMA0,
  76         DDP_COMPONENT_WDMA1,
  77         DDP_COMPONENT_ID_MAX,
  78 };
  79
  80 void mtk_mmsys_ddp_connect(struct device *dev,
  81                            enum mtk_ddp_comp_id cur,
  82                            enum mtk_ddp_comp_id next);
  83
  84 void mtk_mmsys_ddp_disconnect(struct device *dev,
  85                               enum mtk_ddp_comp_id cur,
  86                               enum mtk_ddp_comp_id next);
  87
  88 void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
  89
  90 void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width,
  91                                   int height, struct cmdq_pkt *cmdq_pkt);
  92
  93 void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
  94                           struct cmdq_pkt *cmdq_pkt);
  95
  96 void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
  97                                u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt);
  98
  99 void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
 100                                      struct cmdq_pkt *cmdq_pkt);
 101
 102 void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable,
 103                                     struct cmdq_pkt *cmdq_pkt);
 104
 105 void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable,
 106                                   struct cmdq_pkt *cmdq_pkt);
 107
 108 #endif /* __MTK_MMSYS_H */