drivers/video/fbdev/omap2/omapfb/dss/dispc.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * linux/drivers/video/omap2/dss/dispc.h
   4  *
   5  * Copyright (C) 2011 Texas Instruments
   6  * Author: Archit Taneja <[email protected]>
   7  */
   8
   9 #ifndef __OMAP2_DISPC_REG_H
  10 #define __OMAP2_DISPC_REG_H
  11
  12 /* DISPC common registers */
  13 #define DISPC_REVISION                  0x0000
  14 #define DISPC_SYSCONFIG                 0x0010
  15 #define DISPC_SYSSTATUS                 0x0014
  16 #define DISPC_IRQSTATUS                 0x0018
  17 #define DISPC_IRQENABLE                 0x001C
  18 #define DISPC_CONTROL                   0x0040
  19 #define DISPC_CONFIG                    0x0044
  20 #define DISPC_CAPABLE                   0x0048
  21 #define DISPC_LINE_STATUS               0x005C
  22 #define DISPC_LINE_NUMBER               0x0060
  23 #define DISPC_GLOBAL_ALPHA              0x0074
  24 #define DISPC_CONTROL2                  0x0238
  25 #define DISPC_CONFIG2                   0x0620
  26 #define DISPC_DIVISOR                   0x0804
  27 #define DISPC_GLOBAL_BUFFER             0x0800
  28 #define DISPC_CONTROL3                  0x0848
  29 #define DISPC_CONFIG3                   0x084C
  30 #define DISPC_MSTANDBY_CTRL             0x0858
  31 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE    0x085C
  32
  33 /* DISPC overlay registers */
  34 #define DISPC_OVL_BA0(n)                (DISPC_OVL_BASE(n) + \
  35                                         DISPC_BA0_OFFSET(n))
  36 #define DISPC_OVL_BA1(n)                (DISPC_OVL_BASE(n) + \
  37                                         DISPC_BA1_OFFSET(n))
  38 #define DISPC_OVL_BA0_UV(n)             (DISPC_OVL_BASE(n) + \
  39                                         DISPC_BA0_UV_OFFSET(n))
  40 #define DISPC_OVL_BA1_UV(n)             (DISPC_OVL_BASE(n) + \
  41                                         DISPC_BA1_UV_OFFSET(n))
  42 #define DISPC_OVL_POSITION(n)           (DISPC_OVL_BASE(n) + \
  43                                         DISPC_POS_OFFSET(n))
  44 #define DISPC_OVL_SIZE(n)               (DISPC_OVL_BASE(n) + \
  45                                         DISPC_SIZE_OFFSET(n))
  46 #define DISPC_OVL_ATTRIBUTES(n)         (DISPC_OVL_BASE(n) + \
  47                                         DISPC_ATTR_OFFSET(n))
  48 #define DISPC_OVL_ATTRIBUTES2(n)        (DISPC_OVL_BASE(n) + \
  49                                         DISPC_ATTR2_OFFSET(n))
  50 #define DISPC_OVL_FIFO_THRESHOLD(n)     (DISPC_OVL_BASE(n) + \
  51                                         DISPC_FIFO_THRESH_OFFSET(n))
  52 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
  53                                         DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  54 #define DISPC_OVL_ROW_INC(n)            (DISPC_OVL_BASE(n) + \
  55                                         DISPC_ROW_INC_OFFSET(n))
  56 #define DISPC_OVL_PIXEL_INC(n)          (DISPC_OVL_BASE(n) + \
  57                                         DISPC_PIX_INC_OFFSET(n))
  58 #define DISPC_OVL_WINDOW_SKIP(n)        (DISPC_OVL_BASE(n) + \
  59                                         DISPC_WINDOW_SKIP_OFFSET(n))
  60 #define DISPC_OVL_TABLE_BA(n)           (DISPC_OVL_BASE(n) + \
  61                                         DISPC_TABLE_BA_OFFSET(n))
  62 #define DISPC_OVL_FIR(n)                (DISPC_OVL_BASE(n) + \
  63                                         DISPC_FIR_OFFSET(n))
  64 #define DISPC_OVL_FIR2(n)               (DISPC_OVL_BASE(n) + \
  65                                         DISPC_FIR2_OFFSET(n))
  66 #define DISPC_OVL_PICTURE_SIZE(n)       (DISPC_OVL_BASE(n) + \
  67                                         DISPC_PIC_SIZE_OFFSET(n))
  68 #define DISPC_OVL_ACCU0(n)              (DISPC_OVL_BASE(n) + \
  69                                         DISPC_ACCU0_OFFSET(n))
  70 #define DISPC_OVL_ACCU1(n)              (DISPC_OVL_BASE(n) + \
  71                                         DISPC_ACCU1_OFFSET(n))
  72 #define DISPC_OVL_ACCU2_0(n)            (DISPC_OVL_BASE(n) + \
  73                                         DISPC_ACCU2_0_OFFSET(n))
  74 #define DISPC_OVL_ACCU2_1(n)            (DISPC_OVL_BASE(n) + \
  75                                         DISPC_ACCU2_1_OFFSET(n))
  76 #define DISPC_OVL_FIR_COEF_H(n, i)      (DISPC_OVL_BASE(n) + \
  77                                         DISPC_FIR_COEF_H_OFFSET(n, i))
  78 #define DISPC_OVL_FIR_COEF_HV(n, i)     (DISPC_OVL_BASE(n) + \
  79                                         DISPC_FIR_COEF_HV_OFFSET(n, i))
  80 #define DISPC_OVL_FIR_COEF_H2(n, i)     (DISPC_OVL_BASE(n) + \
  81                                         DISPC_FIR_COEF_H2_OFFSET(n, i))
  82 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
  83                                         DISPC_FIR_COEF_HV2_OFFSET(n, i))
  84 #define DISPC_OVL_CONV_COEF(n, i)       (DISPC_OVL_BASE(n) + \
  85                                         DISPC_CONV_COEF_OFFSET(n, i))
  86 #define DISPC_OVL_FIR_COEF_V(n, i)      (DISPC_OVL_BASE(n) + \
  87                                         DISPC_FIR_COEF_V_OFFSET(n, i))
  88 #define DISPC_OVL_FIR_COEF_V2(n, i)     (DISPC_OVL_BASE(n) + \
  89                                         DISPC_FIR_COEF_V2_OFFSET(n, i))
  90 #define DISPC_OVL_PRELOAD(n)            (DISPC_OVL_BASE(n) + \
  91                                         DISPC_PRELOAD_OFFSET(n))
  92 #define DISPC_OVL_MFLAG_THRESHOLD(n)    DISPC_MFLAG_THRESHOLD_OFFSET(n)
  93
  94 /* DISPC up/downsampling FIR filter coefficient structure */
  95 struct dispc_coef {
  96         s8 hc4_vc22;
  97         s8 hc3_vc2;
  98         u8 hc2_vc1;
  99         s8 hc1_vc0;
 100         s8 hc0_vc00;
 101 };
 102
 103 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
 104
 105 /* DISPC manager/channel specific registers */
 106 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
 107 {
 108         switch (channel) {
 109         case OMAP_DSS_CHANNEL_LCD:
 110                 return 0x004C;
 111         case OMAP_DSS_CHANNEL_DIGIT:
 112                 return 0x0050;
 113         case OMAP_DSS_CHANNEL_LCD2:
 114                 return 0x03AC;
 115         case OMAP_DSS_CHANNEL_LCD3:
 116                 return 0x0814;
 117         default:
 118                 BUG();
 119                 return 0;
 120         }
 121 }
 122
 123 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
 124 {
 125         switch (channel) {
 126         case OMAP_DSS_CHANNEL_LCD:
 127                 return 0x0054;
 128         case OMAP_DSS_CHANNEL_DIGIT:
 129                 return 0x0058;
 130         case OMAP_DSS_CHANNEL_LCD2:
 131                 return 0x03B0;
 132         case OMAP_DSS_CHANNEL_LCD3:
 133                 return 0x0818;
 134         default:
 135                 BUG();
 136                 return 0;
 137         }
 138 }
 139
 140 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
 141 {
 142         switch (channel) {
 143         case OMAP_DSS_CHANNEL_LCD:
 144                 return 0x0064;
 145         case OMAP_DSS_CHANNEL_DIGIT:
 146                 BUG();
 147                 return 0;
 148         case OMAP_DSS_CHANNEL_LCD2:
 149                 return 0x0400;
 150         case OMAP_DSS_CHANNEL_LCD3:
 151                 return 0x0840;
 152         default:
 153                 BUG();
 154                 return 0;
 155         }
 156 }
 157
 158 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
 159 {
 160         switch (channel) {
 161         case OMAP_DSS_CHANNEL_LCD:
 162                 return 0x0068;
 163         case OMAP_DSS_CHANNEL_DIGIT:
 164                 BUG();
 165                 return 0;
 166         case OMAP_DSS_CHANNEL_LCD2:
 167                 return 0x0404;
 168         case OMAP_DSS_CHANNEL_LCD3:
 169                 return 0x0844;
 170         default:
 171                 BUG();
 172                 return 0;
 173         }
 174 }
 175
 176 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
 177 {
 178         switch (channel) {
 179         case OMAP_DSS_CHANNEL_LCD:
 180                 return 0x006C;
 181         case OMAP_DSS_CHANNEL_DIGIT:
 182                 BUG();
 183                 return 0;
 184         case OMAP_DSS_CHANNEL_LCD2:
 185                 return 0x0408;
 186         case OMAP_DSS_CHANNEL_LCD3:
 187                 return 0x083C;
 188         default:
 189                 BUG();
 190                 return 0;
 191         }
 192 }
 193
 194 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
 195 {
 196         switch (channel) {
 197         case OMAP_DSS_CHANNEL_LCD:
 198                 return 0x0070;
 199         case OMAP_DSS_CHANNEL_DIGIT:
 200                 BUG();
 201                 return 0;
 202         case OMAP_DSS_CHANNEL_LCD2:
 203                 return 0x040C;
 204         case OMAP_DSS_CHANNEL_LCD3:
 205                 return 0x0838;
 206         default:
 207                 BUG();
 208                 return 0;
 209         }
 210 }
 211
 212 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
 213 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
 214 {
 215         switch (channel) {
 216         case OMAP_DSS_CHANNEL_LCD:
 217                 return 0x007C;
 218         case OMAP_DSS_CHANNEL_DIGIT:
 219                 return 0x0078;
 220         case OMAP_DSS_CHANNEL_LCD2:
 221                 return 0x03CC;
 222         case OMAP_DSS_CHANNEL_LCD3:
 223                 return 0x0834;
 224         default:
 225                 BUG();
 226                 return 0;
 227         }
 228 }
 229
 230 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
 231 {
 232         switch (channel) {
 233         case OMAP_DSS_CHANNEL_LCD:
 234                 return 0x01D4;
 235         case OMAP_DSS_CHANNEL_DIGIT:
 236                 BUG();
 237                 return 0;
 238         case OMAP_DSS_CHANNEL_LCD2:
 239                 return 0x03C0;
 240         case OMAP_DSS_CHANNEL_LCD3:
 241                 return 0x0828;
 242         default:
 243                 BUG();
 244                 return 0;
 245         }
 246 }
 247
 248 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
 249 {
 250         switch (channel) {
 251         case OMAP_DSS_CHANNEL_LCD:
 252                 return 0x01D8;
 253         case OMAP_DSS_CHANNEL_DIGIT:
 254                 BUG();
 255                 return 0;
 256         case OMAP_DSS_CHANNEL_LCD2:
 257                 return 0x03C4;
 258         case OMAP_DSS_CHANNEL_LCD3:
 259                 return 0x082C;
 260         default:
 261                 BUG();
 262                 return 0;
 263         }
 264 }
 265
 266 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
 267 {
 268         switch (channel) {
 269         case OMAP_DSS_CHANNEL_LCD:
 270                 return 0x01DC;
 271         case OMAP_DSS_CHANNEL_DIGIT:
 272                 BUG();
 273                 return 0;
 274         case OMAP_DSS_CHANNEL_LCD2:
 275                 return 0x03C8;
 276         case OMAP_DSS_CHANNEL_LCD3:
 277                 return 0x0830;
 278         default:
 279                 BUG();
 280                 return 0;
 281         }
 282 }
 283
 284 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
 285 {
 286         switch (channel) {
 287         case OMAP_DSS_CHANNEL_LCD:
 288                 return 0x0220;
 289         case OMAP_DSS_CHANNEL_DIGIT:
 290                 BUG();
 291                 return 0;
 292         case OMAP_DSS_CHANNEL_LCD2:
 293                 return 0x03BC;
 294         case OMAP_DSS_CHANNEL_LCD3:
 295                 return 0x0824;
 296         default:
 297                 BUG();
 298                 return 0;
 299         }
 300 }
 301
 302 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
 303 {
 304         switch (channel) {
 305         case OMAP_DSS_CHANNEL_LCD:
 306                 return 0x0224;
 307         case OMAP_DSS_CHANNEL_DIGIT:
 308                 BUG();
 309                 return 0;
 310         case OMAP_DSS_CHANNEL_LCD2:
 311                 return 0x03B8;
 312         case OMAP_DSS_CHANNEL_LCD3:
 313                 return 0x0820;
 314         default:
 315                 BUG();
 316                 return 0;
 317         }
 318 }
 319
 320 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
 321 {
 322         switch (channel) {
 323         case OMAP_DSS_CHANNEL_LCD:
 324                 return 0x0228;
 325         case OMAP_DSS_CHANNEL_DIGIT:
 326                 BUG();
 327                 return 0;
 328         case OMAP_DSS_CHANNEL_LCD2:
 329                 return 0x03B4;
 330         case OMAP_DSS_CHANNEL_LCD3:
 331                 return 0x081C;
 332         default:
 333                 BUG();
 334                 return 0;
 335         }
 336 }
 337
 338 /* DISPC overlay register base addresses */
 339 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 340 {
 341         switch (plane) {
 342         case OMAP_DSS_GFX:
 343                 return 0x0080;
 344         case OMAP_DSS_VIDEO1:
 345                 return 0x00BC;
 346         case OMAP_DSS_VIDEO2:
 347                 return 0x014C;
 348         case OMAP_DSS_VIDEO3:
 349                 return 0x0300;
 350         case OMAP_DSS_WB:
 351                 return 0x0500;
 352         default:
 353                 BUG();
 354                 return 0;
 355         }
 356 }
 357
 358 /* DISPC overlay register offsets */
 359 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 360 {
 361         switch (plane) {
 362         case OMAP_DSS_GFX:
 363         case OMAP_DSS_VIDEO1:
 364         case OMAP_DSS_VIDEO2:
 365                 return 0x0000;
 366         case OMAP_DSS_VIDEO3:
 367         case OMAP_DSS_WB:
 368                 return 0x0008;
 369         default:
 370                 BUG();
 371                 return 0;
 372         }
 373 }
 374
 375 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 376 {
 377         switch (plane) {
 378         case OMAP_DSS_GFX:
 379         case OMAP_DSS_VIDEO1:
 380         case OMAP_DSS_VIDEO2:
 381                 return 0x0004;
 382         case OMAP_DSS_VIDEO3:
 383         case OMAP_DSS_WB:
 384                 return 0x000C;
 385         default:
 386                 BUG();
 387                 return 0;
 388         }
 389 }
 390
 391 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
 392 {
 393         switch (plane) {
 394         case OMAP_DSS_GFX:
 395                 BUG();
 396                 return 0;
 397         case OMAP_DSS_VIDEO1:
 398                 return 0x0544;
 399         case OMAP_DSS_VIDEO2:
 400                 return 0x04BC;
 401         case OMAP_DSS_VIDEO3:
 402                 return 0x0310;
 403         case OMAP_DSS_WB:
 404                 return 0x0118;
 405         default:
 406                 BUG();
 407                 return 0;
 408         }
 409 }
 410
 411 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
 412 {
 413         switch (plane) {
 414         case OMAP_DSS_GFX:
 415                 BUG();
 416                 return 0;
 417         case OMAP_DSS_VIDEO1:
 418                 return 0x0548;
 419         case OMAP_DSS_VIDEO2:
 420                 return 0x04C0;
 421         case OMAP_DSS_VIDEO3:
 422                 return 0x0314;
 423         case OMAP_DSS_WB:
 424                 return 0x011C;
 425         default:
 426                 BUG();
 427                 return 0;
 428         }
 429 }
 430
 431 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 432 {
 433         switch (plane) {
 434         case OMAP_DSS_GFX:
 435         case OMAP_DSS_VIDEO1:
 436         case OMAP_DSS_VIDEO2:
 437                 return 0x0008;
 438         case OMAP_DSS_VIDEO3:
 439                 return 0x009C;
 440         default:
 441                 BUG();
 442                 return 0;
 443         }
 444 }
 445
 446 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 447 {
 448         switch (plane) {
 449         case OMAP_DSS_GFX:
 450         case OMAP_DSS_VIDEO1:
 451         case OMAP_DSS_VIDEO2:
 452                 return 0x000C;
 453         case OMAP_DSS_VIDEO3:
 454         case OMAP_DSS_WB:
 455                 return 0x00A8;
 456         default:
 457                 BUG();
 458                 return 0;
 459         }
 460 }
 461
 462 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 463 {
 464         switch (plane) {
 465         case OMAP_DSS_GFX:
 466                 return 0x0020;
 467         case OMAP_DSS_VIDEO1:
 468         case OMAP_DSS_VIDEO2:
 469                 return 0x0010;
 470         case OMAP_DSS_VIDEO3:
 471         case OMAP_DSS_WB:
 472                 return 0x0070;
 473         default:
 474                 BUG();
 475                 return 0;
 476         }
 477 }
 478
 479 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
 480 {
 481         switch (plane) {
 482         case OMAP_DSS_GFX:
 483                 BUG();
 484                 return 0;
 485         case OMAP_DSS_VIDEO1:
 486                 return 0x0568;
 487         case OMAP_DSS_VIDEO2:
 488                 return 0x04DC;
 489         case OMAP_DSS_VIDEO3:
 490                 return 0x032C;
 491         case OMAP_DSS_WB:
 492                 return 0x0310;
 493         default:
 494                 BUG();
 495                 return 0;
 496         }
 497 }
 498
 499 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 500 {
 501         switch (plane) {
 502         case OMAP_DSS_GFX:
 503                 return 0x0024;
 504         case OMAP_DSS_VIDEO1:
 505         case OMAP_DSS_VIDEO2:
 506                 return 0x0014;
 507         case OMAP_DSS_VIDEO3:
 508         case OMAP_DSS_WB:
 509                 return 0x008C;
 510         default:
 511                 BUG();
 512                 return 0;
 513         }
 514 }
 515
 516 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 517 {
 518         switch (plane) {
 519         case OMAP_DSS_GFX:
 520                 return 0x0028;
 521         case OMAP_DSS_VIDEO1:
 522         case OMAP_DSS_VIDEO2:
 523                 return 0x0018;
 524         case OMAP_DSS_VIDEO3:
 525         case OMAP_DSS_WB:
 526                 return 0x0088;
 527         default:
 528                 BUG();
 529                 return 0;
 530         }
 531 }
 532
 533 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 534 {
 535         switch (plane) {
 536         case OMAP_DSS_GFX:
 537                 return 0x002C;
 538         case OMAP_DSS_VIDEO1:
 539         case OMAP_DSS_VIDEO2:
 540                 return 0x001C;
 541         case OMAP_DSS_VIDEO3:
 542         case OMAP_DSS_WB:
 543                 return 0x00A4;
 544         default:
 545                 BUG();
 546                 return 0;
 547         }
 548 }
 549
 550 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 551 {
 552         switch (plane) {
 553         case OMAP_DSS_GFX:
 554                 return 0x0030;
 555         case OMAP_DSS_VIDEO1:
 556         case OMAP_DSS_VIDEO2:
 557                 return 0x0020;
 558         case OMAP_DSS_VIDEO3:
 559         case OMAP_DSS_WB:
 560                 return 0x0098;
 561         default:
 562                 BUG();
 563                 return 0;
 564         }
 565 }
 566
 567 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 568 {
 569         switch (plane) {
 570         case OMAP_DSS_GFX:
 571                 return 0x0034;
 572         case OMAP_DSS_VIDEO1:
 573         case OMAP_DSS_VIDEO2:
 574         case OMAP_DSS_VIDEO3:
 575                 BUG();
 576                 return 0;
 577         default:
 578                 BUG();
 579                 return 0;
 580         }
 581 }
 582
 583 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 584 {
 585         switch (plane) {
 586         case OMAP_DSS_GFX:
 587                 return 0x0038;
 588         case OMAP_DSS_VIDEO1:
 589         case OMAP_DSS_VIDEO2:
 590         case OMAP_DSS_VIDEO3:
 591                 BUG();
 592                 return 0;
 593         default:
 594                 BUG();
 595                 return 0;
 596         }
 597 }
 598
 599 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 600 {
 601         switch (plane) {
 602         case OMAP_DSS_GFX:
 603                 BUG();
 604                 return 0;
 605         case OMAP_DSS_VIDEO1:
 606         case OMAP_DSS_VIDEO2:
 607                 return 0x0024;
 608         case OMAP_DSS_VIDEO3:
 609         case OMAP_DSS_WB:
 610                 return 0x0090;
 611         default:
 612                 BUG();
 613                 return 0;
 614         }
 615 }
 616
 617 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
 618 {
 619         switch (plane) {
 620         case OMAP_DSS_GFX:
 621                 BUG();
 622                 return 0;
 623         case OMAP_DSS_VIDEO1:
 624                 return 0x0580;
 625         case OMAP_DSS_VIDEO2:
 626                 return 0x055C;
 627         case OMAP_DSS_VIDEO3:
 628                 return 0x0424;
 629         case OMAP_DSS_WB:
 630                 return 0x290;
 631         default:
 632                 BUG();
 633                 return 0;
 634         }
 635 }
 636
 637 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 638 {
 639         switch (plane) {
 640         case OMAP_DSS_GFX:
 641                 BUG();
 642                 return 0;
 643         case OMAP_DSS_VIDEO1:
 644         case OMAP_DSS_VIDEO2:
 645                 return 0x0028;
 646         case OMAP_DSS_VIDEO3:
 647         case OMAP_DSS_WB:
 648                 return 0x0094;
 649         default:
 650                 BUG();
 651                 return 0;
 652         }
 653 }
 654
 655
 656 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 657 {
 658         switch (plane) {
 659         case OMAP_DSS_GFX:
 660                 BUG();
 661                 return 0;
 662         case OMAP_DSS_VIDEO1:
 663         case OMAP_DSS_VIDEO2:
 664                 return 0x002C;
 665         case OMAP_DSS_VIDEO3:
 666         case OMAP_DSS_WB:
 667                 return 0x0000;
 668         default:
 669                 BUG();
 670                 return 0;
 671         }
 672 }
 673
 674 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
 675 {
 676         switch (plane) {
 677         case OMAP_DSS_GFX:
 678                 BUG();
 679                 return 0;
 680         case OMAP_DSS_VIDEO1:
 681                 return 0x0584;
 682         case OMAP_DSS_VIDEO2:
 683                 return 0x0560;
 684         case OMAP_DSS_VIDEO3:
 685                 return 0x0428;
 686         case OMAP_DSS_WB:
 687                 return 0x0294;
 688         default:
 689                 BUG();
 690                 return 0;
 691         }
 692 }
 693
 694 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 695 {
 696         switch (plane) {
 697         case OMAP_DSS_GFX:
 698                 BUG();
 699                 return 0;
 700         case OMAP_DSS_VIDEO1:
 701         case OMAP_DSS_VIDEO2:
 702                 return 0x0030;
 703         case OMAP_DSS_VIDEO3:
 704         case OMAP_DSS_WB:
 705                 return 0x0004;
 706         default:
 707                 BUG();
 708                 return 0;
 709         }
 710 }
 711
 712 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
 713 {
 714         switch (plane) {
 715         case OMAP_DSS_GFX:
 716                 BUG();
 717                 return 0;
 718         case OMAP_DSS_VIDEO1:
 719                 return 0x0588;
 720         case OMAP_DSS_VIDEO2:
 721                 return 0x0564;
 722         case OMAP_DSS_VIDEO3:
 723                 return 0x042C;
 724         case OMAP_DSS_WB:
 725                 return 0x0298;
 726         default:
 727                 BUG();
 728                 return 0;
 729         }
 730 }
 731
 732 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 733 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 734 {
 735         switch (plane) {
 736         case OMAP_DSS_GFX:
 737                 BUG();
 738                 return 0;
 739         case OMAP_DSS_VIDEO1:
 740         case OMAP_DSS_VIDEO2:
 741                 return 0x0034 + i * 0x8;
 742         case OMAP_DSS_VIDEO3:
 743         case OMAP_DSS_WB:
 744                 return 0x0010 + i * 0x8;
 745         default:
 746                 BUG();
 747                 return 0;
 748         }
 749 }
 750
 751 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 752 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
 753 {
 754         switch (plane) {
 755         case OMAP_DSS_GFX:
 756                 BUG();
 757                 return 0;
 758         case OMAP_DSS_VIDEO1:
 759                 return 0x058C + i * 0x8;
 760         case OMAP_DSS_VIDEO2:
 761                 return 0x0568 + i * 0x8;
 762         case OMAP_DSS_VIDEO3:
 763                 return 0x0430 + i * 0x8;
 764         case OMAP_DSS_WB:
 765                 return 0x02A0 + i * 0x8;
 766         default:
 767                 BUG();
 768                 return 0;
 769         }
 770 }
 771
 772 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 773 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 774 {
 775         switch (plane) {
 776         case OMAP_DSS_GFX:
 777                 BUG();
 778                 return 0;
 779         case OMAP_DSS_VIDEO1:
 780         case OMAP_DSS_VIDEO2:
 781                 return 0x0038 + i * 0x8;
 782         case OMAP_DSS_VIDEO3:
 783         case OMAP_DSS_WB:
 784                 return 0x0014 + i * 0x8;
 785         default:
 786                 BUG();
 787                 return 0;
 788         }
 789 }
 790
 791 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 792 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
 793 {
 794         switch (plane) {
 795         case OMAP_DSS_GFX:
 796                 BUG();
 797                 return 0;
 798         case OMAP_DSS_VIDEO1:
 799                 return 0x0590 + i * 8;
 800         case OMAP_DSS_VIDEO2:
 801                 return 0x056C + i * 0x8;
 802         case OMAP_DSS_VIDEO3:
 803                 return 0x0434 + i * 0x8;
 804         case OMAP_DSS_WB:
 805                 return 0x02A4 + i * 0x8;
 806         default:
 807                 BUG();
 808                 return 0;
 809         }
 810 }
 811
 812 /* coef index i = {0, 1, 2, 3, 4,} */
 813 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 814 {
 815         switch (plane) {
 816         case OMAP_DSS_GFX:
 817                 BUG();
 818                 return 0;
 819         case OMAP_DSS_VIDEO1:
 820         case OMAP_DSS_VIDEO2:
 821         case OMAP_DSS_VIDEO3:
 822         case OMAP_DSS_WB:
 823                 return 0x0074 + i * 0x4;
 824         default:
 825                 BUG();
 826                 return 0;
 827         }
 828 }
 829
 830 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 831 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 832 {
 833         switch (plane) {
 834         case OMAP_DSS_GFX:
 835                 BUG();
 836                 return 0;
 837         case OMAP_DSS_VIDEO1:
 838                 return 0x0124 + i * 0x4;
 839         case OMAP_DSS_VIDEO2:
 840                 return 0x00B4 + i * 0x4;
 841         case OMAP_DSS_VIDEO3:
 842         case OMAP_DSS_WB:
 843                 return 0x0050 + i * 0x4;
 844         default:
 845                 BUG();
 846                 return 0;
 847         }
 848 }
 849
 850 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 851 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
 852 {
 853         switch (plane) {
 854         case OMAP_DSS_GFX:
 855                 BUG();
 856                 return 0;
 857         case OMAP_DSS_VIDEO1:
 858                 return 0x05CC + i * 0x4;
 859         case OMAP_DSS_VIDEO2:
 860                 return 0x05A8 + i * 0x4;
 861         case OMAP_DSS_VIDEO3:
 862                 return 0x0470 + i * 0x4;
 863         case OMAP_DSS_WB:
 864                 return 0x02E0 + i * 0x4;
 865         default:
 866                 BUG();
 867                 return 0;
 868         }
 869 }
 870
 871 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 872 {
 873         switch (plane) {
 874         case OMAP_DSS_GFX:
 875                 return 0x01AC;
 876         case OMAP_DSS_VIDEO1:
 877                 return 0x0174;
 878         case OMAP_DSS_VIDEO2:
 879                 return 0x00E8;
 880         case OMAP_DSS_VIDEO3:
 881                 return 0x00A0;
 882         default:
 883                 BUG();
 884                 return 0;
 885         }
 886 }
 887
 888 static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
 889 {
 890         switch (plane) {
 891         case OMAP_DSS_GFX:
 892                 return 0x0860;
 893         case OMAP_DSS_VIDEO1:
 894                 return 0x0864;
 895         case OMAP_DSS_VIDEO2:
 896                 return 0x0868;
 897         case OMAP_DSS_VIDEO3:
 898                 return 0x086c;
 899         case OMAP_DSS_WB:
 900                 return 0x0870;
 901         default:
 902                 BUG();
 903                 return 0;
 904         }
 905 }
 906
 907 #endif