drivers/staging/qlge/qlge_dbg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   3
   4 #include <linux/slab.h>
   5
   6 #include "qlge.h"
   7
   8 /* Read a NIC register from the alternate function. */
   9 static u32 qlge_read_other_func_reg(struct qlge_adapter *qdev,
  10                                     u32 reg)
  11 {
  12         u32 register_to_read;
  13         u32 reg_val;
  14         unsigned int status = 0;
  15
  16         register_to_read = MPI_NIC_REG_BLOCK
  17                                 | MPI_NIC_READ
  18                                 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
  19                                 | reg;
  20         status = qlge_read_mpi_reg(qdev, register_to_read, &reg_val);
  21         if (status != 0)
  22                 return 0xffffffff;
  23
  24         return reg_val;
  25 }
  26
  27 /* Write a NIC register from the alternate function. */
  28 static int qlge_write_other_func_reg(struct qlge_adapter *qdev,
  29                                      u32 reg, u32 reg_val)
  30 {
  31         u32 register_to_read;
  32
  33         register_to_read = MPI_NIC_REG_BLOCK
  34                                 | MPI_NIC_READ
  35                                 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
  36                                 | reg;
  37
  38         return qlge_write_mpi_reg(qdev, register_to_read, reg_val);
  39 }
  40
  41 static int qlge_wait_other_func_reg_rdy(struct qlge_adapter *qdev, u32 reg,
  42                                         u32 bit, u32 err_bit)
  43 {
  44         u32 temp;
  45         int count;
  46
  47         for (count = 10; count; count--) {
  48                 temp = qlge_read_other_func_reg(qdev, reg);
  49
  50                 /* check for errors */
  51                 if (temp & err_bit)
  52                         return -1;
  53                 else if (temp & bit)
  54                         return 0;
  55                 mdelay(10);
  56         }
  57         return -1;
  58 }
  59
  60 static int qlge_read_other_func_serdes_reg(struct qlge_adapter *qdev, u32 reg,
  61                                            u32 *data)
  62 {
  63         int status;
  64
  65         /* wait for reg to come ready */
  66         status = qlge_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
  67                                               XG_SERDES_ADDR_RDY, 0);
  68         if (status)
  69                 goto exit;
  70
  71         /* set up for reg read */
  72         qlge_write_other_func_reg(qdev, XG_SERDES_ADDR / 4, reg | PROC_ADDR_R);
  73
  74         /* wait for reg to come ready */
  75         status = qlge_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
  76                                               XG_SERDES_ADDR_RDY, 0);
  77         if (status)
  78                 goto exit;
  79
  80         /* get the data */
  81         *data = qlge_read_other_func_reg(qdev, (XG_SERDES_DATA / 4));
  82 exit:
  83         return status;
  84 }
  85
  86 /* Read out the SERDES registers */
  87 static int qlge_read_serdes_reg(struct qlge_adapter *qdev, u32 reg, u32 *data)
  88 {
  89         int status;
  90
  91         /* wait for reg to come ready */
  92         status = qlge_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
  93         if (status)
  94                 goto exit;
  95
  96         /* set up for reg read */
  97         qlge_write32(qdev, XG_SERDES_ADDR, reg | PROC_ADDR_R);
  98
  99         /* wait for reg to come ready */
 100         status = qlge_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
 101         if (status)
 102                 goto exit;
 103
 104         /* get the data */
 105         *data = qlge_read32(qdev, XG_SERDES_DATA);
 106 exit:
 107         return status;
 108 }
 109
 110 static void qlge_get_both_serdes(struct qlge_adapter *qdev, u32 addr,
 111                                  u32 *direct_ptr, u32 *indirect_ptr,
 112                                  bool direct_valid, bool indirect_valid)
 113 {
 114         unsigned int status;
 115
 116         status = 1;
 117         if (direct_valid)
 118                 status = qlge_read_serdes_reg(qdev, addr, direct_ptr);
 119         /* Dead fill any failures or invalids. */
 120         if (status)
 121                 *direct_ptr = 0xDEADBEEF;
 122
 123         status = 1;
 124         if (indirect_valid)
 125                 status = qlge_read_other_func_serdes_reg(qdev, addr,
 126                                                          indirect_ptr);
 127         /* Dead fill any failures or invalids. */
 128         if (status)
 129                 *indirect_ptr = 0xDEADBEEF;
 130 }
 131
 132 static int qlge_get_serdes_regs(struct qlge_adapter *qdev,
 133                                 struct qlge_mpi_coredump *mpi_coredump)
 134 {
 135         int status;
 136         bool xfi_direct_valid = false, xfi_indirect_valid = false;
 137         bool xaui_direct_valid = true, xaui_indirect_valid = true;
 138         unsigned int i;
 139         u32 *direct_ptr, temp;
 140         u32 *indirect_ptr;
 141
 142         /* The XAUI needs to be read out per port */
 143         status = qlge_read_other_func_serdes_reg(qdev,
 144                                                  XG_SERDES_XAUI_HSS_PCS_START,
 145                                                  &temp);
 146         if (status)
 147                 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
 148
 149         if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
 150                                 XG_SERDES_ADDR_XAUI_PWR_DOWN)
 151                 xaui_indirect_valid = false;
 152
 153         status = qlge_read_serdes_reg(qdev, XG_SERDES_XAUI_HSS_PCS_START, &temp);
 154
 155         if (status)
 156                 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
 157
 158         if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
 159                                 XG_SERDES_ADDR_XAUI_PWR_DOWN)
 160                 xaui_direct_valid = false;
 161
 162         /*
 163          * XFI register is shared so only need to read one
 164          * functions and then check the bits.
 165          */
 166         status = qlge_read_serdes_reg(qdev, XG_SERDES_ADDR_STS, &temp);
 167         if (status)
 168                 temp = 0;
 169
 170         if ((temp & XG_SERDES_ADDR_XFI1_PWR_UP) ==
 171                                         XG_SERDES_ADDR_XFI1_PWR_UP) {
 172                 /* now see if i'm NIC 1 or NIC 2 */
 173                 if (qdev->func & 1)
 174                         /* I'm NIC 2, so the indirect (NIC1) xfi is up. */
 175                         xfi_indirect_valid = true;
 176                 else
 177                         xfi_direct_valid = true;
 178         }
 179         if ((temp & XG_SERDES_ADDR_XFI2_PWR_UP) ==
 180                                         XG_SERDES_ADDR_XFI2_PWR_UP) {
 181                 /* now see if i'm NIC 1 or NIC 2 */
 182                 if (qdev->func & 1)
 183                         /* I'm NIC 2, so the indirect (NIC1) xfi is up. */
 184                         xfi_direct_valid = true;
 185                 else
 186                         xfi_indirect_valid = true;
 187         }
 188
 189         /* Get XAUI_AN register block. */
 190         if (qdev->func & 1) {
 191                 /* Function 2 is direct */
 192                 direct_ptr = mpi_coredump->serdes2_xaui_an;
 193                 indirect_ptr = mpi_coredump->serdes_xaui_an;
 194         } else {
 195                 /* Function 1 is direct */
 196                 direct_ptr = mpi_coredump->serdes_xaui_an;
 197                 indirect_ptr = mpi_coredump->serdes2_xaui_an;
 198         }
 199
 200         for (i = 0; i <= 0x000000034; i += 4, direct_ptr++, indirect_ptr++)
 201                 qlge_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
 202                                      xaui_direct_valid, xaui_indirect_valid);
 203
 204         /* Get XAUI_HSS_PCS register block. */
 205         if (qdev->func & 1) {
 206                 direct_ptr =
 207                         mpi_coredump->serdes2_xaui_hss_pcs;
 208                 indirect_ptr =
 209                         mpi_coredump->serdes_xaui_hss_pcs;
 210         } else {
 211                 direct_ptr =
 212                         mpi_coredump->serdes_xaui_hss_pcs;
 213                 indirect_ptr =
 214                         mpi_coredump->serdes2_xaui_hss_pcs;
 215         }
 216
 217         for (i = 0x800; i <= 0x880; i += 4, direct_ptr++, indirect_ptr++)
 218                 qlge_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
 219                                      xaui_direct_valid, xaui_indirect_valid);
 220
 221         /* Get XAUI_XFI_AN register block. */
 222         if (qdev->func & 1) {
 223                 direct_ptr = mpi_coredump->serdes2_xfi_an;
 224                 indirect_ptr = mpi_coredump->serdes_xfi_an;
 225         } else {
 226                 direct_ptr = mpi_coredump->serdes_xfi_an;
 227                 indirect_ptr = mpi_coredump->serdes2_xfi_an;
 228         }
 229
 230         for (i = 0x1000; i <= 0x1034; i += 4, direct_ptr++, indirect_ptr++)
 231                 qlge_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
 232                                      xfi_direct_valid, xfi_indirect_valid);
 233
 234         /* Get XAUI_XFI_TRAIN register block. */
 235         if (qdev->func & 1) {
 236                 direct_ptr = mpi_coredump->serdes2_xfi_train;
 237                 indirect_ptr =
 238                         mpi_coredump->serdes_xfi_train;
 239         } else {
 240                 direct_ptr = mpi_coredump->serdes_xfi_train;
 241                 indirect_ptr =
 242                         mpi_coredump->serdes2_xfi_train;
 243         }
 244
 245         for (i = 0x1050; i <= 0x107c; i += 4, direct_ptr++, indirect_ptr++)
 246                 qlge_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
 247                                      xfi_direct_valid, xfi_indirect_valid);
 248
 249         /* Get XAUI_XFI_HSS_PCS register block. */
 250         if (qdev->func & 1) {
 251                 direct_ptr =
 252                         mpi_coredump->serdes2_xfi_hss_pcs;
 253                 indirect_ptr =
 254                         mpi_coredump->serdes_xfi_hss_pcs;
 255         } else {
 256                 direct_ptr =
 257                         mpi_coredump->serdes_xfi_hss_pcs;
 258                 indirect_ptr =
 259                         mpi_coredump->serdes2_xfi_hss_pcs;
 260         }
 261
 262         for (i = 0x1800; i <= 0x1838; i += 4, direct_ptr++, indirect_ptr++)
 263                 qlge_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
 264                                      xfi_direct_valid, xfi_indirect_valid);
 265
 266         /* Get XAUI_XFI_HSS_TX register block. */
 267         if (qdev->func & 1) {
 268                 direct_ptr =
 269                         mpi_coredump->serdes2_xfi_hss_tx;
 270                 indirect_ptr =
 271                         mpi_coredump->serdes_xfi_hss_tx;
 272         } else {
 273                 direct_ptr = mpi_coredump->serdes_xfi_hss_tx;
 274                 indirect_ptr =
 275                         mpi_coredump->serdes2_xfi_hss_tx;
 276         }
 277         for (i = 0x1c00; i <= 0x1c1f; i++, direct_ptr++, indirect_ptr++)
 278                 qlge_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
 279                                      xfi_direct_valid, xfi_indirect_valid);
 280
 281         /* Get XAUI_XFI_HSS_RX register block. */
 282         if (qdev->func & 1) {
 283                 direct_ptr =
 284                         mpi_coredump->serdes2_xfi_hss_rx;
 285                 indirect_ptr =
 286                         mpi_coredump->serdes_xfi_hss_rx;
 287         } else {
 288                 direct_ptr = mpi_coredump->serdes_xfi_hss_rx;
 289                 indirect_ptr =
 290                         mpi_coredump->serdes2_xfi_hss_rx;
 291         }
 292
 293         for (i = 0x1c40; i <= 0x1c5f; i++, direct_ptr++, indirect_ptr++)
 294                 qlge_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
 295                                      xfi_direct_valid, xfi_indirect_valid);
 296
 297         /* Get XAUI_XFI_HSS_PLL register block. */
 298         if (qdev->func & 1) {
 299                 direct_ptr =
 300                         mpi_coredump->serdes2_xfi_hss_pll;
 301                 indirect_ptr =
 302                         mpi_coredump->serdes_xfi_hss_pll;
 303         } else {
 304                 direct_ptr =
 305                         mpi_coredump->serdes_xfi_hss_pll;
 306                 indirect_ptr =
 307                         mpi_coredump->serdes2_xfi_hss_pll;
 308         }
 309         for (i = 0x1e00; i <= 0x1e1f; i++, direct_ptr++, indirect_ptr++)
 310                 qlge_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
 311                                      xfi_direct_valid, xfi_indirect_valid);
 312         return 0;
 313 }
 314
 315 static int qlge_read_other_func_xgmac_reg(struct qlge_adapter *qdev, u32 reg,
 316                                           u32 *data)
 317 {
 318         int status = 0;
 319
 320         /* wait for reg to come ready */
 321         status = qlge_wait_other_func_reg_rdy(qdev, XGMAC_ADDR / 4,
 322                                               XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 323         if (status)
 324                 goto exit;
 325
 326         /* set up for reg read */
 327         qlge_write_other_func_reg(qdev, XGMAC_ADDR / 4, reg | XGMAC_ADDR_R);
 328
 329         /* wait for reg to come ready */
 330         status = qlge_wait_other_func_reg_rdy(qdev, XGMAC_ADDR / 4,
 331                                               XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 332         if (status)
 333                 goto exit;
 334
 335         /* get the data */
 336         *data = qlge_read_other_func_reg(qdev, XGMAC_DATA / 4);
 337 exit:
 338         return status;
 339 }
 340
 341 /* Read the 400 xgmac control/statistics registers
 342  * skipping unused locations.
 343  */
 344 static int qlge_get_xgmac_regs(struct qlge_adapter *qdev, u32 *buf,
 345                                unsigned int other_function)
 346 {
 347         int status = 0;
 348         int i;
 349
 350         for (i = PAUSE_SRC_LO; i < XGMAC_REGISTER_END; i += 4, buf++) {
 351                 /* We're reading 400 xgmac registers, but we filter out
 352                  * several locations that are non-responsive to reads.
 353                  */
 354                 if ((i == 0x00000114) || (i == 0x00000118) ||
 355                     (i == 0x0000013c) || (i == 0x00000140) ||
 356                     (i > 0x00000150 && i < 0x000001fc) ||
 357                     (i > 0x00000278 && i < 0x000002a0) ||
 358                     (i > 0x000002c0 && i < 0x000002cf) ||
 359                     (i > 0x000002dc && i < 0x000002f0) ||
 360                     (i > 0x000003c8 && i < 0x00000400) ||
 361                     (i > 0x00000400 && i < 0x00000410) ||
 362                     (i > 0x00000410 && i < 0x00000420) ||
 363                     (i > 0x00000420 && i < 0x00000430) ||
 364                     (i > 0x00000430 && i < 0x00000440) ||
 365                     (i > 0x00000440 && i < 0x00000450) ||
 366                     (i > 0x00000450 && i < 0x00000500) ||
 367                     (i > 0x0000054c && i < 0x00000568) ||
 368                     (i > 0x000005c8 && i < 0x00000600)) {
 369                         if (other_function)
 370                                 status = qlge_read_other_func_xgmac_reg(qdev, i, buf);
 371                         else
 372                                 status = qlge_read_xgmac_reg(qdev, i, buf);
 373
 374                         if (status)
 375                                 *buf = 0xdeadbeef;
 376                         break;
 377                 }
 378         }
 379         return status;
 380 }
 381
 382 static int qlge_get_ets_regs(struct qlge_adapter *qdev, u32 *buf)
 383 {
 384         int i;
 385
 386         for (i = 0; i < 8; i++, buf++) {
 387                 qlge_write32(qdev, NIC_ETS, i << 29 | 0x08000000);
 388                 *buf = qlge_read32(qdev, NIC_ETS);
 389         }
 390
 391         for (i = 0; i < 2; i++, buf++) {
 392                 qlge_write32(qdev, CNA_ETS, i << 29 | 0x08000000);
 393                 *buf = qlge_read32(qdev, CNA_ETS);
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void qlge_get_intr_states(struct qlge_adapter *qdev, u32 *buf)
 400 {
 401         int i;
 402
 403         for (i = 0; i < qdev->rx_ring_count; i++, buf++) {
 404                 qlge_write32(qdev, INTR_EN,
 405                              qdev->intr_context[i].intr_read_mask);
 406                 *buf = qlge_read32(qdev, INTR_EN);
 407         }
 408 }
 409
 410 static int qlge_get_cam_entries(struct qlge_adapter *qdev, u32 *buf)
 411 {
 412         int i, status;
 413         u32 value[3];
 414
 415         status = qlge_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 416         if (status)
 417                 return status;
 418
 419         for (i = 0; i < 16; i++) {
 420                 status = qlge_get_mac_addr_reg(qdev,
 421                                                MAC_ADDR_TYPE_CAM_MAC, i, value);
 422                 if (status) {
 423                         netif_err(qdev, drv, qdev->ndev,
 424                                   "Failed read of mac index register\n");
 425                         goto err;
 426                 }
 427                 *buf++ = value[0];      /* lower MAC address */
 428                 *buf++ = value[1];      /* upper MAC address */
 429                 *buf++ = value[2];      /* output */
 430         }
 431         for (i = 0; i < 32; i++) {
 432                 status = qlge_get_mac_addr_reg(qdev, MAC_ADDR_TYPE_MULTI_MAC,
 433                                                i, value);
 434                 if (status) {
 435                         netif_err(qdev, drv, qdev->ndev,
 436                                   "Failed read of mac index register\n");
 437                         goto err;
 438                 }
 439                 *buf++ = value[0];      /* lower Mcast address */
 440                 *buf++ = value[1];      /* upper Mcast address */
 441         }
 442 err:
 443         qlge_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 444         return status;
 445 }
 446
 447 static int qlge_get_routing_entries(struct qlge_adapter *qdev, u32 *buf)
 448 {
 449         int status;
 450         u32 value, i;
 451
 452         status = qlge_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 453         if (status)
 454                 return status;
 455
 456         for (i = 0; i < 16; i++) {
 457                 status = qlge_get_routing_reg(qdev, i, &value);
 458                 if (status) {
 459                         netif_err(qdev, drv, qdev->ndev,
 460                                   "Failed read of routing index register\n");
 461                         goto err;
 462                 } else {
 463                         *buf++ = value;
 464                 }
 465         }
 466 err:
 467         qlge_sem_unlock(qdev, SEM_RT_IDX_MASK);
 468         return status;
 469 }
 470
 471 /* Read the MPI Processor shadow registers */
 472 static int qlge_get_mpi_shadow_regs(struct qlge_adapter *qdev, u32 *buf)
 473 {
 474         u32 i;
 475         int status;
 476
 477         for (i = 0; i < MPI_CORE_SH_REGS_CNT; i++, buf++) {
 478                 status = qlge_write_mpi_reg(qdev,
 479                                             RISC_124,
 480                                             (SHADOW_OFFSET | i << SHADOW_REG_SHIFT));
 481                 if (status)
 482                         goto end;
 483                 status = qlge_read_mpi_reg(qdev, RISC_127, buf);
 484                 if (status)
 485                         goto end;
 486         }
 487 end:
 488         return status;
 489 }
 490
 491 /* Read the MPI Processor core registers */
 492 static int qlge_get_mpi_regs(struct qlge_adapter *qdev, u32 *buf,
 493                              u32 offset, u32 count)
 494 {
 495         int i, status = 0;
 496
 497         for (i = 0; i < count; i++, buf++) {
 498                 status = qlge_read_mpi_reg(qdev, offset + i, buf);
 499                 if (status)
 500                         return status;
 501         }
 502         return status;
 503 }
 504
 505 /* Read the ASIC probe dump */
 506 static unsigned int *qlge_get_probe(struct qlge_adapter *qdev, u32 clock,
 507                                     u32 valid, u32 *buf)
 508 {
 509         u32 module, mux_sel, probe, lo_val, hi_val;
 510
 511         for (module = 0; module < PRB_MX_ADDR_MAX_MODS; module++) {
 512                 if (!((valid >> module) & 1))
 513                         continue;
 514                 for (mux_sel = 0; mux_sel < PRB_MX_ADDR_MAX_MUX; mux_sel++) {
 515                         probe = clock
 516                                 | PRB_MX_ADDR_ARE
 517                                 | mux_sel
 518                                 | (module << PRB_MX_ADDR_MOD_SEL_SHIFT);
 519                         qlge_write32(qdev, PRB_MX_ADDR, probe);
 520                         lo_val = qlge_read32(qdev, PRB_MX_DATA);
 521                         if (mux_sel == 0) {
 522                                 *buf = probe;
 523                                 buf++;
 524                         }
 525                         probe |= PRB_MX_ADDR_UP;
 526                         qlge_write32(qdev, PRB_MX_ADDR, probe);
 527                         hi_val = qlge_read32(qdev, PRB_MX_DATA);
 528                         *buf = lo_val;
 529                         buf++;
 530                         *buf = hi_val;
 531                         buf++;
 532                 }
 533         }
 534         return buf;
 535 }
 536
 537 static int qlge_get_probe_dump(struct qlge_adapter *qdev, unsigned int *buf)
 538 {
 539         /* First we have to enable the probe mux */
 540         qlge_write_mpi_reg(qdev, MPI_TEST_FUNC_PRB_CTL, MPI_TEST_FUNC_PRB_EN);
 541         buf = qlge_get_probe(qdev, PRB_MX_ADDR_SYS_CLOCK,
 542                              PRB_MX_ADDR_VALID_SYS_MOD, buf);
 543         buf = qlge_get_probe(qdev, PRB_MX_ADDR_PCI_CLOCK,
 544                              PRB_MX_ADDR_VALID_PCI_MOD, buf);
 545         buf = qlge_get_probe(qdev, PRB_MX_ADDR_XGM_CLOCK,
 546                              PRB_MX_ADDR_VALID_XGM_MOD, buf);
 547         buf = qlge_get_probe(qdev, PRB_MX_ADDR_FC_CLOCK,
 548                              PRB_MX_ADDR_VALID_FC_MOD, buf);
 549         return 0;
 550 }
 551
 552 /* Read out the routing index registers */
 553 static int qlge_get_routing_index_registers(struct qlge_adapter *qdev, u32 *buf)
 554 {
 555         int status;
 556         u32 type, index, index_max;
 557         u32 result_index;
 558         u32 result_data;
 559         u32 val;
 560
 561         status = qlge_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 562         if (status)
 563                 return status;
 564
 565         for (type = 0; type < 4; type++) {
 566                 if (type < 2)
 567                         index_max = 8;
 568                 else
 569                         index_max = 16;
 570                 for (index = 0; index < index_max; index++) {
 571                         val = RT_IDX_RS
 572                                 | (type << RT_IDX_TYPE_SHIFT)
 573                                 | (index << RT_IDX_IDX_SHIFT);
 574                         qlge_write32(qdev, RT_IDX, val);
 575                         result_index = 0;
 576                         while ((result_index & RT_IDX_MR) == 0)
 577                                 result_index = qlge_read32(qdev, RT_IDX);
 578                         result_data = qlge_read32(qdev, RT_DATA);
 579                         *buf = type;
 580                         buf++;
 581                         *buf = index;
 582                         buf++;
 583                         *buf = result_index;
 584                         buf++;
 585                         *buf = result_data;
 586                         buf++;
 587                 }
 588         }
 589         qlge_sem_unlock(qdev, SEM_RT_IDX_MASK);
 590         return status;
 591 }
 592
 593 /* Read out the MAC protocol registers */
 594 static void qlge_get_mac_protocol_registers(struct qlge_adapter *qdev, u32 *buf)
 595 {
 596         u32 result_index, result_data;
 597         u32 type;
 598         u32 index;
 599         u32 offset;
 600         u32 val;
 601         u32 initial_val = MAC_ADDR_RS;
 602         u32 max_index;
 603         u32 max_offset;
 604
 605         for (type = 0; type < MAC_ADDR_TYPE_COUNT; type++) {
 606                 switch (type) {
 607                 case 0: /* CAM */
 608                         initial_val |= MAC_ADDR_ADR;
 609                         max_index = MAC_ADDR_MAX_CAM_ENTRIES;
 610                         max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
 611                         break;
 612                 case 1: /* Multicast MAC Address */
 613                         max_index = MAC_ADDR_MAX_CAM_WCOUNT;
 614                         max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
 615                         break;
 616                 case 2: /* VLAN filter mask */
 617                 case 3: /* MC filter mask */
 618                         max_index = MAC_ADDR_MAX_CAM_WCOUNT;
 619                         max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
 620                         break;
 621                 case 4: /* FC MAC addresses */
 622                         max_index = MAC_ADDR_MAX_FC_MAC_ENTRIES;
 623                         max_offset = MAC_ADDR_MAX_FC_MAC_WCOUNT;
 624                         break;
 625                 case 5: /* Mgmt MAC addresses */
 626                         max_index = MAC_ADDR_MAX_MGMT_MAC_ENTRIES;
 627                         max_offset = MAC_ADDR_MAX_MGMT_MAC_WCOUNT;
 628                         break;
 629                 case 6: /* Mgmt VLAN addresses */
 630                         max_index = MAC_ADDR_MAX_MGMT_VLAN_ENTRIES;
 631                         max_offset = MAC_ADDR_MAX_MGMT_VLAN_WCOUNT;
 632                         break;
 633                 case 7: /* Mgmt IPv4 address */
 634                         max_index = MAC_ADDR_MAX_MGMT_V4_ENTRIES;
 635                         max_offset = MAC_ADDR_MAX_MGMT_V4_WCOUNT;
 636                         break;
 637                 case 8: /* Mgmt IPv6 address */
 638                         max_index = MAC_ADDR_MAX_MGMT_V6_ENTRIES;
 639                         max_offset = MAC_ADDR_MAX_MGMT_V6_WCOUNT;
 640                         break;
 641                 case 9: /* Mgmt TCP/UDP Dest port */
 642                         max_index = MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES;
 643                         max_offset = MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT;
 644                         break;
 645                 default:
 646                         netdev_err(qdev->ndev, "Bad type!!! 0x%08x\n", type);
 647                         max_index = 0;
 648                         max_offset = 0;
 649                         break;
 650                 }
 651                 for (index = 0; index < max_index; index++) {
 652                         for (offset = 0; offset < max_offset; offset++) {
 653                                 val = initial_val
 654                                         | (type << MAC_ADDR_TYPE_SHIFT)
 655                                         | (index << MAC_ADDR_IDX_SHIFT)
 656                                         | (offset);
 657                                 qlge_write32(qdev, MAC_ADDR_IDX, val);
 658                                 result_index = 0;
 659                                 while ((result_index & MAC_ADDR_MR) == 0) {
 660                                         result_index = qlge_read32(qdev,
 661                                                                    MAC_ADDR_IDX);
 662                                 }
 663                                 result_data = qlge_read32(qdev, MAC_ADDR_DATA);
 664                                 *buf = result_index;
 665                                 buf++;
 666                                 *buf = result_data;
 667                                 buf++;
 668                         }
 669                 }
 670         }
 671 }
 672
 673 static void qlge_get_sem_registers(struct qlge_adapter *qdev, u32 *buf)
 674 {
 675         u32 func_num, reg, reg_val;
 676         int status;
 677
 678         for (func_num = 0; func_num < MAX_SEMAPHORE_FUNCTIONS ; func_num++) {
 679                 reg = MPI_NIC_REG_BLOCK
 680                         | (func_num << MPI_NIC_FUNCTION_SHIFT)
 681                         | (SEM / 4);
 682                 status = qlge_read_mpi_reg(qdev, reg, &reg_val);
 683                 *buf = reg_val;
 684                 /* if the read failed then dead fill the element. */
 685                 if (!status)
 686                         *buf = 0xdeadbeef;
 687                 buf++;
 688         }
 689 }
 690
 691 /* Create a coredump segment header */
 692 static void qlge_build_coredump_seg_header(struct mpi_coredump_segment_header *seg_hdr,
 693                                            u32 seg_number, u32 seg_size, u8 *desc)
 694 {
 695         memset(seg_hdr, 0, sizeof(struct mpi_coredump_segment_header));
 696         seg_hdr->cookie = MPI_COREDUMP_COOKIE;
 697         seg_hdr->seg_num = seg_number;
 698         seg_hdr->seg_size = seg_size;
 699         strncpy(seg_hdr->description, desc, (sizeof(seg_hdr->description)) - 1);
 700 }
 701
 702 /*
 703  * This function should be called when a coredump / probedump
 704  * is to be extracted from the HBA. It is assumed there is a
 705  * qdev structure that contains the base address of the register
 706  * space for this function as well as a coredump structure that
 707  * will contain the dump.
 708  */
 709 int qlge_core_dump(struct qlge_adapter *qdev, struct qlge_mpi_coredump *mpi_coredump)
 710 {
 711         int status;
 712         int i;
 713
 714         if (!mpi_coredump) {
 715                 netif_err(qdev, drv, qdev->ndev, "No memory allocated\n");
 716                 return -EINVAL;
 717         }
 718
 719         /* Try to get the spinlock, but dont worry if
 720          * it isn't available.  If the firmware died it
 721          * might be holding the sem.
 722          */
 723         qlge_sem_spinlock(qdev, SEM_PROC_REG_MASK);
 724
 725         status = qlge_pause_mpi_risc(qdev);
 726         if (status) {
 727                 netif_err(qdev, drv, qdev->ndev,
 728                           "Failed RISC pause. Status = 0x%.08x\n", status);
 729                 goto err;
 730         }
 731
 732         /* Insert the global header */
 733         memset(&mpi_coredump->mpi_global_header, 0,
 734                sizeof(struct mpi_coredump_global_header));
 735         mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
 736         mpi_coredump->mpi_global_header.header_size =
 737                 sizeof(struct mpi_coredump_global_header);
 738         mpi_coredump->mpi_global_header.image_size =
 739                 sizeof(struct qlge_mpi_coredump);
 740         strncpy(mpi_coredump->mpi_global_header.id_string, "MPI Coredump",
 741                 sizeof(mpi_coredump->mpi_global_header.id_string));
 742
 743         /* Get generic NIC reg dump */
 744         qlge_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
 745                                        NIC1_CONTROL_SEG_NUM,
 746                                        sizeof(struct mpi_coredump_segment_header) +
 747                                        sizeof(mpi_coredump->nic_regs), "NIC1 Registers");
 748
 749         qlge_build_coredump_seg_header(&mpi_coredump->nic2_regs_seg_hdr,
 750                                        NIC2_CONTROL_SEG_NUM,
 751                                        sizeof(struct mpi_coredump_segment_header) +
 752                                        sizeof(mpi_coredump->nic2_regs), "NIC2 Registers");
 753
 754         /* Get XGMac registers. (Segment 18, Rev C. step 21) */
 755         qlge_build_coredump_seg_header(&mpi_coredump->xgmac1_seg_hdr,
 756                                        NIC1_XGMAC_SEG_NUM,
 757                                        sizeof(struct mpi_coredump_segment_header) +
 758                                        sizeof(mpi_coredump->xgmac1), "NIC1 XGMac Registers");
 759
 760         qlge_build_coredump_seg_header(&mpi_coredump->xgmac2_seg_hdr,
 761                                        NIC2_XGMAC_SEG_NUM,
 762                                        sizeof(struct mpi_coredump_segment_header) +
 763                                        sizeof(mpi_coredump->xgmac2), "NIC2 XGMac Registers");
 764
 765         if (qdev->func & 1) {
 766                 /* Odd means our function is NIC 2 */
 767                 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
 768                         mpi_coredump->nic2_regs[i] =
 769                                 qlge_read32(qdev, i * sizeof(u32));
 770
 771                 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
 772                         mpi_coredump->nic_regs[i] =
 773                                 qlge_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
 774
 775                 qlge_get_xgmac_regs(qdev, &mpi_coredump->xgmac2[0], 0);
 776                 qlge_get_xgmac_regs(qdev, &mpi_coredump->xgmac1[0], 1);
 777         } else {
 778                 /* Even means our function is NIC 1 */
 779                 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
 780                         mpi_coredump->nic_regs[i] =
 781                                 qlge_read32(qdev, i * sizeof(u32));
 782                 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
 783                         mpi_coredump->nic2_regs[i] =
 784                                 qlge_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
 785
 786                 qlge_get_xgmac_regs(qdev, &mpi_coredump->xgmac1[0], 0);
 787                 qlge_get_xgmac_regs(qdev, &mpi_coredump->xgmac2[0], 1);
 788         }
 789
 790         /* Rev C. Step 20a */
 791         qlge_build_coredump_seg_header(&mpi_coredump->xaui_an_hdr,
 792                                        XAUI_AN_SEG_NUM,
 793                                        sizeof(struct mpi_coredump_segment_header) +
 794                                        sizeof(mpi_coredump->serdes_xaui_an),
 795                                        "XAUI AN Registers");
 796
 797         /* Rev C. Step 20b */
 798         qlge_build_coredump_seg_header(&mpi_coredump->xaui_hss_pcs_hdr,
 799                                        XAUI_HSS_PCS_SEG_NUM,
 800                                        sizeof(struct mpi_coredump_segment_header) +
 801                                        sizeof(mpi_coredump->serdes_xaui_hss_pcs),
 802                                        "XAUI HSS PCS Registers");
 803
 804         qlge_build_coredump_seg_header(&mpi_coredump->xfi_an_hdr, XFI_AN_SEG_NUM,
 805                                        sizeof(struct mpi_coredump_segment_header) +
 806                                        sizeof(mpi_coredump->serdes_xfi_an),
 807                                        "XFI AN Registers");
 808
 809         qlge_build_coredump_seg_header(&mpi_coredump->xfi_train_hdr,
 810                                        XFI_TRAIN_SEG_NUM,
 811                                        sizeof(struct mpi_coredump_segment_header) +
 812                                        sizeof(mpi_coredump->serdes_xfi_train),
 813                                        "XFI TRAIN Registers");
 814
 815         qlge_build_coredump_seg_header(&mpi_coredump->xfi_hss_pcs_hdr,
 816                                        XFI_HSS_PCS_SEG_NUM,
 817                                        sizeof(struct mpi_coredump_segment_header) +
 818                                        sizeof(mpi_coredump->serdes_xfi_hss_pcs),
 819                                        "XFI HSS PCS Registers");
 820
 821         qlge_build_coredump_seg_header(&mpi_coredump->xfi_hss_tx_hdr,
 822                                        XFI_HSS_TX_SEG_NUM,
 823                                        sizeof(struct mpi_coredump_segment_header) +
 824                                        sizeof(mpi_coredump->serdes_xfi_hss_tx),
 825                                        "XFI HSS TX Registers");
 826
 827         qlge_build_coredump_seg_header(&mpi_coredump->xfi_hss_rx_hdr,
 828                                        XFI_HSS_RX_SEG_NUM,
 829                                        sizeof(struct mpi_coredump_segment_header) +
 830                                        sizeof(mpi_coredump->serdes_xfi_hss_rx),
 831                                        "XFI HSS RX Registers");
 832
 833         qlge_build_coredump_seg_header(&mpi_coredump->xfi_hss_pll_hdr,
 834                                        XFI_HSS_PLL_SEG_NUM,
 835                                        sizeof(struct mpi_coredump_segment_header) +
 836                                        sizeof(mpi_coredump->serdes_xfi_hss_pll),
 837                                        "XFI HSS PLL Registers");
 838
 839         qlge_build_coredump_seg_header(&mpi_coredump->xaui2_an_hdr,
 840                                        XAUI2_AN_SEG_NUM,
 841                                        sizeof(struct mpi_coredump_segment_header) +
 842                                        sizeof(mpi_coredump->serdes2_xaui_an),
 843                                        "XAUI2 AN Registers");
 844
 845         qlge_build_coredump_seg_header(&mpi_coredump->xaui2_hss_pcs_hdr,
 846                                        XAUI2_HSS_PCS_SEG_NUM,
 847                                        sizeof(struct mpi_coredump_segment_header) +
 848                                        sizeof(mpi_coredump->serdes2_xaui_hss_pcs),
 849                                        "XAUI2 HSS PCS Registers");
 850
 851         qlge_build_coredump_seg_header(&mpi_coredump->xfi2_an_hdr,
 852                                        XFI2_AN_SEG_NUM,
 853                                        sizeof(struct mpi_coredump_segment_header) +
 854                                        sizeof(mpi_coredump->serdes2_xfi_an),
 855                                        "XFI2 AN Registers");
 856
 857         qlge_build_coredump_seg_header(&mpi_coredump->xfi2_train_hdr,
 858                                        XFI2_TRAIN_SEG_NUM,
 859                                        sizeof(struct mpi_coredump_segment_header) +
 860                                        sizeof(mpi_coredump->serdes2_xfi_train),
 861                                        "XFI2 TRAIN Registers");
 862
 863         qlge_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pcs_hdr,
 864                                        XFI2_HSS_PCS_SEG_NUM,
 865                                        sizeof(struct mpi_coredump_segment_header) +
 866                                        sizeof(mpi_coredump->serdes2_xfi_hss_pcs),
 867                                        "XFI2 HSS PCS Registers");
 868
 869         qlge_build_coredump_seg_header(&mpi_coredump->xfi2_hss_tx_hdr,
 870                                        XFI2_HSS_TX_SEG_NUM,
 871                                        sizeof(struct mpi_coredump_segment_header) +
 872                                        sizeof(mpi_coredump->serdes2_xfi_hss_tx),
 873                                        "XFI2 HSS TX Registers");
 874
 875         qlge_build_coredump_seg_header(&mpi_coredump->xfi2_hss_rx_hdr,
 876                                        XFI2_HSS_RX_SEG_NUM,
 877                                        sizeof(struct mpi_coredump_segment_header) +
 878                                        sizeof(mpi_coredump->serdes2_xfi_hss_rx),
 879                                        "XFI2 HSS RX Registers");
 880
 881         qlge_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pll_hdr,
 882                                        XFI2_HSS_PLL_SEG_NUM,
 883                                        sizeof(struct mpi_coredump_segment_header) +
 884                                        sizeof(mpi_coredump->serdes2_xfi_hss_pll),
 885                                        "XFI2 HSS PLL Registers");
 886
 887         status = qlge_get_serdes_regs(qdev, mpi_coredump);
 888         if (status) {
 889                 netif_err(qdev, drv, qdev->ndev,
 890                           "Failed Dump of Serdes Registers. Status = 0x%.08x\n",
 891                           status);
 892                 goto err;
 893         }
 894
 895         qlge_build_coredump_seg_header(&mpi_coredump->core_regs_seg_hdr,
 896                                        CORE_SEG_NUM,
 897                                        sizeof(mpi_coredump->core_regs_seg_hdr) +
 898                                        sizeof(mpi_coredump->mpi_core_regs) +
 899                                        sizeof(mpi_coredump->mpi_core_sh_regs),
 900                                        "Core Registers");
 901
 902         /* Get the MPI Core Registers */
 903         status = qlge_get_mpi_regs(qdev, &mpi_coredump->mpi_core_regs[0],
 904                                    MPI_CORE_REGS_ADDR, MPI_CORE_REGS_CNT);
 905         if (status)
 906                 goto err;
 907         /* Get the 16 MPI shadow registers */
 908         status = qlge_get_mpi_shadow_regs(qdev,
 909                                           &mpi_coredump->mpi_core_sh_regs[0]);
 910         if (status)
 911                 goto err;
 912
 913         /* Get the Test Logic Registers */
 914         qlge_build_coredump_seg_header(&mpi_coredump->test_logic_regs_seg_hdr,
 915                                        TEST_LOGIC_SEG_NUM,
 916                                        sizeof(struct mpi_coredump_segment_header)
 917                                        + sizeof(mpi_coredump->test_logic_regs),
 918                                        "Test Logic Regs");
 919         status = qlge_get_mpi_regs(qdev, &mpi_coredump->test_logic_regs[0],
 920                                    TEST_REGS_ADDR, TEST_REGS_CNT);
 921         if (status)
 922                 goto err;
 923
 924         /* Get the RMII Registers */
 925         qlge_build_coredump_seg_header(&mpi_coredump->rmii_regs_seg_hdr,
 926                                        RMII_SEG_NUM,
 927                                        sizeof(struct mpi_coredump_segment_header)
 928                                        + sizeof(mpi_coredump->rmii_regs),
 929                                        "RMII Registers");
 930         status = qlge_get_mpi_regs(qdev, &mpi_coredump->rmii_regs[0],
 931                                    RMII_REGS_ADDR, RMII_REGS_CNT);
 932         if (status)
 933                 goto err;
 934
 935         /* Get the FCMAC1 Registers */
 936         qlge_build_coredump_seg_header(&mpi_coredump->fcmac1_regs_seg_hdr,
 937                                        FCMAC1_SEG_NUM,
 938                                        sizeof(struct mpi_coredump_segment_header)
 939                                        + sizeof(mpi_coredump->fcmac1_regs),
 940                                        "FCMAC1 Registers");
 941         status = qlge_get_mpi_regs(qdev, &mpi_coredump->fcmac1_regs[0],
 942                                    FCMAC1_REGS_ADDR, FCMAC_REGS_CNT);
 943         if (status)
 944                 goto err;
 945
 946         /* Get the FCMAC2 Registers */
 947
 948         qlge_build_coredump_seg_header(&mpi_coredump->fcmac2_regs_seg_hdr,
 949                                        FCMAC2_SEG_NUM,
 950                                        sizeof(struct mpi_coredump_segment_header)
 951                                        + sizeof(mpi_coredump->fcmac2_regs),
 952                                        "FCMAC2 Registers");
 953
 954         status = qlge_get_mpi_regs(qdev, &mpi_coredump->fcmac2_regs[0],
 955                                    FCMAC2_REGS_ADDR, FCMAC_REGS_CNT);
 956         if (status)
 957                 goto err;
 958
 959         /* Get the FC1 MBX Registers */
 960         qlge_build_coredump_seg_header(&mpi_coredump->fc1_mbx_regs_seg_hdr,
 961                                        FC1_MBOX_SEG_NUM,
 962                                        sizeof(struct mpi_coredump_segment_header)
 963                                        + sizeof(mpi_coredump->fc1_mbx_regs),
 964                                        "FC1 MBox Regs");
 965         status = qlge_get_mpi_regs(qdev, &mpi_coredump->fc1_mbx_regs[0],
 966                                    FC1_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
 967         if (status)
 968                 goto err;
 969
 970         /* Get the IDE Registers */
 971         qlge_build_coredump_seg_header(&mpi_coredump->ide_regs_seg_hdr,
 972                                        IDE_SEG_NUM,
 973                                        sizeof(struct mpi_coredump_segment_header)
 974                                        + sizeof(mpi_coredump->ide_regs),
 975                                        "IDE Registers");
 976         status = qlge_get_mpi_regs(qdev, &mpi_coredump->ide_regs[0],
 977                                    IDE_REGS_ADDR, IDE_REGS_CNT);
 978         if (status)
 979                 goto err;
 980
 981         /* Get the NIC1 MBX Registers */
 982         qlge_build_coredump_seg_header(&mpi_coredump->nic1_mbx_regs_seg_hdr,
 983                                        NIC1_MBOX_SEG_NUM,
 984                                        sizeof(struct mpi_coredump_segment_header)
 985                                        + sizeof(mpi_coredump->nic1_mbx_regs),
 986                                        "NIC1 MBox Regs");
 987         status = qlge_get_mpi_regs(qdev, &mpi_coredump->nic1_mbx_regs[0],
 988                                    NIC1_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
 989         if (status)
 990                 goto err;
 991
 992         /* Get the SMBus Registers */
 993         qlge_build_coredump_seg_header(&mpi_coredump->smbus_regs_seg_hdr,
 994                                        SMBUS_SEG_NUM,
 995                                        sizeof(struct mpi_coredump_segment_header)
 996                                        + sizeof(mpi_coredump->smbus_regs),
 997                                        "SMBus Registers");
 998         status = qlge_get_mpi_regs(qdev, &mpi_coredump->smbus_regs[0],
 999                                    SMBUS_REGS_ADDR, SMBUS_REGS_CNT);
1000         if (status)
1001                 goto err;
1002
1003         /* Get the FC2 MBX Registers */
1004         qlge_build_coredump_seg_header(&mpi_coredump->fc2_mbx_regs_seg_hdr,
1005                                        FC2_MBOX_SEG_NUM,
1006                                        sizeof(struct mpi_coredump_segment_header)
1007                                        + sizeof(mpi_coredump->fc2_mbx_regs),
1008                                        "FC2 MBox Regs");
1009         status = qlge_get_mpi_regs(qdev, &mpi_coredump->fc2_mbx_regs[0],
1010                                    FC2_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
1011         if (status)
1012                 goto err;
1013
1014         /* Get the NIC2 MBX Registers */
1015         qlge_build_coredump_seg_header(&mpi_coredump->nic2_mbx_regs_seg_hdr,
1016                                        NIC2_MBOX_SEG_NUM,
1017                                        sizeof(struct mpi_coredump_segment_header)
1018                                        + sizeof(mpi_coredump->nic2_mbx_regs),
1019                                        "NIC2 MBox Regs");
1020         status = qlge_get_mpi_regs(qdev, &mpi_coredump->nic2_mbx_regs[0],
1021                                    NIC2_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
1022         if (status)
1023                 goto err;
1024
1025         /* Get the I2C Registers */
1026         qlge_build_coredump_seg_header(&mpi_coredump->i2c_regs_seg_hdr,
1027                                        I2C_SEG_NUM,
1028                                        sizeof(struct mpi_coredump_segment_header)
1029                                        + sizeof(mpi_coredump->i2c_regs),
1030                                        "I2C Registers");
1031         status = qlge_get_mpi_regs(qdev, &mpi_coredump->i2c_regs[0],
1032                                    I2C_REGS_ADDR, I2C_REGS_CNT);
1033         if (status)
1034                 goto err;
1035
1036         /* Get the MEMC Registers */
1037         qlge_build_coredump_seg_header(&mpi_coredump->memc_regs_seg_hdr,
1038                                        MEMC_SEG_NUM,
1039                                        sizeof(struct mpi_coredump_segment_header)
1040                                        + sizeof(mpi_coredump->memc_regs),
1041                                        "MEMC Registers");
1042         status = qlge_get_mpi_regs(qdev, &mpi_coredump->memc_regs[0],
1043                                    MEMC_REGS_ADDR, MEMC_REGS_CNT);
1044         if (status)
1045                 goto err;
1046
1047         /* Get the PBus Registers */
1048         qlge_build_coredump_seg_header(&mpi_coredump->pbus_regs_seg_hdr,
1049                                        PBUS_SEG_NUM,
1050                                        sizeof(struct mpi_coredump_segment_header)
1051                                        + sizeof(mpi_coredump->pbus_regs),
1052                                        "PBUS Registers");
1053         status = qlge_get_mpi_regs(qdev, &mpi_coredump->pbus_regs[0],
1054                                    PBUS_REGS_ADDR, PBUS_REGS_CNT);
1055         if (status)
1056                 goto err;
1057
1058         /* Get the MDE Registers */
1059         qlge_build_coredump_seg_header(&mpi_coredump->mde_regs_seg_hdr,
1060                                        MDE_SEG_NUM,
1061                                        sizeof(struct mpi_coredump_segment_header)
1062                                        + sizeof(mpi_coredump->mde_regs),
1063                                        "MDE Registers");
1064         status = qlge_get_mpi_regs(qdev, &mpi_coredump->mde_regs[0],
1065                                    MDE_REGS_ADDR, MDE_REGS_CNT);
1066         if (status)
1067                 goto err;
1068
1069         qlge_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
1070                                        MISC_NIC_INFO_SEG_NUM,
1071                                        sizeof(struct mpi_coredump_segment_header)
1072                                        + sizeof(mpi_coredump->misc_nic_info),
1073                                        "MISC NIC INFO");
1074         mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
1075         mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
1076         mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
1077         mpi_coredump->misc_nic_info.function = qdev->func;
1078
1079         /* Segment 31 */
1080         /* Get indexed register values. */
1081         qlge_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
1082                                        INTR_STATES_SEG_NUM,
1083                                        sizeof(struct mpi_coredump_segment_header)
1084                                        + sizeof(mpi_coredump->intr_states),
1085                                        "INTR States");
1086         qlge_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
1087
1088         qlge_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
1089                                        CAM_ENTRIES_SEG_NUM,
1090                                        sizeof(struct mpi_coredump_segment_header)
1091                                        + sizeof(mpi_coredump->cam_entries),
1092                                        "CAM Entries");
1093         status = qlge_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
1094         if (status)
1095                 goto err;
1096
1097         qlge_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
1098                                        ROUTING_WORDS_SEG_NUM,
1099                                        sizeof(struct mpi_coredump_segment_header)
1100                                        + sizeof(mpi_coredump->nic_routing_words),
1101                                        "Routing Words");
1102         status = qlge_get_routing_entries(qdev,
1103                                           &mpi_coredump->nic_routing_words[0]);
1104         if (status)
1105                 goto err;
1106
1107         /* Segment 34 (Rev C. step 23) */
1108         qlge_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
1109                                        ETS_SEG_NUM,
1110                                        sizeof(struct mpi_coredump_segment_header)
1111                                        + sizeof(mpi_coredump->ets),
1112                                        "ETS Registers");
1113         status = qlge_get_ets_regs(qdev, &mpi_coredump->ets[0]);
1114         if (status)
1115                 goto err;
1116
1117         qlge_build_coredump_seg_header(&mpi_coredump->probe_dump_seg_hdr,
1118                                        PROBE_DUMP_SEG_NUM,
1119                                        sizeof(struct mpi_coredump_segment_header)
1120                                        + sizeof(mpi_coredump->probe_dump),
1121                                        "Probe Dump");
1122         qlge_get_probe_dump(qdev, &mpi_coredump->probe_dump[0]);
1123
1124         qlge_build_coredump_seg_header(&mpi_coredump->routing_reg_seg_hdr,
1125                                        ROUTING_INDEX_SEG_NUM,
1126                                        sizeof(struct mpi_coredump_segment_header)
1127                                        + sizeof(mpi_coredump->routing_regs),
1128                                        "Routing Regs");
1129         status = qlge_get_routing_index_registers(qdev,
1130                                                   &mpi_coredump->routing_regs[0]);
1131         if (status)
1132                 goto err;
1133
1134         qlge_build_coredump_seg_header(&mpi_coredump->mac_prot_reg_seg_hdr,
1135                                        MAC_PROTOCOL_SEG_NUM,
1136                                        sizeof(struct mpi_coredump_segment_header)
1137                                        + sizeof(mpi_coredump->mac_prot_regs),
1138                                        "MAC Prot Regs");
1139         qlge_get_mac_protocol_registers(qdev, &mpi_coredump->mac_prot_regs[0]);
1140
1141         /* Get the semaphore registers for all 5 functions */
1142         qlge_build_coredump_seg_header(&mpi_coredump->sem_regs_seg_hdr,
1143                                        SEM_REGS_SEG_NUM,
1144                                        sizeof(struct mpi_coredump_segment_header) +
1145                                        sizeof(mpi_coredump->sem_regs),  "Sem Registers");
1146
1147         qlge_get_sem_registers(qdev, &mpi_coredump->sem_regs[0]);
1148
1149         /* Prevent the mpi restarting while we dump the memory.*/
1150         qlge_write_mpi_reg(qdev, MPI_TEST_FUNC_RST_STS, MPI_TEST_FUNC_RST_FRC);
1151
1152         /* clear the pause */
1153         status = qlge_unpause_mpi_risc(qdev);
1154         if (status) {
1155                 netif_err(qdev, drv, qdev->ndev,
1156                           "Failed RISC unpause. Status = 0x%.08x\n", status);
1157                 goto err;
1158         }
1159
1160         /* Reset the RISC so we can dump RAM */
1161         status = qlge_hard_reset_mpi_risc(qdev);
1162         if (status) {
1163                 netif_err(qdev, drv, qdev->ndev,
1164                           "Failed RISC reset. Status = 0x%.08x\n", status);
1165                 goto err;
1166         }
1167
1168         qlge_build_coredump_seg_header(&mpi_coredump->code_ram_seg_hdr,
1169                                        WCS_RAM_SEG_NUM,
1170                                        sizeof(struct mpi_coredump_segment_header)
1171                                        + sizeof(mpi_coredump->code_ram),
1172                                        "WCS RAM");
1173         status = qlge_dump_risc_ram_area(qdev, &mpi_coredump->code_ram[0],
1174                                          CODE_RAM_ADDR, CODE_RAM_CNT);
1175         if (status) {
1176                 netif_err(qdev, drv, qdev->ndev,
1177                           "Failed Dump of CODE RAM. Status = 0x%.08x\n",
1178                           status);
1179                 goto err;
1180         }
1181
1182         /* Insert the segment header */
1183         qlge_build_coredump_seg_header(&mpi_coredump->memc_ram_seg_hdr,
1184                                        MEMC_RAM_SEG_NUM,
1185                                        sizeof(struct mpi_coredump_segment_header)
1186                                        + sizeof(mpi_coredump->memc_ram),
1187                                        "MEMC RAM");
1188         status = qlge_dump_risc_ram_area(qdev, &mpi_coredump->memc_ram[0],
1189                                          MEMC_RAM_ADDR, MEMC_RAM_CNT);
1190         if (status) {
1191                 netif_err(qdev, drv, qdev->ndev,
1192                           "Failed Dump of MEMC RAM. Status = 0x%.08x\n",
1193                           status);
1194                 goto err;
1195         }
1196 err:
1197         qlge_sem_unlock(qdev, SEM_PROC_REG_MASK); /* does flush too */
1198         return status;
1199 }
1200
1201 static void qlge_get_core_dump(struct qlge_adapter *qdev)
1202 {
1203         if (!qlge_own_firmware(qdev)) {
1204                 netif_err(qdev, drv, qdev->ndev, "Don't own firmware!\n");
1205                 return;
1206         }
1207
1208         if (!netif_running(qdev->ndev)) {
1209                 netif_err(qdev, ifup, qdev->ndev,
1210                           "Force Coredump can only be done from interface that is up\n");
1211                 return;
1212         }
1213         qlge_queue_fw_error(qdev);
1214 }
1215
1216 static void qlge_gen_reg_dump(struct qlge_adapter *qdev,
1217                               struct qlge_reg_dump *mpi_coredump)
1218 {
1219         int i, status;
1220
1221         memset(&mpi_coredump->mpi_global_header, 0,
1222                sizeof(struct mpi_coredump_global_header));
1223         mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
1224         mpi_coredump->mpi_global_header.header_size =
1225                 sizeof(struct mpi_coredump_global_header);
1226         mpi_coredump->mpi_global_header.image_size =
1227                 sizeof(struct qlge_reg_dump);
1228         strncpy(mpi_coredump->mpi_global_header.id_string, "MPI Coredump",
1229                 sizeof(mpi_coredump->mpi_global_header.id_string));
1230
1231         /* segment 16 */
1232         qlge_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
1233                                        MISC_NIC_INFO_SEG_NUM,
1234                                        sizeof(struct mpi_coredump_segment_header)
1235                                        + sizeof(mpi_coredump->misc_nic_info),
1236                                        "MISC NIC INFO");
1237         mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
1238         mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
1239         mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
1240         mpi_coredump->misc_nic_info.function = qdev->func;
1241
1242         /* Segment 16, Rev C. Step 18 */
1243         qlge_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
1244                                        NIC1_CONTROL_SEG_NUM,
1245                                        sizeof(struct mpi_coredump_segment_header)
1246                                        + sizeof(mpi_coredump->nic_regs),
1247                                        "NIC Registers");
1248         /* Get generic reg dump */
1249         for (i = 0; i < 64; i++)
1250                 mpi_coredump->nic_regs[i] = qlge_read32(qdev, i * sizeof(u32));
1251
1252         /* Segment 31 */
1253         /* Get indexed register values. */
1254         qlge_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
1255                                        INTR_STATES_SEG_NUM,
1256                                        sizeof(struct mpi_coredump_segment_header)
1257                                        + sizeof(mpi_coredump->intr_states),
1258                                        "INTR States");
1259         qlge_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
1260
1261         qlge_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
1262                                        CAM_ENTRIES_SEG_NUM,
1263                                        sizeof(struct mpi_coredump_segment_header)
1264                                        + sizeof(mpi_coredump->cam_entries),
1265                                        "CAM Entries");
1266         status = qlge_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
1267         if (status)
1268                 return;
1269
1270         qlge_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
1271                                        ROUTING_WORDS_SEG_NUM,
1272                                        sizeof(struct mpi_coredump_segment_header)
1273                                        + sizeof(mpi_coredump->nic_routing_words),
1274                                        "Routing Words");
1275         status = qlge_get_routing_entries(qdev,
1276                                           &mpi_coredump->nic_routing_words[0]);
1277         if (status)
1278                 return;
1279
1280         /* Segment 34 (Rev C. step 23) */
1281         qlge_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
1282                                        ETS_SEG_NUM,
1283                                        sizeof(struct mpi_coredump_segment_header)
1284                                        + sizeof(mpi_coredump->ets),
1285                                        "ETS Registers");
1286         status = qlge_get_ets_regs(qdev, &mpi_coredump->ets[0]);
1287         if (status)
1288                 return;
1289 }
1290
1291 void qlge_get_dump(struct qlge_adapter *qdev, void *buff)
1292 {
1293         /*
1294          * If the dump has already been taken and is stored
1295          * in our internal buffer and if force dump is set then
1296          * just start the spool to dump it to the log file
1297          * and also, take a snapshot of the general regs
1298          * to the user's buffer or else take complete dump
1299          * to the user's buffer if force is not set.
1300          */
1301
1302         if (!test_bit(QL_FRC_COREDUMP, &qdev->flags)) {
1303                 if (!qlge_core_dump(qdev, buff))
1304                         qlge_soft_reset_mpi_risc(qdev);
1305                 else
1306                         netif_err(qdev, drv, qdev->ndev, "coredump failed!\n");
1307         } else {
1308                 qlge_gen_reg_dump(qdev, buff);
1309                 qlge_get_core_dump(qdev);
1310         }
1311 }