drivers/scsi/mvsas/mv_init.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Marvell 88SE64xx/88SE94xx pci init
   4  *
   5  * Copyright 2007 Red Hat, Inc.
   6  * Copyright 2008 Marvell. <[email protected]>
   7  * Copyright 2009-2011 Marvell. <[email protected]>
   8 */
   9
  10
  11 #include "mv_sas.h"
  12
  13 int interrupt_coalescing = 0x80;
  14
  15 static struct scsi_transport_template *mvs_stt;
  16 static const struct mvs_chip_info mvs_chips[] = {
  17         [chip_6320] =   { 1, 2, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  18         [chip_6440] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  19         [chip_6485] =   { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
  20         [chip_9180] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  21         [chip_9480] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  22         [chip_9445] =   { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
  23         [chip_9485] =   { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
  24         [chip_1300] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  25         [chip_1320] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  26 };
  27
  28 static const struct attribute_group *mvst_host_groups[];
  29
  30 #define SOC_SAS_NUM 2
  31
  32 static const struct scsi_host_template mvs_sht = {
  33         .module                 = THIS_MODULE,
  34         .name                   = DRV_NAME,
  35         .queuecommand           = sas_queuecommand,
  36         .dma_need_drain         = ata_scsi_dma_need_drain,
  37         .target_alloc           = sas_target_alloc,
  38         .slave_configure        = sas_slave_configure,
  39         .scan_finished          = mvs_scan_finished,
  40         .scan_start             = mvs_scan_start,
  41         .change_queue_depth     = sas_change_queue_depth,
  42         .bios_param             = sas_bios_param,
  43         .can_queue              = 1,
  44         .this_id                = -1,
  45         .sg_tablesize           = SG_ALL,
  46         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  47         .eh_device_reset_handler = sas_eh_device_reset_handler,
  48         .eh_target_reset_handler = sas_eh_target_reset_handler,
  49         .slave_alloc            = sas_slave_alloc,
  50         .target_destroy         = sas_target_destroy,
  51         .ioctl                  = sas_ioctl,
  52 #ifdef CONFIG_COMPAT
  53         .compat_ioctl           = sas_ioctl,
  54 #endif
  55         .shost_groups           = mvst_host_groups,
  56         .track_queue_depth      = 1,
  57 };
  58
  59 static struct sas_domain_function_template mvs_transport_ops = {
  60         .lldd_dev_found         = mvs_dev_found,
  61         .lldd_dev_gone          = mvs_dev_gone,
  62         .lldd_execute_task      = mvs_queue_command,
  63         .lldd_control_phy       = mvs_phy_control,
  64
  65         .lldd_abort_task        = mvs_abort_task,
  66         .lldd_abort_task_set    = sas_abort_task_set,
  67         .lldd_clear_task_set    = sas_clear_task_set,
  68         .lldd_I_T_nexus_reset   = mvs_I_T_nexus_reset,
  69         .lldd_lu_reset          = mvs_lu_reset,
  70         .lldd_query_task        = mvs_query_task,
  71         .lldd_port_formed       = mvs_port_formed,
  72         .lldd_port_deformed     = mvs_port_deformed,
  73
  74         .lldd_write_gpio        = mvs_gpio_write,
  75
  76 };
  77
  78 static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
  79 {
  80         struct mvs_phy *phy = &mvi->phy[phy_id];
  81         struct asd_sas_phy *sas_phy = &phy->sas_phy;
  82
  83         phy->mvi = mvi;
  84         phy->port = NULL;
  85         timer_setup(&phy->timer, NULL, 0);
  86         sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
  87         sas_phy->class = SAS;
  88         sas_phy->iproto = SAS_PROTOCOL_ALL;
  89         sas_phy->tproto = 0;
  90         sas_phy->type = PHY_TYPE_PHYSICAL;
  91         sas_phy->role = PHY_ROLE_INITIATOR;
  92         sas_phy->oob_mode = OOB_NOT_CONNECTED;
  93         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
  94
  95         sas_phy->id = phy_id;
  96         sas_phy->sas_addr = &mvi->sas_addr[0];
  97         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
  98         sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
  99         sas_phy->lldd_phy = phy;
 100 }
 101
 102 static void mvs_free(struct mvs_info *mvi)
 103 {
 104         struct mvs_wq *mwq;
 105         int slot_nr;
 106
 107         if (!mvi)
 108                 return;
 109
 110         if (mvi->flags & MVF_FLAG_SOC)
 111                 slot_nr = MVS_SOC_SLOTS;
 112         else
 113                 slot_nr = MVS_CHIP_SLOT_SZ;
 114
 115         dma_pool_destroy(mvi->dma_pool);
 116
 117         if (mvi->tx)
 118                 dma_free_coherent(mvi->dev,
 119                                   sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 120                                   mvi->tx, mvi->tx_dma);
 121         if (mvi->rx_fis)
 122                 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
 123                                   mvi->rx_fis, mvi->rx_fis_dma);
 124         if (mvi->rx)
 125                 dma_free_coherent(mvi->dev,
 126                                   sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 127                                   mvi->rx, mvi->rx_dma);
 128         if (mvi->slot)
 129                 dma_free_coherent(mvi->dev,
 130                                   sizeof(*mvi->slot) * slot_nr,
 131                                   mvi->slot, mvi->slot_dma);
 132
 133         if (mvi->bulk_buffer)
 134                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 135                                   mvi->bulk_buffer, mvi->bulk_buffer_dma);
 136         if (mvi->bulk_buffer1)
 137                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 138                                   mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
 139
 140         MVS_CHIP_DISP->chip_iounmap(mvi);
 141         if (mvi->shost)
 142                 scsi_host_put(mvi->shost);
 143         list_for_each_entry(mwq, &mvi->wq_list, entry)
 144                 cancel_delayed_work(&mwq->work_q);
 145         kfree(mvi->rsvd_tags);
 146         kfree(mvi);
 147 }
 148
 149 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 150 static void mvs_tasklet(unsigned long opaque)
 151 {
 152         u32 stat;
 153         u16 core_nr, i = 0;
 154
 155         struct mvs_info *mvi;
 156         struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
 157
 158         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 159         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 160
 161         if (unlikely(!mvi))
 162                 BUG_ON(1);
 163
 164         stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
 165         if (!stat)
 166                 goto out;
 167
 168         for (i = 0; i < core_nr; i++) {
 169                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 170                 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
 171         }
 172 out:
 173         MVS_CHIP_DISP->interrupt_enable(mvi);
 174
 175 }
 176 #endif
 177
 178 static irqreturn_t mvs_interrupt(int irq, void *opaque)
 179 {
 180         u32 stat;
 181         struct mvs_info *mvi;
 182         struct sas_ha_struct *sha = opaque;
 183 #ifndef CONFIG_SCSI_MVSAS_TASKLET
 184         u32 i;
 185         u32 core_nr;
 186
 187         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 188 #endif
 189
 190         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 191
 192         if (unlikely(!mvi))
 193                 return IRQ_NONE;
 194 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 195         MVS_CHIP_DISP->interrupt_disable(mvi);
 196 #endif
 197
 198         stat = MVS_CHIP_DISP->isr_status(mvi, irq);
 199         if (!stat) {
 200         #ifdef CONFIG_SCSI_MVSAS_TASKLET
 201                 MVS_CHIP_DISP->interrupt_enable(mvi);
 202         #endif
 203                 return IRQ_NONE;
 204         }
 205
 206 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 207         tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
 208 #else
 209         for (i = 0; i < core_nr; i++) {
 210                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 211                 MVS_CHIP_DISP->isr(mvi, irq, stat);
 212         }
 213 #endif
 214         return IRQ_HANDLED;
 215 }
 216
 217 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
 218 {
 219         int i = 0, slot_nr;
 220         char pool_name[32];
 221
 222         if (mvi->flags & MVF_FLAG_SOC)
 223                 slot_nr = MVS_SOC_SLOTS;
 224         else
 225                 slot_nr = MVS_CHIP_SLOT_SZ;
 226
 227         spin_lock_init(&mvi->lock);
 228         for (i = 0; i < mvi->chip->n_phy; i++) {
 229                 mvs_phy_init(mvi, i);
 230                 mvi->port[i].wide_port_phymap = 0;
 231                 mvi->port[i].port_attached = 0;
 232                 INIT_LIST_HEAD(&mvi->port[i].list);
 233         }
 234         for (i = 0; i < MVS_MAX_DEVICES; i++) {
 235                 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
 236                 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
 237                 mvi->devices[i].device_id = i;
 238                 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
 239         }
 240
 241         /*
 242          * alloc and init our DMA areas
 243          */
 244         mvi->tx = dma_alloc_coherent(mvi->dev,
 245                                      sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 246                                      &mvi->tx_dma, GFP_KERNEL);
 247         if (!mvi->tx)
 248                 goto err_out;
 249         mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
 250                                          &mvi->rx_fis_dma, GFP_KERNEL);
 251         if (!mvi->rx_fis)
 252                 goto err_out;
 253
 254         mvi->rx = dma_alloc_coherent(mvi->dev,
 255                                      sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 256                                      &mvi->rx_dma, GFP_KERNEL);
 257         if (!mvi->rx)
 258                 goto err_out;
 259         mvi->rx[0] = cpu_to_le32(0xfff);
 260         mvi->rx_cons = 0xfff;
 261
 262         mvi->slot = dma_alloc_coherent(mvi->dev,
 263                                        sizeof(*mvi->slot) * slot_nr,
 264                                        &mvi->slot_dma, GFP_KERNEL);
 265         if (!mvi->slot)
 266                 goto err_out;
 267
 268         mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
 269                                        TRASH_BUCKET_SIZE,
 270                                        &mvi->bulk_buffer_dma, GFP_KERNEL);
 271         if (!mvi->bulk_buffer)
 272                 goto err_out;
 273
 274         mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
 275                                        TRASH_BUCKET_SIZE,
 276                                        &mvi->bulk_buffer_dma1, GFP_KERNEL);
 277         if (!mvi->bulk_buffer1)
 278                 goto err_out;
 279
 280         sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
 281         mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev,
 282                                         MVS_SLOT_BUF_SZ, 16, 0);
 283         if (!mvi->dma_pool) {
 284                         printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
 285                         goto err_out;
 286         }
 287
 288         return 0;
 289 err_out:
 290         return 1;
 291 }
 292
 293
 294 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
 295 {
 296         unsigned long res_start, res_len, res_flag_ex = 0;
 297         struct pci_dev *pdev = mvi->pdev;
 298         if (bar_ex != -1) {
 299                 /*
 300                  * ioremap main and peripheral registers
 301                  */
 302                 res_start = pci_resource_start(pdev, bar_ex);
 303                 res_len = pci_resource_len(pdev, bar_ex);
 304                 if (!res_start || !res_len)
 305                         goto err_out;
 306
 307                 res_flag_ex = pci_resource_flags(pdev, bar_ex);
 308                 if (res_flag_ex & IORESOURCE_MEM)
 309                         mvi->regs_ex = ioremap(res_start, res_len);
 310                 else
 311                         mvi->regs_ex = (void *)res_start;
 312                 if (!mvi->regs_ex)
 313                         goto err_out;
 314         }
 315
 316         res_start = pci_resource_start(pdev, bar);
 317         res_len = pci_resource_len(pdev, bar);
 318         if (!res_start || !res_len) {
 319                 iounmap(mvi->regs_ex);
 320                 mvi->regs_ex = NULL;
 321                 goto err_out;
 322         }
 323
 324         mvi->regs = ioremap(res_start, res_len);
 325
 326         if (!mvi->regs) {
 327                 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
 328                         iounmap(mvi->regs_ex);
 329                 mvi->regs_ex = NULL;
 330                 goto err_out;
 331         }
 332
 333         return 0;
 334 err_out:
 335         return -1;
 336 }
 337
 338 void mvs_iounmap(void __iomem *regs)
 339 {
 340         iounmap(regs);
 341 }
 342
 343 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
 344                                 const struct pci_device_id *ent,
 345                                 struct Scsi_Host *shost, unsigned int id)
 346 {
 347         struct mvs_info *mvi = NULL;
 348         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 349
 350         mvi = kzalloc(sizeof(*mvi) +
 351                 (1L << mvs_chips[ent->driver_data].slot_width) *
 352                 sizeof(struct mvs_slot_info), GFP_KERNEL);
 353         if (!mvi)
 354                 return NULL;
 355
 356         mvi->pdev = pdev;
 357         mvi->dev = &pdev->dev;
 358         mvi->chip_id = ent->driver_data;
 359         mvi->chip = &mvs_chips[mvi->chip_id];
 360         INIT_LIST_HEAD(&mvi->wq_list);
 361
 362         ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
 363         ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
 364
 365         mvi->id = id;
 366         mvi->sas = sha;
 367         mvi->shost = shost;
 368
 369         mvi->rsvd_tags = bitmap_zalloc(MVS_RSVD_SLOTS, GFP_KERNEL);
 370         if (!mvi->rsvd_tags)
 371                 goto err_out;
 372
 373         if (MVS_CHIP_DISP->chip_ioremap(mvi))
 374                 goto err_out;
 375         if (!mvs_alloc(mvi, shost))
 376                 return mvi;
 377 err_out:
 378         mvs_free(mvi);
 379         return NULL;
 380 }
 381
 382 static int pci_go_64(struct pci_dev *pdev)
 383 {
 384         int rc;
 385
 386         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 387         if (rc) {
 388                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 389                 if (rc) {
 390                         dev_printk(KERN_ERR, &pdev->dev,
 391                                    "32-bit DMA enable failed\n");
 392                         return rc;
 393                 }
 394         }
 395
 396         return rc;
 397 }
 398
 399 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
 400                                 const struct mvs_chip_info *chip_info)
 401 {
 402         int phy_nr, port_nr; unsigned short core_nr;
 403         struct asd_sas_phy **arr_phy;
 404         struct asd_sas_port **arr_port;
 405         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 406
 407         core_nr = chip_info->n_host;
 408         phy_nr  = core_nr * chip_info->n_phy;
 409         port_nr = phy_nr;
 410
 411         memset(sha, 0x00, sizeof(struct sas_ha_struct));
 412         arr_phy  = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 413         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 414         if (!arr_phy || !arr_port)
 415                 goto exit_free;
 416
 417         sha->sas_phy = arr_phy;
 418         sha->sas_port = arr_port;
 419         sha->core.shost = shost;
 420
 421         sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
 422         if (!sha->lldd_ha)
 423                 goto exit_free;
 424
 425         ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
 426
 427         shost->transportt = mvs_stt;
 428         shost->max_id = MVS_MAX_DEVICES;
 429         shost->max_lun = ~0;
 430         shost->max_channel = 1;
 431         shost->max_cmd_len = 16;
 432
 433         return 0;
 434 exit_free:
 435         kfree(arr_phy);
 436         kfree(arr_port);
 437         return -1;
 438
 439 }
 440
 441 static void  mvs_post_sas_ha_init(struct Scsi_Host *shost,
 442                         const struct mvs_chip_info *chip_info)
 443 {
 444         int can_queue, i = 0, j = 0;
 445         struct mvs_info *mvi = NULL;
 446         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 447         unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 448
 449         for (j = 0; j < nr_core; j++) {
 450                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
 451                 for (i = 0; i < chip_info->n_phy; i++) {
 452                         sha->sas_phy[j * chip_info->n_phy  + i] =
 453                                 &mvi->phy[i].sas_phy;
 454                         sha->sas_port[j * chip_info->n_phy + i] =
 455                                 &mvi->port[i].sas_port;
 456                 }
 457         }
 458
 459         sha->sas_ha_name = DRV_NAME;
 460         sha->dev = mvi->dev;
 461         sha->lldd_module = THIS_MODULE;
 462         sha->sas_addr = &mvi->sas_addr[0];
 463
 464         sha->num_phys = nr_core * chip_info->n_phy;
 465
 466         if (mvi->flags & MVF_FLAG_SOC)
 467                 can_queue = MVS_SOC_CAN_QUEUE;
 468         else
 469                 can_queue = MVS_CHIP_SLOT_SZ;
 470
 471         can_queue -= MVS_RSVD_SLOTS;
 472
 473         shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
 474         shost->can_queue = can_queue;
 475         mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
 476         sha->core.shost = mvi->shost;
 477 }
 478
 479 static void mvs_init_sas_add(struct mvs_info *mvi)
 480 {
 481         u8 i;
 482         for (i = 0; i < mvi->chip->n_phy; i++) {
 483                 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
 484                 mvi->phy[i].dev_sas_addr =
 485                         cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
 486         }
 487
 488         memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
 489 }
 490
 491 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
 492 {
 493         unsigned int rc, nhost = 0;
 494         struct mvs_info *mvi;
 495         irq_handler_t irq_handler = mvs_interrupt;
 496         struct Scsi_Host *shost = NULL;
 497         const struct mvs_chip_info *chip;
 498
 499         dev_printk(KERN_INFO, &pdev->dev,
 500                 "mvsas: driver version %s\n", DRV_VERSION);
 501         rc = pci_enable_device(pdev);
 502         if (rc)
 503                 goto err_out_enable;
 504
 505         pci_set_master(pdev);
 506
 507         rc = pci_request_regions(pdev, DRV_NAME);
 508         if (rc)
 509                 goto err_out_disable;
 510
 511         rc = pci_go_64(pdev);
 512         if (rc)
 513                 goto err_out_regions;
 514
 515         shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
 516         if (!shost) {
 517                 rc = -ENOMEM;
 518                 goto err_out_regions;
 519         }
 520
 521         chip = &mvs_chips[ent->driver_data];
 522         SHOST_TO_SAS_HA(shost) =
 523                 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
 524         if (!SHOST_TO_SAS_HA(shost)) {
 525                 scsi_host_put(shost);
 526                 rc = -ENOMEM;
 527                 goto err_out_regions;
 528         }
 529
 530         rc = mvs_prep_sas_ha_init(shost, chip);
 531         if (rc) {
 532                 scsi_host_put(shost);
 533                 rc = -ENOMEM;
 534                 goto err_out_regions;
 535         }
 536
 537         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
 538
 539         do {
 540                 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
 541                 if (!mvi) {
 542                         rc = -ENOMEM;
 543                         goto err_out_regions;
 544                 }
 545
 546                 memset(&mvi->hba_info_param, 0xFF,
 547                         sizeof(struct hba_info_page));
 548
 549                 mvs_init_sas_add(mvi);
 550
 551                 mvi->instance = nhost;
 552                 rc = MVS_CHIP_DISP->chip_init(mvi);
 553                 if (rc) {
 554                         mvs_free(mvi);
 555                         goto err_out_regions;
 556                 }
 557                 nhost++;
 558         } while (nhost < chip->n_host);
 559 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 560         {
 561         struct mvs_prv_info *mpi = SHOST_TO_SAS_HA(shost)->lldd_ha;
 562
 563         tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
 564                      (unsigned long)SHOST_TO_SAS_HA(shost));
 565         }
 566 #endif
 567
 568         mvs_post_sas_ha_init(shost, chip);
 569
 570         rc = scsi_add_host(shost, &pdev->dev);
 571         if (rc)
 572                 goto err_out_shost;
 573
 574         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
 575         if (rc)
 576                 goto err_out_shost;
 577         rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
 578                 DRV_NAME, SHOST_TO_SAS_HA(shost));
 579         if (rc)
 580                 goto err_not_sas;
 581
 582         MVS_CHIP_DISP->interrupt_enable(mvi);
 583
 584         scsi_scan_host(mvi->shost);
 585
 586         return 0;
 587
 588 err_not_sas:
 589         sas_unregister_ha(SHOST_TO_SAS_HA(shost));
 590 err_out_shost:
 591         scsi_remove_host(mvi->shost);
 592 err_out_regions:
 593         pci_release_regions(pdev);
 594 err_out_disable:
 595         pci_disable_device(pdev);
 596 err_out_enable:
 597         return rc;
 598 }
 599
 600 static void mvs_pci_remove(struct pci_dev *pdev)
 601 {
 602         unsigned short core_nr, i = 0;
 603         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 604         struct mvs_info *mvi = NULL;
 605
 606         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 607         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 608
 609 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 610         tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
 611 #endif
 612
 613         sas_unregister_ha(sha);
 614         sas_remove_host(mvi->shost);
 615
 616         MVS_CHIP_DISP->interrupt_disable(mvi);
 617         free_irq(mvi->pdev->irq, sha);
 618         for (i = 0; i < core_nr; i++) {
 619                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 620                 mvs_free(mvi);
 621         }
 622         kfree(sha->sas_phy);
 623         kfree(sha->sas_port);
 624         kfree(sha);
 625         pci_release_regions(pdev);
 626         pci_disable_device(pdev);
 627         return;
 628 }
 629
 630 static struct pci_device_id mvs_pci_table[] = {
 631         { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
 632         { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
 633         {
 634                 .vendor         = PCI_VENDOR_ID_MARVELL,
 635                 .device         = 0x6440,
 636                 .subvendor      = PCI_ANY_ID,
 637                 .subdevice      = 0x6480,
 638                 .class          = 0,
 639                 .class_mask     = 0,
 640                 .driver_data    = chip_6485,
 641         },
 642         { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
 643         { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
 644         { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
 645         { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
 646         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
 647         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
 648         { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
 649         { PCI_VDEVICE(TTI, 0x2640), chip_6440 },
 650         { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
 651         { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
 652         { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
 653         { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
 654         { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
 655         { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
 656         { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
 657         {
 658                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 659                 .device         = 0x9480,
 660                 .subvendor      = PCI_ANY_ID,
 661                 .subdevice      = 0x9480,
 662                 .class          = 0,
 663                 .class_mask     = 0,
 664                 .driver_data    = chip_9480,
 665         },
 666         {
 667                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 668                 .device         = 0x9445,
 669                 .subvendor      = PCI_ANY_ID,
 670                 .subdevice      = 0x9480,
 671                 .class          = 0,
 672                 .class_mask     = 0,
 673                 .driver_data    = chip_9445,
 674         },
 675         { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */
 676         { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
 677         { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 678         { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 679         { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 680         { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 681         { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 682         { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 683         { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 684         { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 685         { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 686
 687         { }     /* terminate list */
 688 };
 689
 690 static struct pci_driver mvs_pci_driver = {
 691         .name           = DRV_NAME,
 692         .id_table       = mvs_pci_table,
 693         .probe          = mvs_pci_init,
 694         .remove         = mvs_pci_remove,
 695 };
 696
 697 static ssize_t driver_version_show(struct device *cdev,
 698                                    struct device_attribute *attr, char *buffer)
 699 {
 700         return sysfs_emit(buffer, "%s\n", DRV_VERSION);
 701 }
 702
 703 static DEVICE_ATTR_RO(driver_version);
 704
 705 static ssize_t interrupt_coalescing_store(struct device *cdev,
 706                                           struct device_attribute *attr,
 707                                           const char *buffer, size_t size)
 708 {
 709         unsigned int val = 0;
 710         struct mvs_info *mvi = NULL;
 711         struct Scsi_Host *shost = class_to_shost(cdev);
 712         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 713         u8 i, core_nr;
 714         if (buffer == NULL)
 715                 return size;
 716
 717         if (sscanf(buffer, "%u", &val) != 1)
 718                 return -EINVAL;
 719
 720         if (val >= 0x10000) {
 721                 mv_dprintk("interrupt coalescing timer %d us is"
 722                         "too long\n", val);
 723                 return strlen(buffer);
 724         }
 725
 726         interrupt_coalescing = val;
 727
 728         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 729         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 730
 731         if (unlikely(!mvi))
 732                 return -EINVAL;
 733
 734         for (i = 0; i < core_nr; i++) {
 735                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 736                 if (MVS_CHIP_DISP->tune_interrupt)
 737                         MVS_CHIP_DISP->tune_interrupt(mvi,
 738                                 interrupt_coalescing);
 739         }
 740         mv_dprintk("set interrupt coalescing time to %d us\n",
 741                 interrupt_coalescing);
 742         return strlen(buffer);
 743 }
 744
 745 static ssize_t interrupt_coalescing_show(struct device *cdev,
 746                                          struct device_attribute *attr, char *buffer)
 747 {
 748         return sysfs_emit(buffer, "%d\n", interrupt_coalescing);
 749 }
 750
 751 static DEVICE_ATTR_RW(interrupt_coalescing);
 752
 753 static int __init mvs_init(void)
 754 {
 755         int rc;
 756         mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
 757         if (!mvs_stt)
 758                 return -ENOMEM;
 759
 760         rc = pci_register_driver(&mvs_pci_driver);
 761         if (rc)
 762                 goto err_out;
 763
 764         return 0;
 765
 766 err_out:
 767         sas_release_transport(mvs_stt);
 768         return rc;
 769 }
 770
 771 static void __exit mvs_exit(void)
 772 {
 773         pci_unregister_driver(&mvs_pci_driver);
 774         sas_release_transport(mvs_stt);
 775 }
 776
 777 static struct attribute *mvst_host_attrs[] = {
 778         &dev_attr_driver_version.attr,
 779         &dev_attr_interrupt_coalescing.attr,
 780         NULL,
 781 };
 782
 783 ATTRIBUTE_GROUPS(mvst_host);
 784
 785 module_init(mvs_init);
 786 module_exit(mvs_exit);
 787
 788 MODULE_AUTHOR("Jeff Garzik <[email protected]>");
 789 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
 790 MODULE_VERSION(DRV_VERSION);
 791 MODULE_LICENSE("GPL");
 792 #ifdef CONFIG_PCI
 793 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
 794 #endif