drivers/net/wireless/ath/ath12k/qmi.h

   1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2 /*
   3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #ifndef ATH12K_QMI_H
   8 #define ATH12K_QMI_H
   9
  10 #include <linux/mutex.h>
  11 #include <linux/soc/qcom/qmi.h>
  12
  13 #define ATH12K_HOST_VERSION_STRING              "WIN"
  14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS            10000
  15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE       64
  16 #define ATH12K_QMI_CALDB_ADDRESS                0x4BA00000
  17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01  128
  18 #define ATH12K_QMI_WLFW_NODE_ID_BASE            0x07
  19 #define ATH12K_QMI_WLFW_SERVICE_ID_V01          0x45
  20 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01        0x01
  21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01      0x02
  22 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1
  23
  24 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274      0x07
  25 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32
  26 #define ATH12K_QMI_RESP_LEN_MAX                 8192
  27 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01   52
  28 #define ATH12K_QMI_CALDB_SIZE                   0x480000
  29 #define ATH12K_QMI_BDF_EXT_STR_LENGTH           0x20
  30 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT       3
  31 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4
  32 #define ATH12K_QMI_DEVMEM_CMEM_INDEX    0
  33
  34 #define QMI_WLFW_REQUEST_MEM_IND_V01            0x0035
  35 #define QMI_WLFW_FW_MEM_READY_IND_V01           0x0037
  36 #define QMI_WLFW_FW_READY_IND_V01               0x0038
  37
  38 #define QMI_WLANFW_MAX_DATA_SIZE_V01            6144
  39 #define ATH12K_FIRMWARE_MODE_OFF                4
  40 #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT      0
  41
  42 #define ATH12K_BOARD_ID_DEFAULT 0xFF
  43
  44 struct ath12k_base;
  45
  46 enum ath12k_qmi_file_type {
  47         ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0,
  48         ATH12K_QMI_FILE_TYPE_CALDATA    = 2,
  49         ATH12K_QMI_FILE_TYPE_EEPROM     = 3,
  50         ATH12K_QMI_MAX_FILE_TYPE        = 4,
  51 };
  52
  53 enum ath12k_qmi_bdf_type {
  54         ATH12K_QMI_BDF_TYPE_BIN                 = 0,
  55         ATH12K_QMI_BDF_TYPE_ELF                 = 1,
  56         ATH12K_QMI_BDF_TYPE_REGDB               = 4,
  57         ATH12K_QMI_BDF_TYPE_CALIBRATION         = 5,
  58 };
  59
  60 enum ath12k_qmi_event_type {
  61         ATH12K_QMI_EVENT_SERVER_ARRIVE,
  62         ATH12K_QMI_EVENT_SERVER_EXIT,
  63         ATH12K_QMI_EVENT_REQUEST_MEM,
  64         ATH12K_QMI_EVENT_FW_MEM_READY,
  65         ATH12K_QMI_EVENT_FW_READY,
  66         ATH12K_QMI_EVENT_REGISTER_DRIVER,
  67         ATH12K_QMI_EVENT_UNREGISTER_DRIVER,
  68         ATH12K_QMI_EVENT_RECOVERY,
  69         ATH12K_QMI_EVENT_FORCE_FW_ASSERT,
  70         ATH12K_QMI_EVENT_POWER_UP,
  71         ATH12K_QMI_EVENT_POWER_DOWN,
  72         ATH12K_QMI_EVENT_MAX,
  73 };
  74
  75 struct ath12k_qmi_driver_event {
  76         struct list_head list;
  77         enum ath12k_qmi_event_type type;
  78         void *data;
  79 };
  80
  81 struct ath12k_qmi_ce_cfg {
  82         const struct ce_pipe_config *tgt_ce;
  83         int tgt_ce_len;
  84         const struct service_to_pipe *svc_to_ce_map;
  85         int svc_to_ce_map_len;
  86         const u8 *shadow_reg;
  87         int shadow_reg_len;
  88         u32 *shadow_reg_v3;
  89         int shadow_reg_v3_len;
  90 };
  91
  92 struct ath12k_qmi_event_msg {
  93         struct list_head list;
  94         enum ath12k_qmi_event_type type;
  95 };
  96
  97 struct target_mem_chunk {
  98         u32 size;
  99         u32 type;
 100         dma_addr_t paddr;
 101         union {
 102                 void __iomem *ioaddr;
 103                 void *addr;
 104         } v;
 105 };
 106
 107 struct target_info {
 108         u32 chip_id;
 109         u32 chip_family;
 110         u32 board_id;
 111         u32 soc_id;
 112         u32 fw_version;
 113         u32 eeprom_caldata;
 114         char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
 115         char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
 116         char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH];
 117 };
 118
 119 struct m3_mem_region {
 120         u32 size;
 121         dma_addr_t paddr;
 122         void *vaddr;
 123 };
 124
 125 struct dev_mem_info {
 126         u64 start;
 127         u64 size;
 128 };
 129
 130 struct ath12k_qmi {
 131         struct ath12k_base *ab;
 132         struct qmi_handle handle;
 133         struct sockaddr_qrtr sq;
 134         struct work_struct event_work;
 135         struct workqueue_struct *event_wq;
 136         struct list_head event_list;
 137         spinlock_t event_lock; /* spinlock for qmi event list */
 138         struct ath12k_qmi_ce_cfg ce_cfg;
 139         struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 140         u32 mem_seg_count;
 141         u32 target_mem_mode;
 142         bool target_mem_delayed;
 143         u8 cal_done;
 144         struct target_info target;
 145         struct m3_mem_region m3_mem;
 146         unsigned int service_ins_id;
 147         struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
 148 };
 149
 150 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN         261
 151 #define QMI_WLANFW_HOST_CAP_REQ_V01                     0x0034
 152 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN        7
 153 #define QMI_WLFW_HOST_CAP_RESP_V01                      0x0034
 154 #define QMI_WLFW_MAX_NUM_GPIO_V01                       32
 155 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01            64
 156 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01          3
 157
 158 struct qmi_wlanfw_host_ddr_range {
 159         u64 start;
 160         u64 size;
 161 };
 162
 163 enum ath12k_qmi_target_mem {
 164         HOST_DDR_REGION_TYPE = 0x1,
 165         BDF_MEM_REGION_TYPE = 0x2,
 166         M3_DUMP_REGION_TYPE = 0x3,
 167         CALDB_MEM_REGION_TYPE = 0x4,
 168         PAGEABLE_MEM_REGION_TYPE = 0x9,
 169 };
 170
 171 enum qmi_wlanfw_host_build_type {
 172         WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
 173         QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0,
 174         QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1,
 175         QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2,
 176         WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
 177 };
 178
 179 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3
 180 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2
 181
 182 struct wlfw_host_mlo_chip_info_s_v01 {
 183         u8 chip_id;
 184         u8 num_local_links;
 185         u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
 186         u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
 187 };
 188
 189 enum ath12k_qmi_cnss_feature {
 190         CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN,
 191         CNSS_QDSS_CFG_MISS_V01 = 3,
 192         CNSS_MAX_FEATURE_V01 = 64,
 193         CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX,
 194 };
 195
 196 struct qmi_wlanfw_host_cap_req_msg_v01 {
 197         u8 num_clients_valid;
 198         u32 num_clients;
 199         u8 wake_msi_valid;
 200         u32 wake_msi;
 201         u8 gpios_valid;
 202         u32 gpios_len;
 203         u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
 204         u8 nm_modem_valid;
 205         u8 nm_modem;
 206         u8 bdf_support_valid;
 207         u8 bdf_support;
 208         u8 bdf_cache_support_valid;
 209         u8 bdf_cache_support;
 210         u8 m3_support_valid;
 211         u8 m3_support;
 212         u8 m3_cache_support_valid;
 213         u8 m3_cache_support;
 214         u8 cal_filesys_support_valid;
 215         u8 cal_filesys_support;
 216         u8 cal_cache_support_valid;
 217         u8 cal_cache_support;
 218         u8 cal_done_valid;
 219         u8 cal_done;
 220         u8 mem_bucket_valid;
 221         u32 mem_bucket;
 222         u8 mem_cfg_mode_valid;
 223         u8 mem_cfg_mode;
 224         u8 cal_duration_valid;
 225         u16 cal_duraiton;
 226         u8 platform_name_valid;
 227         char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1];
 228         u8 ddr_range_valid;
 229         struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01];
 230         u8 host_build_type_valid;
 231         enum qmi_wlanfw_host_build_type host_build_type;
 232         u8 mlo_capable_valid;
 233         u8 mlo_capable;
 234         u8 mlo_chip_id_valid;
 235         u16 mlo_chip_id;
 236         u8 mlo_group_id_valid;
 237         u8 mlo_group_id;
 238         u8 max_mlo_peer_valid;
 239         u16 max_mlo_peer;
 240         u8 mlo_num_chips_valid;
 241         u8 mlo_num_chips;
 242         u8 mlo_chip_info_valid;
 243         struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01];
 244         u8 feature_list_valid;
 245         u64 feature_list;
 246
 247 };
 248
 249 struct qmi_wlanfw_host_cap_resp_msg_v01 {
 250         struct qmi_response_type_v01 resp;
 251 };
 252
 253 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN             54
 254 #define QMI_WLANFW_IND_REGISTER_REQ_V01                         0x0020
 255 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN            18
 256 #define QMI_WLANFW_IND_REGISTER_RESP_V01                        0x0020
 257 #define QMI_WLANFW_CLIENT_ID                                    0x4b4e454c
 258
 259 struct qmi_wlanfw_ind_register_req_msg_v01 {
 260         u8 fw_ready_enable_valid;
 261         u8 fw_ready_enable;
 262         u8 initiate_cal_download_enable_valid;
 263         u8 initiate_cal_download_enable;
 264         u8 initiate_cal_update_enable_valid;
 265         u8 initiate_cal_update_enable;
 266         u8 msa_ready_enable_valid;
 267         u8 msa_ready_enable;
 268         u8 pin_connect_result_enable_valid;
 269         u8 pin_connect_result_enable;
 270         u8 client_id_valid;
 271         u32 client_id;
 272         u8 request_mem_enable_valid;
 273         u8 request_mem_enable;
 274         u8 fw_mem_ready_enable_valid;
 275         u8 fw_mem_ready_enable;
 276         u8 fw_init_done_enable_valid;
 277         u8 fw_init_done_enable;
 278         u8 rejuvenate_enable_valid;
 279         u32 rejuvenate_enable;
 280         u8 xo_cal_enable_valid;
 281         u8 xo_cal_enable;
 282         u8 cal_done_enable_valid;
 283         u8 cal_done_enable;
 284 };
 285
 286 struct qmi_wlanfw_ind_register_resp_msg_v01 {
 287         struct qmi_response_type_v01 resp;
 288         u8 fw_status_valid;
 289         u64 fw_status;
 290 };
 291
 292 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN      1824
 293 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN      888
 294 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN     7
 295 #define QMI_WLANFW_REQUEST_MEM_IND_V01                  0x0035
 296 #define QMI_WLANFW_RESPOND_MEM_REQ_V01                  0x0036
 297 #define QMI_WLANFW_RESPOND_MEM_RESP_V01                 0x0036
 298 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01                  2
 299 #define QMI_WLANFW_MAX_STR_LEN_V01                      16
 300
 301 struct qmi_wlanfw_mem_cfg_s_v01 {
 302         u64 offset;
 303         u32 size;
 304         u8 secure_flag;
 305 };
 306
 307 enum qmi_wlanfw_mem_type_enum_v01 {
 308         WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
 309         QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
 310         QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
 311         QMI_WLANFW_MEM_BDF_V01 = 2,
 312         QMI_WLANFW_MEM_M3_V01 = 3,
 313         QMI_WLANFW_MEM_CAL_V01 = 4,
 314         QMI_WLANFW_MEM_DPD_V01 = 5,
 315         WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
 316 };
 317
 318 struct qmi_wlanfw_mem_seg_s_v01 {
 319         u32 size;
 320         enum qmi_wlanfw_mem_type_enum_v01 type;
 321         u32 mem_cfg_len;
 322         struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
 323 };
 324
 325 struct qmi_wlanfw_request_mem_ind_msg_v01 {
 326         u32 mem_seg_len;
 327         struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 328 };
 329
 330 struct qmi_wlanfw_mem_seg_resp_s_v01 {
 331         u64 addr;
 332         u32 size;
 333         enum qmi_wlanfw_mem_type_enum_v01 type;
 334         u8 restore;
 335 };
 336
 337 struct qmi_wlanfw_respond_mem_req_msg_v01 {
 338         u32 mem_seg_len;
 339         struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 340 };
 341
 342 struct qmi_wlanfw_respond_mem_resp_msg_v01 {
 343         struct qmi_response_type_v01 resp;
 344 };
 345
 346 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
 347         char placeholder;
 348 };
 349
 350 struct qmi_wlanfw_fw_ready_ind_msg_v01 {
 351         char placeholder;
 352 };
 353
 354 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN      0
 355 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN     207
 356 #define QMI_WLANFW_CAP_REQ_V01                  0x0024
 357 #define QMI_WLANFW_CAP_RESP_V01                 0x0024
 358
 359 enum qmi_wlanfw_pipedir_enum_v01 {
 360         QMI_WLFW_PIPEDIR_NONE_V01 = 0,
 361         QMI_WLFW_PIPEDIR_IN_V01 = 1,
 362         QMI_WLFW_PIPEDIR_OUT_V01 = 2,
 363         QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
 364 };
 365
 366 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
 367         __le32 pipe_num;
 368         __le32 pipe_dir;
 369         __le32 nentries;
 370         __le32 nbytes_max;
 371         __le32 flags;
 372 };
 373
 374 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
 375         __le32 service_id;
 376         __le32 pipe_dir;
 377         __le32 pipe_num;
 378 };
 379
 380 struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
 381         u16 id;
 382         u16 offset;
 383 };
 384
 385 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 {
 386         u32 addr;
 387 };
 388
 389 struct qmi_wlanfw_memory_region_info_s_v01 {
 390         u64 region_addr;
 391         u32 size;
 392         u8 secure_flag;
 393 };
 394
 395 struct qmi_wlanfw_rf_chip_info_s_v01 {
 396         u32 chip_id;
 397         u32 chip_family;
 398 };
 399
 400 struct qmi_wlanfw_rf_board_info_s_v01 {
 401         u32 board_id;
 402 };
 403
 404 struct qmi_wlanfw_soc_info_s_v01 {
 405         u32 soc_id;
 406 };
 407
 408 struct qmi_wlanfw_fw_version_info_s_v01 {
 409         u32 fw_version;
 410         char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
 411 };
 412
 413 struct qmi_wlanfw_dev_mem_info_s_v01 {
 414         u64 start;
 415         u64 size;
 416 };
 417
 418 enum qmi_wlanfw_cal_temp_id_enum_v01 {
 419         QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
 420         QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
 421         QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
 422         QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
 423         QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
 424         QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
 425 };
 426
 427 enum qmi_wlanfw_rd_card_chain_cap_v01 {
 428         WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN,
 429         WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0,
 430         WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1,
 431         WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2,
 432         WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX,
 433 };
 434
 435 struct qmi_wlanfw_cap_resp_msg_v01 {
 436         struct qmi_response_type_v01 resp;
 437         u8 chip_info_valid;
 438         struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
 439         u8 board_info_valid;
 440         struct qmi_wlanfw_rf_board_info_s_v01 board_info;
 441         u8 soc_info_valid;
 442         struct qmi_wlanfw_soc_info_s_v01 soc_info;
 443         u8 fw_version_info_valid;
 444         struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
 445         u8 fw_build_id_valid;
 446         char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
 447         u8 num_macs_valid;
 448         u8 num_macs;
 449         u8 voltage_mv_valid;
 450         u32 voltage_mv;
 451         u8 time_freq_hz_valid;
 452         u32 time_freq_hz;
 453         u8 otp_version_valid;
 454         u32 otp_version;
 455         u8 eeprom_caldata_read_timeout_valid;
 456         u32 eeprom_caldata_read_timeout;
 457         u8 fw_caps_valid;
 458         u64 fw_caps;
 459         u8 rd_card_chain_cap_valid;
 460         enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap;
 461         u8 dev_mem_info_valid;
 462         struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
 463 };
 464
 465 struct qmi_wlanfw_cap_req_msg_v01 {
 466         char placeholder;
 467 };
 468
 469 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN     6182
 470 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN    7
 471 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01                0x0025
 472 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01                 0x0025
 473 /* TODO: Need to check with MCL and FW team that data can be pointer and
 474  * can be last element in structure
 475  */
 476 struct qmi_wlanfw_bdf_download_req_msg_v01 {
 477         u8 valid;
 478         u8 file_id_valid;
 479         enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
 480         u8 total_size_valid;
 481         u32 total_size;
 482         u8 seg_id_valid;
 483         u32 seg_id;
 484         u8 data_valid;
 485         u32 data_len;
 486         u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
 487         u8 end_valid;
 488         u8 end;
 489         u8 bdf_type_valid;
 490         u8 bdf_type;
 491
 492 };
 493
 494 struct qmi_wlanfw_bdf_download_resp_msg_v01 {
 495         struct qmi_response_type_v01 resp;
 496 };
 497
 498 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN      18
 499 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN     7
 500 #define QMI_WLANFW_M3_INFO_RESP_V01             0x003C
 501 #define QMI_WLANFW_M3_INFO_REQ_V01              0x003C
 502
 503 struct qmi_wlanfw_m3_info_req_msg_v01 {
 504         u64 addr;
 505         u32 size;
 506 };
 507
 508 struct qmi_wlanfw_m3_info_resp_msg_v01 {
 509         struct qmi_response_type_v01 resp;
 510 };
 511
 512 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN        11
 513 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN       7
 514 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN         803
 515 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN        7
 516 #define QMI_WLANFW_WLAN_MODE_REQ_V01                    0x0022
 517 #define QMI_WLANFW_WLAN_MODE_RESP_V01                   0x0022
 518 #define QMI_WLANFW_WLAN_CFG_REQ_V01                     0x0023
 519 #define QMI_WLANFW_WLAN_CFG_RESP_V01                    0x0023
 520 #define QMI_WLANFW_MAX_STR_LEN_V01                      16
 521 #define QMI_WLANFW_MAX_NUM_CE_V01                       12
 522 #define QMI_WLANFW_MAX_NUM_SVC_V01                      24
 523 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01               24
 524 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01            60
 525
 526 struct qmi_wlanfw_wlan_mode_req_msg_v01 {
 527         u32 mode;
 528         u8 hw_debug_valid;
 529         u8 hw_debug;
 530 };
 531
 532 struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
 533         struct qmi_response_type_v01 resp;
 534 };
 535
 536 struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
 537         u8 host_version_valid;
 538         char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
 539         u8  tgt_cfg_valid;
 540         u32  tgt_cfg_len;
 541         struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
 542                         tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
 543         u8  svc_cfg_valid;
 544         u32 svc_cfg_len;
 545         struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
 546                         svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
 547         u8 shadow_reg_valid;
 548         u32 shadow_reg_len;
 549         struct qmi_wlanfw_shadow_reg_cfg_s_v01
 550                 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
 551         u8 shadow_reg_v3_valid;
 552         u32 shadow_reg_v3_len;
 553         struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01
 554                 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01];
 555 };
 556
 557 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
 558         struct qmi_response_type_v01 resp;
 559 };
 560
 561 int ath12k_qmi_firmware_start(struct ath12k_base *ab,
 562                               u32 mode);
 563 void ath12k_qmi_firmware_stop(struct ath12k_base *ab);
 564 void ath12k_qmi_event_work(struct work_struct *work);
 565 void ath12k_qmi_msg_recv_work(struct work_struct *work);
 566 void ath12k_qmi_deinit_service(struct ath12k_base *ab);
 567 int ath12k_qmi_init_service(struct ath12k_base *ab);
 568
 569 #endif