drivers/net/can/rcar/rcar_canfd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Renesas R-Car CAN FD device driver
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corp.
   5  */
   6
   7 /* The R-Car CAN FD controller can operate in either one of the below two modes
   8  *  - CAN FD only mode
   9  *  - Classical CAN (CAN 2.0) only mode
  10  *
  11  * This driver puts the controller in CAN FD only mode by default. In this
  12  * mode, the controller acts as a CAN FD node that can also interoperate with
  13  * CAN 2.0 nodes.
  14  *
  15  * To switch the controller to Classical CAN (CAN 2.0) only mode, add
  16  * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
  17  * also required to switch modes.
  18  *
  19  * Note: The h/w manual register naming convention is clumsy and not acceptable
  20  * to use as it is in the driver. However, those names are added as comments
  21  * wherever it is modified to a readable name.
  22  */
  23
  24 #include <linux/bitmap.h>
  25 #include <linux/bitops.h>
  26 #include <linux/can/dev.h>
  27 #include <linux/clk.h>
  28 #include <linux/errno.h>
  29 #include <linux/ethtool.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/iopoll.h>
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38 #include <linux/phy/phy.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/reset.h>
  41 #include <linux/types.h>
  42
  43 #define RCANFD_DRV_NAME                 "rcar_canfd"
  44
  45 /* Global register bits */
  46
  47 /* RSCFDnCFDGRMCFG */
  48 #define RCANFD_GRMCFG_RCMC              BIT(0)
  49
  50 /* RSCFDnCFDGCFG / RSCFDnGCFG */
  51 #define RCANFD_GCFG_EEFE                BIT(6)
  52 #define RCANFD_GCFG_CMPOC               BIT(5)  /* CAN FD only */
  53 #define RCANFD_GCFG_DCS                 BIT(4)
  54 #define RCANFD_GCFG_DCE                 BIT(1)
  55 #define RCANFD_GCFG_TPRI                BIT(0)
  56
  57 /* RSCFDnCFDGCTR / RSCFDnGCTR */
  58 #define RCANFD_GCTR_TSRST               BIT(16)
  59 #define RCANFD_GCTR_CFMPOFIE            BIT(11) /* CAN FD only */
  60 #define RCANFD_GCTR_THLEIE              BIT(10)
  61 #define RCANFD_GCTR_MEIE                BIT(9)
  62 #define RCANFD_GCTR_DEIE                BIT(8)
  63 #define RCANFD_GCTR_GSLPR               BIT(2)
  64 #define RCANFD_GCTR_GMDC_MASK           (0x3)
  65 #define RCANFD_GCTR_GMDC_GOPM           (0x0)
  66 #define RCANFD_GCTR_GMDC_GRESET         (0x1)
  67 #define RCANFD_GCTR_GMDC_GTEST          (0x2)
  68
  69 /* RSCFDnCFDGSTS / RSCFDnGSTS */
  70 #define RCANFD_GSTS_GRAMINIT            BIT(3)
  71 #define RCANFD_GSTS_GSLPSTS             BIT(2)
  72 #define RCANFD_GSTS_GHLTSTS             BIT(1)
  73 #define RCANFD_GSTS_GRSTSTS             BIT(0)
  74 /* Non-operational status */
  75 #define RCANFD_GSTS_GNOPM               (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  76
  77 /* RSCFDnCFDGERFL / RSCFDnGERFL */
  78 #define RCANFD_GERFL_EEF0_7             GENMASK(23, 16)
  79 #define RCANFD_GERFL_EEF(ch)            BIT(16 + (ch))
  80 #define RCANFD_GERFL_CMPOF              BIT(3)  /* CAN FD only */
  81 #define RCANFD_GERFL_THLES              BIT(2)
  82 #define RCANFD_GERFL_MES                BIT(1)
  83 #define RCANFD_GERFL_DEF                BIT(0)
  84
  85 #define RCANFD_GERFL_ERR(gpriv, x) \
  86         ((x) & (reg_gen4(gpriv, RCANFD_GERFL_EEF0_7, \
  87                          RCANFD_GERFL_EEF(0) | RCANFD_GERFL_EEF(1)) | \
  88                 RCANFD_GERFL_MES | \
  89                 ((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
  90
  91 /* AFL Rx rules registers */
  92
  93 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
  94 #define RCANFD_GAFLCFG_SETRNC(gpriv, n, x) \
  95         (((x) & reg_gen4(gpriv, 0x1ff, 0xff)) << \
  96          (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8)))
  97
  98 #define RCANFD_GAFLCFG_GETRNC(gpriv, n, x) \
  99         (((x) >> (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8))) & \
 100          reg_gen4(gpriv, 0x1ff, 0xff))
 101
 102 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 103 #define RCANFD_GAFLECTR_AFLDAE          BIT(8)
 104 #define RCANFD_GAFLECTR_AFLPN(gpriv, x) ((x) & reg_gen4(gpriv, 0x7f, 0x1f))
 105
 106 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 107 #define RCANFD_GAFLID_GAFLLB            BIT(29)
 108
 109 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
 110 #define RCANFD_GAFLP1_GAFLFDP(x)        (1 << (x))
 111
 112 /* Channel register bits */
 113
 114 /* RSCFDnCmCFG - Classical CAN only */
 115 #define RCANFD_CFG_SJW(x)               (((x) & 0x3) << 24)
 116 #define RCANFD_CFG_TSEG2(x)             (((x) & 0x7) << 20)
 117 #define RCANFD_CFG_TSEG1(x)             (((x) & 0xf) << 16)
 118 #define RCANFD_CFG_BRP(x)               (((x) & 0x3ff) << 0)
 119
 120 /* RSCFDnCFDCmNCFG - CAN FD only */
 121 #define RCANFD_NCFG_NTSEG2(gpriv, x) \
 122         (((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 25, 24))
 123
 124 #define RCANFD_NCFG_NTSEG1(gpriv, x) \
 125         (((x) & reg_gen4(gpriv, 0xff, 0x7f)) << reg_gen4(gpriv, 17, 16))
 126
 127 #define RCANFD_NCFG_NSJW(gpriv, x) \
 128         (((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 10, 11))
 129
 130 #define RCANFD_NCFG_NBRP(x)             (((x) & 0x3ff) << 0)
 131
 132 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 133 #define RCANFD_CCTR_CTME                BIT(24)
 134 #define RCANFD_CCTR_ERRD                BIT(23)
 135 #define RCANFD_CCTR_BOM_MASK            (0x3 << 21)
 136 #define RCANFD_CCTR_BOM_ISO             (0x0 << 21)
 137 #define RCANFD_CCTR_BOM_BENTRY          (0x1 << 21)
 138 #define RCANFD_CCTR_BOM_BEND            (0x2 << 21)
 139 #define RCANFD_CCTR_TDCVFIE             BIT(19)
 140 #define RCANFD_CCTR_SOCOIE              BIT(18)
 141 #define RCANFD_CCTR_EOCOIE              BIT(17)
 142 #define RCANFD_CCTR_TAIE                BIT(16)
 143 #define RCANFD_CCTR_ALIE                BIT(15)
 144 #define RCANFD_CCTR_BLIE                BIT(14)
 145 #define RCANFD_CCTR_OLIE                BIT(13)
 146 #define RCANFD_CCTR_BORIE               BIT(12)
 147 #define RCANFD_CCTR_BOEIE               BIT(11)
 148 #define RCANFD_CCTR_EPIE                BIT(10)
 149 #define RCANFD_CCTR_EWIE                BIT(9)
 150 #define RCANFD_CCTR_BEIE                BIT(8)
 151 #define RCANFD_CCTR_CSLPR               BIT(2)
 152 #define RCANFD_CCTR_CHMDC_MASK          (0x3)
 153 #define RCANFD_CCTR_CHDMC_COPM          (0x0)
 154 #define RCANFD_CCTR_CHDMC_CRESET        (0x1)
 155 #define RCANFD_CCTR_CHDMC_CHLT          (0x2)
 156
 157 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 158 #define RCANFD_CSTS_COMSTS              BIT(7)
 159 #define RCANFD_CSTS_RECSTS              BIT(6)
 160 #define RCANFD_CSTS_TRMSTS              BIT(5)
 161 #define RCANFD_CSTS_BOSTS               BIT(4)
 162 #define RCANFD_CSTS_EPSTS               BIT(3)
 163 #define RCANFD_CSTS_SLPSTS              BIT(2)
 164 #define RCANFD_CSTS_HLTSTS              BIT(1)
 165 #define RCANFD_CSTS_CRSTSTS             BIT(0)
 166
 167 #define RCANFD_CSTS_TECCNT(x)           (((x) >> 24) & 0xff)
 168 #define RCANFD_CSTS_RECCNT(x)           (((x) >> 16) & 0xff)
 169
 170 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 171 #define RCANFD_CERFL_ADERR              BIT(14)
 172 #define RCANFD_CERFL_B0ERR              BIT(13)
 173 #define RCANFD_CERFL_B1ERR              BIT(12)
 174 #define RCANFD_CERFL_CERR               BIT(11)
 175 #define RCANFD_CERFL_AERR               BIT(10)
 176 #define RCANFD_CERFL_FERR               BIT(9)
 177 #define RCANFD_CERFL_SERR               BIT(8)
 178 #define RCANFD_CERFL_ALF                BIT(7)
 179 #define RCANFD_CERFL_BLF                BIT(6)
 180 #define RCANFD_CERFL_OVLF               BIT(5)
 181 #define RCANFD_CERFL_BORF               BIT(4)
 182 #define RCANFD_CERFL_BOEF               BIT(3)
 183 #define RCANFD_CERFL_EPF                BIT(2)
 184 #define RCANFD_CERFL_EWF                BIT(1)
 185 #define RCANFD_CERFL_BEF                BIT(0)
 186
 187 #define RCANFD_CERFL_ERR(x)             ((x) & (0x7fff)) /* above bits 14:0 */
 188
 189 /* RSCFDnCFDCmDCFG */
 190 #define RCANFD_DCFG_DSJW(gpriv, x)      (((x) & reg_gen4(gpriv, 0xf, 0x7)) << 24)
 191
 192 #define RCANFD_DCFG_DTSEG2(gpriv, x) \
 193         (((x) & reg_gen4(gpriv, 0x0f, 0x7)) << reg_gen4(gpriv, 16, 20))
 194
 195 #define RCANFD_DCFG_DTSEG1(gpriv, x) \
 196         (((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 8, 16))
 197
 198 #define RCANFD_DCFG_DBRP(x)             (((x) & 0xff) << 0)
 199
 200 /* RSCFDnCFDCmFDCFG */
 201 #define RCANFD_GEN4_FDCFG_CLOE          BIT(30)
 202 #define RCANFD_GEN4_FDCFG_FDOE          BIT(28)
 203 #define RCANFD_FDCFG_TDCE               BIT(9)
 204 #define RCANFD_FDCFG_TDCOC              BIT(8)
 205 #define RCANFD_FDCFG_TDCO(x)            (((x) & 0x7f) >> 16)
 206
 207 /* RSCFDnCFDRFCCx */
 208 #define RCANFD_RFCC_RFIM                BIT(12)
 209 #define RCANFD_RFCC_RFDC(x)             (((x) & 0x7) << 8)
 210 #define RCANFD_RFCC_RFPLS(x)            (((x) & 0x7) << 4)
 211 #define RCANFD_RFCC_RFIE                BIT(1)
 212 #define RCANFD_RFCC_RFE                 BIT(0)
 213
 214 /* RSCFDnCFDRFSTSx */
 215 #define RCANFD_RFSTS_RFIF               BIT(3)
 216 #define RCANFD_RFSTS_RFMLT              BIT(2)
 217 #define RCANFD_RFSTS_RFFLL              BIT(1)
 218 #define RCANFD_RFSTS_RFEMP              BIT(0)
 219
 220 /* RSCFDnCFDRFIDx */
 221 #define RCANFD_RFID_RFIDE               BIT(31)
 222 #define RCANFD_RFID_RFRTR               BIT(30)
 223
 224 /* RSCFDnCFDRFPTRx */
 225 #define RCANFD_RFPTR_RFDLC(x)           (((x) >> 28) & 0xf)
 226 #define RCANFD_RFPTR_RFPTR(x)           (((x) >> 16) & 0xfff)
 227 #define RCANFD_RFPTR_RFTS(x)            (((x) >> 0) & 0xffff)
 228
 229 /* RSCFDnCFDRFFDSTSx */
 230 #define RCANFD_RFFDSTS_RFFDF            BIT(2)
 231 #define RCANFD_RFFDSTS_RFBRS            BIT(1)
 232 #define RCANFD_RFFDSTS_RFESI            BIT(0)
 233
 234 /* Common FIFO bits */
 235
 236 /* RSCFDnCFDCFCCk */
 237 #define RCANFD_CFCC_CFTML(gpriv, x)     \
 238         (((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 16, 20))
 239 #define RCANFD_CFCC_CFM(gpriv, x)       (((x) & 0x3) << reg_gen4(gpriv,  8, 16))
 240 #define RCANFD_CFCC_CFIM                BIT(12)
 241 #define RCANFD_CFCC_CFDC(gpriv, x)      (((x) & 0x7) << reg_gen4(gpriv, 21,  8))
 242 #define RCANFD_CFCC_CFPLS(x)            (((x) & 0x7) << 4)
 243 #define RCANFD_CFCC_CFTXIE              BIT(2)
 244 #define RCANFD_CFCC_CFE                 BIT(0)
 245
 246 /* RSCFDnCFDCFSTSk */
 247 #define RCANFD_CFSTS_CFMC(x)            (((x) >> 8) & 0xff)
 248 #define RCANFD_CFSTS_CFTXIF             BIT(4)
 249 #define RCANFD_CFSTS_CFMLT              BIT(2)
 250 #define RCANFD_CFSTS_CFFLL              BIT(1)
 251 #define RCANFD_CFSTS_CFEMP              BIT(0)
 252
 253 /* RSCFDnCFDCFIDk */
 254 #define RCANFD_CFID_CFIDE               BIT(31)
 255 #define RCANFD_CFID_CFRTR               BIT(30)
 256 #define RCANFD_CFID_CFID_MASK(x)        ((x) & 0x1fffffff)
 257
 258 /* RSCFDnCFDCFPTRk */
 259 #define RCANFD_CFPTR_CFDLC(x)           (((x) & 0xf) << 28)
 260 #define RCANFD_CFPTR_CFPTR(x)           (((x) & 0xfff) << 16)
 261 #define RCANFD_CFPTR_CFTS(x)            (((x) & 0xff) << 0)
 262
 263 /* RSCFDnCFDCFFDCSTSk */
 264 #define RCANFD_CFFDCSTS_CFFDF           BIT(2)
 265 #define RCANFD_CFFDCSTS_CFBRS           BIT(1)
 266 #define RCANFD_CFFDCSTS_CFESI           BIT(0)
 267
 268 /* This controller supports either Classical CAN only mode or CAN FD only mode.
 269  * These modes are supported in two separate set of register maps & names.
 270  * However, some of the register offsets are common for both modes. Those
 271  * offsets are listed below as Common registers.
 272  *
 273  * The CAN FD only mode specific registers & Classical CAN only mode specific
 274  * registers are listed separately. Their register names starts with
 275  * RCANFD_F_xxx & RCANFD_C_xxx respectively.
 276  */
 277
 278 /* Common registers */
 279
 280 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
 281 #define RCANFD_CCFG(m)                  (0x0000 + (0x10 * (m)))
 282 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 283 #define RCANFD_CCTR(m)                  (0x0004 + (0x10 * (m)))
 284 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 285 #define RCANFD_CSTS(m)                  (0x0008 + (0x10 * (m)))
 286 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 287 #define RCANFD_CERFL(m)                 (0x000C + (0x10 * (m)))
 288
 289 /* RSCFDnCFDGCFG / RSCFDnGCFG */
 290 #define RCANFD_GCFG                     (0x0084)
 291 /* RSCFDnCFDGCTR / RSCFDnGCTR */
 292 #define RCANFD_GCTR                     (0x0088)
 293 /* RSCFDnCFDGCTS / RSCFDnGCTS */
 294 #define RCANFD_GSTS                     (0x008c)
 295 /* RSCFDnCFDGERFL / RSCFDnGERFL */
 296 #define RCANFD_GERFL                    (0x0090)
 297 /* RSCFDnCFDGTSC / RSCFDnGTSC */
 298 #define RCANFD_GTSC                     (0x0094)
 299 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 300 #define RCANFD_GAFLECTR                 (0x0098)
 301 /* RSCFDnCFDGAFLCFG / RSCFDnGAFLCFG */
 302 #define RCANFD_GAFLCFG(ch)              (0x009c + (0x04 * ((ch) / 2)))
 303 /* RSCFDnCFDRMNB / RSCFDnRMNB */
 304 #define RCANFD_RMNB                     (0x00a4)
 305 /* RSCFDnCFDRMND / RSCFDnRMND */
 306 #define RCANFD_RMND(y)                  (0x00a8 + (0x04 * (y)))
 307
 308 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
 309 #define RCANFD_RFCC(gpriv, x)           (reg_gen4(gpriv, 0x00c0, 0x00b8) + (0x04 * (x)))
 310 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
 311 #define RCANFD_RFSTS(gpriv, x)          (RCANFD_RFCC(gpriv, x) + 0x20)
 312 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
 313 #define RCANFD_RFPCTR(gpriv, x)         (RCANFD_RFCC(gpriv, x) + 0x40)
 314
 315 /* Common FIFO Control registers */
 316
 317 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
 318 #define RCANFD_CFCC(gpriv, ch, idx) \
 319         (reg_gen4(gpriv, 0x0120, 0x0118) + (0x0c * (ch)) + (0x04 * (idx)))
 320 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
 321 #define RCANFD_CFSTS(gpriv, ch, idx) \
 322         (reg_gen4(gpriv, 0x01e0, 0x0178) + (0x0c * (ch)) + (0x04 * (idx)))
 323 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
 324 #define RCANFD_CFPCTR(gpriv, ch, idx) \
 325         (reg_gen4(gpriv, 0x0240, 0x01d8) + (0x0c * (ch)) + (0x04 * (idx)))
 326
 327 /* RSCFDnCFDFESTS / RSCFDnFESTS */
 328 #define RCANFD_FESTS                    (0x0238)
 329 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
 330 #define RCANFD_FFSTS                    (0x023c)
 331 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
 332 #define RCANFD_FMSTS                    (0x0240)
 333 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
 334 #define RCANFD_RFISTS                   (0x0244)
 335 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
 336 #define RCANFD_CFRISTS                  (0x0248)
 337 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
 338 #define RCANFD_CFTISTS                  (0x024c)
 339
 340 /* RSCFDnCFDTMCp / RSCFDnTMCp */
 341 #define RCANFD_TMC(p)                   (0x0250 + (0x01 * (p)))
 342 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
 343 #define RCANFD_TMSTS(p)                 (0x02d0 + (0x01 * (p)))
 344
 345 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
 346 #define RCANFD_TMTRSTS(y)               (0x0350 + (0x04 * (y)))
 347 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
 348 #define RCANFD_TMTARSTS(y)              (0x0360 + (0x04 * (y)))
 349 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
 350 #define RCANFD_TMTCSTS(y)               (0x0370 + (0x04 * (y)))
 351 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
 352 #define RCANFD_TMTASTS(y)               (0x0380 + (0x04 * (y)))
 353 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
 354 #define RCANFD_TMIEC(y)                 (0x0390 + (0x04 * (y)))
 355
 356 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
 357 #define RCANFD_TXQCC(m)                 (0x03a0 + (0x04 * (m)))
 358 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
 359 #define RCANFD_TXQSTS(m)                (0x03c0 + (0x04 * (m)))
 360 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
 361 #define RCANFD_TXQPCTR(m)               (0x03e0 + (0x04 * (m)))
 362
 363 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
 364 #define RCANFD_THLCC(m)                 (0x0400 + (0x04 * (m)))
 365 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
 366 #define RCANFD_THLSTS(m)                (0x0420 + (0x04 * (m)))
 367 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
 368 #define RCANFD_THLPCTR(m)               (0x0440 + (0x04 * (m)))
 369
 370 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
 371 #define RCANFD_GTINTSTS0                (0x0460)
 372 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
 373 #define RCANFD_GTINTSTS1                (0x0464)
 374 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
 375 #define RCANFD_GTSTCFG                  (0x0468)
 376 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
 377 #define RCANFD_GTSTCTR                  (0x046c)
 378 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
 379 #define RCANFD_GLOCKK                   (0x047c)
 380 /* RSCFDnCFDGRMCFG */
 381 #define RCANFD_GRMCFG                   (0x04fc)
 382
 383 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 384 #define RCANFD_GAFLID(offset, j)        ((offset) + (0x10 * (j)))
 385 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
 386 #define RCANFD_GAFLM(offset, j)         ((offset) + 0x04 + (0x10 * (j)))
 387 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
 388 #define RCANFD_GAFLP0(offset, j)        ((offset) + 0x08 + (0x10 * (j)))
 389 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
 390 #define RCANFD_GAFLP1(offset, j)        ((offset) + 0x0c + (0x10 * (j)))
 391
 392 /* Classical CAN only mode register map */
 393
 394 /* RSCFDnGAFLXXXj offset */
 395 #define RCANFD_C_GAFL_OFFSET            (0x0500)
 396
 397 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
 398 #define RCANFD_C_RMID(q)                (0x0600 + (0x10 * (q)))
 399 #define RCANFD_C_RMPTR(q)               (0x0604 + (0x10 * (q)))
 400 #define RCANFD_C_RMDF0(q)               (0x0608 + (0x10 * (q)))
 401 #define RCANFD_C_RMDF1(q)               (0x060c + (0x10 * (q)))
 402
 403 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
 404 #define RCANFD_C_RFOFFSET       (0x0e00)
 405 #define RCANFD_C_RFID(x)        (RCANFD_C_RFOFFSET + (0x10 * (x)))
 406 #define RCANFD_C_RFPTR(x)       (RCANFD_C_RFOFFSET + 0x04 + (0x10 * (x)))
 407 #define RCANFD_C_RFDF(x, df) \
 408                 (RCANFD_C_RFOFFSET + 0x08 + (0x10 * (x)) + (0x04 * (df)))
 409
 410 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
 411 #define RCANFD_C_CFOFFSET               (0x0e80)
 412
 413 #define RCANFD_C_CFID(ch, idx) \
 414         (RCANFD_C_CFOFFSET + (0x30 * (ch)) + (0x10 * (idx)))
 415
 416 #define RCANFD_C_CFPTR(ch, idx) \
 417         (RCANFD_C_CFOFFSET + 0x04 + (0x30 * (ch)) + (0x10 * (idx)))
 418
 419 #define RCANFD_C_CFDF(ch, idx, df) \
 420         (RCANFD_C_CFOFFSET + 0x08 + (0x30 * (ch)) + (0x10 * (idx)) + (0x04 * (df)))
 421
 422 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
 423 #define RCANFD_C_TMID(p)                (0x1000 + (0x10 * (p)))
 424 #define RCANFD_C_TMPTR(p)               (0x1004 + (0x10 * (p)))
 425 #define RCANFD_C_TMDF0(p)               (0x1008 + (0x10 * (p)))
 426 #define RCANFD_C_TMDF1(p)               (0x100c + (0x10 * (p)))
 427
 428 /* RSCFDnTHLACCm */
 429 #define RCANFD_C_THLACC(m)              (0x1800 + (0x04 * (m)))
 430 /* RSCFDnRPGACCr */
 431 #define RCANFD_C_RPGACC(r)              (0x1900 + (0x04 * (r)))
 432
 433 /* R-Car Gen4 Classical and CAN FD mode specific register map */
 434 #define RCANFD_GEN4_FDCFG(m)            (0x1404 + (0x20 * (m)))
 435
 436 #define RCANFD_GEN4_GAFL_OFFSET         (0x1800)
 437
 438 /* CAN FD mode specific register map */
 439
 440 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
 441 #define RCANFD_F_DCFG(gpriv, m)         (reg_gen4(gpriv, 0x1400, 0x0500) + (0x20 * (m)))
 442 #define RCANFD_F_CFDCFG(m)              (0x0504 + (0x20 * (m)))
 443 #define RCANFD_F_CFDCTR(m)              (0x0508 + (0x20 * (m)))
 444 #define RCANFD_F_CFDSTS(m)              (0x050c + (0x20 * (m)))
 445 #define RCANFD_F_CFDCRC(m)              (0x0510 + (0x20 * (m)))
 446
 447 /* RSCFDnCFDGAFLXXXj offset */
 448 #define RCANFD_F_GAFL_OFFSET            (0x1000)
 449
 450 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
 451 #define RCANFD_F_RMID(q)                (0x2000 + (0x20 * (q)))
 452 #define RCANFD_F_RMPTR(q)               (0x2004 + (0x20 * (q)))
 453 #define RCANFD_F_RMFDSTS(q)             (0x2008 + (0x20 * (q)))
 454 #define RCANFD_F_RMDF(q, b)             (0x200c + (0x04 * (b)) + (0x20 * (q)))
 455
 456 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
 457 #define RCANFD_F_RFOFFSET(gpriv)        reg_gen4(gpriv, 0x6000, 0x3000)
 458 #define RCANFD_F_RFID(gpriv, x)         (RCANFD_F_RFOFFSET(gpriv) + (0x80 * (x)))
 459 #define RCANFD_F_RFPTR(gpriv, x)        (RCANFD_F_RFOFFSET(gpriv) + 0x04 + (0x80 * (x)))
 460 #define RCANFD_F_RFFDSTS(gpriv, x)      (RCANFD_F_RFOFFSET(gpriv) + 0x08 + (0x80 * (x)))
 461 #define RCANFD_F_RFDF(gpriv, x, df) \
 462         (RCANFD_F_RFOFFSET(gpriv) + 0x0c + (0x80 * (x)) + (0x04 * (df)))
 463
 464 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
 465 #define RCANFD_F_CFOFFSET(gpriv)        reg_gen4(gpriv, 0x6400, 0x3400)
 466
 467 #define RCANFD_F_CFID(gpriv, ch, idx) \
 468         (RCANFD_F_CFOFFSET(gpriv) + (0x180 * (ch)) + (0x80 * (idx)))
 469
 470 #define RCANFD_F_CFPTR(gpriv, ch, idx) \
 471         (RCANFD_F_CFOFFSET(gpriv) + 0x04 + (0x180 * (ch)) + (0x80 * (idx)))
 472
 473 #define RCANFD_F_CFFDCSTS(gpriv, ch, idx) \
 474         (RCANFD_F_CFOFFSET(gpriv) + 0x08 + (0x180 * (ch)) + (0x80 * (idx)))
 475
 476 #define RCANFD_F_CFDF(gpriv, ch, idx, df) \
 477         (RCANFD_F_CFOFFSET(gpriv) + 0x0c + (0x180 * (ch)) + (0x80 * (idx)) + \
 478          (0x04 * (df)))
 479
 480 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
 481 #define RCANFD_F_TMID(p)                (0x4000 + (0x20 * (p)))
 482 #define RCANFD_F_TMPTR(p)               (0x4004 + (0x20 * (p)))
 483 #define RCANFD_F_TMFDCTR(p)             (0x4008 + (0x20 * (p)))
 484 #define RCANFD_F_TMDF(p, b)             (0x400c + (0x20 * (p)) + (0x04 * (b)))
 485
 486 /* RSCFDnCFDTHLACCm */
 487 #define RCANFD_F_THLACC(m)              (0x6000 + (0x04 * (m)))
 488 /* RSCFDnCFDRPGACCr */
 489 #define RCANFD_F_RPGACC(r)              (0x6400 + (0x04 * (r)))
 490
 491 /* Constants */
 492 #define RCANFD_FIFO_DEPTH               8       /* Tx FIFO depth */
 493 #define RCANFD_NAPI_WEIGHT              8       /* Rx poll quota */
 494
 495 #define RCANFD_NUM_CHANNELS             8       /* Eight channels max */
 496 #define RCANFD_CHANNELS_MASK            BIT((RCANFD_NUM_CHANNELS) - 1)
 497
 498 #define RCANFD_GAFL_PAGENUM(entry)      ((entry) / 16)
 499 #define RCANFD_CHANNEL_NUMRULES         1       /* only one rule per channel */
 500
 501 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
 502  * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
 503  * number is added to RFFIFO index.
 504  */
 505 #define RCANFD_RFFIFO_IDX               0
 506
 507 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
 508  * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
 509  */
 510 #define RCANFD_CFFIFO_IDX               0
 511
 512 /* fCAN clock select register settings */
 513 enum rcar_canfd_fcanclk {
 514         RCANFD_CANFDCLK = 0,            /* CANFD clock */
 515         RCANFD_EXTCLK,                  /* Externally input clock */
 516 };
 517
 518 struct rcar_canfd_global;
 519
 520 struct rcar_canfd_hw_info {
 521         u8 max_channels;
 522         u8 postdiv;
 523         /* hardware features */
 524         unsigned shared_global_irqs:1;  /* Has shared global irqs */
 525         unsigned multi_channel_irqs:1;  /* Has multiple channel irqs */
 526 };
 527
 528 /* Channel priv data */
 529 struct rcar_canfd_channel {
 530         struct can_priv can;                    /* Must be the first member */
 531         struct net_device *ndev;
 532         struct rcar_canfd_global *gpriv;        /* Controller reference */
 533         void __iomem *base;                     /* Register base address */
 534         struct phy *transceiver;                /* Optional transceiver */
 535         struct napi_struct napi;
 536         u32 tx_head;                            /* Incremented on xmit */
 537         u32 tx_tail;                            /* Incremented on xmit done */
 538         u32 channel;                            /* Channel number */
 539         spinlock_t tx_lock;                     /* To protect tx path */
 540 };
 541
 542 /* Global priv data */
 543 struct rcar_canfd_global {
 544         struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
 545         void __iomem *base;             /* Register base address */
 546         struct platform_device *pdev;   /* Respective platform device */
 547         struct clk *clkp;               /* Peripheral clock */
 548         struct clk *can_clk;            /* fCAN clock */
 549         enum rcar_canfd_fcanclk fcan;   /* CANFD or Ext clock */
 550         unsigned long channels_mask;    /* Enabled channels mask */
 551         bool fdmode;                    /* CAN FD or Classical CAN only mode */
 552         struct reset_control *rstc1;
 553         struct reset_control *rstc2;
 554         const struct rcar_canfd_hw_info *info;
 555 };
 556
 557 /* CAN FD mode nominal rate constants */
 558 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
 559         .name = RCANFD_DRV_NAME,
 560         .tseg1_min = 2,
 561         .tseg1_max = 128,
 562         .tseg2_min = 2,
 563         .tseg2_max = 32,
 564         .sjw_max = 32,
 565         .brp_min = 1,
 566         .brp_max = 1024,
 567         .brp_inc = 1,
 568 };
 569
 570 /* CAN FD mode data rate constants */
 571 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
 572         .name = RCANFD_DRV_NAME,
 573         .tseg1_min = 2,
 574         .tseg1_max = 16,
 575         .tseg2_min = 2,
 576         .tseg2_max = 8,
 577         .sjw_max = 8,
 578         .brp_min = 1,
 579         .brp_max = 256,
 580         .brp_inc = 1,
 581 };
 582
 583 /* Classical CAN mode bitrate constants */
 584 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
 585         .name = RCANFD_DRV_NAME,
 586         .tseg1_min = 4,
 587         .tseg1_max = 16,
 588         .tseg2_min = 2,
 589         .tseg2_max = 8,
 590         .sjw_max = 4,
 591         .brp_min = 1,
 592         .brp_max = 1024,
 593         .brp_inc = 1,
 594 };
 595
 596 static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
 597         .max_channels = 2,
 598         .postdiv = 2,
 599         .shared_global_irqs = 1,
 600 };
 601
 602 static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
 603         .max_channels = 8,
 604         .postdiv = 2,
 605         .shared_global_irqs = 1,
 606 };
 607
 608 static const struct rcar_canfd_hw_info rzg2l_hw_info = {
 609         .max_channels = 2,
 610         .postdiv = 1,
 611         .multi_channel_irqs = 1,
 612 };
 613
 614 /* Helper functions */
 615 static inline bool is_gen4(struct rcar_canfd_global *gpriv)
 616 {
 617         return gpriv->info == &rcar_gen4_hw_info;
 618 }
 619
 620 static inline u32 reg_gen4(struct rcar_canfd_global *gpriv,
 621                            u32 gen4, u32 not_gen4)
 622 {
 623         return is_gen4(gpriv) ? gen4 : not_gen4;
 624 }
 625
 626 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
 627 {
 628         u32 data = readl(reg);
 629
 630         data &= ~mask;
 631         data |= (val & mask);
 632         writel(data, reg);
 633 }
 634
 635 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
 636 {
 637         return readl(base + (offset));
 638 }
 639
 640 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
 641 {
 642         writel(val, base + (offset));
 643 }
 644
 645 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
 646 {
 647         rcar_canfd_update(val, val, base + (reg));
 648 }
 649
 650 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
 651 {
 652         rcar_canfd_update(val, 0, base + (reg));
 653 }
 654
 655 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
 656                                   u32 mask, u32 val)
 657 {
 658         rcar_canfd_update(mask, val, base + (reg));
 659 }
 660
 661 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
 662                                 struct canfd_frame *cf, u32 off)
 663 {
 664         u32 i, lwords;
 665
 666         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 667         for (i = 0; i < lwords; i++)
 668                 *((u32 *)cf->data + i) =
 669                         rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
 670 }
 671
 672 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
 673                                 struct canfd_frame *cf, u32 off)
 674 {
 675         u32 i, lwords;
 676
 677         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 678         for (i = 0; i < lwords; i++)
 679                 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
 680                                  *((u32 *)cf->data + i));
 681 }
 682
 683 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
 684 {
 685         u32 i;
 686
 687         for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
 688                 can_free_echo_skb(ndev, i, NULL);
 689 }
 690
 691 static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv)
 692 {
 693         if (is_gen4(gpriv)) {
 694                 u32 ch, val = gpriv->fdmode ? RCANFD_GEN4_FDCFG_FDOE
 695                                             : RCANFD_GEN4_FDCFG_CLOE;
 696
 697                 for_each_set_bit(ch, &gpriv->channels_mask,
 698                                  gpriv->info->max_channels)
 699                         rcar_canfd_set_bit(gpriv->base, RCANFD_GEN4_FDCFG(ch),
 700                                            val);
 701         } else {
 702                 if (gpriv->fdmode)
 703                         rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 704                                            RCANFD_GRMCFG_RCMC);
 705                 else
 706                         rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
 707                                              RCANFD_GRMCFG_RCMC);
 708         }
 709 }
 710
 711 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 712 {
 713         u32 sts, ch;
 714         int err;
 715
 716         /* Check RAMINIT flag as CAN RAM initialization takes place
 717          * after the MCU reset
 718          */
 719         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 720                                  !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
 721         if (err) {
 722                 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
 723                 return err;
 724         }
 725
 726         /* Transition to Global Reset mode */
 727         rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
 728         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
 729                               RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
 730
 731         /* Ensure Global reset mode */
 732         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 733                                  (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
 734         if (err) {
 735                 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
 736                 return err;
 737         }
 738
 739         /* Reset Global error flags */
 740         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 741
 742         /* Set the controller into appropriate mode */
 743         rcar_canfd_set_mode(gpriv);
 744
 745         /* Transition all Channels to reset mode */
 746         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
 747                 rcar_canfd_clear_bit(gpriv->base,
 748                                      RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 749
 750                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 751                                       RCANFD_CCTR_CHMDC_MASK,
 752                                       RCANFD_CCTR_CHDMC_CRESET);
 753
 754                 /* Ensure Channel reset mode */
 755                 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
 756                                          (sts & RCANFD_CSTS_CRSTSTS),
 757                                          2, 500000);
 758                 if (err) {
 759                         dev_dbg(&gpriv->pdev->dev,
 760                                 "channel %u reset failed\n", ch);
 761                         return err;
 762                 }
 763         }
 764         return 0;
 765 }
 766
 767 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 768 {
 769         u32 cfg, ch;
 770
 771         /* Global configuration settings */
 772
 773         /* ECC Error flag Enable */
 774         cfg = RCANFD_GCFG_EEFE;
 775
 776         if (gpriv->fdmode)
 777                 /* Truncate payload to configured message size RFPLS */
 778                 cfg |= RCANFD_GCFG_CMPOC;
 779
 780         /* Set External Clock if selected */
 781         if (gpriv->fcan != RCANFD_CANFDCLK)
 782                 cfg |= RCANFD_GCFG_DCS;
 783
 784         rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 785
 786         /* Channel configuration settings */
 787         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
 788                 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
 789                                    RCANFD_CCTR_ERRD);
 790                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 791                                       RCANFD_CCTR_BOM_MASK,
 792                                       RCANFD_CCTR_BOM_BENTRY);
 793         }
 794 }
 795
 796 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 797                                            u32 ch)
 798 {
 799         u32 cfg;
 800         int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 801         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 802
 803         if (ch == 0) {
 804                 start = 0; /* Channel 0 always starts from 0th rule */
 805         } else {
 806                 /* Get number of Channel 0 rules and adjust */
 807                 cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG(ch));
 808                 start = RCANFD_GAFLCFG_GETRNC(gpriv, 0, cfg);
 809         }
 810
 811         /* Enable write access to entry */
 812         page = RCANFD_GAFL_PAGENUM(start);
 813         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 814                            (RCANFD_GAFLECTR_AFLPN(gpriv, page) |
 815                             RCANFD_GAFLECTR_AFLDAE));
 816
 817         /* Write number of rules for channel */
 818         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(ch),
 819                            RCANFD_GAFLCFG_SETRNC(gpriv, ch, num_rules));
 820         if (is_gen4(gpriv))
 821                 offset = RCANFD_GEN4_GAFL_OFFSET;
 822         else if (gpriv->fdmode)
 823                 offset = RCANFD_F_GAFL_OFFSET;
 824         else
 825                 offset = RCANFD_C_GAFL_OFFSET;
 826
 827         /* Accept all IDs */
 828         rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
 829         /* IDE or RTR is not considered for matching */
 830         rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
 831         /* Any data length accepted */
 832         rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
 833         /* Place the msg in corresponding Rx FIFO entry */
 834         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, start),
 835                            RCANFD_GAFLP1_GAFLFDP(ridx));
 836
 837         /* Disable write access to page */
 838         rcar_canfd_clear_bit(gpriv->base,
 839                              RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
 840 }
 841
 842 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 843 {
 844         /* Rx FIFO is used for reception */
 845         u32 cfg;
 846         u16 rfdc, rfpls;
 847
 848         /* Select Rx FIFO based on channel */
 849         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 850
 851         rfdc = 2;               /* b010 - 8 messages Rx FIFO depth */
 852         if (gpriv->fdmode)
 853                 rfpls = 7;      /* b111 - Max 64 bytes payload */
 854         else
 855                 rfpls = 0;      /* b000 - Max 8 bytes payload */
 856
 857         cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 858                 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 859         rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
 860 }
 861
 862 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 863 {
 864         /* Tx/Rx(Common) FIFO configured in Tx mode is
 865          * used for transmission
 866          *
 867          * Each channel has 3 Common FIFO dedicated to them.
 868          * Use the 1st (index 0) out of 3
 869          */
 870         u32 cfg;
 871         u16 cftml, cfm, cfdc, cfpls;
 872
 873         cftml = 0;              /* 0th buffer */
 874         cfm = 1;                /* b01 - Transmit mode */
 875         cfdc = 2;               /* b010 - 8 messages Tx FIFO depth */
 876         if (gpriv->fdmode)
 877                 cfpls = 7;      /* b111 - Max 64 bytes payload */
 878         else
 879                 cfpls = 0;      /* b000 - Max 8 bytes payload */
 880
 881         cfg = (RCANFD_CFCC_CFTML(gpriv, cftml) | RCANFD_CFCC_CFM(gpriv, cfm) |
 882                 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(gpriv, cfdc) |
 883                 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
 884         rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
 885
 886         if (gpriv->fdmode)
 887                 /* Clear FD mode specific control/status register */
 888                 rcar_canfd_write(gpriv->base,
 889                                  RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 0);
 890 }
 891
 892 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 893 {
 894         u32 ctr;
 895
 896         /* Clear any stray error interrupt flags */
 897         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 898
 899         /* Global interrupts setup */
 900         ctr = RCANFD_GCTR_MEIE;
 901         if (gpriv->fdmode)
 902                 ctr |= RCANFD_GCTR_CFMPOFIE;
 903
 904         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 905 }
 906
 907 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
 908                                                  *gpriv)
 909 {
 910         /* Disable all interrupts */
 911         rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
 912
 913         /* Clear any stray error interrupt flags */
 914         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 915 }
 916
 917 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
 918                                                  *priv)
 919 {
 920         u32 ctr, ch = priv->channel;
 921
 922         /* Clear any stray error flags */
 923         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 924
 925         /* Channel interrupts setup */
 926         ctr = (RCANFD_CCTR_TAIE |
 927                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 928                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 929                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 930                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 931         rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
 932 }
 933
 934 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
 935                                                   *priv)
 936 {
 937         u32 ctr, ch = priv->channel;
 938
 939         ctr = (RCANFD_CCTR_TAIE |
 940                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 941                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 942                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 943                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 944         rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
 945
 946         /* Clear any stray error flags */
 947         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 948 }
 949
 950 static void rcar_canfd_global_error(struct net_device *ndev)
 951 {
 952         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 953         struct rcar_canfd_global *gpriv = priv->gpriv;
 954         struct net_device_stats *stats = &ndev->stats;
 955         u32 ch = priv->channel;
 956         u32 gerfl, sts;
 957         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 958
 959         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
 960         if (gerfl & RCANFD_GERFL_EEF(ch)) {
 961                 netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch);
 962                 stats->tx_dropped++;
 963         }
 964         if (gerfl & RCANFD_GERFL_MES) {
 965                 sts = rcar_canfd_read(priv->base,
 966                                       RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
 967                 if (sts & RCANFD_CFSTS_CFMLT) {
 968                         netdev_dbg(ndev, "Tx Message Lost flag\n");
 969                         stats->tx_dropped++;
 970                         rcar_canfd_write(priv->base,
 971                                          RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
 972                                          sts & ~RCANFD_CFSTS_CFMLT);
 973                 }
 974
 975                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
 976                 if (sts & RCANFD_RFSTS_RFMLT) {
 977                         netdev_dbg(ndev, "Rx Message Lost flag\n");
 978                         stats->rx_dropped++;
 979                         rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
 980                                          sts & ~RCANFD_RFSTS_RFMLT);
 981                 }
 982         }
 983         if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
 984                 /* Message Lost flag will be set for respective channel
 985                  * when this condition happens with counters and flags
 986                  * already updated.
 987                  */
 988                 netdev_dbg(ndev, "global payload overflow interrupt\n");
 989         }
 990
 991         /* Clear all global error interrupts. Only affected channels bits
 992          * get cleared
 993          */
 994         rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
 995 }
 996
 997 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
 998                              u16 txerr, u16 rxerr)
 999 {
1000         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1001         struct net_device_stats *stats = &ndev->stats;
1002         struct can_frame *cf;
1003         struct sk_buff *skb;
1004         u32 ch = priv->channel;
1005
1006         netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
1007
1008         /* Propagate the error condition to the CAN stack */
1009         skb = alloc_can_err_skb(ndev, &cf);
1010         if (!skb) {
1011                 stats->rx_dropped++;
1012                 return;
1013         }
1014
1015         /* Channel error interrupts */
1016         if (cerfl & RCANFD_CERFL_BEF) {
1017                 netdev_dbg(ndev, "Bus error\n");
1018                 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1019                 cf->data[2] = CAN_ERR_PROT_UNSPEC;
1020                 priv->can.can_stats.bus_error++;
1021         }
1022         if (cerfl & RCANFD_CERFL_ADERR) {
1023                 netdev_dbg(ndev, "ACK Delimiter Error\n");
1024                 stats->tx_errors++;
1025                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1026         }
1027         if (cerfl & RCANFD_CERFL_B0ERR) {
1028                 netdev_dbg(ndev, "Bit Error (dominant)\n");
1029                 stats->tx_errors++;
1030                 cf->data[2] |= CAN_ERR_PROT_BIT0;
1031         }
1032         if (cerfl & RCANFD_CERFL_B1ERR) {
1033                 netdev_dbg(ndev, "Bit Error (recessive)\n");
1034                 stats->tx_errors++;
1035                 cf->data[2] |= CAN_ERR_PROT_BIT1;
1036         }
1037         if (cerfl & RCANFD_CERFL_CERR) {
1038                 netdev_dbg(ndev, "CRC Error\n");
1039                 stats->rx_errors++;
1040                 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1041         }
1042         if (cerfl & RCANFD_CERFL_AERR) {
1043                 netdev_dbg(ndev, "ACK Error\n");
1044                 stats->tx_errors++;
1045                 cf->can_id |= CAN_ERR_ACK;
1046                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1047         }
1048         if (cerfl & RCANFD_CERFL_FERR) {
1049                 netdev_dbg(ndev, "Form Error\n");
1050                 stats->rx_errors++;
1051                 cf->data[2] |= CAN_ERR_PROT_FORM;
1052         }
1053         if (cerfl & RCANFD_CERFL_SERR) {
1054                 netdev_dbg(ndev, "Stuff Error\n");
1055                 stats->rx_errors++;
1056                 cf->data[2] |= CAN_ERR_PROT_STUFF;
1057         }
1058         if (cerfl & RCANFD_CERFL_ALF) {
1059                 netdev_dbg(ndev, "Arbitration lost Error\n");
1060                 priv->can.can_stats.arbitration_lost++;
1061                 cf->can_id |= CAN_ERR_LOSTARB;
1062                 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1063         }
1064         if (cerfl & RCANFD_CERFL_BLF) {
1065                 netdev_dbg(ndev, "Bus Lock Error\n");
1066                 stats->rx_errors++;
1067                 cf->can_id |= CAN_ERR_BUSERROR;
1068         }
1069         if (cerfl & RCANFD_CERFL_EWF) {
1070                 netdev_dbg(ndev, "Error warning interrupt\n");
1071                 priv->can.state = CAN_STATE_ERROR_WARNING;
1072                 priv->can.can_stats.error_warning++;
1073                 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1074                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1075                         CAN_ERR_CRTL_RX_WARNING;
1076                 cf->data[6] = txerr;
1077                 cf->data[7] = rxerr;
1078         }
1079         if (cerfl & RCANFD_CERFL_EPF) {
1080                 netdev_dbg(ndev, "Error passive interrupt\n");
1081                 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1082                 priv->can.can_stats.error_passive++;
1083                 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1084                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1085                         CAN_ERR_CRTL_RX_PASSIVE;
1086                 cf->data[6] = txerr;
1087                 cf->data[7] = rxerr;
1088         }
1089         if (cerfl & RCANFD_CERFL_BOEF) {
1090                 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1091                 rcar_canfd_tx_failure_cleanup(ndev);
1092                 priv->can.state = CAN_STATE_BUS_OFF;
1093                 priv->can.can_stats.bus_off++;
1094                 can_bus_off(ndev);
1095                 cf->can_id |= CAN_ERR_BUSOFF;
1096         }
1097         if (cerfl & RCANFD_CERFL_OVLF) {
1098                 netdev_dbg(ndev,
1099                            "Overload Frame Transmission error interrupt\n");
1100                 stats->tx_errors++;
1101                 cf->can_id |= CAN_ERR_PROT;
1102                 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1103         }
1104
1105         /* Clear channel error interrupts that are handled */
1106         rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1107                          RCANFD_CERFL_ERR(~cerfl));
1108         netif_rx(skb);
1109 }
1110
1111 static void rcar_canfd_tx_done(struct net_device *ndev)
1112 {
1113         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1114         struct rcar_canfd_global *gpriv = priv->gpriv;
1115         struct net_device_stats *stats = &ndev->stats;
1116         u32 sts;
1117         unsigned long flags;
1118         u32 ch = priv->channel;
1119
1120         do {
1121                 u8 unsent, sent;
1122
1123                 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1124                 stats->tx_packets++;
1125                 stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
1126
1127                 spin_lock_irqsave(&priv->tx_lock, flags);
1128                 priv->tx_tail++;
1129                 sts = rcar_canfd_read(priv->base,
1130                                       RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1131                 unsent = RCANFD_CFSTS_CFMC(sts);
1132
1133                 /* Wake producer only when there is room */
1134                 if (unsent != RCANFD_FIFO_DEPTH)
1135                         netif_wake_queue(ndev);
1136
1137                 if (priv->tx_head - priv->tx_tail <= unsent) {
1138                         spin_unlock_irqrestore(&priv->tx_lock, flags);
1139                         break;
1140                 }
1141                 spin_unlock_irqrestore(&priv->tx_lock, flags);
1142
1143         } while (1);
1144
1145         /* Clear interrupt */
1146         rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1147                          sts & ~RCANFD_CFSTS_CFTXIF);
1148 }
1149
1150 static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1151 {
1152         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1153         struct net_device *ndev = priv->ndev;
1154         u32 gerfl;
1155
1156         /* Handle global error interrupts */
1157         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1158         if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1159                 rcar_canfd_global_error(ndev);
1160 }
1161
1162 static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1163 {
1164         struct rcar_canfd_global *gpriv = dev_id;
1165         u32 ch;
1166
1167         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1168                 rcar_canfd_handle_global_err(gpriv, ch);
1169
1170         return IRQ_HANDLED;
1171 }
1172
1173 static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1174 {
1175         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1176         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1177         u32 sts, cc;
1178
1179         /* Handle Rx interrupts */
1180         sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1181         cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx));
1182         if (likely(sts & RCANFD_RFSTS_RFIF &&
1183                    cc & RCANFD_RFCC_RFIE)) {
1184                 if (napi_schedule_prep(&priv->napi)) {
1185                         /* Disable Rx FIFO interrupts */
1186                         rcar_canfd_clear_bit(priv->base,
1187                                              RCANFD_RFCC(gpriv, ridx),
1188                                              RCANFD_RFCC_RFIE);
1189                         __napi_schedule(&priv->napi);
1190                 }
1191         }
1192 }
1193
1194 static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1195 {
1196         struct rcar_canfd_global *gpriv = dev_id;
1197         u32 ch;
1198
1199         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1200                 rcar_canfd_handle_global_receive(gpriv, ch);
1201
1202         return IRQ_HANDLED;
1203 }
1204
1205 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1206 {
1207         struct rcar_canfd_global *gpriv = dev_id;
1208         u32 ch;
1209
1210         /* Global error interrupts still indicate a condition specific
1211          * to a channel. RxFIFO interrupt is a global interrupt.
1212          */
1213         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1214                 rcar_canfd_handle_global_err(gpriv, ch);
1215                 rcar_canfd_handle_global_receive(gpriv, ch);
1216         }
1217         return IRQ_HANDLED;
1218 }
1219
1220 static void rcar_canfd_state_change(struct net_device *ndev,
1221                                     u16 txerr, u16 rxerr)
1222 {
1223         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1224         struct net_device_stats *stats = &ndev->stats;
1225         enum can_state rx_state, tx_state, state = priv->can.state;
1226         struct can_frame *cf;
1227         struct sk_buff *skb;
1228
1229         /* Handle transition from error to normal states */
1230         if (txerr < 96 && rxerr < 96)
1231                 state = CAN_STATE_ERROR_ACTIVE;
1232         else if (txerr < 128 && rxerr < 128)
1233                 state = CAN_STATE_ERROR_WARNING;
1234
1235         if (state != priv->can.state) {
1236                 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1237                            state, priv->can.state, txerr, rxerr);
1238                 skb = alloc_can_err_skb(ndev, &cf);
1239                 if (!skb) {
1240                         stats->rx_dropped++;
1241                         return;
1242                 }
1243                 tx_state = txerr >= rxerr ? state : 0;
1244                 rx_state = txerr <= rxerr ? state : 0;
1245
1246                 can_change_state(ndev, cf, tx_state, rx_state);
1247                 netif_rx(skb);
1248         }
1249 }
1250
1251 static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1252 {
1253         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1254         struct net_device *ndev = priv->ndev;
1255         u32 sts;
1256
1257         /* Handle Tx interrupts */
1258         sts = rcar_canfd_read(priv->base,
1259                               RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1260         if (likely(sts & RCANFD_CFSTS_CFTXIF))
1261                 rcar_canfd_tx_done(ndev);
1262 }
1263
1264 static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1265 {
1266         struct rcar_canfd_channel *priv = dev_id;
1267
1268         rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1269
1270         return IRQ_HANDLED;
1271 }
1272
1273 static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1274 {
1275         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1276         struct net_device *ndev = priv->ndev;
1277         u16 txerr, rxerr;
1278         u32 sts, cerfl;
1279
1280         /* Handle channel error interrupts */
1281         cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1282         sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1283         txerr = RCANFD_CSTS_TECCNT(sts);
1284         rxerr = RCANFD_CSTS_RECCNT(sts);
1285         if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1286                 rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1287
1288         /* Handle state change to lower states */
1289         if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1290                      priv->can.state != CAN_STATE_BUS_OFF))
1291                 rcar_canfd_state_change(ndev, txerr, rxerr);
1292 }
1293
1294 static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1295 {
1296         struct rcar_canfd_channel *priv = dev_id;
1297
1298         rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1299
1300         return IRQ_HANDLED;
1301 }
1302
1303 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1304 {
1305         struct rcar_canfd_global *gpriv = dev_id;
1306         u32 ch;
1307
1308         /* Common FIFO is a per channel resource */
1309         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1310                 rcar_canfd_handle_channel_err(gpriv, ch);
1311                 rcar_canfd_handle_channel_tx(gpriv, ch);
1312         }
1313
1314         return IRQ_HANDLED;
1315 }
1316
1317 static void rcar_canfd_set_bittiming(struct net_device *dev)
1318 {
1319         struct rcar_canfd_channel *priv = netdev_priv(dev);
1320         struct rcar_canfd_global *gpriv = priv->gpriv;
1321         const struct can_bittiming *bt = &priv->can.bittiming;
1322         const struct can_bittiming *dbt = &priv->can.data_bittiming;
1323         u16 brp, sjw, tseg1, tseg2;
1324         u32 cfg;
1325         u32 ch = priv->channel;
1326
1327         /* Nominal bit timing settings */
1328         brp = bt->brp - 1;
1329         sjw = bt->sjw - 1;
1330         tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1331         tseg2 = bt->phase_seg2 - 1;
1332
1333         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1334                 /* CAN FD only mode */
1335                 cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | RCANFD_NCFG_NBRP(brp) |
1336                        RCANFD_NCFG_NSJW(gpriv, sjw) | RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1337
1338                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1339                 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1340                            brp, sjw, tseg1, tseg2);
1341
1342                 /* Data bit timing settings */
1343                 brp = dbt->brp - 1;
1344                 sjw = dbt->sjw - 1;
1345                 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1346                 tseg2 = dbt->phase_seg2 - 1;
1347
1348                 cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
1349                        RCANFD_DCFG_DSJW(gpriv, sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
1350
1351                 rcar_canfd_write(priv->base, RCANFD_F_DCFG(gpriv, ch), cfg);
1352                 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1353                            brp, sjw, tseg1, tseg2);
1354         } else {
1355                 /* Classical CAN only mode */
1356                 if (is_gen4(gpriv)) {
1357                         cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) |
1358                                RCANFD_NCFG_NBRP(brp) |
1359                                RCANFD_NCFG_NSJW(gpriv, sjw) |
1360                                RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1361                 } else {
1362                         cfg = (RCANFD_CFG_TSEG1(tseg1) |
1363                                RCANFD_CFG_BRP(brp) |
1364                                RCANFD_CFG_SJW(sjw) |
1365                                RCANFD_CFG_TSEG2(tseg2));
1366                 }
1367
1368                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1369                 netdev_dbg(priv->ndev,
1370                            "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1371                            brp, sjw, tseg1, tseg2);
1372         }
1373 }
1374
1375 static int rcar_canfd_start(struct net_device *ndev)
1376 {
1377         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1378         struct rcar_canfd_global *gpriv = priv->gpriv;
1379         int err = -EOPNOTSUPP;
1380         u32 sts, ch = priv->channel;
1381         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1382
1383         rcar_canfd_set_bittiming(ndev);
1384
1385         rcar_canfd_enable_channel_interrupts(priv);
1386
1387         /* Set channel to Operational mode */
1388         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1389                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1390
1391         /* Verify channel mode change */
1392         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1393                                  (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1394         if (err) {
1395                 netdev_err(ndev, "channel %u communication state failed\n", ch);
1396                 goto fail_mode_change;
1397         }
1398
1399         /* Enable Common & Rx FIFO */
1400         rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1401                            RCANFD_CFCC_CFE);
1402         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1403
1404         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1405         return 0;
1406
1407 fail_mode_change:
1408         rcar_canfd_disable_channel_interrupts(priv);
1409         return err;
1410 }
1411
1412 static int rcar_canfd_open(struct net_device *ndev)
1413 {
1414         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1415         struct rcar_canfd_global *gpriv = priv->gpriv;
1416         int err;
1417
1418         err = phy_power_on(priv->transceiver);
1419         if (err) {
1420                 netdev_err(ndev, "failed to power on PHY: %pe\n", ERR_PTR(err));
1421                 return err;
1422         }
1423
1424         /* Peripheral clock is already enabled in probe */
1425         err = clk_prepare_enable(gpriv->can_clk);
1426         if (err) {
1427                 netdev_err(ndev, "failed to enable CAN clock: %pe\n", ERR_PTR(err));
1428                 goto out_phy;
1429         }
1430
1431         err = open_candev(ndev);
1432         if (err) {
1433                 netdev_err(ndev, "open_candev() failed: %pe\n", ERR_PTR(err));
1434                 goto out_can_clock;
1435         }
1436
1437         napi_enable(&priv->napi);
1438         err = rcar_canfd_start(ndev);
1439         if (err)
1440                 goto out_close;
1441         netif_start_queue(ndev);
1442         return 0;
1443 out_close:
1444         napi_disable(&priv->napi);
1445         close_candev(ndev);
1446 out_can_clock:
1447         clk_disable_unprepare(gpriv->can_clk);
1448 out_phy:
1449         phy_power_off(priv->transceiver);
1450         return err;
1451 }
1452
1453 static void rcar_canfd_stop(struct net_device *ndev)
1454 {
1455         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1456         struct rcar_canfd_global *gpriv = priv->gpriv;
1457         int err;
1458         u32 sts, ch = priv->channel;
1459         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1460
1461         /* Transition to channel reset mode  */
1462         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1463                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1464
1465         /* Check Channel reset mode */
1466         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1467                                  (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1468         if (err)
1469                 netdev_err(ndev, "channel %u reset failed\n", ch);
1470
1471         rcar_canfd_disable_channel_interrupts(priv);
1472
1473         /* Disable Common & Rx FIFO */
1474         rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1475                              RCANFD_CFCC_CFE);
1476         rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1477
1478         /* Set the state as STOPPED */
1479         priv->can.state = CAN_STATE_STOPPED;
1480 }
1481
1482 static int rcar_canfd_close(struct net_device *ndev)
1483 {
1484         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1485         struct rcar_canfd_global *gpriv = priv->gpriv;
1486
1487         netif_stop_queue(ndev);
1488         rcar_canfd_stop(ndev);
1489         napi_disable(&priv->napi);
1490         clk_disable_unprepare(gpriv->can_clk);
1491         close_candev(ndev);
1492         phy_power_off(priv->transceiver);
1493         return 0;
1494 }
1495
1496 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1497                                          struct net_device *ndev)
1498 {
1499         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1500         struct rcar_canfd_global *gpriv = priv->gpriv;
1501         struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1502         u32 sts = 0, id, dlc;
1503         unsigned long flags;
1504         u32 ch = priv->channel;
1505
1506         if (can_dev_dropped_skb(ndev, skb))
1507                 return NETDEV_TX_OK;
1508
1509         if (cf->can_id & CAN_EFF_FLAG) {
1510                 id = cf->can_id & CAN_EFF_MASK;
1511                 id |= RCANFD_CFID_CFIDE;
1512         } else {
1513                 id = cf->can_id & CAN_SFF_MASK;
1514         }
1515
1516         if (cf->can_id & CAN_RTR_FLAG)
1517                 id |= RCANFD_CFID_CFRTR;
1518
1519         dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1520
1521         if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1522                 rcar_canfd_write(priv->base,
1523                                  RCANFD_F_CFID(gpriv, ch, RCANFD_CFFIFO_IDX), id);
1524                 rcar_canfd_write(priv->base,
1525                                  RCANFD_F_CFPTR(gpriv, ch, RCANFD_CFFIFO_IDX), dlc);
1526
1527                 if (can_is_canfd_skb(skb)) {
1528                         /* CAN FD frame format */
1529                         sts |= RCANFD_CFFDCSTS_CFFDF;
1530                         if (cf->flags & CANFD_BRS)
1531                                 sts |= RCANFD_CFFDCSTS_CFBRS;
1532
1533                         if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1534                                 sts |= RCANFD_CFFDCSTS_CFESI;
1535                 }
1536
1537                 rcar_canfd_write(priv->base,
1538                                  RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), sts);
1539
1540                 rcar_canfd_put_data(priv, cf,
1541                                     RCANFD_F_CFDF(gpriv, ch, RCANFD_CFFIFO_IDX, 0));
1542         } else {
1543                 rcar_canfd_write(priv->base,
1544                                  RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1545                 rcar_canfd_write(priv->base,
1546                                  RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1547                 rcar_canfd_put_data(priv, cf,
1548                                     RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1549         }
1550
1551         can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1552
1553         spin_lock_irqsave(&priv->tx_lock, flags);
1554         priv->tx_head++;
1555
1556         /* Stop the queue if we've filled all FIFO entries */
1557         if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1558                 netif_stop_queue(ndev);
1559
1560         /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1561          * pointer for the Common FIFO
1562          */
1563         rcar_canfd_write(priv->base,
1564                          RCANFD_CFPCTR(gpriv, ch, RCANFD_CFFIFO_IDX), 0xff);
1565
1566         spin_unlock_irqrestore(&priv->tx_lock, flags);
1567         return NETDEV_TX_OK;
1568 }
1569
1570 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1571 {
1572         struct net_device_stats *stats = &priv->ndev->stats;
1573         struct rcar_canfd_global *gpriv = priv->gpriv;
1574         struct canfd_frame *cf;
1575         struct sk_buff *skb;
1576         u32 sts = 0, id, dlc;
1577         u32 ch = priv->channel;
1578         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1579
1580         if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1581                 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1582                 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1583
1584                 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1585
1586                 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1587                     sts & RCANFD_RFFDSTS_RFFDF)
1588                         skb = alloc_canfd_skb(priv->ndev, &cf);
1589                 else
1590                         skb = alloc_can_skb(priv->ndev,
1591                                             (struct can_frame **)&cf);
1592         } else {
1593                 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1594                 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1595                 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1596         }
1597
1598         if (!skb) {
1599                 stats->rx_dropped++;
1600                 return;
1601         }
1602
1603         if (id & RCANFD_RFID_RFIDE)
1604                 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1605         else
1606                 cf->can_id = id & CAN_SFF_MASK;
1607
1608         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1609                 if (sts & RCANFD_RFFDSTS_RFFDF)
1610                         cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1611                 else
1612                         cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1613
1614                 if (sts & RCANFD_RFFDSTS_RFESI) {
1615                         cf->flags |= CANFD_ESI;
1616                         netdev_dbg(priv->ndev, "ESI Error\n");
1617                 }
1618
1619                 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1620                         cf->can_id |= CAN_RTR_FLAG;
1621                 } else {
1622                         if (sts & RCANFD_RFFDSTS_RFBRS)
1623                                 cf->flags |= CANFD_BRS;
1624
1625                         rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1626                 }
1627         } else {
1628                 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1629                 if (id & RCANFD_RFID_RFRTR)
1630                         cf->can_id |= CAN_RTR_FLAG;
1631                 else if (is_gen4(gpriv))
1632                         rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1633                 else
1634                         rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1635         }
1636
1637         /* Write 0xff to RFPC to increment the CPU-side
1638          * pointer of the Rx FIFO
1639          */
1640         rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
1641
1642         if (!(cf->can_id & CAN_RTR_FLAG))
1643                 stats->rx_bytes += cf->len;
1644         stats->rx_packets++;
1645         netif_receive_skb(skb);
1646 }
1647
1648 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1649 {
1650         struct rcar_canfd_channel *priv =
1651                 container_of(napi, struct rcar_canfd_channel, napi);
1652         struct rcar_canfd_global *gpriv = priv->gpriv;
1653         int num_pkts;
1654         u32 sts;
1655         u32 ch = priv->channel;
1656         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1657
1658         for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1659                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1660                 /* Check FIFO empty condition */
1661                 if (sts & RCANFD_RFSTS_RFEMP)
1662                         break;
1663
1664                 rcar_canfd_rx_pkt(priv);
1665
1666                 /* Clear interrupt bit */
1667                 if (sts & RCANFD_RFSTS_RFIF)
1668                         rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1669                                          sts & ~RCANFD_RFSTS_RFIF);
1670         }
1671
1672         /* All packets processed */
1673         if (num_pkts < quota) {
1674                 if (napi_complete_done(napi, num_pkts)) {
1675                         /* Enable Rx FIFO interrupts */
1676                         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1677                                            RCANFD_RFCC_RFIE);
1678                 }
1679         }
1680         return num_pkts;
1681 }
1682
1683 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1684 {
1685         int err;
1686
1687         switch (mode) {
1688         case CAN_MODE_START:
1689                 err = rcar_canfd_start(ndev);
1690                 if (err)
1691                         return err;
1692                 netif_wake_queue(ndev);
1693                 return 0;
1694         default:
1695                 return -EOPNOTSUPP;
1696         }
1697 }
1698
1699 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1700                                        struct can_berr_counter *bec)
1701 {
1702         struct rcar_canfd_channel *priv = netdev_priv(dev);
1703         u32 val, ch = priv->channel;
1704
1705         /* Peripheral clock is already enabled in probe */
1706         val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1707         bec->txerr = RCANFD_CSTS_TECCNT(val);
1708         bec->rxerr = RCANFD_CSTS_RECCNT(val);
1709         return 0;
1710 }
1711
1712 static const struct net_device_ops rcar_canfd_netdev_ops = {
1713         .ndo_open = rcar_canfd_open,
1714         .ndo_stop = rcar_canfd_close,
1715         .ndo_start_xmit = rcar_canfd_start_xmit,
1716         .ndo_change_mtu = can_change_mtu,
1717 };
1718
1719 static const struct ethtool_ops rcar_canfd_ethtool_ops = {
1720         .get_ts_info = ethtool_op_get_ts_info,
1721 };
1722
1723 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1724                                     u32 fcan_freq, struct phy *transceiver)
1725 {
1726         const struct rcar_canfd_hw_info *info = gpriv->info;
1727         struct platform_device *pdev = gpriv->pdev;
1728         struct device *dev = &pdev->dev;
1729         struct rcar_canfd_channel *priv;
1730         struct net_device *ndev;
1731         int err = -ENODEV;
1732
1733         ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1734         if (!ndev)
1735                 return -ENOMEM;
1736
1737         priv = netdev_priv(ndev);
1738
1739         ndev->netdev_ops = &rcar_canfd_netdev_ops;
1740         ndev->ethtool_ops = &rcar_canfd_ethtool_ops;
1741         ndev->flags |= IFF_ECHO;
1742         priv->ndev = ndev;
1743         priv->base = gpriv->base;
1744         priv->transceiver = transceiver;
1745         priv->channel = ch;
1746         priv->gpriv = gpriv;
1747         if (transceiver)
1748                 priv->can.bitrate_max = transceiver->attrs.max_link_rate;
1749         priv->can.clock.freq = fcan_freq;
1750         dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
1751
1752         if (info->multi_channel_irqs) {
1753                 char *irq_name;
1754                 int err_irq;
1755                 int tx_irq;
1756
1757                 err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
1758                 if (err_irq < 0) {
1759                         err = err_irq;
1760                         goto fail;
1761                 }
1762
1763                 tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
1764                 if (tx_irq < 0) {
1765                         err = tx_irq;
1766                         goto fail;
1767                 }
1768
1769                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_err",
1770                                           ch);
1771                 if (!irq_name) {
1772                         err = -ENOMEM;
1773                         goto fail;
1774                 }
1775                 err = devm_request_irq(dev, err_irq,
1776                                        rcar_canfd_channel_err_interrupt, 0,
1777                                        irq_name, priv);
1778                 if (err) {
1779                         dev_err(dev, "devm_request_irq CH Err %d failed: %pe\n",
1780                                 err_irq, ERR_PTR(err));
1781                         goto fail;
1782                 }
1783                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_trx",
1784                                           ch);
1785                 if (!irq_name) {
1786                         err = -ENOMEM;
1787                         goto fail;
1788                 }
1789                 err = devm_request_irq(dev, tx_irq,
1790                                        rcar_canfd_channel_tx_interrupt, 0,
1791                                        irq_name, priv);
1792                 if (err) {
1793                         dev_err(dev, "devm_request_irq Tx %d failed: %pe\n",
1794                                 tx_irq, ERR_PTR(err));
1795                         goto fail;
1796                 }
1797         }
1798
1799         if (gpriv->fdmode) {
1800                 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1801                 priv->can.data_bittiming_const =
1802                         &rcar_canfd_data_bittiming_const;
1803
1804                 /* Controller starts in CAN FD only mode */
1805                 err = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1806                 if (err)
1807                         goto fail;
1808                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1809         } else {
1810                 /* Controller starts in Classical CAN only mode */
1811                 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1812                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1813         }
1814
1815         priv->can.do_set_mode = rcar_canfd_do_set_mode;
1816         priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1817         SET_NETDEV_DEV(ndev, dev);
1818
1819         netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1820                               RCANFD_NAPI_WEIGHT);
1821         spin_lock_init(&priv->tx_lock);
1822         gpriv->ch[priv->channel] = priv;
1823         err = register_candev(ndev);
1824         if (err) {
1825                 dev_err(dev, "register_candev() failed: %pe\n", ERR_PTR(err));
1826                 goto fail_candev;
1827         }
1828         dev_info(dev, "device registered (channel %u)\n", priv->channel);
1829         return 0;
1830
1831 fail_candev:
1832         netif_napi_del(&priv->napi);
1833 fail:
1834         free_candev(ndev);
1835         return err;
1836 }
1837
1838 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1839 {
1840         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1841
1842         if (priv) {
1843                 unregister_candev(priv->ndev);
1844                 netif_napi_del(&priv->napi);
1845                 free_candev(priv->ndev);
1846         }
1847 }
1848
1849 static int rcar_canfd_probe(struct platform_device *pdev)
1850 {
1851         struct phy *transceivers[RCANFD_NUM_CHANNELS] = { NULL, };
1852         const struct rcar_canfd_hw_info *info;
1853         struct device *dev = &pdev->dev;
1854         void __iomem *addr;
1855         u32 sts, ch, fcan_freq;
1856         struct rcar_canfd_global *gpriv;
1857         struct device_node *of_child;
1858         unsigned long channels_mask = 0;
1859         int err, ch_irq, g_irq;
1860         int g_err_irq, g_recc_irq;
1861         bool fdmode = true;                     /* CAN FD only mode - default */
1862         char name[9] = "channelX";
1863         int i;
1864
1865         info = of_device_get_match_data(dev);
1866
1867         if (of_property_read_bool(dev->of_node, "renesas,no-can-fd"))
1868                 fdmode = false;                 /* Classical CAN only mode */
1869
1870         for (i = 0; i < info->max_channels; ++i) {
1871                 name[7] = '0' + i;
1872                 of_child = of_get_child_by_name(dev->of_node, name);
1873                 if (of_child && of_device_is_available(of_child)) {
1874                         channels_mask |= BIT(i);
1875                         transceivers[i] = devm_of_phy_optional_get(dev,
1876                                                         of_child, NULL);
1877                 }
1878                 of_node_put(of_child);
1879                 if (IS_ERR(transceivers[i]))
1880                         return PTR_ERR(transceivers[i]);
1881         }
1882
1883         if (info->shared_global_irqs) {
1884                 ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
1885                 if (ch_irq < 0) {
1886                         /* For backward compatibility get irq by index */
1887                         ch_irq = platform_get_irq(pdev, 0);
1888                         if (ch_irq < 0)
1889                                 return ch_irq;
1890                 }
1891
1892                 g_irq = platform_get_irq_byname_optional(pdev, "g_int");
1893                 if (g_irq < 0) {
1894                         /* For backward compatibility get irq by index */
1895                         g_irq = platform_get_irq(pdev, 1);
1896                         if (g_irq < 0)
1897                                 return g_irq;
1898                 }
1899         } else {
1900                 g_err_irq = platform_get_irq_byname(pdev, "g_err");
1901                 if (g_err_irq < 0)
1902                         return g_err_irq;
1903
1904                 g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
1905                 if (g_recc_irq < 0)
1906                         return g_recc_irq;
1907         }
1908
1909         /* Global controller context */
1910         gpriv = devm_kzalloc(dev, sizeof(*gpriv), GFP_KERNEL);
1911         if (!gpriv)
1912                 return -ENOMEM;
1913
1914         gpriv->pdev = pdev;
1915         gpriv->channels_mask = channels_mask;
1916         gpriv->fdmode = fdmode;
1917         gpriv->info = info;
1918
1919         gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
1920         if (IS_ERR(gpriv->rstc1))
1921                 return dev_err_probe(dev, PTR_ERR(gpriv->rstc1),
1922                                      "failed to get rstp_n\n");
1923
1924         gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
1925         if (IS_ERR(gpriv->rstc2))
1926                 return dev_err_probe(dev, PTR_ERR(gpriv->rstc2),
1927                                      "failed to get rstc_n\n");
1928
1929         /* Peripheral clock */
1930         gpriv->clkp = devm_clk_get(dev, "fck");
1931         if (IS_ERR(gpriv->clkp))
1932                 return dev_err_probe(dev, PTR_ERR(gpriv->clkp),
1933                                      "cannot get peripheral clock\n");
1934
1935         /* fCAN clock: Pick External clock. If not available fallback to
1936          * CANFD clock
1937          */
1938         gpriv->can_clk = devm_clk_get(dev, "can_clk");
1939         if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1940                 gpriv->can_clk = devm_clk_get(dev, "canfd");
1941                 if (IS_ERR(gpriv->can_clk))
1942                         return dev_err_probe(dev, PTR_ERR(gpriv->can_clk),
1943                                              "cannot get canfd clock\n");
1944
1945                 gpriv->fcan = RCANFD_CANFDCLK;
1946
1947         } else {
1948                 gpriv->fcan = RCANFD_EXTCLK;
1949         }
1950         fcan_freq = clk_get_rate(gpriv->can_clk);
1951
1952         if (gpriv->fcan == RCANFD_CANFDCLK)
1953                 /* CANFD clock is further divided by (1/2) within the IP */
1954                 fcan_freq /= info->postdiv;
1955
1956         addr = devm_platform_ioremap_resource(pdev, 0);
1957         if (IS_ERR(addr)) {
1958                 err = PTR_ERR(addr);
1959                 goto fail_dev;
1960         }
1961         gpriv->base = addr;
1962
1963         /* Request IRQ that's common for both channels */
1964         if (info->shared_global_irqs) {
1965                 err = devm_request_irq(dev, ch_irq,
1966                                        rcar_canfd_channel_interrupt, 0,
1967                                        "canfd.ch_int", gpriv);
1968                 if (err) {
1969                         dev_err(dev, "devm_request_irq %d failed: %pe\n",
1970                                 ch_irq, ERR_PTR(err));
1971                         goto fail_dev;
1972                 }
1973
1974                 err = devm_request_irq(dev, g_irq, rcar_canfd_global_interrupt,
1975                                        0, "canfd.g_int", gpriv);
1976                 if (err) {
1977                         dev_err(dev, "devm_request_irq %d failed: %pe\n",
1978                                 g_irq, ERR_PTR(err));
1979                         goto fail_dev;
1980                 }
1981         } else {
1982                 err = devm_request_irq(dev, g_recc_irq,
1983                                        rcar_canfd_global_receive_fifo_interrupt, 0,
1984                                        "canfd.g_recc", gpriv);
1985
1986                 if (err) {
1987                         dev_err(dev, "devm_request_irq %d failed: %pe\n",
1988                                 g_recc_irq, ERR_PTR(err));
1989                         goto fail_dev;
1990                 }
1991
1992                 err = devm_request_irq(dev, g_err_irq,
1993                                        rcar_canfd_global_err_interrupt, 0,
1994                                        "canfd.g_err", gpriv);
1995                 if (err) {
1996                         dev_err(dev, "devm_request_irq %d failed: %pe\n",
1997                                 g_err_irq, ERR_PTR(err));
1998                         goto fail_dev;
1999                 }
2000         }
2001
2002         err = reset_control_reset(gpriv->rstc1);
2003         if (err)
2004                 goto fail_dev;
2005         err = reset_control_reset(gpriv->rstc2);
2006         if (err) {
2007                 reset_control_assert(gpriv->rstc1);
2008                 goto fail_dev;
2009         }
2010
2011         /* Enable peripheral clock for register access */
2012         err = clk_prepare_enable(gpriv->clkp);
2013         if (err) {
2014                 dev_err(dev, "failed to enable peripheral clock: %pe\n",
2015                         ERR_PTR(err));
2016                 goto fail_reset;
2017         }
2018
2019         err = rcar_canfd_reset_controller(gpriv);
2020         if (err) {
2021                 dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err));
2022                 goto fail_clk;
2023         }
2024
2025         /* Controller in Global reset & Channel reset mode */
2026         rcar_canfd_configure_controller(gpriv);
2027
2028         /* Configure per channel attributes */
2029         for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2030                 /* Configure Channel's Rx fifo */
2031                 rcar_canfd_configure_rx(gpriv, ch);
2032
2033                 /* Configure Channel's Tx (Common) fifo */
2034                 rcar_canfd_configure_tx(gpriv, ch);
2035
2036                 /* Configure receive rules */
2037                 rcar_canfd_configure_afl_rules(gpriv, ch);
2038         }
2039
2040         /* Configure common interrupts */
2041         rcar_canfd_enable_global_interrupts(gpriv);
2042
2043         /* Start Global operation mode */
2044         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2045                               RCANFD_GCTR_GMDC_GOPM);
2046
2047         /* Verify mode change */
2048         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2049                                  !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
2050         if (err) {
2051                 dev_err(dev, "global operational mode failed\n");
2052                 goto fail_mode;
2053         }
2054
2055         for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2056                 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq,
2057                                                transceivers[ch]);
2058                 if (err)
2059                         goto fail_channel;
2060         }
2061
2062         platform_set_drvdata(pdev, gpriv);
2063         dev_info(dev, "global operational state (clk %d, fdmode %d)\n",
2064                  gpriv->fcan, gpriv->fdmode);
2065         return 0;
2066
2067 fail_channel:
2068         for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
2069                 rcar_canfd_channel_remove(gpriv, ch);
2070 fail_mode:
2071         rcar_canfd_disable_global_interrupts(gpriv);
2072 fail_clk:
2073         clk_disable_unprepare(gpriv->clkp);
2074 fail_reset:
2075         reset_control_assert(gpriv->rstc1);
2076         reset_control_assert(gpriv->rstc2);
2077 fail_dev:
2078         return err;
2079 }
2080
2081 static int rcar_canfd_remove(struct platform_device *pdev)
2082 {
2083         struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
2084         u32 ch;
2085
2086         rcar_canfd_reset_controller(gpriv);
2087         rcar_canfd_disable_global_interrupts(gpriv);
2088
2089         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2090                 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2091                 rcar_canfd_channel_remove(gpriv, ch);
2092         }
2093
2094         /* Enter global sleep mode */
2095         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2096         clk_disable_unprepare(gpriv->clkp);
2097         reset_control_assert(gpriv->rstc1);
2098         reset_control_assert(gpriv->rstc2);
2099
2100         return 0;
2101 }
2102
2103 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
2104 {
2105         return 0;
2106 }
2107
2108 static int __maybe_unused rcar_canfd_resume(struct device *dev)
2109 {
2110         return 0;
2111 }
2112
2113 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2114                          rcar_canfd_resume);
2115
2116 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2117         { .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info },
2118         { .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info },
2119         { .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info },
2120         { .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },
2121         { }
2122 };
2123
2124 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2125
2126 static struct platform_driver rcar_canfd_driver = {
2127         .driver = {
2128                 .name = RCANFD_DRV_NAME,
2129                 .of_match_table = of_match_ptr(rcar_canfd_of_table),
2130                 .pm = &rcar_canfd_pm_ops,
2131         },
2132         .probe = rcar_canfd_probe,
2133         .remove = rcar_canfd_remove,
2134 };
2135
2136 module_platform_driver(rcar_canfd_driver);
2137
2138 MODULE_AUTHOR("Ramesh Shanmugasundaram <[email protected]>");
2139 MODULE_LICENSE("GPL");
2140 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2141 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);