drivers/media/platform/nxp/imx7-media-csi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * V4L2 Capture CSI Subdev for Freescale i.MX6UL/L / i.MX7 SOC
   4  *
   5  * Copyright (c) 2019 Linaro Ltd
   6  *
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_graph.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19 #include <linux/slab.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/types.h>
  22
  23 #include <media/v4l2-device.h>
  24 #include <media/v4l2-fwnode.h>
  25 #include <media/v4l2-ioctl.h>
  26 #include <media/v4l2-mc.h>
  27 #include <media/v4l2-subdev.h>
  28 #include <media/videobuf2-dma-contig.h>
  29
  30 #define IMX7_CSI_PAD_SINK               0
  31 #define IMX7_CSI_PAD_SRC                1
  32 #define IMX7_CSI_PADS_NUM               2
  33
  34 /* csi control reg 1 */
  35 #define BIT_SWAP16_EN                   BIT(31)
  36 #define BIT_EXT_VSYNC                   BIT(30)
  37 #define BIT_EOF_INT_EN                  BIT(29)
  38 #define BIT_PRP_IF_EN                   BIT(28)
  39 #define BIT_CCIR_MODE                   BIT(27)
  40 #define BIT_COF_INT_EN                  BIT(26)
  41 #define BIT_SF_OR_INTEN                 BIT(25)
  42 #define BIT_RF_OR_INTEN                 BIT(24)
  43 #define BIT_SFF_DMA_DONE_INTEN          BIT(22)
  44 #define BIT_STATFF_INTEN                BIT(21)
  45 #define BIT_FB2_DMA_DONE_INTEN          BIT(20)
  46 #define BIT_FB1_DMA_DONE_INTEN          BIT(19)
  47 #define BIT_RXFF_INTEN                  BIT(18)
  48 #define BIT_SOF_POL                     BIT(17)
  49 #define BIT_SOF_INTEN                   BIT(16)
  50 #define BIT_MCLKDIV(n)                  ((n) << 12)
  51 #define BIT_MCLKDIV_MASK                (0xf << 12)
  52 #define BIT_HSYNC_POL                   BIT(11)
  53 #define BIT_CCIR_EN                     BIT(10)
  54 #define BIT_MCLKEN                      BIT(9)
  55 #define BIT_FCC                         BIT(8)
  56 #define BIT_PACK_DIR                    BIT(7)
  57 #define BIT_CLR_STATFIFO                BIT(6)
  58 #define BIT_CLR_RXFIFO                  BIT(5)
  59 #define BIT_GCLK_MODE                   BIT(4)
  60 #define BIT_INV_DATA                    BIT(3)
  61 #define BIT_INV_PCLK                    BIT(2)
  62 #define BIT_REDGE                       BIT(1)
  63 #define BIT_PIXEL_BIT                   BIT(0)
  64
  65 /* control reg 2 */
  66 #define BIT_DMA_BURST_TYPE_RFF_INCR4    (1 << 30)
  67 #define BIT_DMA_BURST_TYPE_RFF_INCR8    (2 << 30)
  68 #define BIT_DMA_BURST_TYPE_RFF_INCR16   (3 << 30)
  69 #define BIT_DMA_BURST_TYPE_RFF_MASK     (3 << 30)
  70
  71 /* control reg 3 */
  72 #define BIT_FRMCNT(n)                   ((n) << 16)
  73 #define BIT_FRMCNT_MASK                 (0xffff << 16)
  74 #define BIT_FRMCNT_RST                  BIT(15)
  75 #define BIT_DMA_REFLASH_RFF             BIT(14)
  76 #define BIT_DMA_REFLASH_SFF             BIT(13)
  77 #define BIT_DMA_REQ_EN_RFF              BIT(12)
  78 #define BIT_DMA_REQ_EN_SFF              BIT(11)
  79 #define BIT_STATFF_LEVEL(n)             ((n) << 8)
  80 #define BIT_STATFF_LEVEL_MASK           (0x7 << 8)
  81 #define BIT_HRESP_ERR_EN                BIT(7)
  82 #define BIT_RXFF_LEVEL(n)               ((n) << 4)
  83 #define BIT_RXFF_LEVEL_MASK             (0x7 << 4)
  84 #define BIT_TWO_8BIT_SENSOR             BIT(3)
  85 #define BIT_ZERO_PACK_EN                BIT(2)
  86 #define BIT_ECC_INT_EN                  BIT(1)
  87 #define BIT_ECC_AUTO_EN                 BIT(0)
  88
  89 /* csi status reg */
  90 #define BIT_ADDR_CH_ERR_INT             BIT(28)
  91 #define BIT_FIELD0_INT                  BIT(27)
  92 #define BIT_FIELD1_INT                  BIT(26)
  93 #define BIT_SFF_OR_INT                  BIT(25)
  94 #define BIT_RFF_OR_INT                  BIT(24)
  95 #define BIT_DMA_TSF_DONE_SFF            BIT(22)
  96 #define BIT_STATFF_INT                  BIT(21)
  97 #define BIT_DMA_TSF_DONE_FB2            BIT(20)
  98 #define BIT_DMA_TSF_DONE_FB1            BIT(19)
  99 #define BIT_RXFF_INT                    BIT(18)
 100 #define BIT_EOF_INT                     BIT(17)
 101 #define BIT_SOF_INT                     BIT(16)
 102 #define BIT_F2_INT                      BIT(15)
 103 #define BIT_F1_INT                      BIT(14)
 104 #define BIT_COF_INT                     BIT(13)
 105 #define BIT_HRESP_ERR_INT               BIT(7)
 106 #define BIT_ECC_INT                     BIT(1)
 107 #define BIT_DRDY                        BIT(0)
 108
 109 /* csi image parameter reg */
 110 #define BIT_IMAGE_WIDTH(n)              ((n) << 16)
 111 #define BIT_IMAGE_HEIGHT(n)             (n)
 112
 113 /* csi control reg 18 */
 114 #define BIT_CSI_HW_ENABLE               BIT(31)
 115 #define BIT_MIPI_DATA_FORMAT_RAW8       (0x2a << 25)
 116 #define BIT_MIPI_DATA_FORMAT_RAW10      (0x2b << 25)
 117 #define BIT_MIPI_DATA_FORMAT_RAW12      (0x2c << 25)
 118 #define BIT_MIPI_DATA_FORMAT_RAW14      (0x2d << 25)
 119 #define BIT_MIPI_DATA_FORMAT_YUV422_8B  (0x1e << 25)
 120 #define BIT_MIPI_DATA_FORMAT_MASK       (0x3f << 25)
 121 #define BIT_DATA_FROM_MIPI              BIT(22)
 122 #define BIT_MIPI_YU_SWAP                BIT(21)
 123 #define BIT_MIPI_DOUBLE_CMPNT           BIT(20)
 124 #define BIT_MASK_OPTION_FIRST_FRAME     (0 << 18)
 125 #define BIT_MASK_OPTION_CSI_EN          (1 << 18)
 126 #define BIT_MASK_OPTION_SECOND_FRAME    (2 << 18)
 127 #define BIT_MASK_OPTION_ON_DATA         (3 << 18)
 128 #define BIT_BASEADDR_CHG_ERR_EN         BIT(9)
 129 #define BIT_BASEADDR_SWITCH_SEL         BIT(5)
 130 #define BIT_BASEADDR_SWITCH_EN          BIT(4)
 131 #define BIT_PARALLEL24_EN               BIT(3)
 132 #define BIT_DEINTERLACE_EN              BIT(2)
 133 #define BIT_TVDECODER_IN_EN             BIT(1)
 134 #define BIT_NTSC_EN                     BIT(0)
 135
 136 #define CSI_MCLK_VF                     1
 137 #define CSI_MCLK_ENC                    2
 138 #define CSI_MCLK_RAW                    4
 139 #define CSI_MCLK_I2C                    8
 140
 141 #define CSI_CSICR1                      0x00
 142 #define CSI_CSICR2                      0x04
 143 #define CSI_CSICR3                      0x08
 144 #define CSI_STATFIFO                    0x0c
 145 #define CSI_CSIRXFIFO                   0x10
 146 #define CSI_CSIRXCNT                    0x14
 147 #define CSI_CSISR                       0x18
 148
 149 #define CSI_CSIDBG                      0x1c
 150 #define CSI_CSIDMASA_STATFIFO           0x20
 151 #define CSI_CSIDMATS_STATFIFO           0x24
 152 #define CSI_CSIDMASA_FB1                0x28
 153 #define CSI_CSIDMASA_FB2                0x2c
 154 #define CSI_CSIFBUF_PARA                0x30
 155 #define CSI_CSIIMAG_PARA                0x34
 156
 157 #define CSI_CSICR18                     0x48
 158 #define CSI_CSICR19                     0x4c
 159
 160 #define IMX7_CSI_VIDEO_NAME             "imx-capture"
 161 /* In bytes, per queue */
 162 #define IMX7_CSI_VIDEO_MEM_LIMIT        SZ_512M
 163 #define IMX7_CSI_VIDEO_EOF_TIMEOUT      2000
 164
 165 #define IMX7_CSI_DEF_MBUS_CODE          MEDIA_BUS_FMT_UYVY8_2X8
 166 #define IMX7_CSI_DEF_PIX_FORMAT         V4L2_PIX_FMT_UYVY
 167 #define IMX7_CSI_DEF_PIX_WIDTH          640
 168 #define IMX7_CSI_DEF_PIX_HEIGHT         480
 169
 170 enum imx_csi_model {
 171         IMX7_CSI_IMX7 = 0,
 172         IMX7_CSI_IMX8MQ,
 173 };
 174
 175 struct imx7_csi_pixfmt {
 176         /* the in-memory FourCC pixel format */
 177         u32     fourcc;
 178         /*
 179          * the set of equivalent media bus codes for the fourcc.
 180          * NOTE! codes pointer is NULL for in-memory-only formats.
 181          */
 182         const u32 *codes;
 183         int     bpp;     /* total bpp */
 184         bool    yuv;
 185 };
 186
 187 struct imx7_csi_vb2_buffer {
 188         struct vb2_v4l2_buffer vbuf;
 189         struct list_head list;
 190 };
 191
 192 static inline struct imx7_csi_vb2_buffer *
 193 to_imx7_csi_vb2_buffer(struct vb2_buffer *vb)
 194 {
 195         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 196
 197         return container_of(vbuf, struct imx7_csi_vb2_buffer, vbuf);
 198 }
 199
 200 struct imx7_csi_dma_buf {
 201         void *virt;
 202         dma_addr_t dma_addr;
 203         unsigned long len;
 204 };
 205
 206 struct imx7_csi {
 207         struct device *dev;
 208
 209         /* Resources and locks */
 210         void __iomem *regbase;
 211         int irq;
 212         struct clk *mclk;
 213
 214         spinlock_t irqlock; /* Protects last_eof */
 215
 216         /* Media and V4L2 device */
 217         struct media_device mdev;
 218         struct v4l2_device v4l2_dev;
 219         struct v4l2_async_notifier notifier;
 220         struct media_pipeline pipe;
 221
 222         struct v4l2_subdev *src_sd;
 223         bool is_csi2;
 224
 225         /* V4L2 subdev */
 226         struct v4l2_subdev sd;
 227         struct media_pad pad[IMX7_CSI_PADS_NUM];
 228
 229         /* Video device */
 230         struct video_device *vdev;              /* Video device */
 231         struct media_pad vdev_pad;              /* Video device pad */
 232
 233         struct v4l2_pix_format vdev_fmt;        /* The user format */
 234         const struct imx7_csi_pixfmt *vdev_cc;
 235         struct v4l2_rect vdev_compose;          /* The compose rectangle */
 236
 237         struct mutex vdev_mutex;                /* Protect vdev operations */
 238
 239         struct vb2_queue q;                     /* The videobuf2 queue */
 240         struct list_head ready_q;               /* List of queued buffers */
 241         spinlock_t q_lock;                      /* Protect ready_q */
 242
 243         /* Buffers and streaming state */
 244         struct imx7_csi_vb2_buffer *active_vb2_buf[2];
 245         struct imx7_csi_dma_buf underrun_buf;
 246
 247         bool is_streaming;
 248         int buf_num;
 249         u32 frame_sequence;
 250
 251         bool last_eof;
 252         struct completion last_eof_completion;
 253
 254         enum imx_csi_model model;
 255 };
 256
 257 static struct imx7_csi *
 258 imx7_csi_notifier_to_dev(struct v4l2_async_notifier *n)
 259 {
 260         return container_of(n, struct imx7_csi, notifier);
 261 }
 262
 263 /* -----------------------------------------------------------------------------
 264  * Hardware Configuration
 265  */
 266
 267 static u32 imx7_csi_reg_read(struct imx7_csi *csi, unsigned int offset)
 268 {
 269         return readl(csi->regbase + offset);
 270 }
 271
 272 static void imx7_csi_reg_write(struct imx7_csi *csi, unsigned int value,
 273                                unsigned int offset)
 274 {
 275         writel(value, csi->regbase + offset);
 276 }
 277
 278 static u32 imx7_csi_irq_clear(struct imx7_csi *csi)
 279 {
 280         u32 isr;
 281
 282         isr = imx7_csi_reg_read(csi, CSI_CSISR);
 283         imx7_csi_reg_write(csi, isr, CSI_CSISR);
 284
 285         return isr;
 286 }
 287
 288 static void imx7_csi_init_default(struct imx7_csi *csi)
 289 {
 290         imx7_csi_reg_write(csi, BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE |
 291                            BIT_HSYNC_POL | BIT_FCC | BIT_MCLKDIV(1) |
 292                            BIT_MCLKEN, CSI_CSICR1);
 293         imx7_csi_reg_write(csi, 0, CSI_CSICR2);
 294         imx7_csi_reg_write(csi, BIT_FRMCNT_RST, CSI_CSICR3);
 295
 296         imx7_csi_reg_write(csi, BIT_IMAGE_WIDTH(IMX7_CSI_DEF_PIX_WIDTH) |
 297                            BIT_IMAGE_HEIGHT(IMX7_CSI_DEF_PIX_HEIGHT),
 298                            CSI_CSIIMAG_PARA);
 299
 300         imx7_csi_reg_write(csi, BIT_DMA_REFLASH_RFF, CSI_CSICR3);
 301 }
 302
 303 static void imx7_csi_hw_enable_irq(struct imx7_csi *csi)
 304 {
 305         u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
 306
 307         cr1 |= BIT_RFF_OR_INT;
 308         cr1 |= BIT_FB1_DMA_DONE_INTEN;
 309         cr1 |= BIT_FB2_DMA_DONE_INTEN;
 310
 311         imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
 312 }
 313
 314 static void imx7_csi_hw_disable_irq(struct imx7_csi *csi)
 315 {
 316         u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
 317
 318         cr1 &= ~BIT_RFF_OR_INT;
 319         cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
 320         cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
 321
 322         imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
 323 }
 324
 325 static void imx7_csi_hw_enable(struct imx7_csi *csi)
 326 {
 327         u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
 328
 329         cr |= BIT_CSI_HW_ENABLE;
 330
 331         imx7_csi_reg_write(csi, cr, CSI_CSICR18);
 332 }
 333
 334 static void imx7_csi_hw_disable(struct imx7_csi *csi)
 335 {
 336         u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
 337
 338         cr &= ~BIT_CSI_HW_ENABLE;
 339
 340         imx7_csi_reg_write(csi, cr, CSI_CSICR18);
 341 }
 342
 343 static void imx7_csi_dma_reflash(struct imx7_csi *csi)
 344 {
 345         u32 cr3;
 346
 347         cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
 348         cr3 |= BIT_DMA_REFLASH_RFF;
 349         imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
 350 }
 351
 352 static void imx7_csi_rx_fifo_clear(struct imx7_csi *csi)
 353 {
 354         u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1) & ~BIT_FCC;
 355
 356         imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
 357         imx7_csi_reg_write(csi, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);
 358         imx7_csi_reg_write(csi, cr1 | BIT_FCC, CSI_CSICR1);
 359 }
 360
 361 static void imx7_csi_dmareq_rff_enable(struct imx7_csi *csi)
 362 {
 363         u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
 364
 365         cr3 |= BIT_DMA_REQ_EN_RFF;
 366         cr3 |= BIT_HRESP_ERR_EN;
 367         cr3 &= ~BIT_RXFF_LEVEL_MASK;
 368         cr3 |= BIT_RXFF_LEVEL(2);
 369
 370         imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
 371 }
 372
 373 static void imx7_csi_dmareq_rff_disable(struct imx7_csi *csi)
 374 {
 375         u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
 376
 377         cr3 &= ~BIT_DMA_REQ_EN_RFF;
 378         cr3 &= ~BIT_HRESP_ERR_EN;
 379         imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
 380 }
 381
 382 static void imx7_csi_update_buf(struct imx7_csi *csi, dma_addr_t dma_addr,
 383                                 int buf_num)
 384 {
 385         if (buf_num == 1)
 386                 imx7_csi_reg_write(csi, dma_addr, CSI_CSIDMASA_FB2);
 387         else
 388                 imx7_csi_reg_write(csi, dma_addr, CSI_CSIDMASA_FB1);
 389 }
 390
 391 static struct imx7_csi_vb2_buffer *imx7_csi_video_next_buf(struct imx7_csi *csi);
 392
 393 static void imx7_csi_setup_vb2_buf(struct imx7_csi *csi)
 394 {
 395         struct imx7_csi_vb2_buffer *buf;
 396         struct vb2_buffer *vb2_buf;
 397         int i;
 398
 399         for (i = 0; i < 2; i++) {
 400                 dma_addr_t dma_addr;
 401
 402                 buf = imx7_csi_video_next_buf(csi);
 403                 if (buf) {
 404                         csi->active_vb2_buf[i] = buf;
 405                         vb2_buf = &buf->vbuf.vb2_buf;
 406                         dma_addr = vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
 407                 } else {
 408                         csi->active_vb2_buf[i] = NULL;
 409                         dma_addr = csi->underrun_buf.dma_addr;
 410                 }
 411
 412                 imx7_csi_update_buf(csi, dma_addr, i);
 413         }
 414 }
 415
 416 static void imx7_csi_dma_unsetup_vb2_buf(struct imx7_csi *csi,
 417                                          enum vb2_buffer_state return_status)
 418 {
 419         struct imx7_csi_vb2_buffer *buf;
 420         int i;
 421
 422         /* return any remaining active frames with return_status */
 423         for (i = 0; i < 2; i++) {
 424                 buf = csi->active_vb2_buf[i];
 425                 if (buf) {
 426                         struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
 427
 428                         vb->timestamp = ktime_get_ns();
 429                         vb2_buffer_done(vb, return_status);
 430                         csi->active_vb2_buf[i] = NULL;
 431                 }
 432         }
 433 }
 434
 435 static void imx7_csi_free_dma_buf(struct imx7_csi *csi,
 436                                   struct imx7_csi_dma_buf *buf)
 437 {
 438         if (buf->virt)
 439                 dma_free_coherent(csi->dev, buf->len, buf->virt, buf->dma_addr);
 440
 441         buf->virt = NULL;
 442         buf->dma_addr = 0;
 443 }
 444
 445 static int imx7_csi_alloc_dma_buf(struct imx7_csi *csi,
 446                                   struct imx7_csi_dma_buf *buf, int size)
 447 {
 448         imx7_csi_free_dma_buf(csi, buf);
 449
 450         buf->len = PAGE_ALIGN(size);
 451         buf->virt = dma_alloc_coherent(csi->dev, buf->len, &buf->dma_addr,
 452                                        GFP_DMA | GFP_KERNEL);
 453         if (!buf->virt)
 454                 return -ENOMEM;
 455
 456         return 0;
 457 }
 458
 459 static int imx7_csi_dma_setup(struct imx7_csi *csi)
 460 {
 461         int ret;
 462
 463         ret = imx7_csi_alloc_dma_buf(csi, &csi->underrun_buf,
 464                                      csi->vdev_fmt.sizeimage);
 465         if (ret < 0) {
 466                 v4l2_warn(&csi->sd, "consider increasing the CMA area\n");
 467                 return ret;
 468         }
 469
 470         csi->frame_sequence = 0;
 471         csi->last_eof = false;
 472         init_completion(&csi->last_eof_completion);
 473
 474         imx7_csi_setup_vb2_buf(csi);
 475
 476         return 0;
 477 }
 478
 479 static void imx7_csi_dma_cleanup(struct imx7_csi *csi,
 480                                  enum vb2_buffer_state return_status)
 481 {
 482         imx7_csi_dma_unsetup_vb2_buf(csi, return_status);
 483         imx7_csi_free_dma_buf(csi, &csi->underrun_buf);
 484 }
 485
 486 static void imx7_csi_dma_stop(struct imx7_csi *csi)
 487 {
 488         unsigned long timeout_jiffies;
 489         unsigned long flags;
 490         int ret;
 491
 492         /* mark next EOF interrupt as the last before stream off */
 493         spin_lock_irqsave(&csi->irqlock, flags);
 494         csi->last_eof = true;
 495         spin_unlock_irqrestore(&csi->irqlock, flags);
 496
 497         /*
 498          * and then wait for interrupt handler to mark completion.
 499          */
 500         timeout_jiffies = msecs_to_jiffies(IMX7_CSI_VIDEO_EOF_TIMEOUT);
 501         ret = wait_for_completion_timeout(&csi->last_eof_completion,
 502                                           timeout_jiffies);
 503         if (ret == 0)
 504                 v4l2_warn(&csi->sd, "wait last EOF timeout\n");
 505
 506         imx7_csi_hw_disable_irq(csi);
 507 }
 508
 509 static void imx7_csi_configure(struct imx7_csi *csi,
 510                                struct v4l2_subdev_state *sd_state)
 511 {
 512         struct v4l2_pix_format *out_pix = &csi->vdev_fmt;
 513         int width = out_pix->width;
 514         u32 stride = 0;
 515         u32 cr3 = BIT_FRMCNT_RST;
 516         u32 cr1, cr18;
 517
 518         cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
 519
 520         cr18 &= ~(BIT_CSI_HW_ENABLE | BIT_MIPI_DATA_FORMAT_MASK |
 521                   BIT_DATA_FROM_MIPI | BIT_MIPI_DOUBLE_CMPNT |
 522                   BIT_BASEADDR_CHG_ERR_EN | BIT_BASEADDR_SWITCH_SEL |
 523                   BIT_BASEADDR_SWITCH_EN | BIT_DEINTERLACE_EN);
 524
 525         if (out_pix->field == V4L2_FIELD_INTERLACED) {
 526                 cr18 |= BIT_DEINTERLACE_EN;
 527                 stride = out_pix->width;
 528         }
 529
 530         if (!csi->is_csi2) {
 531                 cr1 = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL
 532                     | BIT_FCC | BIT_MCLKDIV(1) | BIT_MCLKEN;
 533
 534                 cr18 |= BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
 535                         BIT_BASEADDR_CHG_ERR_EN;
 536
 537                 if (out_pix->pixelformat == V4L2_PIX_FMT_UYVY ||
 538                     out_pix->pixelformat == V4L2_PIX_FMT_YUYV)
 539                         width *= 2;
 540         } else {
 541                 const struct v4l2_mbus_framefmt *sink_fmt;
 542
 543                 sink_fmt = v4l2_subdev_get_pad_format(&csi->sd, sd_state,
 544                                                       IMX7_CSI_PAD_SINK);
 545
 546                 cr1 = BIT_SOF_POL | BIT_REDGE | BIT_HSYNC_POL | BIT_FCC
 547                     | BIT_MCLKDIV(1) | BIT_MCLKEN;
 548
 549                 cr18 |= BIT_DATA_FROM_MIPI;
 550
 551                 switch (sink_fmt->code) {
 552                 case MEDIA_BUS_FMT_Y8_1X8:
 553                 case MEDIA_BUS_FMT_SBGGR8_1X8:
 554                 case MEDIA_BUS_FMT_SGBRG8_1X8:
 555                 case MEDIA_BUS_FMT_SGRBG8_1X8:
 556                 case MEDIA_BUS_FMT_SRGGB8_1X8:
 557                         cr18 |= BIT_MIPI_DATA_FORMAT_RAW8;
 558                         break;
 559                 case MEDIA_BUS_FMT_Y10_1X10:
 560                 case MEDIA_BUS_FMT_SBGGR10_1X10:
 561                 case MEDIA_BUS_FMT_SGBRG10_1X10:
 562                 case MEDIA_BUS_FMT_SGRBG10_1X10:
 563                 case MEDIA_BUS_FMT_SRGGB10_1X10:
 564                         cr3 |= BIT_TWO_8BIT_SENSOR;
 565                         cr18 |= BIT_MIPI_DATA_FORMAT_RAW10;
 566                         break;
 567                 case MEDIA_BUS_FMT_Y12_1X12:
 568                 case MEDIA_BUS_FMT_SBGGR12_1X12:
 569                 case MEDIA_BUS_FMT_SGBRG12_1X12:
 570                 case MEDIA_BUS_FMT_SGRBG12_1X12:
 571                 case MEDIA_BUS_FMT_SRGGB12_1X12:
 572                         cr3 |= BIT_TWO_8BIT_SENSOR;
 573                         cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
 574                         break;
 575                 case MEDIA_BUS_FMT_Y14_1X14:
 576                 case MEDIA_BUS_FMT_SBGGR14_1X14:
 577                 case MEDIA_BUS_FMT_SGBRG14_1X14:
 578                 case MEDIA_BUS_FMT_SGRBG14_1X14:
 579                 case MEDIA_BUS_FMT_SRGGB14_1X14:
 580                         cr3 |= BIT_TWO_8BIT_SENSOR;
 581                         cr18 |= BIT_MIPI_DATA_FORMAT_RAW14;
 582                         break;
 583
 584                 /*
 585                  * The CSI bridge has a 16-bit input bus. Depending on the
 586                  * connected source, data may be transmitted with 8 or 10 bits
 587                  * per clock sample (in bits [9:2] or [9:0] respectively) or
 588                  * with 16 bits per clock sample (in bits [15:0]). The data is
 589                  * then packed into a 32-bit FIFO (as shown in figure 13-11 of
 590                  * the i.MX8MM reference manual rev. 3).
 591                  *
 592                  * The data packing in a 32-bit FIFO input word is controlled by
 593                  * the CR3 TWO_8BIT_SENSOR field (also known as SENSOR_16BITS in
 594                  * the i.MX8MM reference manual). When set to 0, data packing
 595                  * groups four 8-bit input samples (bits [9:2]). When set to 1,
 596                  * data packing groups two 16-bit input samples (bits [15:0]).
 597                  *
 598                  * The register field CR18 MIPI_DOUBLE_CMPNT also needs to be
 599                  * configured according to the input format for YUV 4:2:2 data.
 600                  * The field controls the gasket between the CSI-2 receiver and
 601                  * the CSI bridge. On i.MX7 and i.MX8MM, the field must be set
 602                  * to 1 when the CSIS outputs 16-bit samples. On i.MX8MQ, the
 603                  * gasket ignores the MIPI_DOUBLE_CMPNT bit and YUV 4:2:2 always
 604                  * uses 16-bit samples. Setting MIPI_DOUBLE_CMPNT in that case
 605                  * has no effect, but doesn't cause any issue.
 606                  */
 607                 case MEDIA_BUS_FMT_UYVY8_2X8:
 608                 case MEDIA_BUS_FMT_YUYV8_2X8:
 609                         cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;
 610                         break;
 611                 case MEDIA_BUS_FMT_UYVY8_1X16:
 612                 case MEDIA_BUS_FMT_YUYV8_1X16:
 613                         cr3 |= BIT_TWO_8BIT_SENSOR;
 614                         cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B |
 615                                 BIT_MIPI_DOUBLE_CMPNT;
 616                         break;
 617                 }
 618         }
 619
 620         imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
 621         imx7_csi_reg_write(csi, BIT_DMA_BURST_TYPE_RFF_INCR16, CSI_CSICR2);
 622         imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
 623         imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
 624
 625         imx7_csi_reg_write(csi, (width * out_pix->height) >> 2, CSI_CSIRXCNT);
 626         imx7_csi_reg_write(csi, BIT_IMAGE_WIDTH(width) |
 627                            BIT_IMAGE_HEIGHT(out_pix->height),
 628                            CSI_CSIIMAG_PARA);
 629         imx7_csi_reg_write(csi, stride, CSI_CSIFBUF_PARA);
 630 }
 631
 632 static int imx7_csi_init(struct imx7_csi *csi,
 633                          struct v4l2_subdev_state *sd_state)
 634 {
 635         int ret;
 636
 637         ret = clk_prepare_enable(csi->mclk);
 638         if (ret < 0)
 639                 return ret;
 640
 641         imx7_csi_configure(csi, sd_state);
 642
 643         ret = imx7_csi_dma_setup(csi);
 644         if (ret < 0) {
 645                 clk_disable_unprepare(csi->mclk);
 646                 return ret;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static void imx7_csi_deinit(struct imx7_csi *csi,
 653                             enum vb2_buffer_state return_status)
 654 {
 655         imx7_csi_dma_cleanup(csi, return_status);
 656         imx7_csi_init_default(csi);
 657         imx7_csi_dmareq_rff_disable(csi);
 658         clk_disable_unprepare(csi->mclk);
 659 }
 660
 661 static void imx7_csi_baseaddr_switch_on_second_frame(struct imx7_csi *csi)
 662 {
 663         u32 cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
 664
 665         cr18 |= BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
 666                 BIT_BASEADDR_CHG_ERR_EN;
 667         cr18 |= BIT_MASK_OPTION_SECOND_FRAME;
 668         imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
 669 }
 670
 671 static void imx7_csi_enable(struct imx7_csi *csi)
 672 {
 673         /* Clear the Rx FIFO and reflash the DMA controller. */
 674         imx7_csi_rx_fifo_clear(csi);
 675         imx7_csi_dma_reflash(csi);
 676
 677         usleep_range(2000, 3000);
 678
 679         /* Clear and enable the interrupts. */
 680         imx7_csi_irq_clear(csi);
 681         imx7_csi_hw_enable_irq(csi);
 682
 683         /* Enable the RxFIFO DMA and the CSI. */
 684         imx7_csi_dmareq_rff_enable(csi);
 685         imx7_csi_hw_enable(csi);
 686
 687         if (csi->model == IMX7_CSI_IMX8MQ)
 688                 imx7_csi_baseaddr_switch_on_second_frame(csi);
 689 }
 690
 691 static void imx7_csi_disable(struct imx7_csi *csi)
 692 {
 693         imx7_csi_dma_stop(csi);
 694
 695         imx7_csi_dmareq_rff_disable(csi);
 696
 697         imx7_csi_hw_disable_irq(csi);
 698
 699         imx7_csi_hw_disable(csi);
 700 }
 701
 702 /* -----------------------------------------------------------------------------
 703  * Interrupt Handling
 704  */
 705
 706 static void imx7_csi_error_recovery(struct imx7_csi *csi)
 707 {
 708         imx7_csi_hw_disable(csi);
 709
 710         imx7_csi_rx_fifo_clear(csi);
 711
 712         imx7_csi_dma_reflash(csi);
 713
 714         imx7_csi_hw_enable(csi);
 715 }
 716
 717 static void imx7_csi_vb2_buf_done(struct imx7_csi *csi)
 718 {
 719         struct imx7_csi_vb2_buffer *done, *next;
 720         struct vb2_buffer *vb;
 721         dma_addr_t dma_addr;
 722
 723         done = csi->active_vb2_buf[csi->buf_num];
 724         if (done) {
 725                 done->vbuf.field = csi->vdev_fmt.field;
 726                 done->vbuf.sequence = csi->frame_sequence;
 727                 vb = &done->vbuf.vb2_buf;
 728                 vb->timestamp = ktime_get_ns();
 729                 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
 730         }
 731         csi->frame_sequence++;
 732
 733         /* get next queued buffer */
 734         next = imx7_csi_video_next_buf(csi);
 735         if (next) {
 736                 dma_addr = vb2_dma_contig_plane_dma_addr(&next->vbuf.vb2_buf, 0);
 737                 csi->active_vb2_buf[csi->buf_num] = next;
 738         } else {
 739                 dma_addr = csi->underrun_buf.dma_addr;
 740                 csi->active_vb2_buf[csi->buf_num] = NULL;
 741         }
 742
 743         imx7_csi_update_buf(csi, dma_addr, csi->buf_num);
 744 }
 745
 746 static irqreturn_t imx7_csi_irq_handler(int irq, void *data)
 747 {
 748         struct imx7_csi *csi =  data;
 749         u32 status;
 750
 751         spin_lock(&csi->irqlock);
 752
 753         status = imx7_csi_irq_clear(csi);
 754
 755         if (status & BIT_RFF_OR_INT) {
 756                 dev_warn(csi->dev, "Rx fifo overflow\n");
 757                 imx7_csi_error_recovery(csi);
 758         }
 759
 760         if (status & BIT_HRESP_ERR_INT) {
 761                 dev_warn(csi->dev, "Hresponse error detected\n");
 762                 imx7_csi_error_recovery(csi);
 763         }
 764
 765         if (status & BIT_ADDR_CH_ERR_INT) {
 766                 imx7_csi_hw_disable(csi);
 767
 768                 imx7_csi_dma_reflash(csi);
 769
 770                 imx7_csi_hw_enable(csi);
 771         }
 772
 773         if ((status & BIT_DMA_TSF_DONE_FB1) &&
 774             (status & BIT_DMA_TSF_DONE_FB2)) {
 775                 /*
 776                  * For both FB1 and FB2 interrupter bits set case,
 777                  * CSI DMA is work in one of FB1 and FB2 buffer,
 778                  * but software can not know the state.
 779                  * Skip it to avoid base address updated
 780                  * when csi work in field0 and field1 will write to
 781                  * new base address.
 782                  */
 783         } else if (status & BIT_DMA_TSF_DONE_FB1) {
 784                 csi->buf_num = 0;
 785         } else if (status & BIT_DMA_TSF_DONE_FB2) {
 786                 csi->buf_num = 1;
 787         }
 788
 789         if ((status & BIT_DMA_TSF_DONE_FB1) ||
 790             (status & BIT_DMA_TSF_DONE_FB2)) {
 791                 imx7_csi_vb2_buf_done(csi);
 792
 793                 if (csi->last_eof) {
 794                         complete(&csi->last_eof_completion);
 795                         csi->last_eof = false;
 796                 }
 797         }
 798
 799         spin_unlock(&csi->irqlock);
 800
 801         return IRQ_HANDLED;
 802 }
 803
 804 /* -----------------------------------------------------------------------------
 805  * Format Helpers
 806  */
 807
 808 #define IMX_BUS_FMTS(fmt...) (const u32[]) {fmt, 0}
 809
 810 /*
 811  * List of supported pixel formats for the subdevs. Keep V4L2_PIX_FMT_UYVY and
 812  * MEDIA_BUS_FMT_UYVY8_2X8 first to match IMX7_CSI_DEF_PIX_FORMAT and
 813  * IMX7_CSI_DEF_MBUS_CODE.
 814  *
 815  * TODO: Restrict the supported formats list based on the SoC integration.
 816  *
 817  * The CSI bridge can be configured to sample pixel components from the Rx queue
 818  * in single (8bpp) or double (16bpp) component modes. Image format variants
 819  * with different sample sizes (ie YUYV_2X8 vs YUYV_1X16) determine the pixel
 820  * components sampling size per each clock cycle and their packing mode (see
 821  * imx7_csi_configure() for details).
 822  *
 823  * As the CSI bridge can be interfaced with different IP blocks depending on the
 824  * SoC model it is integrated on, the Rx queue sampling size should match the
 825  * size of the samples transferred by the transmitting IP block. To avoid
 826  * misconfigurations of the capture pipeline, the enumeration of the supported
 827  * formats should be restricted to match the pixel source transmitting mode.
 828  *
 829  * Example: i.MX8MM SoC integrates the CSI bridge with the Samsung CSIS CSI-2
 830  * receiver which operates in dual pixel sampling mode. The CSI bridge should
 831  * only expose the 1X16 formats variant which instructs it to operate in dual
 832  * pixel sampling mode. When the CSI bridge is instead integrated on an i.MX7,
 833  * which supports both serial and parallel input, it should expose both
 834  * variants.
 835  *
 836  * This currently only applies to YUYV formats, but other formats might need to
 837  * be handled in the same way.
 838  */
 839 static const struct imx7_csi_pixfmt pixel_formats[] = {
 840         /*** YUV formats start here ***/
 841         {
 842                 .fourcc = V4L2_PIX_FMT_UYVY,
 843                 .codes  = IMX_BUS_FMTS(
 844                         MEDIA_BUS_FMT_UYVY8_2X8,
 845                         MEDIA_BUS_FMT_UYVY8_1X16
 846                 ),
 847                 .yuv    = true,
 848                 .bpp    = 16,
 849         }, {
 850                 .fourcc = V4L2_PIX_FMT_YUYV,
 851                 .codes  = IMX_BUS_FMTS(
 852                         MEDIA_BUS_FMT_YUYV8_2X8,
 853                         MEDIA_BUS_FMT_YUYV8_1X16
 854                 ),
 855                 .yuv    = true,
 856                 .bpp    = 16,
 857         },
 858         /*** raw bayer and grayscale formats start here ***/
 859         {
 860                 .fourcc = V4L2_PIX_FMT_SBGGR8,
 861                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SBGGR8_1X8),
 862                 .bpp    = 8,
 863         }, {
 864                 .fourcc = V4L2_PIX_FMT_SGBRG8,
 865                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGBRG8_1X8),
 866                 .bpp    = 8,
 867         }, {
 868                 .fourcc = V4L2_PIX_FMT_SGRBG8,
 869                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGRBG8_1X8),
 870                 .bpp    = 8,
 871         }, {
 872                 .fourcc = V4L2_PIX_FMT_SRGGB8,
 873                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SRGGB8_1X8),
 874                 .bpp    = 8,
 875         }, {
 876                 .fourcc = V4L2_PIX_FMT_SBGGR10,
 877                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SBGGR10_1X10),
 878                 .bpp    = 16,
 879         }, {
 880                 .fourcc = V4L2_PIX_FMT_SGBRG10,
 881                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGBRG10_1X10),
 882                 .bpp    = 16,
 883         }, {
 884                 .fourcc = V4L2_PIX_FMT_SGRBG10,
 885                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGRBG10_1X10),
 886                 .bpp    = 16,
 887         }, {
 888                 .fourcc = V4L2_PIX_FMT_SRGGB10,
 889                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SRGGB10_1X10),
 890                 .bpp    = 16,
 891         }, {
 892                 .fourcc = V4L2_PIX_FMT_SBGGR12,
 893                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SBGGR12_1X12),
 894                 .bpp    = 16,
 895         }, {
 896                 .fourcc = V4L2_PIX_FMT_SGBRG12,
 897                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGBRG12_1X12),
 898                 .bpp    = 16,
 899         }, {
 900                 .fourcc = V4L2_PIX_FMT_SGRBG12,
 901                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGRBG12_1X12),
 902                 .bpp    = 16,
 903         }, {
 904                 .fourcc = V4L2_PIX_FMT_SRGGB12,
 905                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SRGGB12_1X12),
 906                 .bpp    = 16,
 907         }, {
 908                 .fourcc = V4L2_PIX_FMT_SBGGR14,
 909                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SBGGR14_1X14),
 910                 .bpp    = 16,
 911         }, {
 912                 .fourcc = V4L2_PIX_FMT_SGBRG14,
 913                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGBRG14_1X14),
 914                 .bpp    = 16,
 915         }, {
 916                 .fourcc = V4L2_PIX_FMT_SGRBG14,
 917                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SGRBG14_1X14),
 918                 .bpp    = 16,
 919         }, {
 920                 .fourcc = V4L2_PIX_FMT_SRGGB14,
 921                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_SRGGB14_1X14),
 922                 .bpp    = 16,
 923         }, {
 924                 .fourcc = V4L2_PIX_FMT_GREY,
 925                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_Y8_1X8),
 926                 .bpp    = 8,
 927         }, {
 928                 .fourcc = V4L2_PIX_FMT_Y10,
 929                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_Y10_1X10),
 930                 .bpp    = 16,
 931         }, {
 932                 .fourcc = V4L2_PIX_FMT_Y12,
 933                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_Y12_1X12),
 934                 .bpp    = 16,
 935         }, {
 936                 .fourcc = V4L2_PIX_FMT_Y14,
 937                 .codes  = IMX_BUS_FMTS(MEDIA_BUS_FMT_Y14_1X14),
 938                 .bpp    = 16,
 939         },
 940 };
 941
 942 /*
 943  * Search in the pixel_formats[] array for an entry with the given fourcc
 944  * return it.
 945  */
 946 static const struct imx7_csi_pixfmt *imx7_csi_find_pixel_format(u32 fourcc)
 947 {
 948         unsigned int i;
 949
 950         for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
 951                 const struct imx7_csi_pixfmt *fmt = &pixel_formats[i];
 952
 953                 if (fmt->fourcc == fourcc)
 954                         return fmt;
 955         }
 956
 957         return NULL;
 958 }
 959
 960 /*
 961  * Search in the pixel_formats[] array for an entry with the given media
 962  * bus code and return it.
 963  */
 964 static const struct imx7_csi_pixfmt *imx7_csi_find_mbus_format(u32 code)
 965 {
 966         unsigned int i;
 967
 968         for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
 969                 const struct imx7_csi_pixfmt *fmt = &pixel_formats[i];
 970                 unsigned int j;
 971
 972                 if (!fmt->codes)
 973                         continue;
 974
 975                 for (j = 0; fmt->codes[j]; j++) {
 976                         if (code == fmt->codes[j])
 977                                 return fmt;
 978                 }
 979         }
 980
 981         return NULL;
 982 }
 983
 984 /*
 985  * Enumerate entries in the pixel_formats[] array that match the
 986  * requested search criteria. Return the media-bus code that matches
 987  * the search criteria at the requested match index.
 988  *
 989  * @code: The returned media-bus code that matches the search criteria at
 990  *        the requested match index.
 991  * @index: The requested match index.
 992  */
 993 static int imx7_csi_enum_mbus_formats(u32 *code, u32 index)
 994 {
 995         unsigned int i;
 996
 997         for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
 998                 const struct imx7_csi_pixfmt *fmt = &pixel_formats[i];
 999                 unsigned int j;
1000
1001                 if (!fmt->codes)
1002                         continue;
1003
1004                 for (j = 0; fmt->codes[j]; j++) {
1005                         if (index == 0) {
1006                                 *code = fmt->codes[j];
1007                                 return 0;
1008                         }
1009
1010                         index--;
1011                 }
1012         }
1013
1014         return -EINVAL;
1015 }
1016
1017 static int imx7_csi_mbus_fmt_to_pix_fmt(struct v4l2_pix_format *pix,
1018                                         const struct v4l2_mbus_framefmt *mbus,
1019                                         const struct imx7_csi_pixfmt *cc)
1020 {
1021         u32 width;
1022         u32 stride;
1023
1024         if (!cc) {
1025                 cc = imx7_csi_find_mbus_format(mbus->code);
1026                 if (!cc)
1027                         return -EINVAL;
1028         }
1029
1030         /* Round up width for minimum burst size */
1031         width = round_up(mbus->width, 8);
1032
1033         /* Round up stride for IDMAC line start address alignment */
1034         stride = round_up((width * cc->bpp) >> 3, 8);
1035
1036         pix->width = width;
1037         pix->height = mbus->height;
1038         pix->pixelformat = cc->fourcc;
1039         pix->colorspace = mbus->colorspace;
1040         pix->xfer_func = mbus->xfer_func;
1041         pix->ycbcr_enc = mbus->ycbcr_enc;
1042         pix->quantization = mbus->quantization;
1043         pix->field = mbus->field;
1044         pix->bytesperline = stride;
1045         pix->sizeimage = stride * pix->height;
1046
1047         return 0;
1048 }
1049
1050 /* -----------------------------------------------------------------------------
1051  * Video Capture Device - IOCTLs
1052  */
1053
1054 static int imx7_csi_video_querycap(struct file *file, void *fh,
1055                                    struct v4l2_capability *cap)
1056 {
1057         struct imx7_csi *csi = video_drvdata(file);
1058
1059         strscpy(cap->driver, IMX7_CSI_VIDEO_NAME, sizeof(cap->driver));
1060         strscpy(cap->card, IMX7_CSI_VIDEO_NAME, sizeof(cap->card));
1061         snprintf(cap->bus_info, sizeof(cap->bus_info),
1062                  "platform:%s", dev_name(csi->dev));
1063
1064         return 0;
1065 }
1066
1067 static int imx7_csi_video_enum_fmt_vid_cap(struct file *file, void *fh,
1068                                            struct v4l2_fmtdesc *f)
1069 {
1070         unsigned int index = f->index;
1071         unsigned int i;
1072
1073         for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
1074                 const struct imx7_csi_pixfmt *fmt = &pixel_formats[i];
1075
1076                 /*
1077                  * If a media bus code is specified, only consider formats that
1078                  * match it.
1079                  */
1080                 if (f->mbus_code) {
1081                         unsigned int j;
1082
1083                         if (!fmt->codes)
1084                                 continue;
1085
1086                         for (j = 0; fmt->codes[j]; j++) {
1087                                 if (f->mbus_code == fmt->codes[j])
1088                                         break;
1089                         }
1090
1091                         if (!fmt->codes[j])
1092                                 continue;
1093                 }
1094
1095                 if (index == 0) {
1096                         f->pixelformat = fmt->fourcc;
1097                         return 0;
1098                 }
1099
1100                 index--;
1101         }
1102
1103         return -EINVAL;
1104 }
1105
1106 static int imx7_csi_video_enum_framesizes(struct file *file, void *fh,
1107                                           struct v4l2_frmsizeenum *fsize)
1108 {
1109         const struct imx7_csi_pixfmt *cc;
1110
1111         if (fsize->index > 0)
1112                 return -EINVAL;
1113
1114         cc = imx7_csi_find_pixel_format(fsize->pixel_format);
1115         if (!cc)
1116                 return -EINVAL;
1117
1118         /*
1119          * TODO: The constraints are hardware-specific and may depend on the
1120          * pixel format. This should come from the driver using
1121          * imx_media_capture.
1122          */
1123         fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1124         fsize->stepwise.min_width = 1;
1125         fsize->stepwise.max_width = 65535;
1126         fsize->stepwise.min_height = 1;
1127         fsize->stepwise.max_height = 65535;
1128         fsize->stepwise.step_width = 1;
1129         fsize->stepwise.step_height = 1;
1130
1131         return 0;
1132 }
1133
1134 static int imx7_csi_video_g_fmt_vid_cap(struct file *file, void *fh,
1135                                         struct v4l2_format *f)
1136 {
1137         struct imx7_csi *csi = video_drvdata(file);
1138
1139         f->fmt.pix = csi->vdev_fmt;
1140
1141         return 0;
1142 }
1143
1144 static const struct imx7_csi_pixfmt *
1145 __imx7_csi_video_try_fmt(struct v4l2_pix_format *pixfmt,
1146                          struct v4l2_rect *compose)
1147 {
1148         struct v4l2_mbus_framefmt fmt_src;
1149         const struct imx7_csi_pixfmt *cc;
1150
1151         /*
1152          * Find the pixel format, default to the first supported format if not
1153          * found.
1154          */
1155         cc = imx7_csi_find_pixel_format(pixfmt->pixelformat);
1156         if (!cc) {
1157                 pixfmt->pixelformat = IMX7_CSI_DEF_PIX_FORMAT;
1158                 cc = imx7_csi_find_pixel_format(pixfmt->pixelformat);
1159         }
1160
1161         /* Allow IDMAC interweave but enforce field order from source. */
1162         if (V4L2_FIELD_IS_INTERLACED(pixfmt->field)) {
1163                 switch (pixfmt->field) {
1164                 case V4L2_FIELD_SEQ_TB:
1165                         pixfmt->field = V4L2_FIELD_INTERLACED_TB;
1166                         break;
1167                 case V4L2_FIELD_SEQ_BT:
1168                         pixfmt->field = V4L2_FIELD_INTERLACED_BT;
1169                         break;
1170                 default:
1171                         break;
1172                 }
1173         }
1174
1175         v4l2_fill_mbus_format(&fmt_src, pixfmt, 0);
1176         imx7_csi_mbus_fmt_to_pix_fmt(pixfmt, &fmt_src, cc);
1177
1178         if (compose) {
1179                 compose->width = fmt_src.width;
1180                 compose->height = fmt_src.height;
1181         }
1182
1183         return cc;
1184 }
1185
1186 static int imx7_csi_video_try_fmt_vid_cap(struct file *file, void *fh,
1187                                           struct v4l2_format *f)
1188 {
1189         __imx7_csi_video_try_fmt(&f->fmt.pix, NULL);
1190         return 0;
1191 }
1192
1193 static int imx7_csi_video_s_fmt_vid_cap(struct file *file, void *fh,
1194                                         struct v4l2_format *f)
1195 {
1196         struct imx7_csi *csi = video_drvdata(file);
1197         const struct imx7_csi_pixfmt *cc;
1198
1199         if (vb2_is_busy(&csi->q)) {
1200                 dev_err(csi->dev, "%s queue busy\n", __func__);
1201                 return -EBUSY;
1202         }
1203
1204         cc = __imx7_csi_video_try_fmt(&f->fmt.pix, &csi->vdev_compose);
1205
1206         csi->vdev_cc = cc;
1207         csi->vdev_fmt = f->fmt.pix;
1208
1209         return 0;
1210 }
1211
1212 static int imx7_csi_video_g_selection(struct file *file, void *fh,
1213                                       struct v4l2_selection *s)
1214 {
1215         struct imx7_csi *csi = video_drvdata(file);
1216
1217         if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1218                 return -EINVAL;
1219
1220         switch (s->target) {
1221         case V4L2_SEL_TGT_COMPOSE:
1222         case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1223         case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1224                 /* The compose rectangle is fixed to the source format. */
1225                 s->r = csi->vdev_compose;
1226                 break;
1227         case V4L2_SEL_TGT_COMPOSE_PADDED:
1228                 /*
1229                  * The hardware writes with a configurable but fixed DMA burst
1230                  * size. If the source format width is not burst size aligned,
1231                  * the written frame contains padding to the right.
1232                  */
1233                 s->r.left = 0;
1234                 s->r.top = 0;
1235                 s->r.width = csi->vdev_fmt.width;
1236                 s->r.height = csi->vdev_fmt.height;
1237                 break;
1238         default:
1239                 return -EINVAL;
1240         }
1241
1242         return 0;
1243 }
1244
1245 static const struct v4l2_ioctl_ops imx7_csi_video_ioctl_ops = {
1246         .vidioc_querycap                = imx7_csi_video_querycap,
1247
1248         .vidioc_enum_fmt_vid_cap        = imx7_csi_video_enum_fmt_vid_cap,
1249         .vidioc_enum_framesizes         = imx7_csi_video_enum_framesizes,
1250
1251         .vidioc_g_fmt_vid_cap           = imx7_csi_video_g_fmt_vid_cap,
1252         .vidioc_try_fmt_vid_cap         = imx7_csi_video_try_fmt_vid_cap,
1253         .vidioc_s_fmt_vid_cap           = imx7_csi_video_s_fmt_vid_cap,
1254
1255         .vidioc_g_selection             = imx7_csi_video_g_selection,
1256
1257         .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
1258         .vidioc_create_bufs             = vb2_ioctl_create_bufs,
1259         .vidioc_prepare_buf             = vb2_ioctl_prepare_buf,
1260         .vidioc_querybuf                = vb2_ioctl_querybuf,
1261         .vidioc_qbuf                    = vb2_ioctl_qbuf,
1262         .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
1263         .vidioc_expbuf                  = vb2_ioctl_expbuf,
1264         .vidioc_streamon                = vb2_ioctl_streamon,
1265         .vidioc_streamoff               = vb2_ioctl_streamoff,
1266 };
1267
1268 /* -----------------------------------------------------------------------------
1269  * Video Capture Device - Queue Operations
1270  */
1271
1272 static int imx7_csi_video_queue_setup(struct vb2_queue *vq,
1273                                       unsigned int *nbuffers,
1274                                       unsigned int *nplanes,
1275                                       unsigned int sizes[],
1276                                       struct device *alloc_devs[])
1277 {
1278         struct imx7_csi *csi = vb2_get_drv_priv(vq);
1279         struct v4l2_pix_format *pix = &csi->vdev_fmt;
1280         unsigned int count = *nbuffers;
1281
1282         if (vq->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1283                 return -EINVAL;
1284
1285         if (*nplanes) {
1286                 if (*nplanes != 1 || sizes[0] < pix->sizeimage)
1287                         return -EINVAL;
1288                 count += vq->num_buffers;
1289         }
1290
1291         count = min_t(__u32, IMX7_CSI_VIDEO_MEM_LIMIT / pix->sizeimage, count);
1292
1293         if (*nplanes)
1294                 *nbuffers = (count < vq->num_buffers) ? 0 :
1295                         count - vq->num_buffers;
1296         else
1297                 *nbuffers = count;
1298
1299         *nplanes = 1;
1300         sizes[0] = pix->sizeimage;
1301
1302         return 0;
1303 }
1304
1305 static int imx7_csi_video_buf_init(struct vb2_buffer *vb)
1306 {
1307         struct imx7_csi_vb2_buffer *buf = to_imx7_csi_vb2_buffer(vb);
1308
1309         INIT_LIST_HEAD(&buf->list);
1310
1311         return 0;
1312 }
1313
1314 static int imx7_csi_video_buf_prepare(struct vb2_buffer *vb)
1315 {
1316         struct imx7_csi *csi = vb2_get_drv_priv(vb->vb2_queue);
1317         struct v4l2_pix_format *pix = &csi->vdev_fmt;
1318
1319         if (vb2_plane_size(vb, 0) < pix->sizeimage) {
1320                 dev_err(csi->dev,
1321                         "data will not fit into plane (%lu < %lu)\n",
1322                         vb2_plane_size(vb, 0), (long)pix->sizeimage);
1323                 return -EINVAL;
1324         }
1325
1326         vb2_set_plane_payload(vb, 0, pix->sizeimage);
1327
1328         return 0;
1329 }
1330
1331 static bool imx7_csi_fast_track_buffer(struct imx7_csi *csi,
1332                                        struct imx7_csi_vb2_buffer *buf)
1333 {
1334         unsigned long flags;
1335         dma_addr_t dma_addr;
1336         int buf_num;
1337         u32 isr;
1338
1339         if (!csi->is_streaming)
1340                 return false;
1341
1342         dma_addr = vb2_dma_contig_plane_dma_addr(&buf->vbuf.vb2_buf, 0);
1343
1344         /*
1345          * buf_num holds the framebuffer ID of the most recently (*not* the
1346          * next anticipated) triggered interrupt. Without loss of generality,
1347          * if buf_num is 0, the hardware is capturing to FB2. If FB1 has been
1348          * programmed with a dummy buffer (as indicated by active_vb2_buf[0]
1349          * being NULL), then we can fast-track the new buffer by programming
1350          * its address in FB1 before the hardware completes FB2, instead of
1351          * adding it to the buffer queue and incurring a delay of one
1352          * additional frame.
1353          *
1354          * The irqlock prevents races with the interrupt handler that updates
1355          * buf_num when it programs the next buffer, but we can still race with
1356          * the hardware if we program the buffer in FB1 just after the hardware
1357          * completes FB2 and switches to FB1 and before buf_num can be updated
1358          * by the interrupt handler for FB2.  The fast-tracked buffer would
1359          * then be ignored by the hardware while the driver would think it has
1360          * successfully been processed.
1361          *
1362          * To avoid this problem, if we can't avoid the race, we can detect
1363          * that we have lost it by checking, after programming the buffer in
1364          * FB1, if the interrupt flag indicating completion of FB2 has been
1365          * raised. If that is not the case, fast-tracking succeeded, and we can
1366          * update active_vb2_buf[0]. Otherwise, we may or may not have lost the
1367          * race (as the interrupt flag may have been raised just after
1368          * programming FB1 and before we read the interrupt status register),
1369          * and we need to assume the worst case of a race loss and queue the
1370          * buffer through the slow path.
1371          */
1372
1373         spin_lock_irqsave(&csi->irqlock, flags);
1374
1375         buf_num = csi->buf_num;
1376         if (csi->active_vb2_buf[buf_num]) {
1377                 spin_unlock_irqrestore(&csi->irqlock, flags);
1378                 return false;
1379         }
1380
1381         imx7_csi_update_buf(csi, dma_addr, buf_num);
1382
1383         isr = imx7_csi_reg_read(csi, CSI_CSISR);
1384         if (isr & (buf_num ? BIT_DMA_TSF_DONE_FB1 : BIT_DMA_TSF_DONE_FB2)) {
1385                 /*
1386                  * The interrupt for the /other/ FB just came (the isr hasn't
1387                  * run yet though, because we have the lock here); we can't be
1388                  * sure we've programmed buf_num FB in time, so queue the buffer
1389                  * to the buffer queue normally. No need to undo writing the FB
1390                  * register, since we won't return it as active_vb2_buf is NULL,
1391                  * so it's okay to potentially write it to both FB1 and FB2;
1392                  * only the one where it was queued normally will be returned.
1393                  */
1394                 spin_unlock_irqrestore(&csi->irqlock, flags);
1395                 return false;
1396         }
1397
1398         csi->active_vb2_buf[buf_num] = buf;
1399
1400         spin_unlock_irqrestore(&csi->irqlock, flags);
1401         return true;
1402 }
1403
1404 static void imx7_csi_video_buf_queue(struct vb2_buffer *vb)
1405 {
1406         struct imx7_csi *csi = vb2_get_drv_priv(vb->vb2_queue);
1407         struct imx7_csi_vb2_buffer *buf = to_imx7_csi_vb2_buffer(vb);
1408         unsigned long flags;
1409
1410         if (imx7_csi_fast_track_buffer(csi, buf))
1411                 return;
1412
1413         spin_lock_irqsave(&csi->q_lock, flags);
1414
1415         list_add_tail(&buf->list, &csi->ready_q);
1416
1417         spin_unlock_irqrestore(&csi->q_lock, flags);
1418 }
1419
1420 static int imx7_csi_video_validate_fmt(struct imx7_csi *csi)
1421 {
1422         struct v4l2_subdev_format fmt_src = {
1423                 .pad = IMX7_CSI_PAD_SRC,
1424                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1425         };
1426         const struct imx7_csi_pixfmt *cc;
1427         int ret;
1428
1429         /* Retrieve the media bus format on the source subdev. */
1430         ret = v4l2_subdev_call_state_active(&csi->sd, pad, get_fmt, &fmt_src);
1431         if (ret)
1432                 return ret;
1433
1434         /*
1435          * Verify that the media bus size matches the size set on the video
1436          * node. It is sufficient to check the compose rectangle size without
1437          * checking the rounded size from pix_fmt, as the rounded size is
1438          * derived directly from the compose rectangle size, and will thus
1439          * always match if the compose rectangle matches.
1440          */
1441         if (csi->vdev_compose.width != fmt_src.format.width ||
1442             csi->vdev_compose.height != fmt_src.format.height)
1443                 return -EPIPE;
1444
1445         /*
1446          * Verify that the media bus code is compatible with the pixel format
1447          * set on the video node.
1448          */
1449         cc = imx7_csi_find_mbus_format(fmt_src.format.code);
1450         if (!cc || csi->vdev_cc->yuv != cc->yuv)
1451                 return -EPIPE;
1452
1453         return 0;
1454 }
1455
1456 static int imx7_csi_video_start_streaming(struct vb2_queue *vq,
1457                                           unsigned int count)
1458 {
1459         struct imx7_csi *csi = vb2_get_drv_priv(vq);
1460         struct imx7_csi_vb2_buffer *buf, *tmp;
1461         unsigned long flags;
1462         int ret;
1463
1464         ret = imx7_csi_video_validate_fmt(csi);
1465         if (ret) {
1466                 dev_err(csi->dev, "capture format not valid\n");
1467                 goto err_buffers;
1468         }
1469
1470         mutex_lock(&csi->mdev.graph_mutex);
1471
1472         ret = __video_device_pipeline_start(csi->vdev, &csi->pipe);
1473         if (ret)
1474                 goto err_unlock;
1475
1476         ret = v4l2_subdev_call(&csi->sd, video, s_stream, 1);
1477         if (ret)
1478                 goto err_stop;
1479
1480         mutex_unlock(&csi->mdev.graph_mutex);
1481
1482         return 0;
1483
1484 err_stop:
1485         __video_device_pipeline_stop(csi->vdev);
1486 err_unlock:
1487         mutex_unlock(&csi->mdev.graph_mutex);
1488         dev_err(csi->dev, "pipeline start failed with %d\n", ret);
1489 err_buffers:
1490         spin_lock_irqsave(&csi->q_lock, flags);
1491         list_for_each_entry_safe(buf, tmp, &csi->ready_q, list) {
1492                 list_del(&buf->list);
1493                 vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_QUEUED);
1494         }
1495         spin_unlock_irqrestore(&csi->q_lock, flags);
1496         return ret;
1497 }
1498
1499 static void imx7_csi_video_stop_streaming(struct vb2_queue *vq)
1500 {
1501         struct imx7_csi *csi = vb2_get_drv_priv(vq);
1502         struct imx7_csi_vb2_buffer *frame;
1503         struct imx7_csi_vb2_buffer *tmp;
1504         unsigned long flags;
1505
1506         mutex_lock(&csi->mdev.graph_mutex);
1507         v4l2_subdev_call(&csi->sd, video, s_stream, 0);
1508         __video_device_pipeline_stop(csi->vdev);
1509         mutex_unlock(&csi->mdev.graph_mutex);
1510
1511         /* release all active buffers */
1512         spin_lock_irqsave(&csi->q_lock, flags);
1513         list_for_each_entry_safe(frame, tmp, &csi->ready_q, list) {
1514                 list_del(&frame->list);
1515                 vb2_buffer_done(&frame->vbuf.vb2_buf, VB2_BUF_STATE_ERROR);
1516         }
1517         spin_unlock_irqrestore(&csi->q_lock, flags);
1518 }
1519
1520 static const struct vb2_ops imx7_csi_video_qops = {
1521         .queue_setup     = imx7_csi_video_queue_setup,
1522         .buf_init        = imx7_csi_video_buf_init,
1523         .buf_prepare     = imx7_csi_video_buf_prepare,
1524         .buf_queue       = imx7_csi_video_buf_queue,
1525         .wait_prepare    = vb2_ops_wait_prepare,
1526         .wait_finish     = vb2_ops_wait_finish,
1527         .start_streaming = imx7_csi_video_start_streaming,
1528         .stop_streaming  = imx7_csi_video_stop_streaming,
1529 };
1530
1531 /* -----------------------------------------------------------------------------
1532  * Video Capture Device - File Operations
1533  */
1534
1535 static int imx7_csi_video_open(struct file *file)
1536 {
1537         struct imx7_csi *csi = video_drvdata(file);
1538         int ret;
1539
1540         if (mutex_lock_interruptible(&csi->vdev_mutex))
1541                 return -ERESTARTSYS;
1542
1543         ret = v4l2_fh_open(file);
1544         if (ret) {
1545                 dev_err(csi->dev, "v4l2_fh_open failed\n");
1546                 goto out;
1547         }
1548
1549         ret = v4l2_pipeline_pm_get(&csi->vdev->entity);
1550         if (ret)
1551                 v4l2_fh_release(file);
1552
1553 out:
1554         mutex_unlock(&csi->vdev_mutex);
1555         return ret;
1556 }
1557
1558 static int imx7_csi_video_release(struct file *file)
1559 {
1560         struct imx7_csi *csi = video_drvdata(file);
1561         struct vb2_queue *vq = &csi->q;
1562
1563         mutex_lock(&csi->vdev_mutex);
1564
1565         if (file->private_data == vq->owner) {
1566                 vb2_queue_release(vq);
1567                 vq->owner = NULL;
1568         }
1569
1570         v4l2_pipeline_pm_put(&csi->vdev->entity);
1571
1572         v4l2_fh_release(file);
1573         mutex_unlock(&csi->vdev_mutex);
1574         return 0;
1575 }
1576
1577 static const struct v4l2_file_operations imx7_csi_video_fops = {
1578         .owner          = THIS_MODULE,
1579         .open           = imx7_csi_video_open,
1580         .release        = imx7_csi_video_release,
1581         .poll           = vb2_fop_poll,
1582         .unlocked_ioctl = video_ioctl2,
1583         .mmap           = vb2_fop_mmap,
1584 };
1585
1586 /* -----------------------------------------------------------------------------
1587  * Video Capture Device - Init & Cleanup
1588  */
1589
1590 static struct imx7_csi_vb2_buffer *imx7_csi_video_next_buf(struct imx7_csi *csi)
1591 {
1592         struct imx7_csi_vb2_buffer *buf = NULL;
1593         unsigned long flags;
1594
1595         spin_lock_irqsave(&csi->q_lock, flags);
1596
1597         /* get next queued buffer */
1598         if (!list_empty(&csi->ready_q)) {
1599                 buf = list_entry(csi->ready_q.next, struct imx7_csi_vb2_buffer,
1600                                  list);
1601                 list_del(&buf->list);
1602         }
1603
1604         spin_unlock_irqrestore(&csi->q_lock, flags);
1605
1606         return buf;
1607 }
1608
1609 static int imx7_csi_video_init_format(struct imx7_csi *csi)
1610 {
1611         struct v4l2_mbus_framefmt format = { };
1612
1613         format.code = IMX7_CSI_DEF_MBUS_CODE;
1614         format.width = IMX7_CSI_DEF_PIX_WIDTH;
1615         format.height = IMX7_CSI_DEF_PIX_HEIGHT;
1616         format.field = V4L2_FIELD_NONE;
1617
1618         imx7_csi_mbus_fmt_to_pix_fmt(&csi->vdev_fmt, &format, NULL);
1619         csi->vdev_compose.width = format.width;
1620         csi->vdev_compose.height = format.height;
1621
1622         csi->vdev_cc = imx7_csi_find_pixel_format(csi->vdev_fmt.pixelformat);
1623
1624         return 0;
1625 }
1626
1627 static int imx7_csi_video_register(struct imx7_csi *csi)
1628 {
1629         struct v4l2_subdev *sd = &csi->sd;
1630         struct v4l2_device *v4l2_dev = sd->v4l2_dev;
1631         struct video_device *vdev = csi->vdev;
1632         int ret;
1633
1634         vdev->v4l2_dev = v4l2_dev;
1635
1636         /* Initialize the default format and compose rectangle. */
1637         ret = imx7_csi_video_init_format(csi);
1638         if (ret < 0)
1639                 return ret;
1640
1641         /* Register the video device. */
1642         ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1643         if (ret) {
1644                 dev_err(csi->dev, "Failed to register video device\n");
1645                 return ret;
1646         }
1647
1648         dev_info(csi->dev, "Registered %s as /dev/%s\n", vdev->name,
1649                  video_device_node_name(vdev));
1650
1651         /* Create the link from the CSI subdev to the video device. */
1652         ret = media_create_pad_link(&sd->entity, IMX7_CSI_PAD_SRC,
1653                                     &vdev->entity, 0, MEDIA_LNK_FL_IMMUTABLE |
1654                                     MEDIA_LNK_FL_ENABLED);
1655         if (ret) {
1656                 dev_err(csi->dev, "failed to create link to device node\n");
1657                 video_unregister_device(vdev);
1658                 return ret;
1659         }
1660
1661         return 0;
1662 }
1663
1664 static void imx7_csi_video_unregister(struct imx7_csi *csi)
1665 {
1666         media_entity_cleanup(&csi->vdev->entity);
1667         video_unregister_device(csi->vdev);
1668 }
1669
1670 static int imx7_csi_video_init(struct imx7_csi *csi)
1671 {
1672         struct video_device *vdev;
1673         struct vb2_queue *vq;
1674         int ret;
1675
1676         mutex_init(&csi->vdev_mutex);
1677         INIT_LIST_HEAD(&csi->ready_q);
1678         spin_lock_init(&csi->q_lock);
1679
1680         /* Allocate and initialize the video device. */
1681         vdev = video_device_alloc();
1682         if (!vdev)
1683                 return -ENOMEM;
1684
1685         vdev->fops = &imx7_csi_video_fops;
1686         vdev->ioctl_ops = &imx7_csi_video_ioctl_ops;
1687         vdev->minor = -1;
1688         vdev->release = video_device_release;
1689         vdev->vfl_dir = VFL_DIR_RX;
1690         vdev->tvnorms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM;
1691         vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING
1692                          | V4L2_CAP_IO_MC;
1693         vdev->lock = &csi->vdev_mutex;
1694         vdev->queue = &csi->q;
1695
1696         snprintf(vdev->name, sizeof(vdev->name), "%s capture", csi->sd.name);
1697
1698         video_set_drvdata(vdev, csi);
1699         csi->vdev = vdev;
1700
1701         /* Initialize the video device pad. */
1702         csi->vdev_pad.flags = MEDIA_PAD_FL_SINK;
1703         ret = media_entity_pads_init(&vdev->entity, 1, &csi->vdev_pad);
1704         if (ret) {
1705                 video_device_release(vdev);
1706                 return ret;
1707         }
1708
1709         /* Initialize the vb2 queue. */
1710         vq = &csi->q;
1711         vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1712         vq->io_modes = VB2_MMAP | VB2_DMABUF;
1713         vq->drv_priv = csi;
1714         vq->buf_struct_size = sizeof(struct imx7_csi_vb2_buffer);
1715         vq->ops = &imx7_csi_video_qops;
1716         vq->mem_ops = &vb2_dma_contig_memops;
1717         vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1718         vq->lock = &csi->vdev_mutex;
1719         vq->min_buffers_needed = 2;
1720         vq->dev = csi->dev;
1721
1722         ret = vb2_queue_init(vq);
1723         if (ret) {
1724                 dev_err(csi->dev, "vb2_queue_init failed\n");
1725                 video_device_release(vdev);
1726                 return ret;
1727         }
1728
1729         return 0;
1730 }
1731
1732 /* -----------------------------------------------------------------------------
1733  * V4L2 Subdev Operations
1734  */
1735
1736 static int imx7_csi_s_stream(struct v4l2_subdev *sd, int enable)
1737 {
1738         struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1739         struct v4l2_subdev_state *sd_state;
1740         int ret = 0;
1741
1742         sd_state = v4l2_subdev_lock_and_get_active_state(sd);
1743
1744         if (enable) {
1745                 ret = imx7_csi_init(csi, sd_state);
1746                 if (ret < 0)
1747                         goto out_unlock;
1748
1749                 ret = v4l2_subdev_call(csi->src_sd, video, s_stream, 1);
1750                 if (ret < 0) {
1751                         imx7_csi_deinit(csi, VB2_BUF_STATE_QUEUED);
1752                         goto out_unlock;
1753                 }
1754
1755                 imx7_csi_enable(csi);
1756         } else {
1757                 imx7_csi_disable(csi);
1758
1759                 v4l2_subdev_call(csi->src_sd, video, s_stream, 0);
1760
1761                 imx7_csi_deinit(csi, VB2_BUF_STATE_ERROR);
1762         }
1763
1764         csi->is_streaming = !!enable;
1765
1766 out_unlock:
1767         v4l2_subdev_unlock_state(sd_state);
1768
1769         return ret;
1770 }
1771
1772 static int imx7_csi_init_cfg(struct v4l2_subdev *sd,
1773                              struct v4l2_subdev_state *sd_state)
1774 {
1775         const struct imx7_csi_pixfmt *cc;
1776         int i;
1777
1778         cc = imx7_csi_find_mbus_format(IMX7_CSI_DEF_MBUS_CODE);
1779
1780         for (i = 0; i < IMX7_CSI_PADS_NUM; i++) {
1781                 struct v4l2_mbus_framefmt *mf =
1782                         v4l2_subdev_get_pad_format(sd, sd_state, i);
1783
1784                 mf->code = IMX7_CSI_DEF_MBUS_CODE;
1785                 mf->width = IMX7_CSI_DEF_PIX_WIDTH;
1786                 mf->height = IMX7_CSI_DEF_PIX_HEIGHT;
1787                 mf->field = V4L2_FIELD_NONE;
1788
1789                 mf->colorspace = V4L2_COLORSPACE_SRGB;
1790                 mf->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(mf->colorspace);
1791                 mf->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(mf->colorspace);
1792                 mf->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(!cc->yuv,
1793                                         mf->colorspace, mf->ycbcr_enc);
1794         }
1795
1796         return 0;
1797 }
1798
1799 static int imx7_csi_enum_mbus_code(struct v4l2_subdev *sd,
1800                                    struct v4l2_subdev_state *sd_state,
1801                                    struct v4l2_subdev_mbus_code_enum *code)
1802 {
1803         struct v4l2_mbus_framefmt *in_fmt;
1804         int ret = 0;
1805
1806         in_fmt = v4l2_subdev_get_pad_format(sd, sd_state, IMX7_CSI_PAD_SINK);
1807
1808         switch (code->pad) {
1809         case IMX7_CSI_PAD_SINK:
1810                 ret = imx7_csi_enum_mbus_formats(&code->code, code->index);
1811                 break;
1812
1813         case IMX7_CSI_PAD_SRC:
1814                 if (code->index != 0) {
1815                         ret = -EINVAL;
1816                         break;
1817                 }
1818
1819                 code->code = in_fmt->code;
1820                 break;
1821
1822         default:
1823                 ret = -EINVAL;
1824                 break;
1825         }
1826
1827         return ret;
1828 }
1829
1830 /*
1831  * Default the colorspace in tryfmt to SRGB if set to an unsupported
1832  * colorspace or not initialized. Then set the remaining colorimetry
1833  * parameters based on the colorspace if they are uninitialized.
1834  *
1835  * tryfmt->code must be set on entry.
1836  */
1837 static void imx7_csi_try_colorimetry(struct v4l2_mbus_framefmt *tryfmt)
1838 {
1839         const struct imx7_csi_pixfmt *cc;
1840         bool is_rgb = false;
1841
1842         cc = imx7_csi_find_mbus_format(tryfmt->code);
1843         if (cc && !cc->yuv)
1844                 is_rgb = true;
1845
1846         switch (tryfmt->colorspace) {
1847         case V4L2_COLORSPACE_SMPTE170M:
1848         case V4L2_COLORSPACE_REC709:
1849         case V4L2_COLORSPACE_JPEG:
1850         case V4L2_COLORSPACE_SRGB:
1851         case V4L2_COLORSPACE_BT2020:
1852         case V4L2_COLORSPACE_OPRGB:
1853         case V4L2_COLORSPACE_DCI_P3:
1854         case V4L2_COLORSPACE_RAW:
1855                 break;
1856         default:
1857                 tryfmt->colorspace = V4L2_COLORSPACE_SRGB;
1858                 break;
1859         }
1860
1861         if (tryfmt->xfer_func == V4L2_XFER_FUNC_DEFAULT)
1862                 tryfmt->xfer_func =
1863                         V4L2_MAP_XFER_FUNC_DEFAULT(tryfmt->colorspace);
1864
1865         if (tryfmt->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
1866                 tryfmt->ycbcr_enc =
1867                         V4L2_MAP_YCBCR_ENC_DEFAULT(tryfmt->colorspace);
1868
1869         if (tryfmt->quantization == V4L2_QUANTIZATION_DEFAULT)
1870                 tryfmt->quantization =
1871                         V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb,
1872                                                       tryfmt->colorspace,
1873                                                       tryfmt->ycbcr_enc);
1874 }
1875
1876 static void imx7_csi_try_fmt(struct v4l2_subdev *sd,
1877                              struct v4l2_subdev_state *sd_state,
1878                              struct v4l2_subdev_format *sdformat,
1879                              const struct imx7_csi_pixfmt **cc)
1880 {
1881         const struct imx7_csi_pixfmt *in_cc;
1882         struct v4l2_mbus_framefmt *in_fmt;
1883         u32 code;
1884
1885         in_fmt = v4l2_subdev_get_pad_format(sd, sd_state, IMX7_CSI_PAD_SINK);
1886
1887         switch (sdformat->pad) {
1888         case IMX7_CSI_PAD_SRC:
1889                 in_cc = imx7_csi_find_mbus_format(in_fmt->code);
1890
1891                 sdformat->format.width = in_fmt->width;
1892                 sdformat->format.height = in_fmt->height;
1893                 sdformat->format.code = in_fmt->code;
1894                 sdformat->format.field = in_fmt->field;
1895                 *cc = in_cc;
1896
1897                 sdformat->format.colorspace = in_fmt->colorspace;
1898                 sdformat->format.xfer_func = in_fmt->xfer_func;
1899                 sdformat->format.quantization = in_fmt->quantization;
1900                 sdformat->format.ycbcr_enc = in_fmt->ycbcr_enc;
1901                 break;
1902
1903         case IMX7_CSI_PAD_SINK:
1904                 *cc = imx7_csi_find_mbus_format(sdformat->format.code);
1905                 if (!*cc) {
1906                         code = IMX7_CSI_DEF_MBUS_CODE;
1907                         *cc = imx7_csi_find_mbus_format(code);
1908                         sdformat->format.code = code;
1909                 }
1910
1911                 if (sdformat->format.field != V4L2_FIELD_INTERLACED)
1912                         sdformat->format.field = V4L2_FIELD_NONE;
1913                 break;
1914         }
1915
1916         imx7_csi_try_colorimetry(&sdformat->format);
1917 }
1918
1919 static int imx7_csi_set_fmt(struct v4l2_subdev *sd,
1920                             struct v4l2_subdev_state *sd_state,
1921                             struct v4l2_subdev_format *sdformat)
1922 {
1923         struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1924         const struct imx7_csi_pixfmt *outcc;
1925         struct v4l2_mbus_framefmt *outfmt;
1926         const struct imx7_csi_pixfmt *cc;
1927         struct v4l2_mbus_framefmt *fmt;
1928         struct v4l2_subdev_format format;
1929
1930         if (csi->is_streaming)
1931                 return -EBUSY;
1932
1933         imx7_csi_try_fmt(sd, sd_state, sdformat, &cc);
1934
1935         fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad);
1936
1937         *fmt = sdformat->format;
1938
1939         if (sdformat->pad == IMX7_CSI_PAD_SINK) {
1940                 /* propagate format to source pads */
1941                 format.pad = IMX7_CSI_PAD_SRC;
1942                 format.which = sdformat->which;
1943                 format.format = sdformat->format;
1944                 imx7_csi_try_fmt(sd, sd_state, &format, &outcc);
1945
1946                 outfmt = v4l2_subdev_get_pad_format(sd, sd_state,
1947                                                     IMX7_CSI_PAD_SRC);
1948                 *outfmt = format.format;
1949         }
1950
1951         return 0;
1952 }
1953
1954 static int imx7_csi_pad_link_validate(struct v4l2_subdev *sd,
1955                                       struct media_link *link,
1956                                       struct v4l2_subdev_format *source_fmt,
1957                                       struct v4l2_subdev_format *sink_fmt)
1958 {
1959         struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1960         struct media_pad *pad = NULL;
1961         unsigned int i;
1962         int ret;
1963
1964         /*
1965          * Validate the source link, and record whether the source uses the
1966          * parallel input or the CSI-2 receiver.
1967          */
1968         ret = v4l2_subdev_link_validate_default(sd, link, source_fmt, sink_fmt);
1969         if (ret)
1970                 return ret;
1971
1972         switch (csi->src_sd->entity.function) {
1973         case MEDIA_ENT_F_VID_IF_BRIDGE:
1974                 /* The input is the CSI-2 receiver. */
1975                 csi->is_csi2 = true;
1976                 break;
1977
1978         case MEDIA_ENT_F_VID_MUX:
1979                 /* The input is the mux, check its input. */
1980                 for (i = 0; i < csi->src_sd->entity.num_pads; i++) {
1981                         struct media_pad *spad = &csi->src_sd->entity.pads[i];
1982
1983                         if (!(spad->flags & MEDIA_PAD_FL_SINK))
1984                                 continue;
1985
1986                         pad = media_pad_remote_pad_first(spad);
1987                         if (pad)
1988                                 break;
1989                 }
1990
1991                 if (!pad)
1992                         return -ENODEV;
1993
1994                 csi->is_csi2 = pad->entity->function == MEDIA_ENT_F_VID_IF_BRIDGE;
1995                 break;
1996
1997         default:
1998                 /*
1999                  * The input is an external entity, it must use the parallel
2000                  * bus.
2001                  */
2002                 csi->is_csi2 = false;
2003                 break;
2004         }
2005
2006         return 0;
2007 }
2008
2009 static int imx7_csi_registered(struct v4l2_subdev *sd)
2010 {
2011         struct imx7_csi *csi = v4l2_get_subdevdata(sd);
2012         int ret;
2013
2014         ret = imx7_csi_video_init(csi);
2015         if (ret)
2016                 return ret;
2017
2018         ret = imx7_csi_video_register(csi);
2019         if (ret)
2020                 return ret;
2021
2022         ret = v4l2_device_register_subdev_nodes(&csi->v4l2_dev);
2023         if (ret)
2024                 goto err_unreg;
2025
2026         ret = media_device_register(&csi->mdev);
2027         if (ret)
2028                 goto err_unreg;
2029
2030         return 0;
2031
2032 err_unreg:
2033         imx7_csi_video_unregister(csi);
2034         return ret;
2035 }
2036
2037 static void imx7_csi_unregistered(struct v4l2_subdev *sd)
2038 {
2039         struct imx7_csi *csi = v4l2_get_subdevdata(sd);
2040
2041         imx7_csi_video_unregister(csi);
2042 }
2043
2044 static const struct v4l2_subdev_video_ops imx7_csi_video_ops = {
2045         .s_stream       = imx7_csi_s_stream,
2046 };
2047
2048 static const struct v4l2_subdev_pad_ops imx7_csi_pad_ops = {
2049         .init_cfg       = imx7_csi_init_cfg,
2050         .enum_mbus_code = imx7_csi_enum_mbus_code,
2051         .get_fmt        = v4l2_subdev_get_fmt,
2052         .set_fmt        = imx7_csi_set_fmt,
2053         .link_validate  = imx7_csi_pad_link_validate,
2054 };
2055
2056 static const struct v4l2_subdev_ops imx7_csi_subdev_ops = {
2057         .video          = &imx7_csi_video_ops,
2058         .pad            = &imx7_csi_pad_ops,
2059 };
2060
2061 static const struct v4l2_subdev_internal_ops imx7_csi_internal_ops = {
2062         .registered     = imx7_csi_registered,
2063         .unregistered   = imx7_csi_unregistered,
2064 };
2065
2066 /* -----------------------------------------------------------------------------
2067  * Media Entity Operations
2068  */
2069
2070 static const struct media_entity_operations imx7_csi_entity_ops = {
2071         .link_validate  = v4l2_subdev_link_validate,
2072         .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
2073 };
2074
2075 /* -----------------------------------------------------------------------------
2076  * Probe & Remove
2077  */
2078
2079 static int imx7_csi_notify_bound(struct v4l2_async_notifier *notifier,
2080                                  struct v4l2_subdev *sd,
2081                                  struct v4l2_async_subdev *asd)
2082 {
2083         struct imx7_csi *csi = imx7_csi_notifier_to_dev(notifier);
2084         struct media_pad *sink = &csi->sd.entity.pads[IMX7_CSI_PAD_SINK];
2085
2086         csi->src_sd = sd;
2087
2088         return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED |
2089                                                MEDIA_LNK_FL_IMMUTABLE);
2090 }
2091
2092 static int imx7_csi_notify_complete(struct v4l2_async_notifier *notifier)
2093 {
2094         struct imx7_csi *csi = imx7_csi_notifier_to_dev(notifier);
2095
2096         return v4l2_device_register_subdev_nodes(&csi->v4l2_dev);
2097 }
2098
2099 static const struct v4l2_async_notifier_operations imx7_csi_notify_ops = {
2100         .bound = imx7_csi_notify_bound,
2101         .complete = imx7_csi_notify_complete,
2102 };
2103
2104 static int imx7_csi_async_register(struct imx7_csi *csi)
2105 {
2106         struct v4l2_async_subdev *asd;
2107         struct fwnode_handle *ep;
2108         int ret;
2109
2110         v4l2_async_nf_init(&csi->notifier);
2111
2112         ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0,
2113                                              FWNODE_GRAPH_ENDPOINT_NEXT);
2114         if (!ep) {
2115                 ret = dev_err_probe(csi->dev, -ENOTCONN,
2116                                     "Failed to get remote endpoint\n");
2117                 goto error;
2118         }
2119
2120         asd = v4l2_async_nf_add_fwnode_remote(&csi->notifier, ep,
2121                                               struct v4l2_async_subdev);
2122
2123         fwnode_handle_put(ep);
2124
2125         if (IS_ERR(asd)) {
2126                 ret = dev_err_probe(csi->dev, PTR_ERR(asd),
2127                                     "Failed to add remote subdev to notifier\n");
2128                 goto error;
2129         }
2130
2131         csi->notifier.ops = &imx7_csi_notify_ops;
2132
2133         ret = v4l2_async_nf_register(&csi->v4l2_dev, &csi->notifier);
2134         if (ret)
2135                 goto error;
2136
2137         return 0;
2138
2139 error:
2140         v4l2_async_nf_cleanup(&csi->notifier);
2141         return ret;
2142 }
2143
2144 static void imx7_csi_media_cleanup(struct imx7_csi *csi)
2145 {
2146         v4l2_device_unregister(&csi->v4l2_dev);
2147         media_device_unregister(&csi->mdev);
2148         v4l2_subdev_cleanup(&csi->sd);
2149         media_device_cleanup(&csi->mdev);
2150 }
2151
2152 static const struct media_device_ops imx7_csi_media_ops = {
2153         .link_notify = v4l2_pipeline_link_notify,
2154 };
2155
2156 static int imx7_csi_media_dev_init(struct imx7_csi *csi)
2157 {
2158         int ret;
2159
2160         strscpy(csi->mdev.model, "imx-media", sizeof(csi->mdev.model));
2161         csi->mdev.ops = &imx7_csi_media_ops;
2162         csi->mdev.dev = csi->dev;
2163
2164         csi->v4l2_dev.mdev = &csi->mdev;
2165         strscpy(csi->v4l2_dev.name, "imx-media",
2166                 sizeof(csi->v4l2_dev.name));
2167         snprintf(csi->mdev.bus_info, sizeof(csi->mdev.bus_info),
2168                  "platform:%s", dev_name(csi->mdev.dev));
2169
2170         media_device_init(&csi->mdev);
2171
2172         ret = v4l2_device_register(csi->dev, &csi->v4l2_dev);
2173         if (ret < 0) {
2174                 v4l2_err(&csi->v4l2_dev,
2175                          "Failed to register v4l2_device: %d\n", ret);
2176                 goto cleanup;
2177         }
2178
2179         return 0;
2180
2181 cleanup:
2182         media_device_cleanup(&csi->mdev);
2183
2184         return ret;
2185 }
2186
2187 static int imx7_csi_media_init(struct imx7_csi *csi)
2188 {
2189         unsigned int i;
2190         int ret;
2191
2192         /* add media device */
2193         ret = imx7_csi_media_dev_init(csi);
2194         if (ret)
2195                 return ret;
2196
2197         v4l2_subdev_init(&csi->sd, &imx7_csi_subdev_ops);
2198         v4l2_set_subdevdata(&csi->sd, csi);
2199         csi->sd.internal_ops = &imx7_csi_internal_ops;
2200         csi->sd.entity.ops = &imx7_csi_entity_ops;
2201         csi->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
2202         csi->sd.dev = csi->dev;
2203         csi->sd.owner = THIS_MODULE;
2204         csi->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
2205         snprintf(csi->sd.name, sizeof(csi->sd.name), "csi");
2206
2207         for (i = 0; i < IMX7_CSI_PADS_NUM; i++)
2208                 csi->pad[i].flags = (i == IMX7_CSI_PAD_SINK) ?
2209                         MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
2210
2211         ret = media_entity_pads_init(&csi->sd.entity, IMX7_CSI_PADS_NUM,
2212                                      csi->pad);
2213         if (ret)
2214                 goto error;
2215
2216         ret = v4l2_subdev_init_finalize(&csi->sd);
2217         if (ret)
2218                 goto error;
2219
2220         ret = v4l2_device_register_subdev(&csi->v4l2_dev, &csi->sd);
2221         if (ret)
2222                 goto error;
2223
2224         return 0;
2225
2226 error:
2227         imx7_csi_media_cleanup(csi);
2228         return ret;
2229 }
2230
2231 static int imx7_csi_probe(struct platform_device *pdev)
2232 {
2233         struct device *dev = &pdev->dev;
2234         struct imx7_csi *csi;
2235         int ret;
2236
2237         csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
2238         if (!csi)
2239                 return -ENOMEM;
2240
2241         csi->dev = dev;
2242         platform_set_drvdata(pdev, csi);
2243
2244         spin_lock_init(&csi->irqlock);
2245
2246         /* Acquire resources and install interrupt handler. */
2247         csi->mclk = devm_clk_get(&pdev->dev, "mclk");
2248         if (IS_ERR(csi->mclk)) {
2249                 ret = PTR_ERR(csi->mclk);
2250                 dev_err(dev, "Failed to get mclk: %d", ret);
2251                 return ret;
2252         }
2253
2254         csi->irq = platform_get_irq(pdev, 0);
2255         if (csi->irq < 0)
2256                 return csi->irq;
2257
2258         csi->regbase = devm_platform_ioremap_resource(pdev, 0);
2259         if (IS_ERR(csi->regbase))
2260                 return PTR_ERR(csi->regbase);
2261
2262         csi->model = (enum imx_csi_model)(uintptr_t)of_device_get_match_data(&pdev->dev);
2263
2264         ret = devm_request_irq(dev, csi->irq, imx7_csi_irq_handler, 0, "csi",
2265                                (void *)csi);
2266         if (ret < 0) {
2267                 dev_err(dev, "Request CSI IRQ failed.\n");
2268                 return ret;
2269         }
2270
2271         /* Initialize all the media device infrastructure. */
2272         ret = imx7_csi_media_init(csi);
2273         if (ret)
2274                 return ret;
2275
2276         ret = imx7_csi_async_register(csi);
2277         if (ret)
2278                 goto err_media_cleanup;
2279
2280         return 0;
2281
2282 err_media_cleanup:
2283         imx7_csi_media_cleanup(csi);
2284
2285         return ret;
2286 }
2287
2288 static void imx7_csi_remove(struct platform_device *pdev)
2289 {
2290         struct imx7_csi *csi = platform_get_drvdata(pdev);
2291
2292         imx7_csi_media_cleanup(csi);
2293
2294         v4l2_async_nf_unregister(&csi->notifier);
2295         v4l2_async_nf_cleanup(&csi->notifier);
2296         v4l2_async_unregister_subdev(&csi->sd);
2297 }
2298
2299 static const struct of_device_id imx7_csi_of_match[] = {
2300         { .compatible = "fsl,imx8mq-csi", .data = (void *)IMX7_CSI_IMX8MQ },
2301         { .compatible = "fsl,imx7-csi", .data = (void *)IMX7_CSI_IMX7 },
2302         { .compatible = "fsl,imx6ul-csi", .data = (void *)IMX7_CSI_IMX7 },
2303         { },
2304 };
2305 MODULE_DEVICE_TABLE(of, imx7_csi_of_match);
2306
2307 static struct platform_driver imx7_csi_driver = {
2308         .probe = imx7_csi_probe,
2309         .remove_new = imx7_csi_remove,
2310         .driver = {
2311                 .of_match_table = imx7_csi_of_match,
2312                 .name = "imx7-csi",
2313         },
2314 };
2315 module_platform_driver(imx7_csi_driver);
2316
2317 MODULE_DESCRIPTION("i.MX7 CSI subdev driver");
2318 MODULE_AUTHOR("Rui Miguel Silva <[email protected]>");
2319 MODULE_LICENSE("GPL v2");
2320 MODULE_ALIAS("platform:imx7-csi");