drivers/clk/spear/spear1310_clock.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * arch/arm/mach-spear13xx/spear1310_clock.c
   4  *
   5  * SPEAr1310 machine clock framework source file
   6  *
   7  * Copyright (C) 2012 ST Microelectronics
   8  * Viresh Kumar <[email protected]>
   9  */
  10
  11 #include <linux/clkdev.h>
  12 #include <linux/clk/spear.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/spinlock_types.h>
  17 #include "clk.h"
  18
  19 /* PLL related registers and bit values */
  20 #define SPEAR1310_PLL_CFG                       (misc_base + 0x210)
  21         /* PLL_CFG bit values */
  22         #define SPEAR1310_CLCD_SYNT_CLK_MASK            1
  23         #define SPEAR1310_CLCD_SYNT_CLK_SHIFT           31
  24         #define SPEAR1310_RAS_SYNT2_3_CLK_MASK          2
  25         #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT         29
  26         #define SPEAR1310_RAS_SYNT_CLK_MASK             2
  27         #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT         27
  28         #define SPEAR1310_PLL_CLK_MASK                  2
  29         #define SPEAR1310_PLL3_CLK_SHIFT                24
  30         #define SPEAR1310_PLL2_CLK_SHIFT                22
  31         #define SPEAR1310_PLL1_CLK_SHIFT                20
  32
  33 #define SPEAR1310_PLL1_CTR                      (misc_base + 0x214)
  34 #define SPEAR1310_PLL1_FRQ                      (misc_base + 0x218)
  35 #define SPEAR1310_PLL2_CTR                      (misc_base + 0x220)
  36 #define SPEAR1310_PLL2_FRQ                      (misc_base + 0x224)
  37 #define SPEAR1310_PLL3_CTR                      (misc_base + 0x22C)
  38 #define SPEAR1310_PLL3_FRQ                      (misc_base + 0x230)
  39 #define SPEAR1310_PLL4_CTR                      (misc_base + 0x238)
  40 #define SPEAR1310_PLL4_FRQ                      (misc_base + 0x23C)
  41 #define SPEAR1310_PERIP_CLK_CFG                 (misc_base + 0x244)
  42         /* PERIP_CLK_CFG bit values */
  43         #define SPEAR1310_GPT_OSC24_VAL                 0
  44         #define SPEAR1310_GPT_APB_VAL                   1
  45         #define SPEAR1310_GPT_CLK_MASK                  1
  46         #define SPEAR1310_GPT3_CLK_SHIFT                11
  47         #define SPEAR1310_GPT2_CLK_SHIFT                10
  48         #define SPEAR1310_GPT1_CLK_SHIFT                9
  49         #define SPEAR1310_GPT0_CLK_SHIFT                8
  50         #define SPEAR1310_UART_CLK_PLL5_VAL             0
  51         #define SPEAR1310_UART_CLK_OSC24_VAL            1
  52         #define SPEAR1310_UART_CLK_SYNT_VAL             2
  53         #define SPEAR1310_UART_CLK_MASK                 2
  54         #define SPEAR1310_UART_CLK_SHIFT                4
  55
  56         #define SPEAR1310_AUX_CLK_PLL5_VAL              0
  57         #define SPEAR1310_AUX_CLK_SYNT_VAL              1
  58         #define SPEAR1310_CLCD_CLK_MASK                 2
  59         #define SPEAR1310_CLCD_CLK_SHIFT                2
  60         #define SPEAR1310_C3_CLK_MASK                   1
  61         #define SPEAR1310_C3_CLK_SHIFT                  1
  62
  63 #define SPEAR1310_GMAC_CLK_CFG                  (misc_base + 0x248)
  64         #define SPEAR1310_GMAC_PHY_IF_SEL_MASK          3
  65         #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT         4
  66         #define SPEAR1310_GMAC_PHY_CLK_MASK             1
  67         #define SPEAR1310_GMAC_PHY_CLK_SHIFT            3
  68         #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK       2
  69         #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT      1
  70
  71 #define SPEAR1310_I2S_CLK_CFG                   (misc_base + 0x24C)
  72         /* I2S_CLK_CFG register mask */
  73         #define SPEAR1310_I2S_SCLK_X_MASK               0x1F
  74         #define SPEAR1310_I2S_SCLK_X_SHIFT              27
  75         #define SPEAR1310_I2S_SCLK_Y_MASK               0x1F
  76         #define SPEAR1310_I2S_SCLK_Y_SHIFT              22
  77         #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT         21
  78         #define SPEAR1310_I2S_SCLK_SYNTH_ENB            20
  79         #define SPEAR1310_I2S_PRS1_CLK_X_MASK           0xFF
  80         #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT          12
  81         #define SPEAR1310_I2S_PRS1_CLK_Y_MASK           0xFF
  82         #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT          4
  83         #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT         3
  84         #define SPEAR1310_I2S_REF_SEL_MASK              1
  85         #define SPEAR1310_I2S_REF_SHIFT                 2
  86         #define SPEAR1310_I2S_SRC_CLK_MASK              2
  87         #define SPEAR1310_I2S_SRC_CLK_SHIFT             0
  88
  89 #define SPEAR1310_C3_CLK_SYNT                   (misc_base + 0x250)
  90 #define SPEAR1310_UART_CLK_SYNT                 (misc_base + 0x254)
  91 #define SPEAR1310_GMAC_CLK_SYNT                 (misc_base + 0x258)
  92 #define SPEAR1310_SDHCI_CLK_SYNT                (misc_base + 0x25C)
  93 #define SPEAR1310_CFXD_CLK_SYNT                 (misc_base + 0x260)
  94 #define SPEAR1310_ADC_CLK_SYNT                  (misc_base + 0x264)
  95 #define SPEAR1310_AMBA_CLK_SYNT                 (misc_base + 0x268)
  96 #define SPEAR1310_CLCD_CLK_SYNT                 (misc_base + 0x270)
  97 #define SPEAR1310_RAS_CLK_SYNT0                 (misc_base + 0x280)
  98 #define SPEAR1310_RAS_CLK_SYNT1                 (misc_base + 0x288)
  99 #define SPEAR1310_RAS_CLK_SYNT2                 (misc_base + 0x290)
 100 #define SPEAR1310_RAS_CLK_SYNT3                 (misc_base + 0x298)
 101         /* Check Fractional synthesizer reg masks */
 102
 103 #define SPEAR1310_PERIP1_CLK_ENB                (misc_base + 0x300)
 104         /* PERIP1_CLK_ENB register masks */
 105         #define SPEAR1310_RTC_CLK_ENB                   31
 106         #define SPEAR1310_ADC_CLK_ENB                   30
 107         #define SPEAR1310_C3_CLK_ENB                    29
 108         #define SPEAR1310_JPEG_CLK_ENB                  28
 109         #define SPEAR1310_CLCD_CLK_ENB                  27
 110         #define SPEAR1310_DMA_CLK_ENB                   25
 111         #define SPEAR1310_GPIO1_CLK_ENB                 24
 112         #define SPEAR1310_GPIO0_CLK_ENB                 23
 113         #define SPEAR1310_GPT1_CLK_ENB                  22
 114         #define SPEAR1310_GPT0_CLK_ENB                  21
 115         #define SPEAR1310_I2S0_CLK_ENB                  20
 116         #define SPEAR1310_I2S1_CLK_ENB                  19
 117         #define SPEAR1310_I2C0_CLK_ENB                  18
 118         #define SPEAR1310_SSP_CLK_ENB                   17
 119         #define SPEAR1310_UART_CLK_ENB                  15
 120         #define SPEAR1310_PCIE_SATA_2_CLK_ENB           14
 121         #define SPEAR1310_PCIE_SATA_1_CLK_ENB           13
 122         #define SPEAR1310_PCIE_SATA_0_CLK_ENB           12
 123         #define SPEAR1310_UOC_CLK_ENB                   11
 124         #define SPEAR1310_UHC1_CLK_ENB                  10
 125         #define SPEAR1310_UHC0_CLK_ENB                  9
 126         #define SPEAR1310_GMAC_CLK_ENB                  8
 127         #define SPEAR1310_CFXD_CLK_ENB                  7
 128         #define SPEAR1310_SDHCI_CLK_ENB                 6
 129         #define SPEAR1310_SMI_CLK_ENB                   5
 130         #define SPEAR1310_FSMC_CLK_ENB                  4
 131         #define SPEAR1310_SYSRAM0_CLK_ENB               3
 132         #define SPEAR1310_SYSRAM1_CLK_ENB               2
 133         #define SPEAR1310_SYSROM_CLK_ENB                1
 134         #define SPEAR1310_BUS_CLK_ENB                   0
 135
 136 #define SPEAR1310_PERIP2_CLK_ENB                (misc_base + 0x304)
 137         /* PERIP2_CLK_ENB register masks */
 138         #define SPEAR1310_THSENS_CLK_ENB                8
 139         #define SPEAR1310_I2S_REF_PAD_CLK_ENB           7
 140         #define SPEAR1310_ACP_CLK_ENB                   6
 141         #define SPEAR1310_GPT3_CLK_ENB                  5
 142         #define SPEAR1310_GPT2_CLK_ENB                  4
 143         #define SPEAR1310_KBD_CLK_ENB                   3
 144         #define SPEAR1310_CPU_DBG_CLK_ENB               2
 145         #define SPEAR1310_DDR_CORE_CLK_ENB              1
 146         #define SPEAR1310_DDR_CTRL_CLK_ENB              0
 147
 148 #define SPEAR1310_RAS_CLK_ENB                   (misc_base + 0x310)
 149         /* RAS_CLK_ENB register masks */
 150         #define SPEAR1310_SYNT3_CLK_ENB                 17
 151         #define SPEAR1310_SYNT2_CLK_ENB                 16
 152         #define SPEAR1310_SYNT1_CLK_ENB                 15
 153         #define SPEAR1310_SYNT0_CLK_ENB                 14
 154         #define SPEAR1310_PCLK3_CLK_ENB                 13
 155         #define SPEAR1310_PCLK2_CLK_ENB                 12
 156         #define SPEAR1310_PCLK1_CLK_ENB                 11
 157         #define SPEAR1310_PCLK0_CLK_ENB                 10
 158         #define SPEAR1310_PLL3_CLK_ENB                  9
 159         #define SPEAR1310_PLL2_CLK_ENB                  8
 160         #define SPEAR1310_C125M_PAD_CLK_ENB             7
 161         #define SPEAR1310_C30M_CLK_ENB                  6
 162         #define SPEAR1310_C48M_CLK_ENB                  5
 163         #define SPEAR1310_OSC_25M_CLK_ENB               4
 164         #define SPEAR1310_OSC_32K_CLK_ENB               3
 165         #define SPEAR1310_OSC_24M_CLK_ENB               2
 166         #define SPEAR1310_PCLK_CLK_ENB                  1
 167         #define SPEAR1310_ACLK_CLK_ENB                  0
 168
 169 /* RAS Area Control Register */
 170 #define SPEAR1310_RAS_CTRL_REG0                 (ras_base + 0x000)
 171         #define SPEAR1310_SSP1_CLK_MASK                 3
 172         #define SPEAR1310_SSP1_CLK_SHIFT                26
 173         #define SPEAR1310_TDM_CLK_MASK                  1
 174         #define SPEAR1310_TDM2_CLK_SHIFT                24
 175         #define SPEAR1310_TDM1_CLK_SHIFT                23
 176         #define SPEAR1310_I2C_CLK_MASK                  1
 177         #define SPEAR1310_I2C7_CLK_SHIFT                22
 178         #define SPEAR1310_I2C6_CLK_SHIFT                21
 179         #define SPEAR1310_I2C5_CLK_SHIFT                20
 180         #define SPEAR1310_I2C4_CLK_SHIFT                19
 181         #define SPEAR1310_I2C3_CLK_SHIFT                18
 182         #define SPEAR1310_I2C2_CLK_SHIFT                17
 183         #define SPEAR1310_I2C1_CLK_SHIFT                16
 184         #define SPEAR1310_GPT64_CLK_MASK                1
 185         #define SPEAR1310_GPT64_CLK_SHIFT               15
 186         #define SPEAR1310_RAS_UART_CLK_MASK             1
 187         #define SPEAR1310_UART5_CLK_SHIFT               14
 188         #define SPEAR1310_UART4_CLK_SHIFT               13
 189         #define SPEAR1310_UART3_CLK_SHIFT               12
 190         #define SPEAR1310_UART2_CLK_SHIFT               11
 191         #define SPEAR1310_UART1_CLK_SHIFT               10
 192         #define SPEAR1310_PCI_CLK_MASK                  1
 193         #define SPEAR1310_PCI_CLK_SHIFT                 0
 194
 195 #define SPEAR1310_RAS_CTRL_REG1                 (ras_base + 0x004)
 196         #define SPEAR1310_PHY_CLK_MASK                  0x3
 197         #define SPEAR1310_RMII_PHY_CLK_SHIFT            0
 198         #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT      2
 199
 200 #define SPEAR1310_RAS_SW_CLK_CTRL               (ras_base + 0x0148)
 201         #define SPEAR1310_CAN1_CLK_ENB                  25
 202         #define SPEAR1310_CAN0_CLK_ENB                  24
 203         #define SPEAR1310_GPT64_CLK_ENB                 23
 204         #define SPEAR1310_SSP1_CLK_ENB                  22
 205         #define SPEAR1310_I2C7_CLK_ENB                  21
 206         #define SPEAR1310_I2C6_CLK_ENB                  20
 207         #define SPEAR1310_I2C5_CLK_ENB                  19
 208         #define SPEAR1310_I2C4_CLK_ENB                  18
 209         #define SPEAR1310_I2C3_CLK_ENB                  17
 210         #define SPEAR1310_I2C2_CLK_ENB                  16
 211         #define SPEAR1310_I2C1_CLK_ENB                  15
 212         #define SPEAR1310_UART5_CLK_ENB                 14
 213         #define SPEAR1310_UART4_CLK_ENB                 13
 214         #define SPEAR1310_UART3_CLK_ENB                 12
 215         #define SPEAR1310_UART2_CLK_ENB                 11
 216         #define SPEAR1310_UART1_CLK_ENB                 10
 217         #define SPEAR1310_RS485_1_CLK_ENB               9
 218         #define SPEAR1310_RS485_0_CLK_ENB               8
 219         #define SPEAR1310_TDM2_CLK_ENB                  7
 220         #define SPEAR1310_TDM1_CLK_ENB                  6
 221         #define SPEAR1310_PCI_CLK_ENB                   5
 222         #define SPEAR1310_GMII_CLK_ENB                  4
 223         #define SPEAR1310_MII2_CLK_ENB                  3
 224         #define SPEAR1310_MII1_CLK_ENB                  2
 225         #define SPEAR1310_MII0_CLK_ENB                  1
 226         #define SPEAR1310_ESRAM_CLK_ENB                 0
 227
 228 static DEFINE_SPINLOCK(_lock);
 229
 230 /* pll rate configuration table, in ascending order of rates */
 231 static struct pll_rate_tbl pll_rtbl[] = {
 232         /* PCLK 24MHz */
 233         {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
 234         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
 235         {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
 236         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
 237         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
 238         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
 239         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 240 };
 241
 242 /* vco-pll4 rate configuration table, in ascending order of rates */
 243 static struct pll_rate_tbl pll4_rtbl[] = {
 244         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
 245         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
 246         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
 247         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 248 };
 249
 250 /* aux rate configuration table, in ascending order of rates */
 251 static struct aux_rate_tbl aux_rtbl[] = {
 252         /* For VCO1div2 = 500 MHz */
 253         {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
 254         {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
 255         {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
 256         {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
 257         {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
 258         {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
 259 };
 260
 261 /* gmac rate configuration table, in ascending order of rates */
 262 static struct aux_rate_tbl gmac_rtbl[] = {
 263         /* For gmac phy input clk */
 264         {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
 265         {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
 266         {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
 267         {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
 268 };
 269
 270 /* clcd rate configuration table, in ascending order of rates */
 271 static struct frac_rate_tbl clcd_rtbl[] = {
 272         {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
 273         {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
 274         {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
 275         {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
 276         {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
 277         {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
 278         {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
 279         {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
 280         {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
 281         {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
 282 };
 283
 284 /* i2s prescaler1 masks */
 285 static const struct aux_clk_masks i2s_prs1_masks = {
 286         .eq_sel_mask = AUX_EQ_SEL_MASK,
 287         .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
 288         .eq1_mask = AUX_EQ1_SEL,
 289         .eq2_mask = AUX_EQ2_SEL,
 290         .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
 291         .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
 292         .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
 293         .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
 294 };
 295
 296 /* i2s sclk (bit clock) syynthesizers masks */
 297 static struct aux_clk_masks i2s_sclk_masks = {
 298         .eq_sel_mask = AUX_EQ_SEL_MASK,
 299         .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
 300         .eq1_mask = AUX_EQ1_SEL,
 301         .eq2_mask = AUX_EQ2_SEL,
 302         .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
 303         .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
 304         .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
 305         .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
 306         .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
 307 };
 308
 309 /* i2s prs1 aux rate configuration table, in ascending order of rates */
 310 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
 311         /* For parent clk = 49.152 MHz */
 312         {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
 313         {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
 314         {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
 315         {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
 316
 317         /*
 318          * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
 319          * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
 320          */
 321         {.xscale = 1, .yscale = 3, .eq = 0},
 322
 323         /* For parent clk = 49.152 MHz */
 324         {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
 325
 326         {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
 327 };
 328
 329 /* i2s sclk aux rate configuration table, in ascending order of rates */
 330 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
 331         /* For i2s_ref_clk = 12.288MHz */
 332         {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
 333         {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
 334 };
 335
 336 /* adc rate configuration table, in ascending order of rates */
 337 /* possible adc range is 2.5 MHz to 20 MHz. */
 338 static struct aux_rate_tbl adc_rtbl[] = {
 339         /* For ahb = 166.67 MHz */
 340         {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
 341         {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
 342         {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
 343         {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
 344 };
 345
 346 /* General synth rate configuration table, in ascending order of rates */
 347 static struct frac_rate_tbl gen_rtbl[] = {
 348         /* For vco1div4 = 250 MHz */
 349         {.div = 0x14000}, /* 25 MHz */
 350         {.div = 0x0A000}, /* 50 MHz */
 351         {.div = 0x05000}, /* 100 MHz */
 352         {.div = 0x02000}, /* 250 MHz */
 353 };
 354
 355 /* clock parents */
 356 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
 357 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
 358 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
 359 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
 360 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
 361         "osc_25m_clk", };
 362 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
 363 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
 364 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
 365 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
 366         "i2s_src_pad_clk", };
 367 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
 368 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 369         "pll3_clk", };
 370 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
 371         "pll2_clk", };
 372 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
 373         "ras_pll2_clk", "ras_syn0_clk", };
 374 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
 375         "ras_pll2_clk", "ras_syn0_clk", };
 376 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
 377 static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
 378 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
 379         "ras_plclk0_clk", };
 380 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
 381 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
 382
 383 void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 384 {
 385         struct clk *clk, *clk1;
 386
 387         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
 388         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 389
 390         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
 391         clk_register_clkdev(clk, "osc_24m_clk", NULL);
 392
 393         clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
 394         clk_register_clkdev(clk, "osc_25m_clk", NULL);
 395
 396         clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
 397         clk_register_clkdev(clk, "gmii_pad_clk", NULL);
 398
 399         clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
 400                                       12288000);
 401         clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
 402
 403         /* clock derived from 32 KHz osc clk */
 404         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 405                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
 406                         &_lock);
 407         clk_register_clkdev(clk, NULL, "e0580000.rtc");
 408
 409         /* clock derived from 24 or 25 MHz osc clk */
 410         /* vco-pll */
 411         clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
 412                         ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
 413                         SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT,
 414                         SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 415         clk_register_clkdev(clk, "vco1_mclk", NULL);
 416         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
 417                         0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
 418                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 419         clk_register_clkdev(clk, "vco1_clk", NULL);
 420         clk_register_clkdev(clk1, "pll1_clk", NULL);
 421
 422         clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
 423                         ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
 424                         SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT,
 425                         SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 426         clk_register_clkdev(clk, "vco2_mclk", NULL);
 427         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
 428                         0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
 429                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 430         clk_register_clkdev(clk, "vco2_clk", NULL);
 431         clk_register_clkdev(clk1, "pll2_clk", NULL);
 432
 433         clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
 434                         ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
 435                         SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT,
 436                         SPEAR1310_PLL_CLK_MASK, 0, &_lock);
 437         clk_register_clkdev(clk, "vco3_mclk", NULL);
 438         clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
 439                         0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
 440                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 441         clk_register_clkdev(clk, "vco3_clk", NULL);
 442         clk_register_clkdev(clk1, "pll3_clk", NULL);
 443
 444         clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
 445                         0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
 446                         ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
 447         clk_register_clkdev(clk, "vco4_clk", NULL);
 448         clk_register_clkdev(clk1, "pll4_clk", NULL);
 449
 450         clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
 451                         48000000);
 452         clk_register_clkdev(clk, "pll5_clk", NULL);
 453
 454         clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
 455                         25000000);
 456         clk_register_clkdev(clk, "pll6_clk", NULL);
 457
 458         /* vco div n clocks */
 459         clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
 460                         2);
 461         clk_register_clkdev(clk, "vco1div2_clk", NULL);
 462
 463         clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
 464                         4);
 465         clk_register_clkdev(clk, "vco1div4_clk", NULL);
 466
 467         clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
 468                         2);
 469         clk_register_clkdev(clk, "vco2div2_clk", NULL);
 470
 471         clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
 472                         2);
 473         clk_register_clkdev(clk, "vco3div2_clk", NULL);
 474
 475         /* peripherals */
 476         clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
 477                         128);
 478         clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
 479                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
 480                         &_lock);
 481         clk_register_clkdev(clk, NULL, "spear_thermal");
 482
 483         /* clock derived from pll4 clk */
 484         clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
 485                         1);
 486         clk_register_clkdev(clk, "ddr_clk", NULL);
 487
 488         /* clock derived from pll1 clk */
 489         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
 490                         CLK_SET_RATE_PARENT, 1, 2);
 491         clk_register_clkdev(clk, "cpu_clk", NULL);
 492
 493         clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
 494                         2);
 495         clk_register_clkdev(clk, NULL, "ec800620.wdt");
 496
 497         clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
 498                         2);
 499         clk_register_clkdev(clk, NULL, "smp_twd");
 500
 501         clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
 502                         6);
 503         clk_register_clkdev(clk, "ahb_clk", NULL);
 504
 505         clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
 506                         12);
 507         clk_register_clkdev(clk, "apb_clk", NULL);
 508
 509         /* gpt clocks */
 510         clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
 511                         ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
 512                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT,
 513                         SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 514         clk_register_clkdev(clk, "gpt0_mclk", NULL);
 515         clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 516                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
 517                         &_lock);
 518         clk_register_clkdev(clk, NULL, "gpt0");
 519
 520         clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
 521                         ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
 522                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT,
 523                         SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 524         clk_register_clkdev(clk, "gpt1_mclk", NULL);
 525         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 526                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
 527                         &_lock);
 528         clk_register_clkdev(clk, NULL, "gpt1");
 529
 530         clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
 531                         ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
 532                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT,
 533                         SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 534         clk_register_clkdev(clk, "gpt2_mclk", NULL);
 535         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 536                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
 537                         &_lock);
 538         clk_register_clkdev(clk, NULL, "gpt2");
 539
 540         clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
 541                         ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
 542                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT,
 543                         SPEAR1310_GPT_CLK_MASK, 0, &_lock);
 544         clk_register_clkdev(clk, "gpt3_mclk", NULL);
 545         clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 546                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
 547                         &_lock);
 548         clk_register_clkdev(clk, NULL, "gpt3");
 549
 550         /* others */
 551         clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
 552                         0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
 553                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 554         clk_register_clkdev(clk, "uart_syn_clk", NULL);
 555         clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 556
 557         clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
 558                         ARRAY_SIZE(uart0_parents),
 559                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 560                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
 561                         SPEAR1310_UART_CLK_MASK, 0, &_lock);
 562         clk_register_clkdev(clk, "uart0_mclk", NULL);
 563
 564         clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
 565                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 566                         SPEAR1310_UART_CLK_ENB, 0, &_lock);
 567         clk_register_clkdev(clk, NULL, "e0000000.serial");
 568
 569         clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
 570                         "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
 571                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 572         clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
 573         clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
 574
 575         clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
 576                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 577                         SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
 578         clk_register_clkdev(clk, NULL, "b3000000.sdhci");
 579
 580         clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
 581                         0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
 582                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 583         clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
 584         clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
 585
 586         clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
 587                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 588                         SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
 589         clk_register_clkdev(clk, NULL, "b2800000.cf");
 590         clk_register_clkdev(clk, NULL, "arasan_xd");
 591
 592         clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
 593                         0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
 594                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 595         clk_register_clkdev(clk, "c3_syn_clk", NULL);
 596         clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 597
 598         clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
 599                         ARRAY_SIZE(c3_parents),
 600                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 601                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
 602                         SPEAR1310_C3_CLK_MASK, 0, &_lock);
 603         clk_register_clkdev(clk, "c3_mclk", NULL);
 604
 605         clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
 606                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
 607                         &_lock);
 608         clk_register_clkdev(clk, NULL, "c3");
 609
 610         /* gmac */
 611         clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
 612                         ARRAY_SIZE(gmac_phy_input_parents),
 613                         CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
 614                         SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
 615                         SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 616         clk_register_clkdev(clk, "phy_input_mclk", NULL);
 617
 618         clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
 619                         0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
 620                         ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
 621         clk_register_clkdev(clk, "phy_syn_clk", NULL);
 622         clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 623
 624         clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
 625                         ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
 626                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 627                         SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
 628         clk_register_clkdev(clk, "stmmacphy.0", NULL);
 629
 630         /* clcd */
 631         clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
 632                         ARRAY_SIZE(clcd_synth_parents),
 633                         CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
 634                         SPEAR1310_CLCD_SYNT_CLK_SHIFT,
 635                         SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
 636         clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 637
 638         clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
 639                         SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
 640                         ARRAY_SIZE(clcd_rtbl), &_lock);
 641         clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 642
 643         clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
 644                         ARRAY_SIZE(clcd_pixel_parents),
 645                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 646                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
 647                         SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
 648         clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
 649
 650         clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
 651                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
 652                         &_lock);
 653         clk_register_clkdev(clk, NULL, "e1000000.clcd");
 654
 655         /* i2s */
 656         clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
 657                         ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
 658                         SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT,
 659                         SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock);
 660         clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 661
 662         clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
 663                         SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
 664                         ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
 665         clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 666
 667         clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
 668                         ARRAY_SIZE(i2s_ref_parents),
 669                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 670                         SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
 671                         SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
 672         clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
 673
 674         clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
 675                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
 676                         0, &_lock);
 677         clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
 678
 679         clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
 680                         "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
 681                         &i2s_sclk_masks, i2s_sclk_rtbl,
 682                         ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
 683         clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
 684         clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
 685
 686         /* clock derived from ahb clk */
 687         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
 688                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
 689                         &_lock);
 690         clk_register_clkdev(clk, NULL, "e0280000.i2c");
 691
 692         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
 693                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
 694                         &_lock);
 695         clk_register_clkdev(clk, NULL, "ea800000.dma");
 696         clk_register_clkdev(clk, NULL, "eb000000.dma");
 697
 698         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
 699                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
 700                         &_lock);
 701         clk_register_clkdev(clk, NULL, "b2000000.jpeg");
 702
 703         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
 704                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
 705                         &_lock);
 706         clk_register_clkdev(clk, NULL, "e2000000.eth");
 707
 708         clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
 709                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
 710                         &_lock);
 711         clk_register_clkdev(clk, NULL, "b0000000.flash");
 712
 713         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
 714                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
 715                         &_lock);
 716         clk_register_clkdev(clk, NULL, "ea000000.flash");
 717
 718         clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
 719                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
 720                         &_lock);
 721         clk_register_clkdev(clk, NULL, "e4000000.ohci");
 722         clk_register_clkdev(clk, NULL, "e4800000.ehci");
 723
 724         clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
 725                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
 726                         &_lock);
 727         clk_register_clkdev(clk, NULL, "e5000000.ohci");
 728         clk_register_clkdev(clk, NULL, "e5800000.ehci");
 729
 730         clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
 731                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
 732                         &_lock);
 733         clk_register_clkdev(clk, NULL, "e3800000.otg");
 734
 735         clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 736                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 737                         0, &_lock);
 738         clk_register_clkdev(clk, NULL, "b1000000.pcie");
 739         clk_register_clkdev(clk, NULL, "b1000000.ahci");
 740
 741         clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 742                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 743                         0, &_lock);
 744         clk_register_clkdev(clk, NULL, "b1800000.pcie");
 745         clk_register_clkdev(clk, NULL, "b1800000.ahci");
 746
 747         clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 748                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 749                         0, &_lock);
 750         clk_register_clkdev(clk, NULL, "b4000000.pcie");
 751         clk_register_clkdev(clk, NULL, "b4000000.ahci");
 752
 753         clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
 754                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
 755                         &_lock);
 756         clk_register_clkdev(clk, "sysram0_clk", NULL);
 757
 758         clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
 759                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
 760                         &_lock);
 761         clk_register_clkdev(clk, "sysram1_clk", NULL);
 762
 763         clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
 764                         0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
 765                         ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
 766         clk_register_clkdev(clk, "adc_syn_clk", NULL);
 767         clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
 768
 769         clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
 770                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 771                         SPEAR1310_ADC_CLK_ENB, 0, &_lock);
 772         clk_register_clkdev(clk, NULL, "e0080000.adc");
 773
 774         /* clock derived from apb clk */
 775         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
 776                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
 777                         &_lock);
 778         clk_register_clkdev(clk, NULL, "e0100000.spi");
 779
 780         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
 781                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
 782                         &_lock);
 783         clk_register_clkdev(clk, NULL, "e0600000.gpio");
 784
 785         clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
 786                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
 787                         &_lock);
 788         clk_register_clkdev(clk, NULL, "e0680000.gpio");
 789
 790         clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
 791                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
 792                         &_lock);
 793         clk_register_clkdev(clk, NULL, "e0180000.i2s");
 794
 795         clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
 796                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
 797                         &_lock);
 798         clk_register_clkdev(clk, NULL, "e0200000.i2s");
 799
 800         clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
 801                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
 802                         &_lock);
 803         clk_register_clkdev(clk, NULL, "e0300000.kbd");
 804
 805         /* RAS clks */
 806         clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
 807                         ARRAY_SIZE(gen_synth0_1_parents),
 808                         CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
 809                         SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
 810                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 811         clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
 812
 813         clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
 814                         ARRAY_SIZE(gen_synth2_3_parents),
 815                         CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
 816                         SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
 817                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 818         clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
 819
 820         clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
 821                         SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 822                         &_lock);
 823         clk_register_clkdev(clk, "gen_syn0_clk", NULL);
 824
 825         clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
 826                         SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 827                         &_lock);
 828         clk_register_clkdev(clk, "gen_syn1_clk", NULL);
 829
 830         clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
 831                         SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 832                         &_lock);
 833         clk_register_clkdev(clk, "gen_syn2_clk", NULL);
 834
 835         clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
 836                         SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 837                         &_lock);
 838         clk_register_clkdev(clk, "gen_syn3_clk", NULL);
 839
 840         clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
 841                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
 842                         &_lock);
 843         clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
 844
 845         clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
 846                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
 847                         &_lock);
 848         clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
 849
 850         clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
 851                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
 852                         &_lock);
 853         clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
 854
 855         clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
 856                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
 857                         &_lock);
 858         clk_register_clkdev(clk, "ras_pll2_clk", NULL);
 859
 860         clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
 861                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
 862                         &_lock);
 863         clk_register_clkdev(clk, "ras_pll3_clk", NULL);
 864
 865         clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
 866                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
 867                         &_lock);
 868         clk_register_clkdev(clk, "ras_tx125_clk", NULL);
 869
 870         clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
 871                         30000000);
 872         clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
 873                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
 874                         &_lock);
 875         clk_register_clkdev(clk, "ras_30m_clk", NULL);
 876
 877         clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
 878                         48000000);
 879         clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
 880                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
 881                         &_lock);
 882         clk_register_clkdev(clk, "ras_48m_clk", NULL);
 883
 884         clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
 885                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
 886                         &_lock);
 887         clk_register_clkdev(clk, "ras_ahb_clk", NULL);
 888
 889         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
 890                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
 891                         &_lock);
 892         clk_register_clkdev(clk, "ras_apb_clk", NULL);
 893
 894         clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, 0,
 895                         50000000);
 896
 897         clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, 0, 50000000);
 898
 899         clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
 900                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
 901                         &_lock);
 902         clk_register_clkdev(clk, NULL, "c_can_platform.0");
 903
 904         clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
 905                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
 906                         &_lock);
 907         clk_register_clkdev(clk, NULL, "c_can_platform.1");
 908
 909         clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
 910                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
 911                         &_lock);
 912         clk_register_clkdev(clk, NULL, "5c400000.eth");
 913
 914         clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
 915                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
 916                         &_lock);
 917         clk_register_clkdev(clk, NULL, "5c500000.eth");
 918
 919         clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
 920                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
 921                         &_lock);
 922         clk_register_clkdev(clk, NULL, "5c600000.eth");
 923
 924         clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
 925                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
 926                         &_lock);
 927         clk_register_clkdev(clk, NULL, "5c700000.eth");
 928
 929         clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
 930                         smii_rgmii_phy_parents,
 931                         ARRAY_SIZE(smii_rgmii_phy_parents),
 932                         CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
 933                         SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 934                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 935         clk_register_clkdev(clk, "stmmacphy.1", NULL);
 936         clk_register_clkdev(clk, "stmmacphy.2", NULL);
 937         clk_register_clkdev(clk, "stmmacphy.4", NULL);
 938
 939         clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
 940                         ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
 941                         SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 942                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 943         clk_register_clkdev(clk, "stmmacphy.3", NULL);
 944
 945         clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
 946                         ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
 947                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT,
 948                         SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 949         clk_register_clkdev(clk, "uart1_mclk", NULL);
 950
 951         clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
 952                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
 953                         &_lock);
 954         clk_register_clkdev(clk, NULL, "5c800000.serial");
 955
 956         clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
 957                         ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
 958                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT,
 959                         SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 960         clk_register_clkdev(clk, "uart2_mclk", NULL);
 961
 962         clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
 963                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
 964                         &_lock);
 965         clk_register_clkdev(clk, NULL, "5c900000.serial");
 966
 967         clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
 968                         ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
 969                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT,
 970                         SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 971         clk_register_clkdev(clk, "uart3_mclk", NULL);
 972
 973         clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
 974                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
 975                         &_lock);
 976         clk_register_clkdev(clk, NULL, "5ca00000.serial");
 977
 978         clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
 979                         ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
 980                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT,
 981                         SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 982         clk_register_clkdev(clk, "uart4_mclk", NULL);
 983
 984         clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
 985                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
 986                         &_lock);
 987         clk_register_clkdev(clk, NULL, "5cb00000.serial");
 988
 989         clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
 990                         ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
 991                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT,
 992                         SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
 993         clk_register_clkdev(clk, "uart5_mclk", NULL);
 994
 995         clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
 996                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
 997                         &_lock);
 998         clk_register_clkdev(clk, NULL, "5cc00000.serial");
 999
1000         clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
1001                         ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1002                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT,
1003                         SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1004         clk_register_clkdev(clk, "i2c1_mclk", NULL);
1005
1006         clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
1007                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
1008                         &_lock);
1009         clk_register_clkdev(clk, NULL, "5cd00000.i2c");
1010
1011         clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
1012                         ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1013                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT,
1014                         SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1015         clk_register_clkdev(clk, "i2c2_mclk", NULL);
1016
1017         clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
1018                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1019                         &_lock);
1020         clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1021
1022         clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1023                         ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1024                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT,
1025                         SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1026         clk_register_clkdev(clk, "i2c3_mclk", NULL);
1027
1028         clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
1029                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1030                         &_lock);
1031         clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1032
1033         clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1034                         ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1035                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT,
1036                         SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1037         clk_register_clkdev(clk, "i2c4_mclk", NULL);
1038
1039         clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
1040                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1041                         &_lock);
1042         clk_register_clkdev(clk, NULL, "5d000000.i2c");
1043
1044         clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1045                         ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1046                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT,
1047                         SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1048         clk_register_clkdev(clk, "i2c5_mclk", NULL);
1049
1050         clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
1051                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1052                         &_lock);
1053         clk_register_clkdev(clk, NULL, "5d100000.i2c");
1054
1055         clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1056                         ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1057                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT,
1058                         SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1059         clk_register_clkdev(clk, "i2c6_mclk", NULL);
1060
1061         clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
1062                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1063                         &_lock);
1064         clk_register_clkdev(clk, NULL, "5d200000.i2c");
1065
1066         clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1067                         ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1068                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT,
1069                         SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1070         clk_register_clkdev(clk, "i2c7_mclk", NULL);
1071
1072         clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
1073                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1074                         &_lock);
1075         clk_register_clkdev(clk, NULL, "5d300000.i2c");
1076
1077         clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1078                         ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
1079                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT,
1080                         SPEAR1310_SSP1_CLK_MASK, 0, &_lock);
1081         clk_register_clkdev(clk, "ssp1_mclk", NULL);
1082
1083         clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
1084                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1085                         &_lock);
1086         clk_register_clkdev(clk, NULL, "5d400000.spi");
1087
1088         clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1089                         ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
1090                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT,
1091                         SPEAR1310_PCI_CLK_MASK, 0, &_lock);
1092         clk_register_clkdev(clk, "pci_mclk", NULL);
1093
1094         clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
1095                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1096                         &_lock);
1097         clk_register_clkdev(clk, NULL, "pci");
1098
1099         clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1100                         ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1101                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT,
1102                         SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1103         clk_register_clkdev(clk, "tdm1_mclk", NULL);
1104
1105         clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
1106                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1107                         &_lock);
1108         clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1109
1110         clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1111                         ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1112                         SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT,
1113                         SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1114         clk_register_clkdev(clk, "tdm2_mclk", NULL);
1115
1116         clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
1117                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1118                         &_lock);
1119         clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1120 }