drivers/clk/qcom/gcc-ipq9574.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (c) 2023 The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/regmap.h>
  13
  14 #include <linux/reset-controller.h>
  15 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
  16 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
  17
  18 #include "clk-rcg.h"
  19 #include "clk-branch.h"
  20 #include "clk-alpha-pll.h"
  21 #include "clk-regmap-divider.h"
  22 #include "clk-regmap-mux.h"
  23 #include "clk-regmap-phy-mux.h"
  24 #include "reset.h"
  25
  26 /* Need to match the order of clocks in DT binding */
  27 enum {
  28         DT_XO,
  29         DT_SLEEP_CLK,
  30         DT_BIAS_PLL_UBI_NC_CLK,
  31         DT_PCIE30_PHY0_PIPE_CLK,
  32         DT_PCIE30_PHY1_PIPE_CLK,
  33         DT_PCIE30_PHY2_PIPE_CLK,
  34         DT_PCIE30_PHY3_PIPE_CLK,
  35         DT_USB3PHY_0_CC_PIPE_CLK,
  36 };
  37
  38 enum {
  39         P_XO,
  40         P_PCIE30_PHY0_PIPE,
  41         P_PCIE30_PHY1_PIPE,
  42         P_PCIE30_PHY2_PIPE,
  43         P_PCIE30_PHY3_PIPE,
  44         P_USB3PHY_0_PIPE,
  45         P_GPLL0,
  46         P_GPLL0_DIV2,
  47         P_GPLL0_OUT_AUX,
  48         P_GPLL2,
  49         P_GPLL4,
  50         P_PI_SLEEP,
  51         P_BIAS_PLL_UBI_NC_CLK,
  52 };
  53
  54 static const struct parent_map gcc_xo_map[] = {
  55         { P_XO, 0 },
  56 };
  57
  58 static const struct clk_parent_data gcc_xo_data[] = {
  59         { .index = DT_XO },
  60 };
  61
  62 static const struct clk_parent_data gcc_sleep_clk_data[] = {
  63         { .index = DT_SLEEP_CLK },
  64 };
  65
  66 static struct clk_alpha_pll gpll0_main = {
  67         .offset = 0x20000,
  68         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  69         .clkr = {
  70                 .enable_reg = 0x0b000,
  71                 .enable_mask = BIT(0),
  72                 .hw.init = &(struct clk_init_data) {
  73                         .name = "gpll0_main",
  74                         .parent_data = gcc_xo_data,
  75                         .num_parents = ARRAY_SIZE(gcc_xo_data),
  76                         .ops = &clk_alpha_pll_ops,
  77                 },
  78         },
  79 };
  80
  81 static struct clk_fixed_factor gpll0_out_main_div2 = {
  82         .mult = 1,
  83         .div = 2,
  84         .hw.init = &(struct clk_init_data) {
  85                 .name = "gpll0_out_main_div2",
  86                 .parent_hws = (const struct clk_hw *[]) {
  87                         &gpll0_main.clkr.hw
  88                 },
  89                 .num_parents = 1,
  90                 .flags = CLK_SET_RATE_PARENT,
  91                 .ops = &clk_fixed_factor_ops,
  92         },
  93 };
  94
  95 static struct clk_alpha_pll_postdiv gpll0 = {
  96         .offset = 0x20000,
  97         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  98         .width = 4,
  99         .clkr.hw.init = &(struct clk_init_data) {
 100                 .name = "gpll0",
 101                 .parent_hws = (const struct clk_hw *[]) {
 102                         &gpll0_main.clkr.hw
 103                 },
 104                 .num_parents = 1,
 105                 .flags = CLK_SET_RATE_PARENT,
 106                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 107         },
 108 };
 109
 110 static struct clk_alpha_pll gpll4_main = {
 111         .offset = 0x22000,
 112         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 113         .clkr = {
 114                 .enable_reg = 0x0b000,
 115                 .enable_mask = BIT(2),
 116                 .hw.init = &(struct clk_init_data) {
 117                         .name = "gpll4_main",
 118                         .parent_data = gcc_xo_data,
 119                         .num_parents = ARRAY_SIZE(gcc_xo_data),
 120                         .ops = &clk_alpha_pll_ops,
 121                 },
 122         },
 123 };
 124
 125 static struct clk_alpha_pll_postdiv gpll4 = {
 126         .offset = 0x22000,
 127         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 128         .width = 4,
 129         .clkr.hw.init = &(struct clk_init_data) {
 130                 .name = "gpll4",
 131                 .parent_hws = (const struct clk_hw *[]) {
 132                         &gpll4_main.clkr.hw
 133                 },
 134                 .num_parents = 1,
 135                 .flags = CLK_SET_RATE_PARENT,
 136                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 137         },
 138 };
 139
 140 static struct clk_alpha_pll gpll2_main = {
 141         .offset = 0x21000,
 142         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 143         .clkr = {
 144                 .enable_reg = 0x0b000,
 145                 .enable_mask = BIT(1),
 146                 .hw.init = &(struct clk_init_data) {
 147                         .name = "gpll2_main",
 148                         .parent_data = gcc_xo_data,
 149                         .num_parents = ARRAY_SIZE(gcc_xo_data),
 150                         .ops = &clk_alpha_pll_ops,
 151                 },
 152         },
 153 };
 154
 155 static struct clk_alpha_pll_postdiv gpll2 = {
 156         .offset = 0x21000,
 157         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 158         .width = 4,
 159         .clkr.hw.init = &(struct clk_init_data) {
 160                 .name = "gpll2",
 161                 .parent_hws = (const struct clk_hw *[]) {
 162                         &gpll2_main.clkr.hw
 163                 },
 164                 .num_parents = 1,
 165                 .flags = CLK_SET_RATE_PARENT,
 166                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 167         },
 168 };
 169
 170 static struct clk_branch gcc_sleep_clk_src = {
 171         .halt_reg = 0x3400c,
 172         .clkr = {
 173                 .enable_reg = 0x3400c,
 174                 .enable_mask = BIT(1),
 175                 .hw.init = &(struct clk_init_data) {
 176                         .name = "gcc_sleep_clk_src",
 177                         .parent_data = gcc_sleep_clk_data,
 178                         .num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
 179                         .flags = CLK_IS_CRITICAL,
 180                         .ops = &clk_branch2_ops,
 181                 },
 182         },
 183 };
 184
 185 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
 186         { .index = DT_XO },
 187         { .hw = &gpll0.clkr.hw },
 188         { .hw = &gpll0_out_main_div2.hw },
 189 };
 190
 191 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 192         { P_XO, 0 },
 193         { P_GPLL0, 1 },
 194         { P_GPLL0_DIV2, 4 },
 195 };
 196
 197 static const struct clk_parent_data gcc_xo_gpll0[] = {
 198         { .index = DT_XO },
 199         { .hw = &gpll0.clkr.hw },
 200 };
 201
 202 static const struct parent_map gcc_xo_gpll0_map[] = {
 203         { P_XO, 0 },
 204         { P_GPLL0, 1 },
 205 };
 206
 207 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 208         { .index = DT_XO },
 209         { .hw = &gpll0.clkr.hw },
 210         { .hw = &gpll4.clkr.hw },
 211 };
 212
 213 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 214         { P_XO, 0 },
 215         { P_GPLL0, 1 },
 216         { P_GPLL4, 2 },
 217 };
 218
 219 static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
 220         { .index = DT_XO },
 221         { .hw = &gpll0.clkr.hw },
 222         { .hw = &gpll0_out_main_div2.hw },
 223         { .hw = &gpll0.clkr.hw },
 224 };
 225
 226 static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
 227         { P_XO, 0 },
 228         { P_GPLL0, 1 },
 229         { P_GPLL0_DIV2, 4 },
 230         { P_GPLL0, 5 },
 231 };
 232
 233 static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = {
 234         { .index = DT_XO },
 235         { .hw = &gpll0.clkr.hw },
 236         { .hw = &gpll0_out_main_div2.hw },
 237         { .index = DT_SLEEP_CLK },
 238 };
 239
 240 static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = {
 241         { P_XO, 0 },
 242         { P_GPLL0, 1 },
 243         { P_GPLL0_DIV2, 4 },
 244         { P_PI_SLEEP, 6 },
 245 };
 246
 247 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
 248         { .index = DT_XO },
 249         { .hw = &gpll0.clkr.hw },
 250         { .index = DT_SLEEP_CLK },
 251 };
 252
 253 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
 254         { P_XO, 0 },
 255         { P_GPLL0, 2 },
 256         { P_PI_SLEEP, 6 },
 257 };
 258
 259 static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = {
 260         { .index = DT_XO },
 261         { .hw = &gpll0.clkr.hw },
 262         { .hw = &gpll4.clkr.hw },
 263         { .index = DT_BIAS_PLL_UBI_NC_CLK },
 264 };
 265
 266 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = {
 267         { P_XO, 0 },
 268         { P_GPLL0, 1 },
 269         { P_GPLL4, 2 },
 270         { P_BIAS_PLL_UBI_NC_CLK, 3 },
 271 };
 272
 273 static const struct clk_parent_data
 274                         gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = {
 275         { .index = DT_XO },
 276         { .hw = &gpll0.clkr.hw },
 277         { .hw = &gpll0.clkr.hw },
 278         { .index = DT_SLEEP_CLK },
 279 };
 280
 281 static const struct parent_map
 282                         gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = {
 283         { P_XO, 0 },
 284         { P_GPLL0, 1 },
 285         { P_GPLL0_OUT_AUX, 2 },
 286         { P_PI_SLEEP, 6 },
 287 };
 288
 289 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 290         { .index = DT_XO },
 291         { .hw = &gpll0.clkr.hw },
 292         { .hw = &gpll0_out_main_div2.hw },
 293 };
 294
 295 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 296         { P_XO, 0 },
 297         { P_GPLL0, 1 },
 298         { P_GPLL0_DIV2, 4 },
 299 };
 300
 301 static const struct clk_parent_data
 302                         gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
 303         { .index = DT_XO },
 304         { .hw = &gpll4.clkr.hw },
 305         { .hw = &gpll0.clkr.hw },
 306         { .hw = &gpll0_out_main_div2.hw },
 307 };
 308
 309 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = {
 310         { P_XO, 0 },
 311         { P_GPLL4, 1 },
 312         { P_GPLL0, 3 },
 313         { P_GPLL0_DIV2, 4 },
 314 };
 315
 316 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 317         { .index = DT_USB3PHY_0_CC_PIPE_CLK },
 318         { .index = DT_XO },
 319 };
 320
 321 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 322         { P_USB3PHY_0_PIPE, 0 },
 323         { P_XO, 2 },
 324 };
 325
 326 static const struct clk_parent_data
 327                         gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
 328         { .index = DT_XO },
 329         { .hw = &gpll0.clkr.hw },
 330         { .hw = &gpll2.clkr.hw },
 331         { .hw = &gpll0_out_main_div2.hw },
 332 };
 333
 334 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
 335         { P_XO, 0 },
 336         { P_GPLL0, 1 },
 337         { P_GPLL2, 2 },
 338         { P_GPLL0_DIV2, 4 },
 339 };
 340
 341 static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = {
 342         { .index = DT_XO},
 343         { .hw = &gpll0.clkr.hw },
 344         { .hw = &gpll4.clkr.hw },
 345         { .hw = &gpll0_out_main_div2.hw },
 346 };
 347
 348 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = {
 349         { P_XO, 0 },
 350         { P_GPLL0, 1 },
 351         { P_GPLL4, 2 },
 352         { P_GPLL0_DIV2, 4 },
 353 };
 354
 355 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
 356         { .index = DT_XO },
 357         { .hw = &gpll4.clkr.hw },
 358         { .hw = &gpll0.clkr.hw },
 359         { .hw = &gpll0_out_main_div2.hw },
 360 };
 361
 362 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
 363         { P_XO, 0 },
 364         { P_GPLL4, 1 },
 365         { P_GPLL0, 2 },
 366         { P_GPLL0_DIV2, 4 },
 367 };
 368
 369 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
 370         { .index = DT_XO },
 371         { .hw = &gpll0.clkr.hw },
 372         { .hw = &gpll2.clkr.hw },
 373 };
 374
 375 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 376         { P_XO, 0 },
 377         { P_GPLL0, 1 },
 378         { P_GPLL2, 2 },
 379 };
 380
 381 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = {
 382         { .index = DT_XO },
 383         { .hw = &gpll0.clkr.hw },
 384         { .hw = &gpll2.clkr.hw },
 385         { .hw = &gpll4.clkr.hw },
 386         { .index = DT_SLEEP_CLK },
 387 };
 388
 389 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = {
 390         { P_XO, 0 },
 391         { P_GPLL0, 1 },
 392         { P_GPLL2, 2 },
 393         { P_GPLL4, 3 },
 394         { P_PI_SLEEP, 6 },
 395 };
 396
 397 static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = {
 398         { .index = DT_XO },
 399         { .hw = &gpll0.clkr.hw },
 400         { .hw = &gpll0.clkr.hw },
 401         { .hw = &gpll2.clkr.hw },
 402 };
 403
 404 static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = {
 405         { P_XO, 0 },
 406         { P_GPLL0, 1 },
 407         { P_GPLL0_OUT_AUX, 2 },
 408         { P_GPLL2, 3 },
 409 };
 410
 411 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 412         F(24000000, P_XO, 1, 0, 0),
 413         F(50000000, P_GPLL0, 16, 0, 0),
 414         F(100000000, P_GPLL0, 8, 0, 0),
 415         { }
 416 };
 417
 418 static struct clk_rcg2 apss_ahb_clk_src = {
 419         .cmd_rcgr = 0x2400c,
 420         .freq_tbl = ftbl_apss_ahb_clk_src,
 421         .hid_width = 5,
 422         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 423         .clkr.hw.init = &(struct clk_init_data) {
 424                 .name = "apss_ahb_clk_src",
 425                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 426                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 427                 .ops = &clk_rcg2_ops,
 428         },
 429 };
 430
 431 static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
 432         F(533000000, P_GPLL0, 1.5, 0, 0),
 433         { }
 434 };
 435
 436 static struct clk_rcg2 apss_axi_clk_src = {
 437         .cmd_rcgr = 0x24004,
 438         .freq_tbl = ftbl_apss_axi_clk_src,
 439         .hid_width = 5,
 440         .parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,
 441         .clkr.hw.init = &(struct clk_init_data) {
 442                 .name = "apss_axi_clk_src",
 443                 .parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,
 444                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),
 445                 .ops = &clk_rcg2_ops,
 446         },
 447 };
 448
 449 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 450         F(9600000, P_XO, 2.5, 0, 0),
 451         F(24000000, P_XO, 1, 0, 0),
 452         F(50000000, P_GPLL0, 16, 0, 0),
 453         { }
 454 };
 455
 456 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 457         .cmd_rcgr = 0x02018,
 458         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 459         .hid_width = 5,
 460         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 461         .clkr.hw.init = &(struct clk_init_data) {
 462                 .name = "blsp1_qup1_i2c_apps_clk_src",
 463                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 464                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 465                 .ops = &clk_rcg2_ops,
 466         },
 467 };
 468
 469 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 470         F(960000, P_XO, 10, 2, 5),
 471         F(4800000, P_XO, 5, 0, 0),
 472         F(9600000, P_XO, 2, 4, 5),
 473         F(16000000, P_GPLL0, 10, 1, 5),
 474         F(24000000, P_XO, 1, 0, 0),
 475         F(25000000, P_GPLL0, 16, 1, 2),
 476         F(50000000, P_GPLL0, 16, 0, 0),
 477         { }
 478 };
 479
 480 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 481         .cmd_rcgr = 0x02004,
 482         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 483         .mnd_width = 8,
 484         .hid_width = 5,
 485         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 486         .clkr.hw.init = &(struct clk_init_data) {
 487                 .name = "blsp1_qup1_spi_apps_clk_src",
 488                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 489                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 490                 .ops = &clk_rcg2_ops,
 491         },
 492 };
 493
 494 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 495         .cmd_rcgr = 0x03018,
 496         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 497         .hid_width = 5,
 498         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 499         .clkr.hw.init = &(struct clk_init_data) {
 500                 .name = "blsp1_qup2_i2c_apps_clk_src",
 501                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 502                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 503                 .ops = &clk_rcg2_ops,
 504         },
 505 };
 506
 507 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 508         .cmd_rcgr = 0x03004,
 509         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 510         .mnd_width = 8,
 511         .hid_width = 5,
 512         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 513         .clkr.hw.init = &(struct clk_init_data) {
 514                 .name = "blsp1_qup2_spi_apps_clk_src",
 515                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 516                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 517                 .ops = &clk_rcg2_ops,
 518         },
 519 };
 520
 521 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 522         .cmd_rcgr = 0x04018,
 523         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 524         .hid_width = 5,
 525         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 526         .clkr.hw.init = &(struct clk_init_data) {
 527                 .name = "blsp1_qup3_i2c_apps_clk_src",
 528                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 529                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 530                 .ops = &clk_rcg2_ops,
 531         },
 532 };
 533
 534 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 535         .cmd_rcgr = 0x04004,
 536         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 537         .mnd_width = 8,
 538         .hid_width = 5,
 539         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 540         .clkr.hw.init = &(struct clk_init_data) {
 541                 .name = "blsp1_qup3_spi_apps_clk_src",
 542                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 543                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 544                 .ops = &clk_rcg2_ops,
 545         },
 546 };
 547
 548 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 549         .cmd_rcgr = 0x05018,
 550         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 551         .hid_width = 5,
 552         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 553         .clkr.hw.init = &(struct clk_init_data) {
 554                 .name = "blsp1_qup4_i2c_apps_clk_src",
 555                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 556                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 557                 .ops = &clk_rcg2_ops,
 558         },
 559 };
 560
 561 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 562         .cmd_rcgr = 0x05004,
 563         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 564         .mnd_width = 8,
 565         .hid_width = 5,
 566         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 567         .clkr.hw.init = &(struct clk_init_data) {
 568                 .name = "blsp1_qup4_spi_apps_clk_src",
 569                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 570                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 571                 .ops = &clk_rcg2_ops,
 572         },
 573 };
 574
 575 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 576         .cmd_rcgr = 0x06018,
 577         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 578         .hid_width = 5,
 579         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 580         .clkr.hw.init = &(struct clk_init_data) {
 581                 .name = "blsp1_qup5_i2c_apps_clk_src",
 582                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 583                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 584                 .ops = &clk_rcg2_ops,
 585         },
 586 };
 587
 588 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 589         .cmd_rcgr = 0x06004,
 590         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 591         .mnd_width = 8,
 592         .hid_width = 5,
 593         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 594         .clkr.hw.init = &(struct clk_init_data) {
 595                 .name = "blsp1_qup5_spi_apps_clk_src",
 596                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 597                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 598                 .ops = &clk_rcg2_ops,
 599         },
 600 };
 601
 602 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 603         .cmd_rcgr = 0x07018,
 604         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 605         .hid_width = 5,
 606         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 607         .clkr.hw.init = &(struct clk_init_data) {
 608                 .name = "blsp1_qup6_i2c_apps_clk_src",
 609                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 610                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 611                 .ops = &clk_rcg2_ops,
 612         },
 613 };
 614
 615 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 616         .cmd_rcgr = 0x07004,
 617         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 618         .mnd_width = 8,
 619         .hid_width = 5,
 620         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 621         .clkr.hw.init = &(struct clk_init_data) {
 622                 .name = "blsp1_qup6_spi_apps_clk_src",
 623                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 624                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 625                 .ops = &clk_rcg2_ops,
 626         },
 627 };
 628
 629 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 630         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 631         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 632         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 633         F(24000000, P_XO, 1, 0, 0),
 634         F(25000000, P_GPLL0, 16, 1, 2),
 635         F(32000000, P_GPLL0, 1, 1, 25),
 636         F(40000000, P_GPLL0, 1, 1, 20),
 637         F(46400000, P_GPLL0, 1, 29, 500),
 638         F(48000000, P_GPLL0, 1, 3, 50),
 639         F(51200000, P_GPLL0, 1, 8, 125),
 640         F(56000000, P_GPLL0, 1, 7, 100),
 641         F(58982400, P_GPLL0, 1, 1152, 15625),
 642         F(60000000, P_GPLL0, 1, 3, 40),
 643         F(64000000, P_GPLL0, 12.5, 0, 0),
 644         { }
 645 };
 646
 647 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 648         .cmd_rcgr = 0x0202c,
 649         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 650         .mnd_width = 16,
 651         .hid_width = 5,
 652         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 653         .clkr.hw.init = &(struct clk_init_data) {
 654                 .name = "blsp1_uart1_apps_clk_src",
 655                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 656                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 657                 .ops = &clk_rcg2_ops,
 658         },
 659 };
 660
 661 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 662         .cmd_rcgr = 0x0302c,
 663         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 664         .mnd_width = 16,
 665         .hid_width = 5,
 666         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 667         .clkr.hw.init = &(struct clk_init_data) {
 668                 .name = "blsp1_uart2_apps_clk_src",
 669                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 670                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 671                 .ops = &clk_rcg2_ops,
 672         },
 673 };
 674
 675 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 676         .cmd_rcgr = 0x0402c,
 677         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 678         .mnd_width = 16,
 679         .hid_width = 5,
 680         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 681         .clkr.hw.init = &(struct clk_init_data) {
 682                 .name = "blsp1_uart3_apps_clk_src",
 683                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 684                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 685                 .ops = &clk_rcg2_ops,
 686         },
 687 };
 688
 689 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 690         .cmd_rcgr = 0x0502c,
 691         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 692         .mnd_width = 16,
 693         .hid_width = 5,
 694         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 695         .clkr.hw.init = &(struct clk_init_data) {
 696                 .name = "blsp1_uart4_apps_clk_src",
 697                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 698                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 699                 .ops = &clk_rcg2_ops,
 700         },
 701 };
 702
 703 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 704         .cmd_rcgr = 0x0602c,
 705         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 706         .mnd_width = 16,
 707         .hid_width = 5,
 708         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 709         .clkr.hw.init = &(struct clk_init_data) {
 710                 .name = "blsp1_uart5_apps_clk_src",
 711                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 712                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 713                 .ops = &clk_rcg2_ops,
 714         },
 715 };
 716
 717 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 718         .cmd_rcgr = 0x0702c,
 719         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 720         .mnd_width = 16,
 721         .hid_width = 5,
 722         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 723         .clkr.hw.init = &(struct clk_init_data) {
 724                 .name = "blsp1_uart6_apps_clk_src",
 725                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 726                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 727                 .ops = &clk_rcg2_ops,
 728         },
 729 };
 730
 731 static struct clk_branch gcc_apss_ahb_clk = {
 732         .halt_reg = 0x24018,
 733         .halt_check = BRANCH_HALT_VOTED,
 734         .clkr = {
 735                 .enable_reg = 0x0b004,
 736                 .enable_mask = BIT(0),
 737                 .hw.init = &(struct clk_init_data) {
 738                         .name = "gcc_apss_ahb_clk",
 739                         .parent_hws = (const struct clk_hw *[]) {
 740                                 &apss_ahb_clk_src.clkr.hw
 741                         },
 742                         .num_parents = 1,
 743                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 744                         .ops = &clk_branch2_ops,
 745                 },
 746         },
 747 };
 748
 749 static struct clk_branch gcc_apss_axi_clk = {
 750         .halt_reg = 0x2401c,
 751         .halt_check = BRANCH_HALT_VOTED,
 752         .clkr = {
 753                 .enable_reg = 0x0b004,
 754                 .enable_mask = BIT(1),
 755                 .hw.init = &(struct clk_init_data) {
 756                         .name = "gcc_apss_axi_clk",
 757                         .parent_hws = (const struct clk_hw *[]) {
 758                                 &apss_axi_clk_src.clkr.hw
 759                         },
 760                         .num_parents = 1,
 761                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 762                         .ops = &clk_branch2_ops,
 763                 },
 764         },
 765 };
 766
 767 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 768         .halt_reg = 0x2024,
 769         .clkr = {
 770                 .enable_reg = 0x2024,
 771                 .enable_mask = BIT(0),
 772                 .hw.init = &(struct clk_init_data) {
 773                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
 774                         .parent_hws = (const struct clk_hw *[]) {
 775                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw
 776                         },
 777                         .num_parents = 1,
 778                         .flags = CLK_SET_RATE_PARENT,
 779                         .ops = &clk_branch2_ops,
 780                 },
 781         },
 782 };
 783
 784 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 785         .halt_reg = 0x02020,
 786         .clkr = {
 787                 .enable_reg = 0x02020,
 788                 .enable_mask = BIT(0),
 789                 .hw.init = &(struct clk_init_data) {
 790                         .name = "gcc_blsp1_qup1_spi_apps_clk",
 791                         .parent_hws = (const struct clk_hw *[]) {
 792                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw
 793                         },
 794                         .num_parents = 1,
 795                         .flags = CLK_SET_RATE_PARENT,
 796                         .ops = &clk_branch2_ops,
 797                 },
 798         },
 799 };
 800
 801 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 802         .halt_reg = 0x03024,
 803         .clkr = {
 804                 .enable_reg = 0x03024,
 805                 .enable_mask = BIT(0),
 806                 .hw.init = &(struct clk_init_data) {
 807                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
 808                         .parent_hws = (const struct clk_hw *[]) {
 809                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw
 810                         },
 811                         .num_parents = 1,
 812                         .flags = CLK_SET_RATE_PARENT,
 813                         .ops = &clk_branch2_ops,
 814                 },
 815         },
 816 };
 817
 818 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 819         .halt_reg = 0x03020,
 820         .clkr = {
 821                 .enable_reg = 0x03020,
 822                 .enable_mask = BIT(0),
 823                 .hw.init = &(struct clk_init_data) {
 824                         .name = "gcc_blsp1_qup2_spi_apps_clk",
 825                         .parent_hws = (const struct clk_hw *[]) {
 826                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw
 827                         },
 828                         .num_parents = 1,
 829                         .flags = CLK_SET_RATE_PARENT,
 830                         .ops = &clk_branch2_ops,
 831                 },
 832         },
 833 };
 834
 835 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
 836         .halt_reg = 0x04024,
 837         .clkr = {
 838                 .enable_reg = 0x04024,
 839                 .enable_mask = BIT(0),
 840                 .hw.init = &(struct clk_init_data) {
 841                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
 842                         .parent_hws = (const struct clk_hw *[]) {
 843                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw
 844                         },
 845                         .num_parents = 1,
 846                         .flags = CLK_SET_RATE_PARENT,
 847                         .ops = &clk_branch2_ops,
 848                 },
 849         },
 850 };
 851
 852 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
 853         .halt_reg = 0x04020,
 854         .clkr = {
 855                 .enable_reg = 0x04020,
 856                 .enable_mask = BIT(0),
 857                 .hw.init = &(struct clk_init_data) {
 858                         .name = "gcc_blsp1_qup3_spi_apps_clk",
 859                         .parent_hws = (const struct clk_hw *[]) {
 860                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw
 861                         },
 862                         .num_parents = 1,
 863                         .flags = CLK_SET_RATE_PARENT,
 864                         .ops = &clk_branch2_ops,
 865                 },
 866         },
 867 };
 868
 869 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
 870         .halt_reg = 0x05024,
 871         .clkr = {
 872                 .enable_reg = 0x05024,
 873                 .enable_mask = BIT(0),
 874                 .hw.init = &(struct clk_init_data) {
 875                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
 876                         .parent_hws = (const struct clk_hw *[]) {
 877                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw
 878                         },
 879                         .num_parents = 1,
 880                         .flags = CLK_SET_RATE_PARENT,
 881                         .ops = &clk_branch2_ops,
 882                 },
 883         },
 884 };
 885
 886 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
 887         .halt_reg = 0x05020,
 888         .clkr = {
 889                 .enable_reg = 0x05020,
 890                 .enable_mask = BIT(0),
 891                 .hw.init = &(struct clk_init_data) {
 892                         .name = "gcc_blsp1_qup4_spi_apps_clk",
 893                         .parent_hws = (const struct clk_hw *[]) {
 894                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw
 895                         },
 896                         .num_parents = 1,
 897                         .flags = CLK_SET_RATE_PARENT,
 898                         .ops = &clk_branch2_ops,
 899                 },
 900         },
 901 };
 902
 903 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
 904         .halt_reg = 0x06024,
 905         .clkr = {
 906                 .enable_reg = 0x06024,
 907                 .enable_mask = BIT(0),
 908                 .hw.init = &(struct clk_init_data) {
 909                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
 910                         .parent_hws = (const struct clk_hw *[]) {
 911                                 &blsp1_qup5_i2c_apps_clk_src.clkr.hw
 912                         },
 913                         .num_parents = 1,
 914                         .flags = CLK_SET_RATE_PARENT,
 915                         .ops = &clk_branch2_ops,
 916                 },
 917         },
 918 };
 919
 920 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
 921         .halt_reg = 0x06020,
 922         .clkr = {
 923                 .enable_reg = 0x06020,
 924                 .enable_mask = BIT(0),
 925                 .hw.init = &(struct clk_init_data) {
 926                         .name = "gcc_blsp1_qup5_spi_apps_clk",
 927                         .parent_hws = (const struct clk_hw *[]) {
 928                                 &blsp1_qup5_spi_apps_clk_src.clkr.hw
 929                         },
 930                         .num_parents = 1,
 931                         .flags = CLK_SET_RATE_PARENT,
 932                         .ops = &clk_branch2_ops,
 933                 },
 934         },
 935 };
 936
 937 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
 938         .halt_reg = 0x07024,
 939         .clkr = {
 940                 .enable_reg = 0x07024,
 941                 .enable_mask = BIT(0),
 942                 .hw.init = &(struct clk_init_data) {
 943                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
 944                         .parent_hws = (const struct clk_hw *[]) {
 945                                 &blsp1_qup6_i2c_apps_clk_src.clkr.hw
 946                         },
 947                         .num_parents = 1,
 948                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 949                         .ops = &clk_branch2_ops,
 950                 },
 951         },
 952 };
 953
 954 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
 955         .halt_reg = 0x07020,
 956         .clkr = {
 957                 .enable_reg = 0x07020,
 958                 .enable_mask = BIT(0),
 959                 .hw.init = &(struct clk_init_data) {
 960                         .name = "gcc_blsp1_qup6_spi_apps_clk",
 961                         .parent_hws = (const struct clk_hw *[]) {
 962                                 &blsp1_qup6_spi_apps_clk_src.clkr.hw
 963                         },
 964                         .num_parents = 1,
 965                         .flags = CLK_SET_RATE_PARENT,
 966                         .ops = &clk_branch2_ops,
 967                 },
 968         },
 969 };
 970
 971 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
 972         .halt_reg = 0x02040,
 973         .clkr = {
 974                 .enable_reg = 0x02040,
 975                 .enable_mask = BIT(0),
 976                 .hw.init = &(struct clk_init_data) {
 977                         .name = "gcc_blsp1_uart1_apps_clk",
 978                         .parent_hws = (const struct clk_hw *[]) {
 979                                 &blsp1_uart1_apps_clk_src.clkr.hw
 980                         },
 981                         .num_parents = 1,
 982                         .flags = CLK_SET_RATE_PARENT,
 983                         .ops = &clk_branch2_ops,
 984                 },
 985         },
 986 };
 987
 988 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 989         .halt_reg = 0x03040,
 990         .clkr = {
 991                 .enable_reg = 0x03040,
 992                 .enable_mask = BIT(0),
 993                 .hw.init = &(struct clk_init_data) {
 994                         .name = "gcc_blsp1_uart2_apps_clk",
 995                         .parent_hws = (const struct clk_hw *[]) {
 996                                 &blsp1_uart2_apps_clk_src.clkr.hw
 997                         },
 998                         .num_parents = 1,
 999                         .flags = CLK_SET_RATE_PARENT,
1000                         .ops = &clk_branch2_ops,
1001                 },
1002         },
1003 };
1004
1005 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1006         .halt_reg = 0x04054,
1007         .clkr = {
1008                 .enable_reg = 0x04054,
1009                 .enable_mask = BIT(0),
1010                 .hw.init = &(struct clk_init_data) {
1011                         .name = "gcc_blsp1_uart3_apps_clk",
1012                         .parent_hws = (const struct clk_hw *[]) {
1013                                 &blsp1_uart3_apps_clk_src.clkr.hw
1014                         },
1015                         .num_parents = 1,
1016                         .flags = CLK_SET_RATE_PARENT,
1017                         .ops = &clk_branch2_ops,
1018                 },
1019         },
1020 };
1021
1022 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1023         .halt_reg = 0x05040,
1024         .clkr = {
1025                 .enable_reg = 0x05040,
1026                 .enable_mask = BIT(0),
1027                 .hw.init = &(struct clk_init_data) {
1028                         .name = "gcc_blsp1_uart4_apps_clk",
1029                         .parent_hws = (const struct clk_hw *[]) {
1030                                 &blsp1_uart4_apps_clk_src.clkr.hw
1031                         },
1032                         .num_parents = 1,
1033                         .flags = CLK_SET_RATE_PARENT,
1034                         .ops = &clk_branch2_ops,
1035                 },
1036         },
1037 };
1038
1039 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1040         .halt_reg = 0x06040,
1041         .clkr = {
1042                 .enable_reg = 0x06040,
1043                 .enable_mask = BIT(0),
1044                 .hw.init = &(struct clk_init_data) {
1045                         .name = "gcc_blsp1_uart5_apps_clk",
1046                         .parent_hws = (const struct clk_hw *[]) {
1047                                 &blsp1_uart5_apps_clk_src.clkr.hw
1048                         },
1049                         .num_parents = 1,
1050                         .flags = CLK_SET_RATE_PARENT,
1051                         .ops = &clk_branch2_ops,
1052                 },
1053         },
1054 };
1055
1056 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1057         .halt_reg = 0x07040,
1058         .clkr = {
1059                 .enable_reg = 0x07040,
1060                 .enable_mask = BIT(0),
1061                 .hw.init = &(struct clk_init_data) {
1062                         .name = "gcc_blsp1_uart6_apps_clk",
1063                         .parent_hws = (const struct clk_hw *[]) {
1064                                 &blsp1_uart6_apps_clk_src.clkr.hw
1065                         },
1066                         .num_parents = 1,
1067                         .flags = CLK_SET_RATE_PARENT,
1068                         .ops = &clk_branch2_ops,
1069                 },
1070         },
1071 };
1072
1073 static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = {
1074         F(240000000, P_GPLL4, 5, 0, 0),
1075         { }
1076 };
1077
1078 static struct clk_rcg2 pcie0_axi_m_clk_src = {
1079         .cmd_rcgr = 0x28018,
1080         .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1081         .hid_width = 5,
1082         .parent_map = gcc_xo_gpll0_gpll4_map,
1083         .clkr.hw.init = &(struct clk_init_data) {
1084                 .name = "pcie0_axi_m_clk_src",
1085                 .parent_data = gcc_xo_gpll0_gpll4,
1086                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1087                 .ops = &clk_rcg2_ops,
1088         },
1089 };
1090
1091 static struct clk_branch gcc_pcie0_axi_m_clk = {
1092         .halt_reg = 0x28038,
1093         .clkr = {
1094                 .enable_reg = 0x28038,
1095                 .enable_mask = BIT(0),
1096                 .hw.init = &(struct clk_init_data) {
1097                         .name = "gcc_pcie0_axi_m_clk",
1098                         .parent_hws = (const struct clk_hw *[]) {
1099                                 &pcie0_axi_m_clk_src.clkr.hw
1100                         },
1101                         .num_parents = 1,
1102                         .flags = CLK_SET_RATE_PARENT,
1103                         .ops = &clk_branch2_ops,
1104                 },
1105         },
1106 };
1107
1108 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
1109         .halt_reg = 0x2e07c,
1110         .clkr = {
1111                 .enable_reg = 0x2e07c,
1112                 .enable_mask = BIT(0),
1113                 .hw.init = &(struct clk_init_data) {
1114                         .name = "gcc_anoc_pcie0_1lane_m_clk",
1115                         .parent_hws = (const struct clk_hw *[]) {
1116                                 &pcie0_axi_m_clk_src.clkr.hw
1117                         },
1118                         .num_parents = 1,
1119                         .flags = CLK_SET_RATE_PARENT,
1120                         .ops = &clk_branch2_ops,
1121                 },
1122         },
1123 };
1124
1125 static struct clk_rcg2 pcie1_axi_m_clk_src = {
1126         .cmd_rcgr = 0x29018,
1127         .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1128         .hid_width = 5,
1129         .parent_map = gcc_xo_gpll0_gpll4_map,
1130         .clkr.hw.init = &(struct clk_init_data) {
1131                 .name = "pcie1_axi_m_clk_src",
1132                 .parent_data = gcc_xo_gpll0_gpll4,
1133                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1134                 .ops = &clk_rcg2_ops,
1135         },
1136 };
1137
1138 static struct clk_branch gcc_pcie1_axi_m_clk = {
1139         .halt_reg = 0x29038,
1140         .clkr = {
1141                 .enable_reg = 0x29038,
1142                 .enable_mask = BIT(0),
1143                 .hw.init = &(struct clk_init_data) {
1144                         .name = "gcc_pcie1_axi_m_clk",
1145                         .parent_hws = (const struct clk_hw *[]) {
1146                                 &pcie1_axi_m_clk_src.clkr.hw
1147                         },
1148                         .num_parents = 1,
1149                         .flags = CLK_SET_RATE_PARENT,
1150                         .ops = &clk_branch2_ops,
1151                 },
1152         },
1153 };
1154
1155 static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
1156         .halt_reg = 0x2e08c,
1157         .clkr = {
1158                 .enable_reg = 0x2e08c,
1159                 .enable_mask = BIT(0),
1160                 .hw.init = &(struct clk_init_data) {
1161                         .name = "gcc_anoc_pcie1_1lane_m_clk",
1162                         .parent_hws = (const struct clk_hw *[]) {
1163                                 &pcie1_axi_m_clk_src.clkr.hw
1164                         },
1165                         .num_parents = 1,
1166                         .flags = CLK_SET_RATE_PARENT,
1167                         .ops = &clk_branch2_ops,
1168                 },
1169         },
1170 };
1171
1172 static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = {
1173         F(342857143, P_GPLL4, 3.5, 0, 0),
1174         { }
1175 };
1176
1177 static struct clk_rcg2 pcie2_axi_m_clk_src = {
1178         .cmd_rcgr = 0x2a018,
1179         .freq_tbl = ftbl_pcie2_axi_m_clk_src,
1180         .hid_width = 5,
1181         .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1182         .clkr.hw.init = &(struct clk_init_data) {
1183                 .name = "pcie2_axi_m_clk_src",
1184                 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1185                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1186                 .ops = &clk_rcg2_ops,
1187         },
1188 };
1189
1190 static struct clk_branch gcc_pcie2_axi_m_clk = {
1191         .halt_reg = 0x2a038,
1192         .clkr = {
1193                 .enable_reg = 0x2a038,
1194                 .enable_mask = BIT(0),
1195                 .hw.init = &(struct clk_init_data) {
1196                         .name = "gcc_pcie2_axi_m_clk",
1197                         .parent_hws = (const struct clk_hw *[]) {
1198                                 &pcie2_axi_m_clk_src.clkr.hw
1199                         },
1200                         .num_parents = 1,
1201                         .flags = CLK_SET_RATE_PARENT,
1202                         .ops = &clk_branch2_ops,
1203                 },
1204         },
1205 };
1206
1207 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
1208         .halt_reg = 0x2e080,
1209         .clkr = {
1210                 .enable_reg = 0x2e080,
1211                 .enable_mask = BIT(0),
1212                 .hw.init = &(struct clk_init_data) {
1213                         .name = "gcc_anoc_pcie2_2lane_m_clk",
1214                         .parent_hws = (const struct clk_hw *[]) {
1215                                 &pcie2_axi_m_clk_src.clkr.hw
1216                         },
1217                         .num_parents = 1,
1218                         .flags = CLK_SET_RATE_PARENT,
1219                         .ops = &clk_branch2_ops,
1220                 },
1221         },
1222 };
1223
1224 static struct clk_rcg2 pcie3_axi_m_clk_src = {
1225         .cmd_rcgr = 0x2b018,
1226         .freq_tbl = ftbl_pcie2_axi_m_clk_src,
1227         .hid_width = 5,
1228         .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1229         .clkr.hw.init = &(struct clk_init_data) {
1230                 .name = "pcie3_axi_m_clk_src",
1231                 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1232                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1233                 .ops = &clk_rcg2_ops,
1234         },
1235 };
1236
1237 static struct clk_branch gcc_pcie3_axi_m_clk = {
1238         .halt_reg = 0x2b038,
1239         .clkr = {
1240                 .enable_reg = 0x2b038,
1241                 .enable_mask = BIT(0),
1242                 .hw.init = &(struct clk_init_data) {
1243                         .name = "gcc_pcie3_axi_m_clk",
1244                         .parent_hws = (const struct clk_hw *[]) {
1245                                 &pcie3_axi_m_clk_src.clkr.hw
1246                         },
1247                         .num_parents = 1,
1248                         .flags = CLK_SET_RATE_PARENT,
1249                         .ops = &clk_branch2_ops,
1250                 },
1251         },
1252 };
1253
1254 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
1255         .halt_reg = 0x2e090,
1256         .clkr = {
1257                 .enable_reg = 0x2e090,
1258                 .enable_mask = BIT(0),
1259                 .hw.init = &(struct clk_init_data) {
1260                         .name = "gcc_anoc_pcie3_2lane_m_clk",
1261                         .parent_hws = (const struct clk_hw *[]) {
1262                                 &pcie3_axi_m_clk_src.clkr.hw
1263                         },
1264                         .num_parents = 1,
1265                         .flags = CLK_SET_RATE_PARENT,
1266                         .ops = &clk_branch2_ops,
1267                 },
1268         },
1269 };
1270
1271 static struct clk_rcg2 pcie0_axi_s_clk_src = {
1272         .cmd_rcgr = 0x28020,
1273         .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1274         .hid_width = 5,
1275         .parent_map = gcc_xo_gpll0_gpll4_map,
1276         .clkr.hw.init = &(struct clk_init_data) {
1277                 .name = "pcie0_axi_s_clk_src",
1278                 .parent_data = gcc_xo_gpll0_gpll4,
1279                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1280                 .ops = &clk_rcg2_ops,
1281         },
1282 };
1283
1284 static struct clk_branch gcc_pcie0_axi_s_clk = {
1285         .halt_reg = 0x2803c,
1286         .clkr = {
1287                 .enable_reg = 0x2803c,
1288                 .enable_mask = BIT(0),
1289                 .hw.init = &(struct clk_init_data) {
1290                         .name = "gcc_pcie0_axi_s_clk",
1291                         .parent_hws = (const struct clk_hw *[]) {
1292                                 &pcie0_axi_s_clk_src.clkr.hw
1293                         },
1294                         .num_parents = 1,
1295                         .flags = CLK_SET_RATE_PARENT,
1296                         .ops = &clk_branch2_ops,
1297                 },
1298         },
1299 };
1300
1301 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
1302         .halt_reg = 0x28040,
1303         .clkr = {
1304                 .enable_reg = 0x28040,
1305                 .enable_mask = BIT(0),
1306                 .hw.init = &(struct clk_init_data) {
1307                         .name = "gcc_pcie0_axi_s_bridge_clk",
1308                         .parent_hws = (const struct clk_hw *[]) {
1309                                 &pcie0_axi_s_clk_src.clkr.hw
1310                         },
1311                         .num_parents = 1,
1312                         .flags = CLK_SET_RATE_PARENT,
1313                         .ops = &clk_branch2_ops,
1314                 },
1315         },
1316 };
1317
1318 static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = {
1319         .halt_reg = 0x2e048,
1320         .clkr = {
1321                 .enable_reg = 0x2e048,
1322                 .enable_mask = BIT(0),
1323                 .hw.init = &(struct clk_init_data) {
1324                         .name = "gcc_snoc_pcie0_1lane_s_clk",
1325                         .parent_hws = (const struct clk_hw *[]) {
1326                                 &pcie0_axi_s_clk_src.clkr.hw
1327                         },
1328                         .num_parents = 1,
1329                         .flags = CLK_SET_RATE_PARENT,
1330                         .ops = &clk_branch2_ops,
1331                 },
1332         },
1333 };
1334
1335 static struct clk_rcg2 pcie1_axi_s_clk_src = {
1336         .cmd_rcgr = 0x29020,
1337         .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1338         .hid_width = 5,
1339         .parent_map = gcc_xo_gpll0_gpll4_map,
1340         .clkr.hw.init = &(struct clk_init_data) {
1341                 .name = "pcie1_axi_s_clk_src",
1342                 .parent_data = gcc_xo_gpll0_gpll4,
1343                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1344                 .ops = &clk_rcg2_ops,
1345         },
1346 };
1347
1348 static struct clk_branch gcc_pcie1_axi_s_clk = {
1349         .halt_reg = 0x2903c,
1350         .clkr = {
1351                 .enable_reg = 0x2903c,
1352                 .enable_mask = BIT(0),
1353                 .hw.init = &(struct clk_init_data) {
1354                         .name = "gcc_pcie1_axi_s_clk",
1355                         .parent_hws = (const struct clk_hw *[]) {
1356                                 &pcie1_axi_s_clk_src.clkr.hw
1357                         },
1358                         .num_parents = 1,
1359                         .flags = CLK_SET_RATE_PARENT,
1360                         .ops = &clk_branch2_ops,
1361                 },
1362         },
1363 };
1364
1365 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
1366         .halt_reg = 0x29040,
1367         .clkr = {
1368                 .enable_reg = 0x29040,
1369                 .enable_mask = BIT(0),
1370                 .hw.init = &(struct clk_init_data) {
1371                         .name = "gcc_pcie1_axi_s_bridge_clk",
1372                         .parent_hws = (const struct clk_hw *[]) {
1373                                 &pcie1_axi_s_clk_src.clkr.hw
1374                         },
1375                         .num_parents = 1,
1376                         .flags = CLK_SET_RATE_PARENT,
1377                         .ops = &clk_branch2_ops,
1378                 },
1379         },
1380 };
1381
1382 static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = {
1383         .halt_reg = 0x2e04c,
1384         .clkr = {
1385                 .enable_reg = 0x2e04c,
1386                 .enable_mask = BIT(0),
1387                 .hw.init = &(struct clk_init_data) {
1388                         .name = "gcc_snoc_pcie1_1lane_s_clk",
1389                         .parent_hws = (const struct clk_hw *[]) {
1390                                 &pcie1_axi_s_clk_src.clkr.hw
1391                         },
1392                         .num_parents = 1,
1393                         .flags = CLK_SET_RATE_PARENT,
1394                         .ops = &clk_branch2_ops,
1395                 },
1396         },
1397 };
1398
1399 static struct clk_rcg2 pcie2_axi_s_clk_src = {
1400         .cmd_rcgr = 0x2a020,
1401         .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1402         .hid_width = 5,
1403         .parent_map = gcc_xo_gpll0_gpll4_map,
1404         .clkr.hw.init = &(struct clk_init_data) {
1405                 .name = "pcie2_axi_s_clk_src",
1406                 .parent_data = gcc_xo_gpll0_gpll4,
1407                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1408                 .ops = &clk_rcg2_ops,
1409         },
1410 };
1411
1412 static struct clk_branch gcc_pcie2_axi_s_clk = {
1413         .halt_reg = 0x2a03c,
1414         .clkr = {
1415                 .enable_reg = 0x2a03c,
1416                 .enable_mask = BIT(0),
1417                 .hw.init = &(struct clk_init_data) {
1418                         .name = "gcc_pcie2_axi_s_clk",
1419                         .parent_hws = (const struct clk_hw *[]) {
1420                                 &pcie2_axi_s_clk_src.clkr.hw
1421                         },
1422                         .num_parents = 1,
1423                         .flags = CLK_SET_RATE_PARENT,
1424                         .ops = &clk_branch2_ops,
1425                 },
1426         },
1427 };
1428
1429 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
1430         .halt_reg = 0x2a040,
1431         .clkr = {
1432                 .enable_reg = 0x2a040,
1433                 .enable_mask = BIT(0),
1434                 .hw.init = &(struct clk_init_data) {
1435                         .name = "gcc_pcie2_axi_s_bridge_clk",
1436                         .parent_hws = (const struct clk_hw *[]) {
1437                                 &pcie2_axi_s_clk_src.clkr.hw
1438                         },
1439                         .num_parents = 1,
1440                         .flags = CLK_SET_RATE_PARENT,
1441                         .ops = &clk_branch2_ops,
1442                 },
1443         },
1444 };
1445
1446 static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = {
1447         .halt_reg = 0x2e050,
1448         .clkr = {
1449                 .enable_reg = 0x2e050,
1450                 .enable_mask = BIT(0),
1451                 .hw.init = &(struct clk_init_data) {
1452                         .name = "gcc_snoc_pcie2_2lane_s_clk",
1453                         .parent_hws = (const struct clk_hw *[]) {
1454                                 &pcie2_axi_s_clk_src.clkr.hw
1455                         },
1456                         .num_parents = 1,
1457                         .flags = CLK_SET_RATE_PARENT,
1458                         .ops = &clk_branch2_ops,
1459                 },
1460         },
1461 };
1462
1463 static struct clk_rcg2 pcie3_axi_s_clk_src = {
1464         .cmd_rcgr = 0x2b020,
1465         .freq_tbl = ftbl_pcie0_axi_m_clk_src,
1466         .hid_width = 5,
1467         .parent_map = gcc_xo_gpll0_gpll4_map,
1468         .clkr.hw.init = &(struct clk_init_data) {
1469                 .name = "pcie3_axi_s_clk_src",
1470                 .parent_data = gcc_xo_gpll0_gpll4,
1471                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1472                 .ops = &clk_rcg2_ops,
1473         },
1474 };
1475
1476 static struct clk_branch gcc_pcie3_axi_s_clk = {
1477         .halt_reg = 0x2b03c,
1478         .clkr = {
1479                 .enable_reg = 0x2b03c,
1480                 .enable_mask = BIT(0),
1481                 .hw.init = &(struct clk_init_data) {
1482                         .name = "gcc_pcie3_axi_s_clk",
1483                         .parent_hws = (const struct clk_hw *[]) {
1484                                 &pcie3_axi_s_clk_src.clkr.hw
1485                         },
1486                         .num_parents = 1,
1487                         .flags = CLK_SET_RATE_PARENT,
1488                         .ops = &clk_branch2_ops,
1489                 },
1490         },
1491 };
1492
1493 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
1494         .halt_reg = 0x2b040,
1495         .clkr = {
1496                 .enable_reg = 0x2b040,
1497                 .enable_mask = BIT(0),
1498                 .hw.init = &(struct clk_init_data) {
1499                         .name = "gcc_pcie3_axi_s_bridge_clk",
1500                         .parent_hws = (const struct clk_hw *[]) {
1501                                 &pcie3_axi_s_clk_src.clkr.hw
1502                         },
1503                         .num_parents = 1,
1504                         .flags = CLK_SET_RATE_PARENT,
1505                         .ops = &clk_branch2_ops,
1506                 },
1507         },
1508 };
1509
1510 static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
1511         .halt_reg = 0x2e054,
1512         .clkr = {
1513                 .enable_reg = 0x2e054,
1514                 .enable_mask = BIT(0),
1515                 .hw.init = &(struct clk_init_data) {
1516                         .name = "gcc_snoc_pcie3_2lane_s_clk",
1517                         .parent_hws = (const struct clk_hw *[]) {
1518                                 &pcie3_axi_s_clk_src.clkr.hw
1519                         },
1520                         .num_parents = 1,
1521                         .flags = CLK_SET_RATE_PARENT,
1522                         .ops = &clk_branch2_ops,
1523                 },
1524         },
1525 };
1526
1527 static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
1528         .reg = 0x28064,
1529         .clkr = {
1530                 .hw.init = &(struct clk_init_data) {
1531                         .name = "pcie0_pipe_clk_src",
1532                         .parent_data = &(const struct clk_parent_data) {
1533                                 .index = DT_PCIE30_PHY0_PIPE_CLK,
1534                         },
1535                         .num_parents = 1,
1536                         .ops = &clk_regmap_phy_mux_ops,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
1542         .reg = 0x29064,
1543         .clkr = {
1544                 .hw.init = &(struct clk_init_data) {
1545                         .name = "pcie1_pipe_clk_src",
1546                         .parent_data = &(const struct clk_parent_data) {
1547                                 .index = DT_PCIE30_PHY1_PIPE_CLK,
1548                         },
1549                         .num_parents = 1,
1550                         .ops = &clk_regmap_phy_mux_ops,
1551                 },
1552         },
1553 };
1554
1555 static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
1556         .reg = 0x2a064,
1557         .clkr = {
1558                 .hw.init = &(struct clk_init_data) {
1559                         .name = "pcie2_pipe_clk_src",
1560                         .parent_data = &(const struct clk_parent_data) {
1561                                 .index = DT_PCIE30_PHY2_PIPE_CLK,
1562                         },
1563                         .num_parents = 1,
1564                         .ops = &clk_regmap_phy_mux_ops,
1565                 },
1566         },
1567 };
1568
1569 static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
1570         .reg = 0x2b064,
1571         .clkr = {
1572                 .hw.init = &(struct clk_init_data) {
1573                         .name = "pcie3_pipe_clk_src",
1574                         .parent_data = &(const struct clk_parent_data) {
1575                                 .index = DT_PCIE30_PHY3_PIPE_CLK,
1576                         },
1577                         .num_parents = 1,
1578                         .ops = &clk_regmap_phy_mux_ops,
1579                 },
1580         },
1581 };
1582
1583 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
1584         F(24000000, P_XO, 1, 0, 0),
1585         F(100000000, P_GPLL0, 8, 0, 0),
1586         { }
1587 };
1588
1589 static struct clk_rcg2 pcie0_rchng_clk_src = {
1590         .cmd_rcgr = 0x28028,
1591         .freq_tbl = ftbl_pcie_rchng_clk_src,
1592         .hid_width = 5,
1593         .parent_map = gcc_xo_gpll0_map,
1594         .clkr.hw.init = &(struct clk_init_data) {
1595                 .name = "pcie0_rchng_clk_src",
1596                 .parent_data = gcc_xo_gpll0,
1597                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1598                 .ops = &clk_rcg2_ops,
1599         },
1600 };
1601
1602 static struct clk_branch gcc_pcie0_rchng_clk = {
1603         .halt_reg = 0x28028,
1604         .clkr = {
1605                 .enable_reg = 0x28028,
1606                 .enable_mask = BIT(1),
1607                 .hw.init = &(struct clk_init_data) {
1608                         .name = "gcc_pcie0_rchng_clk",
1609                         .parent_hws = (const struct clk_hw *[]) {
1610                                 &pcie0_rchng_clk_src.clkr.hw
1611
1612                         },
1613                         .num_parents = 1,
1614                         .flags = CLK_SET_RATE_PARENT,
1615                         .ops = &clk_branch2_ops,
1616                 },
1617         },
1618 };
1619
1620 static struct clk_rcg2 pcie1_rchng_clk_src = {
1621         .cmd_rcgr = 0x29028,
1622         .freq_tbl = ftbl_pcie_rchng_clk_src,
1623         .hid_width = 5,
1624         .parent_map = gcc_xo_gpll0_map,
1625         .clkr.hw.init = &(struct clk_init_data) {
1626                 .name = "pcie1_rchng_clk_src",
1627                 .parent_data = gcc_xo_gpll0,
1628                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1629                 .ops = &clk_rcg2_ops,
1630         },
1631 };
1632
1633 static struct clk_branch gcc_pcie1_rchng_clk = {
1634         .halt_reg = 0x29028,
1635         .clkr = {
1636                 .enable_reg = 0x29028,
1637                 .enable_mask = BIT(1),
1638                 .hw.init = &(struct clk_init_data) {
1639                         .name = "gcc_pcie1_rchng_clk",
1640                         .parent_hws = (const struct clk_hw *[]) {
1641                                 &pcie1_rchng_clk_src.clkr.hw
1642                         },
1643                         .num_parents = 1,
1644                         .flags = CLK_SET_RATE_PARENT,
1645                         .ops = &clk_branch2_ops,
1646                 },
1647         },
1648 };
1649
1650 static struct clk_rcg2 pcie2_rchng_clk_src = {
1651         .cmd_rcgr = 0x2a028,
1652         .freq_tbl = ftbl_pcie_rchng_clk_src,
1653         .hid_width = 5,
1654         .parent_map = gcc_xo_gpll0_map,
1655         .clkr.hw.init = &(struct clk_init_data) {
1656                 .name = "pcie2_rchng_clk_src",
1657                 .parent_data = gcc_xo_gpll0,
1658                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1659                 .ops = &clk_rcg2_ops,
1660         },
1661 };
1662
1663 static struct clk_branch gcc_pcie2_rchng_clk = {
1664         .halt_reg = 0x2a028,
1665         .clkr = {
1666                 .enable_reg = 0x2a028,
1667                 .enable_mask = BIT(1),
1668                 .hw.init = &(struct clk_init_data) {
1669                         .name = "gcc_pcie2_rchng_clk",
1670                         .parent_hws = (const struct clk_hw *[]) {
1671                                 &pcie2_rchng_clk_src.clkr.hw
1672                         },
1673                         .num_parents = 1,
1674                         .flags = CLK_SET_RATE_PARENT,
1675                         .ops = &clk_branch2_ops,
1676                 },
1677         },
1678 };
1679
1680 static struct clk_rcg2 pcie3_rchng_clk_src = {
1681         .cmd_rcgr = 0x2b028,
1682         .freq_tbl = ftbl_pcie_rchng_clk_src,
1683         .hid_width = 5,
1684         .parent_map = gcc_xo_gpll0_map,
1685         .clkr.hw.init = &(struct clk_init_data) {
1686                 .name = "pcie3_rchng_clk_src",
1687                 .parent_data = gcc_xo_gpll0,
1688                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1689                 .ops = &clk_rcg2_ops,
1690         },
1691 };
1692
1693 static struct clk_branch gcc_pcie3_rchng_clk = {
1694         .halt_reg = 0x2b028,
1695         .clkr = {
1696                 .enable_reg = 0x2b028,
1697                 .enable_mask = BIT(1),
1698                 .hw.init = &(struct clk_init_data) {
1699                         .name = "gcc_pcie3_rchng_clk",
1700                         .parent_hws = (const struct clk_hw *[]) {
1701                                 &pcie3_rchng_clk_src.clkr.hw
1702                         },
1703                         .num_parents = 1,
1704                         .flags = CLK_SET_RATE_PARENT,
1705                         .ops = &clk_branch2_ops,
1706                 },
1707         },
1708 };
1709
1710 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1711         F(20000000, P_GPLL0, 10, 1, 4),
1712         { }
1713 };
1714
1715 static struct clk_rcg2 pcie_aux_clk_src = {
1716         .cmd_rcgr = 0x28004,
1717         .freq_tbl = ftbl_pcie_aux_clk_src,
1718         .mnd_width = 16,
1719         .hid_width = 5,
1720         .parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,
1721         .clkr.hw.init = &(struct clk_init_data) {
1722                 .name = "pcie_aux_clk_src",
1723                 .parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,
1724                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),
1725                 .ops = &clk_rcg2_ops,
1726         },
1727 };
1728
1729 static struct clk_branch gcc_pcie0_aux_clk = {
1730         .halt_reg = 0x28034,
1731         .clkr = {
1732                 .enable_reg = 0x28034,
1733                 .enable_mask = BIT(0),
1734                 .hw.init = &(struct clk_init_data) {
1735                         .name = "gcc_pcie0_aux_clk",
1736                         .parent_hws = (const struct clk_hw *[]) {
1737                                 &pcie_aux_clk_src.clkr.hw
1738                         },
1739                         .num_parents = 1,
1740                         .flags = CLK_SET_RATE_PARENT,
1741                         .ops = &clk_branch2_ops,
1742                 },
1743         },
1744 };
1745
1746 static struct clk_branch gcc_pcie1_aux_clk = {
1747         .halt_reg = 0x29034,
1748         .clkr = {
1749                 .enable_reg = 0x29034,
1750                 .enable_mask = BIT(0),
1751                 .hw.init = &(struct clk_init_data) {
1752                         .name = "gcc_pcie1_aux_clk",
1753                         .parent_hws = (const struct clk_hw *[]) {
1754                                 &pcie_aux_clk_src.clkr.hw
1755                         },
1756                         .num_parents = 1,
1757                         .flags = CLK_SET_RATE_PARENT,
1758                         .ops = &clk_branch2_ops,
1759                 },
1760         },
1761 };
1762
1763 static struct clk_branch gcc_pcie2_aux_clk = {
1764         .halt_reg = 0x2a034,
1765         .clkr = {
1766                 .enable_reg = 0x2a034,
1767                 .enable_mask = BIT(0),
1768                 .hw.init = &(struct clk_init_data) {
1769                         .name = "gcc_pcie2_aux_clk",
1770                         .parent_hws = (const struct clk_hw *[]) {
1771                                 &pcie_aux_clk_src.clkr.hw
1772                         },
1773                         .num_parents = 1,
1774                         .flags = CLK_SET_RATE_PARENT,
1775                         .ops = &clk_branch2_ops,
1776                 },
1777         },
1778 };
1779
1780 static struct clk_branch gcc_pcie3_aux_clk = {
1781         .halt_reg = 0x2b034,
1782         .clkr = {
1783                 .enable_reg = 0x2b034,
1784                 .enable_mask = BIT(0),
1785                 .hw.init = &(struct clk_init_data) {
1786                         .name = "gcc_pcie3_aux_clk",
1787                         .parent_hws = (const struct clk_hw *[]) {
1788                                 &pcie_aux_clk_src.clkr.hw
1789                         },
1790                         .num_parents = 1,
1791                         .flags = CLK_SET_RATE_PARENT,
1792                         .ops = &clk_branch2_ops,
1793                 },
1794         },
1795 };
1796
1797 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1798         F(24000000, P_XO, 1, 0, 0),
1799         { }
1800 };
1801
1802 static struct clk_rcg2 usb0_aux_clk_src = {
1803         .cmd_rcgr = 0x2c018,
1804         .freq_tbl = ftbl_usb_aux_clk_src,
1805         .mnd_width = 16,
1806         .hid_width = 5,
1807         .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1808         .clkr.hw.init = &(struct clk_init_data) {
1809                 .name = "usb0_aux_clk_src",
1810                 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1811                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1812                 .ops = &clk_rcg2_ops,
1813         },
1814 };
1815
1816 static struct clk_branch gcc_usb0_aux_clk = {
1817         .halt_reg = 0x2c048,
1818         .clkr = {
1819                 .enable_reg = 0x2c048,
1820                 .enable_mask = BIT(0),
1821                 .hw.init = &(struct clk_init_data) {
1822                         .name = "gcc_usb0_aux_clk",
1823                         .parent_hws = (const struct clk_hw *[]) {
1824                                 &usb0_aux_clk_src.clkr.hw
1825                         },
1826                         .num_parents = 1,
1827                         .flags = CLK_SET_RATE_PARENT,
1828                         .ops = &clk_branch2_ops,
1829                 },
1830         },
1831 };
1832
1833 static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
1834         F(100000000, P_GPLL0, 8, 0, 0),
1835         F(200000000, P_GPLL0, 4, 0, 0),
1836         { }
1837 };
1838
1839 static struct clk_rcg2 usb0_master_clk_src = {
1840         .cmd_rcgr = 0x2c004,
1841         .freq_tbl = ftbl_usb0_master_clk_src,
1842         .mnd_width = 8,
1843         .hid_width = 5,
1844         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1845         .clkr.hw.init = &(struct clk_init_data) {
1846                 .name = "usb0_master_clk_src",
1847                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1848                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1849                 .ops = &clk_rcg2_ops,
1850         },
1851 };
1852
1853 static struct clk_branch gcc_usb0_master_clk = {
1854         .halt_reg = 0x2c044,
1855         .clkr = {
1856                 .enable_reg = 0x2c044,
1857                 .enable_mask = BIT(0),
1858                 .hw.init = &(struct clk_init_data) {
1859                         .name = "gcc_usb0_master_clk",
1860                         .parent_hws = (const struct clk_hw *[]) {
1861                                 &usb0_master_clk_src.clkr.hw
1862                         },
1863                         .num_parents = 1,
1864                         .flags = CLK_SET_RATE_PARENT,
1865                         .ops = &clk_branch2_ops,
1866                 },
1867         },
1868 };
1869
1870 static struct clk_branch gcc_snoc_usb_clk = {
1871         .halt_reg = 0x2e058,
1872         .clkr = {
1873                 .enable_reg = 0x2e058,
1874                 .enable_mask = BIT(0),
1875                 .hw.init = &(struct clk_init_data) {
1876                         .name = "gcc_snoc_usb_clk",
1877                         .parent_hws = (const struct clk_hw *[]) {
1878                                 &usb0_master_clk_src.clkr.hw
1879                         },
1880                         .num_parents = 1,
1881                         .flags = CLK_SET_RATE_PARENT,
1882                         .ops = &clk_branch2_ops,
1883                 },
1884         },
1885 };
1886
1887 static struct clk_branch gcc_anoc_usb_axi_clk = {
1888         .halt_reg = 0x2e084,
1889         .clkr = {
1890                 .enable_reg = 0x2e084,
1891                 .enable_mask = BIT(0),
1892                 .hw.init = &(struct clk_init_data) {
1893                         .name = "gcc_anoc_usb_axi_clk",
1894                         .parent_hws = (const struct clk_hw *[]) {
1895                                 &usb0_master_clk_src.clkr.hw
1896                         },
1897                         .num_parents = 1,
1898                         .flags = CLK_SET_RATE_PARENT,
1899                         .ops = &clk_branch2_ops,
1900                 },
1901         },
1902 };
1903
1904 static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
1905         F(24000000, P_XO, 1, 0, 0),
1906         F(60000000, P_GPLL4, 10, 1, 2),
1907         { }
1908 };
1909
1910 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1911         .cmd_rcgr = 0x2c02c,
1912         .freq_tbl = ftbl_usb0_mock_utmi_clk_src,
1913         .mnd_width = 8,
1914         .hid_width = 5,
1915         .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,
1916         .clkr.hw.init = &(struct clk_init_data) {
1917                 .name = "usb0_mock_utmi_clk_src",
1918                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1919                 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1920                 .ops = &clk_rcg2_ops,
1921         },
1922 };
1923
1924 static struct clk_regmap_div usb0_mock_utmi_div_clk_src = {
1925         .reg = 0x2c040,
1926         .shift = 0,
1927         .width = 2,
1928         .clkr.hw.init = &(struct clk_init_data) {
1929                 .name = "usb0_mock_utmi_div_clk_src",
1930                 .parent_data = &(const struct clk_parent_data) {
1931                         .hw = &usb0_mock_utmi_clk_src.clkr.hw,
1932                 },
1933                 .num_parents = 1,
1934                 .flags = CLK_SET_RATE_PARENT,
1935                 .ops = &clk_regmap_div_ro_ops,
1936         },
1937 };
1938
1939 static struct clk_branch gcc_usb0_mock_utmi_clk = {
1940         .halt_reg = 0x2c04c,
1941         .clkr = {
1942                 .enable_reg = 0x2c04c,
1943                 .enable_mask = BIT(0),
1944                 .hw.init = &(struct clk_init_data) {
1945                         .name = "gcc_usb0_mock_utmi_clk",
1946                         .parent_hws = (const struct clk_hw *[]) {
1947                                 &usb0_mock_utmi_div_clk_src.clkr.hw
1948                         },
1949                         .num_parents = 1,
1950                         .flags = CLK_SET_RATE_PARENT,
1951                         .ops = &clk_branch2_ops,
1952                 },
1953         },
1954 };
1955
1956 static struct clk_regmap_mux usb0_pipe_clk_src = {
1957         .reg = 0x2C074,
1958         .shift = 8,
1959         .width = 2,
1960         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1961         .clkr = {
1962                 .hw.init = &(struct clk_init_data) {
1963                         .name = "usb0_pipe_clk_src",
1964                         .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1965                         .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
1966                         .flags = CLK_SET_RATE_PARENT,
1967                         .ops = &clk_regmap_mux_closest_ops,
1968                 },
1969         },
1970 };
1971
1972 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1973         F(144000, P_XO, 16, 12, 125),
1974         F(400000, P_XO, 12, 1, 5),
1975         F(24000000, P_GPLL2, 12, 1, 4),
1976         F(48000000, P_GPLL2, 12, 1, 2),
1977         F(96000000, P_GPLL2, 12, 0, 0),
1978         F(177777778, P_GPLL0, 4.5, 0, 0),
1979         F(192000000, P_GPLL2, 6, 0, 0),
1980         F(384000000, P_GPLL2, 3, 0, 0),
1981         F(400000000, P_GPLL0, 2, 0, 0),
1982         { }
1983 };
1984
1985 static struct clk_rcg2 sdcc1_apps_clk_src = {
1986         .cmd_rcgr = 0x33004,
1987         .freq_tbl = ftbl_sdcc_apps_clk_src,
1988         .mnd_width = 8,
1989         .hid_width = 5,
1990         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1991         .clkr.hw.init = &(struct clk_init_data) {
1992                 .name = "sdcc1_apps_clk_src",
1993                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1994                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1995                 .ops = &clk_rcg2_floor_ops,
1996         },
1997 };
1998
1999 static struct clk_branch gcc_sdcc1_apps_clk = {
2000         .halt_reg = 0x3302c,
2001         .clkr = {
2002                 .enable_reg = 0x3302c,
2003                 .enable_mask = BIT(0),
2004                 .hw.init = &(struct clk_init_data) {
2005                         .name = "gcc_sdcc1_apps_clk",
2006                         .parent_hws = (const struct clk_hw *[]) {
2007                                 &sdcc1_apps_clk_src.clkr.hw
2008                         },
2009                         .num_parents = 1,
2010                         .flags = CLK_SET_RATE_PARENT,
2011                         .ops = &clk_branch2_ops,
2012                 },
2013         },
2014 };
2015
2016 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
2017         F(150000000, P_GPLL4, 8, 0, 0),
2018         F(300000000, P_GPLL4, 4, 0, 0),
2019 };
2020
2021 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
2022         .cmd_rcgr = 0x33018,
2023         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
2024         .mnd_width = 8,
2025         .hid_width = 5,
2026         .parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,
2027         .clkr.hw.init = &(struct clk_init_data) {
2028                 .name = "sdcc1_ice_core_clk_src",
2029                 .parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,
2030                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),
2031                 .ops = &clk_rcg2_ops,
2032         },
2033 };
2034
2035 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2036         .halt_reg = 0x33030,
2037         .clkr = {
2038                 .enable_reg = 0x33030,
2039                 .enable_mask = BIT(0),
2040                 .hw.init = &(struct clk_init_data) {
2041                         .name = "gcc_sdcc1_ice_core_clk",
2042                         .parent_hws = (const struct clk_hw *[]) {
2043                                 &sdcc1_ice_core_clk_src.clkr.hw
2044                         },
2045                         .num_parents = 1,
2046                         .flags = CLK_SET_RATE_PARENT,
2047                         .ops = &clk_branch2_ops,
2048                 },
2049         },
2050 };
2051
2052 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
2053         F(24000000, P_XO, 1, 0, 0),
2054         F(50000000, P_GPLL0, 16, 0, 0),
2055         F(80000000, P_GPLL0, 10, 0, 0),
2056         F(100000000, P_GPLL0, 8, 0, 0),
2057         { }
2058 };
2059
2060 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
2061         .cmd_rcgr = 0x31004,
2062         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
2063         .hid_width = 5,
2064         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2065         .clkr.hw.init = &(struct clk_init_data) {
2066                 .name = "pcnoc_bfdcd_clk_src",
2067                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2068                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2069                 .flags = CLK_IS_CRITICAL,
2070                 .ops = &clk_rcg2_ops,
2071         },
2072 };
2073
2074 static struct clk_branch gcc_nsscfg_clk = {
2075         .halt_reg = 0x1702c,
2076         .clkr = {
2077                 .enable_reg = 0x1702c,
2078                 .enable_mask = BIT(0),
2079                 .hw.init = &(struct clk_init_data) {
2080                         .name = "gcc_nsscfg_clk",
2081                         .parent_hws = (const struct clk_hw *[]) {
2082                                 &pcnoc_bfdcd_clk_src.clkr.hw
2083                         },
2084                         .num_parents = 1,
2085                         .flags = CLK_SET_RATE_PARENT,
2086                         .ops = &clk_branch2_ops,
2087                 },
2088         },
2089 };
2090
2091 static struct clk_branch gcc_nssnoc_nsscc_clk = {
2092         .halt_reg = 0x17030,
2093         .clkr = {
2094                 .enable_reg = 0x17030,
2095                 .enable_mask = BIT(0),
2096                 .hw.init = &(struct clk_init_data) {
2097                         .name = "gcc_nssnoc_nsscc_clk",
2098                         .parent_hws = (const struct clk_hw *[]) {
2099                                 &pcnoc_bfdcd_clk_src.clkr.hw
2100                         },
2101                         .num_parents = 1,
2102                         .flags = CLK_SET_RATE_PARENT,
2103                         .ops = &clk_branch2_ops,
2104                 },
2105         },
2106 };
2107
2108 static struct clk_branch gcc_nsscc_clk = {
2109         .halt_reg = 0x17034,
2110         .clkr = {
2111                 .enable_reg = 0x17034,
2112                 .enable_mask = BIT(0),
2113                 .hw.init = &(struct clk_init_data) {
2114                         .name = "gcc_nsscc_clk",
2115                         .parent_hws = (const struct clk_hw *[]) {
2116                                 &pcnoc_bfdcd_clk_src.clkr.hw
2117                         },
2118                         .num_parents = 1,
2119                         .flags = CLK_SET_RATE_PARENT,
2120                         .ops = &clk_branch2_ops,
2121                 },
2122         },
2123 };
2124
2125 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
2126         .halt_reg = 0x17080,
2127         .clkr = {
2128                 .enable_reg = 0x17080,
2129                 .enable_mask = BIT(0),
2130                 .hw.init = &(struct clk_init_data) {
2131                         .name = "gcc_nssnoc_pcnoc_1_clk",
2132                         .parent_hws = (const struct clk_hw *[]) {
2133                                 &pcnoc_bfdcd_clk_src.clkr.hw
2134                         },
2135                         .num_parents = 1,
2136                         .flags = CLK_SET_RATE_PARENT,
2137                         .ops = &clk_branch2_ops,
2138                 },
2139         },
2140 };
2141
2142 static struct clk_branch gcc_qdss_dap_ahb_clk = {
2143         .halt_reg = 0x2d064,
2144         .clkr = {
2145                 .enable_reg = 0x2d064,
2146                 .enable_mask = BIT(0),
2147                 .hw.init = &(struct clk_init_data) {
2148                         .name = "gcc_qdss_dap_ahb_clk",
2149                         .parent_hws = (const struct clk_hw *[]) {
2150                                 &pcnoc_bfdcd_clk_src.clkr.hw
2151                         },
2152                         .num_parents = 1,
2153                         .flags = CLK_SET_RATE_PARENT,
2154                         .ops = &clk_branch2_ops,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2160         .halt_reg = 0x2d068,
2161         .clkr = {
2162                 .enable_reg = 0x2d068,
2163                 .enable_mask = BIT(0),
2164                 .hw.init = &(struct clk_init_data) {
2165                         .name = "gcc_qdss_cfg_ahb_clk",
2166                         .parent_hws = (const struct clk_hw *[]) {
2167                                 &pcnoc_bfdcd_clk_src.clkr.hw
2168                         },
2169                         .num_parents = 1,
2170                         .flags = CLK_SET_RATE_PARENT,
2171                         .ops = &clk_branch2_ops,
2172                 },
2173         },
2174 };
2175
2176 static struct clk_branch gcc_qpic_ahb_clk = {
2177         .halt_reg = 0x32010,
2178         .clkr = {
2179                 .enable_reg = 0x32010,
2180                 .enable_mask = BIT(0),
2181                 .hw.init = &(struct clk_init_data) {
2182                         .name = "gcc_qpic_ahb_clk",
2183                         .parent_hws = (const struct clk_hw *[]) {
2184                                 &pcnoc_bfdcd_clk_src.clkr.hw
2185                         },
2186                         .num_parents = 1,
2187                         .flags = CLK_SET_RATE_PARENT,
2188                         .ops = &clk_branch2_ops,
2189                 },
2190         },
2191 };
2192
2193 static struct clk_branch gcc_qpic_clk = {
2194         .halt_reg = 0x32014,
2195         .clkr = {
2196                 .enable_reg = 0x32014,
2197                 .enable_mask = BIT(0),
2198                 .hw.init = &(struct clk_init_data) {
2199                         .name = "gcc_qpic_clk",
2200                         .parent_hws = (const struct clk_hw *[]) {
2201                                 &pcnoc_bfdcd_clk_src.clkr.hw
2202                         },
2203                         .num_parents = 1,
2204                         .flags = CLK_SET_RATE_PARENT,
2205                         .ops = &clk_branch2_ops,
2206                 },
2207         },
2208 };
2209
2210 static struct clk_branch gcc_blsp1_ahb_clk = {
2211         .halt_reg = 0x01004,
2212         .halt_check = BRANCH_HALT_VOTED,
2213         .clkr = {
2214                 .enable_reg = 0x0b004,
2215                 .enable_mask = BIT(4),
2216                 .hw.init = &(struct clk_init_data) {
2217                         .name = "gcc_blsp1_ahb_clk",
2218                         .parent_hws = (const struct clk_hw *[]) {
2219                                 &pcnoc_bfdcd_clk_src.clkr.hw
2220                         },
2221                         .num_parents = 1,
2222                         .flags = CLK_SET_RATE_PARENT,
2223                         .ops = &clk_branch2_ops,
2224                 },
2225         },
2226 };
2227
2228 static struct clk_branch gcc_mdio_ahb_clk = {
2229         .halt_reg = 0x17040,
2230         .clkr = {
2231                 .enable_reg = 0x17040,
2232                 .enable_mask = BIT(0),
2233                 .hw.init = &(struct clk_init_data) {
2234                         .name = "gcc_mdio_ahb_clk",
2235                         .parent_hws = (const struct clk_hw *[]) {
2236                                 &pcnoc_bfdcd_clk_src.clkr.hw
2237                         },
2238                         .num_parents = 1,
2239                         .flags = CLK_SET_RATE_PARENT,
2240                         .ops = &clk_branch2_ops,
2241                 },
2242         },
2243 };
2244
2245 static struct clk_branch gcc_prng_ahb_clk = {
2246         .halt_reg = 0x13024,
2247         .halt_check = BRANCH_HALT_VOTED,
2248         .clkr = {
2249                 .enable_reg = 0x0b004,
2250                 .enable_mask = BIT(10),
2251                 .hw.init = &(struct clk_init_data) {
2252                         .name = "gcc_prng_ahb_clk",
2253                         .parent_hws = (const struct clk_hw *[]) {
2254                                 &pcnoc_bfdcd_clk_src.clkr.hw
2255                         },
2256                         .num_parents = 1,
2257                         .flags = CLK_SET_RATE_PARENT,
2258                         .ops = &clk_branch2_ops,
2259                 },
2260         },
2261 };
2262
2263 static struct clk_branch gcc_uniphy0_ahb_clk = {
2264         .halt_reg = 0x1704c,
2265         .clkr = {
2266                 .enable_reg = 0x1704c,
2267                 .enable_mask = BIT(0),
2268                 .hw.init = &(struct clk_init_data) {
2269                         .name = "gcc_uniphy0_ahb_clk",
2270                         .parent_hws = (const struct clk_hw *[]) {
2271                                 &pcnoc_bfdcd_clk_src.clkr.hw
2272                         },
2273                         .num_parents = 1,
2274                         .flags = CLK_SET_RATE_PARENT,
2275                         .ops = &clk_branch2_ops,
2276                 },
2277         },
2278 };
2279
2280 static struct clk_branch gcc_uniphy1_ahb_clk = {
2281         .halt_reg = 0x1705c,
2282         .clkr = {
2283                 .enable_reg = 0x1705c,
2284                 .enable_mask = BIT(0),
2285                 .hw.init = &(struct clk_init_data) {
2286                         .name = "gcc_uniphy1_ahb_clk",
2287                         .parent_hws = (const struct clk_hw *[]) {
2288                                 &pcnoc_bfdcd_clk_src.clkr.hw
2289                         },
2290                         .num_parents = 1,
2291                         .flags = CLK_SET_RATE_PARENT,
2292                         .ops = &clk_branch2_ops,
2293                 },
2294         },
2295 };
2296
2297 static struct clk_branch gcc_uniphy2_ahb_clk = {
2298         .halt_reg = 0x1706c,
2299         .clkr = {
2300                 .enable_reg = 0x1706c,
2301                 .enable_mask = BIT(0),
2302                 .hw.init = &(struct clk_init_data) {
2303                         .name = "gcc_uniphy2_ahb_clk",
2304                         .parent_hws = (const struct clk_hw *[]) {
2305                                 &pcnoc_bfdcd_clk_src.clkr.hw
2306                         },
2307                         .num_parents = 1,
2308                         .flags = CLK_SET_RATE_PARENT,
2309                         .ops = &clk_branch2_ops,
2310                 },
2311         },
2312 };
2313
2314 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
2315         .halt_reg = 0x3a004,
2316         .clkr = {
2317                 .enable_reg = 0x3a004,
2318                 .enable_mask = BIT(0),
2319                 .hw.init = &(struct clk_init_data) {
2320                         .name = "gcc_cmn_12gpll_ahb_clk",
2321                         .parent_hws = (const struct clk_hw *[]) {
2322                                 &pcnoc_bfdcd_clk_src.clkr.hw
2323                         },
2324                         .num_parents = 1,
2325                         .flags = CLK_SET_RATE_PARENT,
2326                         .ops = &clk_branch2_ops,
2327                 },
2328         },
2329 };
2330
2331 static struct clk_branch gcc_cmn_12gpll_apu_clk = {
2332         .halt_reg = 0x3a00c,
2333         .clkr = {
2334                 .enable_reg = 0x3a00c,
2335                 .enable_mask = BIT(0),
2336                 .hw.init = &(struct clk_init_data) {
2337                         .name = "gcc_cmn_12gpll_apu_clk",
2338                         .parent_hws = (const struct clk_hw *[]) {
2339                                 &pcnoc_bfdcd_clk_src.clkr.hw
2340                         },
2341                         .num_parents = 1,
2342                         .flags = CLK_SET_RATE_PARENT,
2343                         .ops = &clk_branch2_ops,
2344                 },
2345         },
2346 };
2347
2348 static struct clk_branch gcc_pcie0_ahb_clk = {
2349         .halt_reg = 0x28030,
2350         .clkr = {
2351                 .enable_reg = 0x28030,
2352                 .enable_mask = BIT(0),
2353                 .hw.init = &(struct clk_init_data) {
2354                         .name = "gcc_pcie0_ahb_clk",
2355                         .parent_hws = (const struct clk_hw *[]) {
2356                                 &pcnoc_bfdcd_clk_src.clkr.hw
2357                         },
2358                         .num_parents = 1,
2359                         .flags = CLK_SET_RATE_PARENT,
2360                         .ops = &clk_branch2_ops,
2361                 },
2362         },
2363 };
2364
2365 static struct clk_branch gcc_pcie1_ahb_clk = {
2366         .halt_reg = 0x29030,
2367         .clkr = {
2368                 .enable_reg = 0x29030,
2369                 .enable_mask = BIT(0),
2370                 .hw.init = &(struct clk_init_data) {
2371                         .name = "gcc_pcie1_ahb_clk",
2372                         .parent_hws = (const struct clk_hw *[]) {
2373                                 &pcnoc_bfdcd_clk_src.clkr.hw
2374                         },
2375                         .num_parents = 1,
2376                         .flags = CLK_SET_RATE_PARENT,
2377                         .ops = &clk_branch2_ops,
2378                 },
2379         },
2380 };
2381
2382 static struct clk_branch gcc_pcie2_ahb_clk = {
2383         .halt_reg = 0x2a030,
2384         .clkr = {
2385                 .enable_reg = 0x2a030,
2386                 .enable_mask = BIT(0),
2387                 .hw.init = &(struct clk_init_data) {
2388                         .name = "gcc_pcie2_ahb_clk",
2389                         .parent_hws = (const struct clk_hw *[]) {
2390                                 &pcnoc_bfdcd_clk_src.clkr.hw
2391                         },
2392                         .num_parents = 1,
2393                         .flags = CLK_SET_RATE_PARENT,
2394                         .ops = &clk_branch2_ops,
2395                 },
2396         },
2397 };
2398
2399 static struct clk_branch gcc_pcie3_ahb_clk = {
2400         .halt_reg = 0x2b030,
2401         .clkr = {
2402                 .enable_reg = 0x2b030,
2403                 .enable_mask = BIT(0),
2404                 .hw.init = &(struct clk_init_data) {
2405                         .name = "gcc_pcie3_ahb_clk",
2406                         .parent_hws = (const struct clk_hw *[]) {
2407                                 &pcnoc_bfdcd_clk_src.clkr.hw
2408                         },
2409                         .num_parents = 1,
2410                         .flags = CLK_SET_RATE_PARENT,
2411                         .ops = &clk_branch2_ops,
2412                 },
2413         },
2414 };
2415
2416 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2417         .halt_reg = 0x2c05c,
2418         .clkr = {
2419                 .enable_reg = 0x2c05c,
2420                 .enable_mask = BIT(0),
2421                 .hw.init = &(struct clk_init_data) {
2422                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2423                         .parent_hws = (const struct clk_hw *[]) {
2424                                 &pcnoc_bfdcd_clk_src.clkr.hw
2425                         },
2426                         .num_parents = 1,
2427                         .flags = CLK_SET_RATE_PARENT,
2428                         .ops = &clk_branch2_ops,
2429                 },
2430         },
2431 };
2432
2433 static struct clk_branch gcc_sdcc1_ahb_clk = {
2434         .halt_reg = 0x33034,
2435         .clkr = {
2436                 .enable_reg = 0x33034,
2437                 .enable_mask = BIT(0),
2438                 .hw.init = &(struct clk_init_data) {
2439                         .name = "gcc_sdcc1_ahb_clk",
2440                         .parent_hws = (const struct clk_hw *[]) {
2441                                 &pcnoc_bfdcd_clk_src.clkr.hw
2442                         },
2443                         .num_parents = 1,
2444                         .flags = CLK_SET_RATE_PARENT,
2445                         .ops = &clk_branch2_ops,
2446                 },
2447         },
2448 };
2449
2450 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
2451         F(24000000, P_XO, 1, 0, 0),
2452         F(133333333, P_GPLL0, 6, 0, 0),
2453         F(200000000, P_GPLL0, 4, 0, 0),
2454         F(342850000, P_GPLL4, 3.5, 0, 0),
2455         { }
2456 };
2457
2458 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
2459         .cmd_rcgr = 0x2e004,
2460         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
2461         .hid_width = 5,
2462         .parent_map = gcc_xo_gpll0_gpll4_map,
2463         .clkr.hw.init = &(struct clk_init_data) {
2464                 .name = "system_noc_bfdcd_clk_src",
2465                 .parent_data = gcc_xo_gpll0_gpll4,
2466                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
2467                 .flags = CLK_IS_CRITICAL,
2468                 .ops = &clk_rcg2_ops,
2469         },
2470 };
2471
2472 static struct clk_branch gcc_q6ss_boot_clk = {
2473         .halt_reg = 0x25080,
2474         .halt_check = BRANCH_HALT_SKIP,
2475         .clkr = {
2476                 .enable_reg = 0x25080,
2477                 .enable_mask = BIT(0),
2478                 .hw.init = &(struct clk_init_data) {
2479                         .name = "gcc_q6ss_boot_clk",
2480                         .parent_hws = (const struct clk_hw *[]) {
2481                                 &system_noc_bfdcd_clk_src.clkr.hw
2482                         },
2483                         .num_parents = 1,
2484                         .flags = CLK_SET_RATE_PARENT,
2485                         .ops = &clk_branch2_ops,
2486                 },
2487         },
2488 };
2489
2490 static struct clk_branch gcc_nssnoc_snoc_clk = {
2491         .halt_reg = 0x17028,
2492         .clkr = {
2493                 .enable_reg = 0x17028,
2494                 .enable_mask = BIT(0),
2495                 .hw.init = &(struct clk_init_data) {
2496                         .name = "gcc_nssnoc_snoc_clk",
2497                         .parent_hws = (const struct clk_hw *[]) {
2498                                 &system_noc_bfdcd_clk_src.clkr.hw
2499                         },
2500                         .num_parents = 1,
2501                         .flags = CLK_SET_RATE_PARENT,
2502                         .ops = &clk_branch2_ops,
2503                 },
2504         },
2505 };
2506
2507 static struct clk_branch gcc_nssnoc_snoc_1_clk = {
2508         .halt_reg = 0x1707c,
2509         .clkr = {
2510                 .enable_reg = 0x1707c,
2511                 .enable_mask = BIT(0),
2512                 .hw.init = &(struct clk_init_data) {
2513                         .name = "gcc_nssnoc_snoc_1_clk",
2514                         .parent_hws = (const struct clk_hw *[]) {
2515                                 &system_noc_bfdcd_clk_src.clkr.hw
2516                         },
2517                         .num_parents = 1,
2518                         .flags = CLK_SET_RATE_PARENT,
2519                         .ops = &clk_branch2_ops,
2520                 },
2521         },
2522 };
2523
2524 static struct clk_branch gcc_qdss_etr_usb_clk = {
2525         .halt_reg = 0x2d060,
2526         .clkr = {
2527                 .enable_reg = 0x2d060,
2528                 .enable_mask = BIT(0),
2529                 .hw.init = &(struct clk_init_data) {
2530                         .name = "gcc_qdss_etr_usb_clk",
2531                         .parent_hws = (const struct clk_hw *[]) {
2532                                 &system_noc_bfdcd_clk_src.clkr.hw
2533                         },
2534                         .num_parents = 1,
2535                         .flags = CLK_SET_RATE_PARENT,
2536                         .ops = &clk_branch2_ops,
2537                 },
2538         },
2539 };
2540
2541 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2542         F(24000000, P_XO, 1, 0, 0),
2543         F(133333333, P_GPLL0, 6, 0, 0),
2544         { }
2545 };
2546
2547 static struct clk_rcg2 wcss_ahb_clk_src = {
2548         .cmd_rcgr = 0x25030,
2549         .freq_tbl = ftbl_wcss_ahb_clk_src,
2550         .hid_width = 5,
2551         .parent_map = gcc_xo_gpll0_map,
2552         .clkr.hw.init = &(struct clk_init_data) {
2553                 .name = "wcss_ahb_clk_src",
2554                 .parent_data = gcc_xo_gpll0,
2555                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2556                 .ops = &clk_rcg2_ops,
2557         },
2558 };
2559
2560 static struct clk_branch gcc_q6_ahb_clk = {
2561         .halt_reg = 0x25014,
2562         .clkr = {
2563                 .enable_reg = 0x25014,
2564                 .enable_mask = BIT(0),
2565                 .hw.init = &(struct clk_init_data) {
2566                         .name = "gcc_q6_ahb_clk",
2567                         .parent_hws = (const struct clk_hw *[]) {
2568                                 &wcss_ahb_clk_src.clkr.hw
2569                         },
2570                         .num_parents = 1,
2571                         .flags = CLK_SET_RATE_PARENT,
2572                         .ops = &clk_branch2_ops,
2573                 },
2574         },
2575 };
2576
2577 static struct clk_branch gcc_q6_ahb_s_clk = {
2578         .halt_reg = 0x25018,
2579         .clkr = {
2580                 .enable_reg = 0x25018,
2581                 .enable_mask = BIT(0),
2582                 .hw.init = &(struct clk_init_data) {
2583                         .name = "gcc_q6_ahb_s_clk",
2584                         .parent_hws = (const struct clk_hw *[]) {
2585                                 &wcss_ahb_clk_src.clkr.hw
2586                         },
2587                         .num_parents = 1,
2588                         .flags = CLK_SET_RATE_PARENT,
2589                         .ops = &clk_branch2_ops,
2590                 },
2591         },
2592 };
2593
2594 static struct clk_branch gcc_wcss_ecahb_clk = {
2595         .halt_reg = 0x25058,
2596         .clkr = {
2597                 .enable_reg = 0x25058,
2598                 .enable_mask = BIT(0),
2599                 .hw.init = &(struct clk_init_data) {
2600                         .name = "gcc_wcss_ecahb_clk",
2601                         .parent_hws = (const struct clk_hw *[]) {
2602                                 &wcss_ahb_clk_src.clkr.hw
2603                         },
2604                         .num_parents = 1,
2605                         .flags = CLK_SET_RATE_PARENT,
2606                         .ops = &clk_branch2_ops,
2607                 },
2608         },
2609 };
2610
2611 static struct clk_branch gcc_wcss_acmt_clk = {
2612         .halt_reg = 0x2505c,
2613         .clkr = {
2614                 .enable_reg = 0x2505c,
2615                 .enable_mask = BIT(0),
2616                 .hw.init = &(struct clk_init_data) {
2617                         .name = "gcc_wcss_acmt_clk",
2618                         .parent_hws = (const struct clk_hw *[]) {
2619                                 &wcss_ahb_clk_src.clkr.hw
2620                         },
2621                         .num_parents = 1,
2622                         .flags = CLK_SET_RATE_PARENT,
2623                         .ops = &clk_branch2_ops,
2624                 },
2625         },
2626 };
2627
2628 static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2629         .halt_reg = 0x2e030,
2630         .clkr = {
2631                 .enable_reg = 0x2e030,
2632                 .enable_mask = BIT(0),
2633                 .hw.init = &(struct clk_init_data) {
2634                         .name = "gcc_sys_noc_wcss_ahb_clk",
2635                         .parent_hws = (const struct clk_hw *[]) {
2636                                 &wcss_ahb_clk_src.clkr.hw
2637                         },
2638                         .num_parents = 1,
2639                         .flags = CLK_SET_RATE_PARENT,
2640                         .ops = &clk_branch2_ops,
2641                 },
2642         },
2643 };
2644
2645 static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
2646         F(24000000, P_XO, 1, 0, 0),
2647         F(133333333, P_GPLL0, 6, 0, 0),
2648         F(266666667, P_GPLL0, 3, 0, 0),
2649         { }
2650 };
2651
2652 static struct clk_rcg2 wcss_axi_m_clk_src = {
2653         .cmd_rcgr = 0x25078,
2654         .freq_tbl = ftbl_wcss_axi_m_clk_src,
2655         .hid_width = 5,
2656         .parent_map = gcc_xo_gpll0_map,
2657         .clkr.hw.init = &(struct clk_init_data) {
2658                 .name = "wcss_axi_m_clk_src",
2659                 .parent_data = gcc_xo_gpll0,
2660                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2661                 .ops = &clk_rcg2_ops,
2662         },
2663 };
2664
2665 static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
2666         .halt_reg = 0x2e0a8,
2667         .clkr = {
2668                 .enable_reg = 0x2e0a8,
2669                 .enable_mask = BIT(0),
2670                 .hw.init = &(struct clk_init_data) {
2671                         .name = "gcc_anoc_wcss_axi_m_clk",
2672                         .parent_hws = (const struct clk_hw *[]) {
2673                                 &wcss_axi_m_clk_src.clkr.hw
2674                         },
2675                         .num_parents = 1,
2676                         .flags = CLK_SET_RATE_PARENT,
2677                         .ops = &clk_branch2_ops,
2678                 },
2679         },
2680 };
2681
2682 static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
2683         F(240000000, P_GPLL4, 5, 0, 0),
2684         { }
2685 };
2686
2687 static struct clk_rcg2 qdss_at_clk_src = {
2688         .cmd_rcgr = 0x2d004,
2689         .freq_tbl = ftbl_qdss_at_clk_src,
2690         .hid_width = 5,
2691         .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2692         .clkr.hw.init = &(struct clk_init_data) {
2693                 .name = "qdss_at_clk_src",
2694                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2695                 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2696                 .ops = &clk_rcg2_ops,
2697         },
2698 };
2699
2700 static struct clk_branch gcc_q6ss_atbm_clk = {
2701         .halt_reg = 0x2501c,
2702         .clkr = {
2703                 .enable_reg = 0x2501c,
2704                 .enable_mask = BIT(0),
2705                 .hw.init = &(struct clk_init_data) {
2706                         .name = "gcc_q6ss_atbm_clk",
2707                         .parent_hws = (const struct clk_hw *[]) {
2708                                 &qdss_at_clk_src.clkr.hw
2709                         },
2710                         .num_parents = 1,
2711                         .flags = CLK_SET_RATE_PARENT,
2712                         .ops = &clk_branch2_ops,
2713                 },
2714         },
2715 };
2716
2717 static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
2718         .halt_reg = 0x2503c,
2719         .clkr = {
2720                 .enable_reg = 0x2503c,
2721                 .enable_mask = BIT(0),
2722                 .hw.init = &(struct clk_init_data) {
2723                         .name = "gcc_wcss_dbg_ifc_atb_clk",
2724                         .parent_hws = (const struct clk_hw *[]) {
2725                                 &qdss_at_clk_src.clkr.hw
2726                         },
2727                         .num_parents = 1,
2728                         .flags = CLK_SET_RATE_PARENT,
2729                         .ops = &clk_branch2_ops,
2730                 },
2731         },
2732 };
2733
2734 static struct clk_branch gcc_nssnoc_atb_clk = {
2735         .halt_reg = 0x17014,
2736         .clkr = {
2737                 .enable_reg = 0x17014,
2738                 .enable_mask = BIT(0),
2739                 .hw.init = &(struct clk_init_data) {
2740                         .name = "gcc_nssnoc_atb_clk",
2741                         .parent_hws = (const struct clk_hw *[]) {
2742                                 &qdss_at_clk_src.clkr.hw
2743                         },
2744                         .num_parents = 1,
2745                         .flags = CLK_SET_RATE_PARENT,
2746                         .ops = &clk_branch2_ops,
2747                 },
2748         },
2749 };
2750
2751 static struct clk_branch gcc_qdss_at_clk = {
2752         .halt_reg = 0x2d038,
2753         .clkr = {
2754                 .enable_reg = 0x2d038,
2755                 .enable_mask = BIT(0),
2756                 .hw.init = &(struct clk_init_data) {
2757                         .name = "gcc_qdss_at_clk",
2758                         .parent_hws = (const struct clk_hw *[]) {
2759                                 &qdss_at_clk_src.clkr.hw
2760                         },
2761                         .num_parents = 1,
2762                         .flags = CLK_SET_RATE_PARENT,
2763                         .ops = &clk_branch2_ops,
2764                 },
2765         },
2766 };
2767
2768 static struct clk_branch gcc_sys_noc_at_clk = {
2769         .halt_reg = 0x2e038,
2770         .clkr = {
2771                 .enable_reg = 0x2e038,
2772                 .enable_mask = BIT(0),
2773                 .hw.init = &(struct clk_init_data) {
2774                         .name = "gcc_sys_noc_at_clk",
2775                         .parent_hws = (const struct clk_hw *[]) {
2776                                 &qdss_at_clk_src.clkr.hw
2777                         },
2778                         .num_parents = 1,
2779                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2780                         .ops = &clk_branch2_ops,
2781                 },
2782         },
2783 };
2784
2785 static struct clk_branch gcc_pcnoc_at_clk = {
2786         .halt_reg = 0x31024,
2787         .clkr = {
2788                 .enable_reg = 0x31024,
2789                 .enable_mask = BIT(0),
2790                 .hw.init = &(struct clk_init_data) {
2791                         .name = "gcc_pcnoc_at_clk",
2792                         .parent_hws = (const struct clk_hw *[]) {
2793                                 &qdss_at_clk_src.clkr.hw
2794                         },
2795                         .num_parents = 1,
2796                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2797                         .ops = &clk_branch2_ops,
2798                 },
2799         },
2800 };
2801
2802 static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2803         .mult = 1,
2804         .div = 6,
2805         .hw.init = &(struct clk_init_data) {
2806                 .name = "gcc_eud_at_div_clk_src",
2807                 .parent_hws = (const struct clk_hw *[]) {
2808                         &qdss_at_clk_src.clkr.hw
2809                 },
2810                 .num_parents = 1,
2811                 .flags = CLK_SET_RATE_PARENT,
2812                 .ops = &clk_fixed_factor_ops,
2813         },
2814 };
2815
2816 static struct clk_branch gcc_usb0_eud_at_clk = {
2817         .halt_reg = 0x30004,
2818         .clkr = {
2819                 .enable_reg = 0x30004,
2820                 .enable_mask = BIT(0),
2821                 .hw.init = &(struct clk_init_data) {
2822                         .name = "gcc_usb0_eud_at_clk",
2823                         .parent_hws = (const struct clk_hw *[]) {
2824                                 &gcc_eud_at_div_clk_src.hw
2825                         },
2826                         .num_parents = 1,
2827                         .flags = CLK_SET_RATE_PARENT,
2828                         .ops = &clk_branch2_ops,
2829                 },
2830         },
2831 };
2832
2833 static struct clk_branch gcc_qdss_eud_at_clk = {
2834         .halt_reg = 0x2d06c,
2835         .clkr = {
2836                 .enable_reg = 0x2d06c,
2837                 .enable_mask = BIT(0),
2838                 .hw.init = &(struct clk_init_data) {
2839                         .name = "gcc_qdss_eud_at_clk",
2840                         .parent_hws = (const struct clk_hw *[]) {
2841                                 &gcc_eud_at_div_clk_src.hw
2842                         },
2843                         .num_parents = 1,
2844                         .flags = CLK_SET_RATE_PARENT,
2845                         .ops = &clk_branch2_ops,
2846                 },
2847         },
2848 };
2849
2850 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
2851         F(24000000, P_XO, 1, 0, 0),
2852         F(200000000, P_GPLL0, 4, 0, 0),
2853         { }
2854 };
2855
2856 static struct clk_rcg2 qdss_stm_clk_src = {
2857         .cmd_rcgr = 0x2d00c,
2858         .freq_tbl = ftbl_qdss_stm_clk_src,
2859         .hid_width = 5,
2860         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2861         .clkr.hw.init = &(struct clk_init_data) {
2862                 .name = "qdss_stm_clk_src",
2863                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2864                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2865                 .ops = &clk_rcg2_ops,
2866         },
2867 };
2868
2869 static struct clk_branch gcc_qdss_stm_clk = {
2870         .halt_reg = 0x2d03c,
2871         .clkr = {
2872                 .enable_reg = 0x2d03c,
2873                 .enable_mask = BIT(0),
2874                 .hw.init = &(struct clk_init_data) {
2875                         .name = "gcc_qdss_stm_clk",
2876                         .parent_hws = (const struct clk_hw *[]) {
2877                                 &qdss_stm_clk_src.clkr.hw
2878                         },
2879                         .num_parents = 1,
2880                         .flags = CLK_SET_RATE_PARENT,
2881                         .ops = &clk_branch2_ops,
2882                 },
2883         },
2884 };
2885
2886 static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
2887         .halt_reg = 0x2e034,
2888         .clkr = {
2889                 .enable_reg = 0x2e034,
2890                 .enable_mask = BIT(0),
2891                 .hw.init = &(struct clk_init_data) {
2892                         .name = "gcc_sys_noc_qdss_stm_axi_clk",
2893                         .parent_hws = (const struct clk_hw *[]) {
2894                                 &qdss_stm_clk_src.clkr.hw
2895                         },
2896                         .num_parents = 1,
2897                         .flags = CLK_SET_RATE_PARENT,
2898                         .ops = &clk_branch2_ops,
2899                 },
2900         },
2901 };
2902
2903 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
2904         F(300000000, P_GPLL4, 4, 0, 0),
2905         { }
2906 };
2907
2908 static struct clk_rcg2 qdss_traceclkin_clk_src = {
2909         .cmd_rcgr = 0x2d014,
2910         .freq_tbl = ftbl_qdss_traceclkin_clk_src,
2911         .hid_width = 5,
2912         .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2913         .clkr.hw.init = &(struct clk_init_data) {
2914                 .name = "qdss_traceclkin_clk_src",
2915                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2916                 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2917                 .ops = &clk_rcg2_ops,
2918         },
2919 };
2920
2921 static struct clk_branch gcc_qdss_traceclkin_clk = {
2922         .halt_reg = 0x2d040,
2923         .clkr = {
2924                 .enable_reg = 0x2d040,
2925                 .enable_mask = BIT(0),
2926                 .hw.init = &(struct clk_init_data) {
2927                         .name = "gcc_qdss_traceclkin_clk",
2928                         .parent_hws = (const struct clk_hw *[]) {
2929                                 &qdss_traceclkin_clk_src.clkr.hw
2930                         },
2931                         .num_parents = 1,
2932                         .flags = CLK_SET_RATE_PARENT,
2933                         .ops = &clk_branch2_ops,
2934                 },
2935         },
2936 };
2937
2938 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
2939         F(600000000, P_GPLL4, 2, 0, 0),
2940         { }
2941 };
2942
2943 static struct clk_rcg2 qdss_tsctr_clk_src = {
2944         .cmd_rcgr = 0x2d01c,
2945         .freq_tbl = ftbl_qdss_tsctr_clk_src,
2946         .hid_width = 5,
2947         .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2948         .clkr.hw.init = &(struct clk_init_data) {
2949                 .name = "qdss_tsctr_clk_src",
2950                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2951                 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2952                 .ops = &clk_rcg2_ops,
2953         },
2954 };
2955
2956 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
2957         .mult = 1,
2958         .div = 2,
2959         .hw.init = &(struct clk_init_data) {
2960                 .name = "qdss_tsctr_div2_clk_src",
2961                 .parent_hws = (const struct clk_hw *[]) {
2962                         &qdss_tsctr_clk_src.clkr.hw
2963                 },
2964                 .num_parents = 1,
2965                 .flags = CLK_SET_RATE_PARENT,
2966                 .ops = &clk_fixed_factor_ops,
2967         },
2968 };
2969
2970 static struct clk_branch gcc_q6_tsctr_1to2_clk = {
2971         .halt_reg = 0x25020,
2972         .clkr = {
2973                 .enable_reg = 0x25020,
2974                 .enable_mask = BIT(0),
2975                 .hw.init = &(struct clk_init_data) {
2976                         .name = "gcc_q6_tsctr_1to2_clk",
2977                         .parent_hws = (const struct clk_hw *[]) {
2978                                 &qdss_tsctr_div2_clk_src.hw
2979                         },
2980                         .num_parents = 1,
2981                         .flags = CLK_SET_RATE_PARENT,
2982                         .ops = &clk_branch2_ops,
2983                 },
2984         },
2985 };
2986
2987 static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
2988         .halt_reg = 0x25040,
2989         .clkr = {
2990                 .enable_reg = 0x25040,
2991                 .enable_mask = BIT(0),
2992                 .hw.init = &(struct clk_init_data) {
2993                         .name = "gcc_wcss_dbg_ifc_nts_clk",
2994                         .parent_hws = (const struct clk_hw *[]) {
2995                                 &qdss_tsctr_div2_clk_src.hw
2996                         },
2997                         .num_parents = 1,
2998                         .flags = CLK_SET_RATE_PARENT,
2999                         .ops = &clk_branch2_ops,
3000                 },
3001         },
3002 };
3003
3004 static struct clk_branch gcc_qdss_tsctr_div2_clk = {
3005         .halt_reg = 0x2d044,
3006         .clkr = {
3007                 .enable_reg = 0x2d044,
3008                 .enable_mask = BIT(0),
3009                 .hw.init = &(struct clk_init_data) {
3010                         .name = "gcc_qdss_tsctr_div2_clk",
3011                         .parent_hws = (const struct clk_hw *[]) {
3012                                 &qdss_tsctr_div2_clk_src.hw
3013                         },
3014                         .num_parents = 1,
3015                         .flags = CLK_SET_RATE_PARENT,
3016                         .ops = &clk_branch2_ops,
3017                 },
3018         },
3019 };
3020
3021 static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
3022         F(24000000, P_XO, 1, 0, 0),
3023         { }
3024 };
3025
3026 static struct clk_rcg2 uniphy_sys_clk_src = {
3027         .cmd_rcgr = 0x17090,
3028         .freq_tbl = ftbl_uniphy_sys_clk_src,
3029         .mnd_width = 8,
3030         .hid_width = 5,
3031         .parent_map = gcc_xo_map,
3032         .clkr.hw.init = &(struct clk_init_data) {
3033                 .name = "uniphy_sys_clk_src",
3034                 .parent_data = gcc_xo_data,
3035                 .num_parents = ARRAY_SIZE(gcc_xo_data),
3036                 .ops = &clk_rcg2_ops,
3037         },
3038 };
3039
3040 static struct clk_rcg2 nss_ts_clk_src = {
3041         .cmd_rcgr = 0x17088,
3042         .freq_tbl = ftbl_uniphy_sys_clk_src,
3043         .mnd_width = 8,
3044         .hid_width = 5,
3045         .parent_map = gcc_xo_map,
3046         .clkr.hw.init = &(struct clk_init_data) {
3047                 .name = "nss_ts_clk_src",
3048                 .parent_data = gcc_xo_data,
3049                 .num_parents = ARRAY_SIZE(gcc_xo_data),
3050                 .ops = &clk_rcg2_ops,
3051         },
3052 };
3053
3054 static struct clk_branch gcc_qdss_ts_clk = {
3055         .halt_reg = 0x2d078,
3056         .clkr = {
3057                 .enable_reg = 0x2d078,
3058                 .enable_mask = BIT(0),
3059                 .hw.init = &(struct clk_init_data) {
3060                         .name = "gcc_qdss_ts_clk",
3061                         .parent_hws = (const struct clk_hw *[]) {
3062                                 &nss_ts_clk_src.clkr.hw
3063                         },
3064                         .num_parents = 1,
3065                         .flags = CLK_SET_RATE_PARENT,
3066                         .ops = &clk_branch2_ops,
3067                 },
3068         },
3069 };
3070
3071 static struct clk_fixed_factor qdss_dap_sync_clk_src = {
3072         .mult = 1,
3073         .div = 4,
3074         .hw.init = &(struct clk_init_data) {
3075                 .name = "qdss_dap_sync_clk_src",
3076                 .parent_hws = (const struct clk_hw *[]) {
3077                         &qdss_tsctr_clk_src.clkr.hw
3078                 },
3079                 .num_parents = 1,
3080                 .ops = &clk_fixed_factor_ops,
3081         },
3082 };
3083
3084 static struct clk_branch gcc_qdss_tsctr_div4_clk = {
3085         .halt_reg = 0x2d04c,
3086         .clkr = {
3087                 .enable_reg = 0x2d04c,
3088                 .enable_mask = BIT(0),
3089                 .hw.init = &(struct clk_init_data) {
3090                         .name = "gcc_qdss_tsctr_div4_clk",
3091                         .parent_hws = (const struct clk_hw *[]) {
3092                                 &qdss_dap_sync_clk_src.hw
3093                         },
3094                         .num_parents = 1,
3095                         .flags = CLK_SET_RATE_PARENT,
3096                         .ops = &clk_branch2_ops,
3097                 },
3098         },
3099 };
3100
3101 static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
3102         .mult = 1,
3103         .div = 8,
3104         .hw.init = &(struct clk_init_data) {
3105                 .name = "qdss_tsctr_div8_clk_src",
3106                 .parent_hws = (const struct clk_hw *[]) {
3107                         &qdss_tsctr_clk_src.clkr.hw
3108                 },
3109                 .num_parents = 1,
3110                 .ops = &clk_fixed_factor_ops,
3111         },
3112 };
3113
3114 static struct clk_branch gcc_nss_ts_clk = {
3115         .halt_reg = 0x17018,
3116         .clkr = {
3117                 .enable_reg = 0x17018,
3118                 .enable_mask = BIT(0),
3119                 .hw.init = &(struct clk_init_data) {
3120                         .name = "gcc_nss_ts_clk",
3121                         .parent_hws = (const struct clk_hw *[]) {
3122                                 &nss_ts_clk_src.clkr.hw
3123                         },
3124                         .num_parents = 1,
3125                         .flags = CLK_SET_RATE_PARENT,
3126                         .ops = &clk_branch2_ops,
3127                 },
3128         },
3129 };
3130
3131 static struct clk_branch gcc_qdss_tsctr_div8_clk = {
3132         .halt_reg = 0x2d050,
3133         .clkr = {
3134                 .enable_reg = 0x2d050,
3135                 .enable_mask = BIT(0),
3136                 .hw.init = &(struct clk_init_data) {
3137                         .name = "gcc_qdss_tsctr_div8_clk",
3138                         .parent_hws = (const struct clk_hw *[]) {
3139                                 &qdss_tsctr_div8_clk_src.hw
3140                         },
3141                         .num_parents = 1,
3142                         .flags = CLK_SET_RATE_PARENT,
3143                         .ops = &clk_branch2_ops,
3144                 },
3145         },
3146 };
3147
3148 static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
3149         .mult = 1,
3150         .div = 16,
3151         .hw.init = &(struct clk_init_data) {
3152                 .name = "qdss_tsctr_div16_clk_src",
3153                 .parent_hws = (const struct clk_hw *[]) {
3154                         &qdss_tsctr_clk_src.clkr.hw
3155                 },
3156                 .num_parents = 1,
3157                 .ops = &clk_fixed_factor_ops,
3158         },
3159 };
3160
3161 static struct clk_branch gcc_qdss_tsctr_div16_clk = {
3162         .halt_reg = 0x2d054,
3163         .clkr = {
3164                 .enable_reg = 0x2d054,
3165                 .enable_mask = BIT(0),
3166                 .hw.init = &(struct clk_init_data) {
3167                         .name = "gcc_qdss_tsctr_div16_clk",
3168                         .parent_hws = (const struct clk_hw *[]) {
3169                                 &qdss_tsctr_div16_clk_src.hw
3170                         },
3171                         .num_parents = 1,
3172                         .flags = CLK_SET_RATE_PARENT,
3173                         .ops = &clk_branch2_ops,
3174                 },
3175         },
3176 };
3177
3178 static struct clk_branch gcc_q6ss_pclkdbg_clk = {
3179         .halt_reg = 0x25024,
3180         .clkr = {
3181                 .enable_reg = 0x25024,
3182                 .enable_mask = BIT(0),
3183                 .hw.init = &(struct clk_init_data) {
3184                         .name = "gcc_q6ss_pclkdbg_clk",
3185                         .parent_hws = (const struct clk_hw *[]) {
3186                                 &qdss_dap_sync_clk_src.hw
3187                         },
3188                         .num_parents = 1,
3189                         .flags = CLK_SET_RATE_PARENT,
3190                         .ops = &clk_branch2_ops,
3191                 },
3192         },
3193 };
3194
3195 static struct clk_branch gcc_q6ss_trig_clk = {
3196         .halt_reg = 0x25068,
3197         .clkr = {
3198                 .enable_reg = 0x25068,
3199                 .enable_mask = BIT(0),
3200                 .hw.init = &(struct clk_init_data) {
3201                         .name = "gcc_q6ss_trig_clk",
3202                         .parent_hws = (const struct clk_hw *[]) {
3203                                 &qdss_dap_sync_clk_src.hw
3204                         },
3205                         .num_parents = 1,
3206                         .flags = CLK_SET_RATE_PARENT,
3207                         .ops = &clk_branch2_ops,
3208                 },
3209         },
3210 };
3211
3212 static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3213         .halt_reg = 0x25038,
3214         .clkr = {
3215                 .enable_reg = 0x25038,
3216                 .enable_mask = BIT(0),
3217                 .hw.init = &(struct clk_init_data) {
3218                         .name = "gcc_wcss_dbg_ifc_apb_clk",
3219                         .parent_hws = (const struct clk_hw *[]) {
3220                                 &qdss_dap_sync_clk_src.hw
3221                         },
3222                         .num_parents = 1,
3223                         .flags = CLK_SET_RATE_PARENT,
3224                         .ops = &clk_branch2_ops,
3225                 },
3226         },
3227 };
3228
3229 static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
3230         .halt_reg = 0x25044,
3231         .clkr = {
3232                 .enable_reg = 0x25044,
3233                 .enable_mask = BIT(0),
3234                 .hw.init = &(struct clk_init_data) {
3235                         .name = "gcc_wcss_dbg_ifc_dapbus_clk",
3236                         .parent_hws = (const struct clk_hw *[]) {
3237                                 &qdss_dap_sync_clk_src.hw
3238                         },
3239                         .num_parents = 1,
3240                         .flags = CLK_SET_RATE_PARENT,
3241                         .ops = &clk_branch2_ops,
3242                 },
3243         },
3244 };
3245
3246 static struct clk_branch gcc_qdss_dap_clk = {
3247         .halt_reg = 0x2d058,
3248         .clkr = {
3249                 .enable_reg = 0x2d058,
3250                 .enable_mask = BIT(0),
3251                 .hw.init = &(struct clk_init_data) {
3252                         .name = "gcc_qdss_dap_clk",
3253                         .parent_hws = (const struct clk_hw *[]) {
3254                                 &qdss_dap_sync_clk_src.hw
3255                         },
3256                         .num_parents = 1,
3257                         .flags = CLK_SET_RATE_PARENT,
3258                         .ops = &clk_branch2_ops,
3259                 },
3260         },
3261 };
3262
3263 static struct clk_branch gcc_qdss_apb2jtag_clk = {
3264         .halt_reg = 0x2d05c,
3265         .clkr = {
3266                 .enable_reg = 0x2d05c,
3267                 .enable_mask = BIT(0),
3268                 .hw.init = &(struct clk_init_data) {
3269                         .name = "gcc_qdss_apb2jtag_clk",
3270                         .parent_hws = (const struct clk_hw *[]) {
3271                                 &qdss_dap_sync_clk_src.hw
3272                         },
3273                         .num_parents = 1,
3274                         .flags = CLK_SET_RATE_PARENT,
3275                         .ops = &clk_branch2_ops,
3276                 },
3277         },
3278 };
3279
3280 static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
3281         .mult = 1,
3282         .div = 3,
3283         .hw.init = &(struct clk_init_data) {
3284                 .name = "qdss_tsctr_div3_clk_src",
3285                 .parent_hws = (const struct clk_hw *[]) {
3286                         &qdss_tsctr_clk_src.clkr.hw
3287                 },
3288                 .num_parents = 1,
3289                 .ops = &clk_fixed_factor_ops,
3290         },
3291 };
3292
3293 static struct clk_branch gcc_qdss_tsctr_div3_clk = {
3294         .halt_reg = 0x2d048,
3295         .clkr = {
3296                 .enable_reg = 0x2d048,
3297                 .enable_mask = BIT(0),
3298                 .hw.init = &(struct clk_init_data) {
3299                         .name = "gcc_qdss_tsctr_div3_clk",
3300                         .parent_hws = (const struct clk_hw *[]) {
3301                                 &qdss_tsctr_div3_clk_src.hw
3302                         },
3303                         .num_parents = 1,
3304                         .flags = CLK_SET_RATE_PARENT,
3305                         .ops = &clk_branch2_ops,
3306                 },
3307         },
3308 };
3309
3310 static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
3311         F(24000000, P_XO, 1, 0, 0),
3312         F(100000000, P_GPLL0, 8, 0, 0),
3313         F(200000000, P_GPLL0, 4, 0, 0),
3314         F(320000000, P_GPLL0, 2.5, 0, 0),
3315         F(400000000, P_GPLL0, 2, 0, 0),
3316         { }
3317 };
3318
3319 static struct clk_rcg2 qpic_io_macro_clk_src = {
3320         .cmd_rcgr = 0x32004,
3321         .freq_tbl = ftbl_qpic_io_macro_clk_src,
3322         .hid_width = 5,
3323         .parent_map = gcc_xo_gpll0_gpll2_map,
3324         .clkr.hw.init = &(struct clk_init_data) {
3325                 .name = "qpic_io_macro_clk_src",
3326                 .parent_data = gcc_xo_gpll0_gpll2,
3327                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
3328                 .ops = &clk_rcg2_ops,
3329         },
3330 };
3331
3332 static struct clk_branch gcc_qpic_io_macro_clk = {
3333         .halt_reg = 0x3200c,
3334         .clkr = {
3335                 .enable_reg = 0x3200c,
3336                 .enable_mask = BIT(0),
3337                 .hw.init = &(struct clk_init_data){
3338                         .name = "gcc_qpic_io_macro_clk",
3339                         .parent_hws = (const struct clk_hw *[]){
3340                                 &qpic_io_macro_clk_src.clkr.hw
3341                         },
3342                         .num_parents = 1,
3343                         .flags = CLK_SET_RATE_PARENT,
3344                         .ops = &clk_branch2_ops,
3345                 },
3346         },
3347 };
3348
3349 static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
3350         F(533333333, P_GPLL0, 1.5, 0, 0),
3351         { }
3352 };
3353
3354 static struct clk_rcg2 q6_axi_clk_src = {
3355         .cmd_rcgr = 0x25004,
3356         .freq_tbl = ftbl_q6_axi_clk_src,
3357         .hid_width = 5,
3358         .parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
3359         .clkr.hw.init = &(struct clk_init_data) {
3360                 .name = "q6_axi_clk_src",
3361                 .parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
3362                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
3363                 .ops = &clk_rcg2_ops,
3364         },
3365 };
3366
3367 static struct clk_branch gcc_q6_axim_clk = {
3368         .halt_reg = 0x2500c,
3369         .clkr = {
3370                 .enable_reg = 0x2500c,
3371                 .enable_mask = BIT(0),
3372                 .hw.init = &(struct clk_init_data) {
3373                         .name = "gcc_q6_axim_clk",
3374                         .parent_hws = (const struct clk_hw *[]) {
3375                                 &q6_axi_clk_src.clkr.hw
3376                         },
3377                         .num_parents = 1,
3378                         .flags = CLK_SET_RATE_PARENT,
3379                         .ops = &clk_branch2_ops,
3380                 },
3381         },
3382 };
3383
3384 static struct clk_branch gcc_wcss_q6_tbu_clk = {
3385         .halt_reg = 0x12050,
3386         .halt_check = BRANCH_HALT_DELAY,
3387         .clkr = {
3388                 .enable_reg = 0xb00c,
3389                 .enable_mask = BIT(6),
3390                 .hw.init = &(struct clk_init_data) {
3391                         .name = "gcc_wcss_q6_tbu_clk",
3392                         .parent_hws = (const struct clk_hw *[]) {
3393                                 &q6_axi_clk_src.clkr.hw
3394                         },
3395                         .num_parents = 1,
3396                         .flags = CLK_SET_RATE_PARENT,
3397                         .ops = &clk_branch2_ops,
3398                 },
3399         },
3400 };
3401
3402 static struct clk_branch gcc_mem_noc_q6_axi_clk = {
3403         .halt_reg = 0x19010,
3404         .clkr = {
3405                 .enable_reg = 0x19010,
3406                 .enable_mask = BIT(0),
3407                 .hw.init = &(struct clk_init_data) {
3408                         .name = "gcc_mem_noc_q6_axi_clk",
3409                         .parent_hws = (const struct clk_hw *[]) {
3410                                 &q6_axi_clk_src.clkr.hw
3411                         },
3412                         .num_parents = 1,
3413                         .flags = CLK_SET_RATE_PARENT,
3414                         .ops = &clk_branch2_ops,
3415                 },
3416         },
3417 };
3418
3419 static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
3420         F(342857143, P_GPLL4, 3.5, 0, 0),
3421         { }
3422 };
3423
3424 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
3425         { P_XO, 0 },
3426         { P_GPLL0, 1 },
3427         { P_GPLL4, 2 },
3428         { P_BIAS_PLL_UBI_NC_CLK, 4 },
3429 };
3430
3431 static struct clk_rcg2 q6_axim2_clk_src = {
3432         .cmd_rcgr = 0x25028,
3433         .freq_tbl = ftbl_q6_axim2_clk_src,
3434         .hid_width = 5,
3435         .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
3436         .clkr.hw.init = &(struct clk_init_data) {
3437                 .name = "q6_axim2_clk_src",
3438                 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
3439                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
3440                 .ops = &clk_rcg2_ops,
3441         },
3442 };
3443
3444 static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
3445         F(533333333, P_GPLL0, 1.5, 0, 0),
3446         { }
3447 };
3448
3449 static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
3450         .cmd_rcgr = 0x17004,
3451         .freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
3452         .hid_width = 5,
3453         .parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
3454         .clkr.hw.init = &(struct clk_init_data) {
3455                 .name = "nssnoc_memnoc_bfdcd_clk_src",
3456                 .parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
3457                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
3458                 .ops = &clk_rcg2_ops,
3459         },
3460 };
3461
3462 static struct clk_branch gcc_nssnoc_memnoc_clk = {
3463         .halt_reg = 0x17024,
3464         .clkr = {
3465                 .enable_reg = 0x17024,
3466                 .enable_mask = BIT(0),
3467                 .hw.init = &(struct clk_init_data) {
3468                         .name = "gcc_nssnoc_memnoc_clk",
3469                         .parent_hws = (const struct clk_hw *[]) {
3470                                 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3471                         },
3472                         .num_parents = 1,
3473                         .flags = CLK_SET_RATE_PARENT,
3474                         .ops = &clk_branch2_ops,
3475                 },
3476         },
3477 };
3478
3479 static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
3480         .halt_reg = 0x17084,
3481         .clkr = {
3482                 .enable_reg = 0x17084,
3483                 .enable_mask = BIT(0),
3484                 .hw.init = &(struct clk_init_data) {
3485                         .name = "gcc_nssnoc_mem_noc_1_clk",
3486                         .parent_hws = (const struct clk_hw *[]) {
3487                                 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3488                         },
3489                         .num_parents = 1,
3490                         .flags = CLK_SET_RATE_PARENT,
3491                         .ops = &clk_branch2_ops,
3492                 },
3493         },
3494 };
3495
3496 static struct clk_branch gcc_nss_tbu_clk = {
3497         .halt_reg = 0x12040,
3498         .clkr = {
3499                 .enable_reg = 0xb00c,
3500                 .enable_mask = BIT(4),
3501                 .hw.init = &(struct clk_init_data) {
3502                         .name = "gcc_nss_tbu_clk",
3503                         .parent_hws = (const struct clk_hw *[]) {
3504                                 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3505                         },
3506                         .num_parents = 1,
3507                         .flags = CLK_SET_RATE_PARENT,
3508                         .ops = &clk_branch2_ops,
3509                 },
3510         },
3511 };
3512
3513 static struct clk_branch gcc_mem_noc_nssnoc_clk = {
3514         .halt_reg = 0x19014,
3515         .clkr = {
3516                 .enable_reg = 0x19014,
3517                 .enable_mask = BIT(0),
3518                 .hw.init = &(struct clk_init_data) {
3519                         .name = "gcc_mem_noc_nssnoc_clk",
3520                         .parent_hws = (const struct clk_hw *[]) {
3521                                 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3522                         },
3523                         .num_parents = 1,
3524                         .flags = CLK_SET_RATE_PARENT,
3525                         .ops = &clk_branch2_ops,
3526                 },
3527         },
3528 };
3529
3530 static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
3531         F(133333333, P_GPLL0, 6, 0, 0),
3532         { }
3533 };
3534
3535 static struct clk_rcg2 lpass_axim_clk_src = {
3536         .cmd_rcgr = 0x2700c,
3537         .freq_tbl = ftbl_lpass_axim_clk_src,
3538         .hid_width = 5,
3539         .parent_map = gcc_xo_gpll0_map,
3540         .clkr.hw.init = &(struct clk_init_data) {
3541                 .name = "lpass_axim_clk_src",
3542                 .parent_data = gcc_xo_gpll0,
3543                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3544                 .ops = &clk_rcg2_ops,
3545         },
3546 };
3547
3548 static struct clk_rcg2 lpass_sway_clk_src = {
3549         .cmd_rcgr = 0x27004,
3550         .freq_tbl = ftbl_lpass_axim_clk_src,
3551         .hid_width = 5,
3552         .parent_map = gcc_xo_gpll0_map,
3553         .clkr.hw.init = &(struct clk_init_data) {
3554                 .name = "lpass_sway_clk_src",
3555                 .parent_data = gcc_xo_gpll0,
3556                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3557                 .ops = &clk_rcg2_ops,
3558         },
3559 };
3560
3561 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
3562         F(24000000, P_XO, 1, 0, 0),
3563         F(100000000, P_GPLL0, 8, 0, 0),
3564         { }
3565 };
3566
3567 static struct clk_rcg2 adss_pwm_clk_src = {
3568         .cmd_rcgr = 0x1c004,
3569         .freq_tbl = ftbl_adss_pwm_clk_src,
3570         .hid_width = 5,
3571         .parent_map = gcc_xo_gpll0_map,
3572         .clkr.hw.init = &(struct clk_init_data) {
3573                 .name = "adss_pwm_clk_src",
3574                 .parent_data = gcc_xo_gpll0,
3575                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3576                 .ops = &clk_rcg2_ops,
3577         },
3578 };
3579
3580 static struct clk_branch gcc_adss_pwm_clk = {
3581         .halt_reg = 0x1c00c,
3582         .clkr = {
3583                 .enable_reg = 0x1c00c,
3584                 .enable_mask = BIT(0),
3585                 .hw.init = &(struct clk_init_data) {
3586                         .name = "gcc_adss_pwm_clk",
3587                         .parent_hws = (const struct clk_hw *[]) {
3588                                 &adss_pwm_clk_src.clkr.hw
3589                         },
3590                         .num_parents = 1,
3591                         .flags = CLK_SET_RATE_PARENT,
3592                         .ops = &clk_branch2_ops,
3593                 },
3594         },
3595 };
3596
3597 static const struct freq_tbl ftbl_gp1_clk_src[] = {
3598         F(24000000, P_XO, 1, 0, 0),
3599         F(200000000, P_GPLL0, 4, 0, 0),
3600         { }
3601 };
3602
3603 static struct clk_rcg2 gp1_clk_src = {
3604         .cmd_rcgr = 0x8004,
3605         .freq_tbl = ftbl_gp1_clk_src,
3606         .hid_width = 5,
3607         .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3608         .clkr.hw.init = &(struct clk_init_data) {
3609                 .name = "gp1_clk_src",
3610                 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3611                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3612                 .ops = &clk_rcg2_ops,
3613         },
3614 };
3615
3616 static struct clk_rcg2 gp2_clk_src = {
3617         .cmd_rcgr = 0x9004,
3618         .freq_tbl = ftbl_gp1_clk_src,
3619         .hid_width = 5,
3620         .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3621         .clkr.hw.init = &(struct clk_init_data) {
3622                 .name = "gp2_clk_src",
3623                 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3624                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3625                 .ops = &clk_rcg2_ops,
3626         },
3627 };
3628
3629 static struct clk_rcg2 gp3_clk_src = {
3630         .cmd_rcgr = 0xa004,
3631         .freq_tbl = ftbl_gp1_clk_src,
3632         .hid_width = 5,
3633         .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3634         .clkr.hw.init = &(struct clk_init_data) {
3635                 .name = "gp3_clk_src",
3636                 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3637                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3638                 .ops = &clk_rcg2_ops,
3639         },
3640 };
3641
3642 static struct clk_branch gcc_xo_clk_src = {
3643         .halt_reg = 0x34004,
3644         .clkr = {
3645                 .enable_reg = 0x34004,
3646                 .enable_mask = BIT(1),
3647                 .hw.init = &(struct clk_init_data) {
3648                         .name = "gcc_xo_clk_src",
3649                         .parent_data = gcc_xo_data,
3650                         .num_parents = ARRAY_SIZE(gcc_xo_data),
3651                         .flags = CLK_SET_RATE_PARENT,
3652                         .ops = &clk_branch2_ops,
3653                 },
3654         },
3655 };
3656
3657 static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
3658         .halt_reg = 0x17074,
3659         .clkr = {
3660                 .enable_reg = 0x17074,
3661                 .enable_mask = BIT(0),
3662                 .hw.init = &(struct clk_init_data) {
3663                         .name = "gcc_nssnoc_xo_dcd_clk",
3664                         .parent_hws = (const struct clk_hw *[]) {
3665                                 &gcc_xo_clk_src.clkr.hw
3666                         },
3667                         .num_parents = 1,
3668                         .flags = CLK_SET_RATE_PARENT,
3669                         .ops = &clk_branch2_ops,
3670                 },
3671         },
3672 };
3673
3674 static struct clk_branch gcc_xo_clk = {
3675         .halt_reg = 0x34018,
3676         .clkr = {
3677                 .enable_reg = 0x34018,
3678                 .enable_mask = BIT(0),
3679                 .hw.init = &(struct clk_init_data) {
3680                         .name = "gcc_xo_clk",
3681                         .parent_hws = (const struct clk_hw *[]) {
3682                                 &gcc_xo_clk_src.clkr.hw
3683                         },
3684                         .num_parents = 1,
3685                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3686                         .ops = &clk_branch2_ops,
3687                 },
3688         },
3689 };
3690
3691 static struct clk_branch gcc_uniphy0_sys_clk = {
3692         .halt_reg = 0x17048,
3693         .clkr = {
3694                 .enable_reg = 0x17048,
3695                 .enable_mask = BIT(0),
3696                 .hw.init = &(struct clk_init_data) {
3697                         .name = "gcc_uniphy0_sys_clk",
3698                         .parent_hws = (const struct clk_hw *[]) {
3699                                 &uniphy_sys_clk_src.clkr.hw
3700                         },
3701                         .num_parents = 1,
3702                         .flags = CLK_SET_RATE_PARENT,
3703                         .ops = &clk_branch2_ops,
3704                 },
3705         },
3706 };
3707
3708 static struct clk_branch gcc_uniphy1_sys_clk = {
3709         .halt_reg = 0x17058,
3710         .clkr = {
3711                 .enable_reg = 0x17058,
3712                 .enable_mask = BIT(0),
3713                 .hw.init = &(struct clk_init_data) {
3714                         .name = "gcc_uniphy1_sys_clk",
3715                         .parent_hws = (const struct clk_hw *[]) {
3716                                 &uniphy_sys_clk_src.clkr.hw
3717                         },
3718                         .num_parents = 1,
3719                         .flags = CLK_SET_RATE_PARENT,
3720                         .ops = &clk_branch2_ops,
3721                 },
3722         },
3723 };
3724
3725 static struct clk_branch gcc_uniphy2_sys_clk = {
3726         .halt_reg = 0x17068,
3727         .clkr = {
3728                 .enable_reg = 0x17068,
3729                 .enable_mask = BIT(0),
3730                 .hw.init = &(struct clk_init_data) {
3731                         .name = "gcc_uniphy2_sys_clk",
3732                         .parent_hws = (const struct clk_hw *[]) {
3733                                 &uniphy_sys_clk_src.clkr.hw
3734                         },
3735                         .num_parents = 1,
3736                         .flags = CLK_SET_RATE_PARENT,
3737                         .ops = &clk_branch2_ops,
3738                 },
3739         },
3740 };
3741
3742 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3743         .halt_reg = 0x3a008,
3744         .clkr = {
3745                 .enable_reg = 0x3a008,
3746                 .enable_mask = BIT(0),
3747                 .hw.init = &(struct clk_init_data) {
3748                         .name = "gcc_cmn_12gpll_sys_clk",
3749                         .parent_hws = (const struct clk_hw *[]) {
3750                                 &uniphy_sys_clk_src.clkr.hw
3751                         },
3752                         .num_parents = 1,
3753                         .flags = CLK_SET_RATE_PARENT,
3754                         .ops = &clk_branch2_ops,
3755                 },
3756         },
3757 };
3758
3759 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
3760         .mult = 1,
3761         .div = 4,
3762         .hw.init = &(struct clk_init_data) {
3763                 .name = "gcc_xo_div4_clk_src",
3764                 .parent_hws = (const struct clk_hw *[]) {
3765                         &gcc_xo_clk_src.clkr.hw
3766                 },
3767                 .num_parents = 1,
3768                 .flags = CLK_SET_RATE_PARENT,
3769                 .ops = &clk_fixed_factor_ops,
3770         },
3771 };
3772
3773 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3774         .halt_reg = 0x1701c,
3775         .clkr = {
3776                 .enable_reg = 0x1701c,
3777                 .enable_mask = BIT(0),
3778                 .hw.init = &(struct clk_init_data) {
3779                         .name = "gcc_nssnoc_qosgen_ref_clk",
3780                         .parent_hws = (const struct clk_hw *[]) {
3781                                 &gcc_xo_div4_clk_src.hw
3782                         },
3783                         .num_parents = 1,
3784                         .flags = CLK_SET_RATE_PARENT,
3785                         .ops = &clk_branch2_ops,
3786                 },
3787         },
3788 };
3789
3790 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3791         .halt_reg = 0x17020,
3792         .clkr = {
3793                 .enable_reg = 0x17020,
3794                 .enable_mask = BIT(0),
3795                 .hw.init = &(struct clk_init_data) {
3796                         .name = "gcc_nssnoc_timeout_ref_clk",
3797                         .parent_hws = (const struct clk_hw *[]) {
3798                                 &gcc_xo_div4_clk_src.hw
3799                         },
3800                         .num_parents = 1,
3801                         .flags = CLK_SET_RATE_PARENT,
3802                         .ops = &clk_branch2_ops,
3803                 },
3804         },
3805 };
3806
3807 static struct clk_branch gcc_xo_div4_clk = {
3808         .halt_reg = 0x3401c,
3809         .clkr = {
3810                 .enable_reg = 0x3401c,
3811                 .enable_mask = BIT(0),
3812                 .hw.init = &(struct clk_init_data) {
3813                         .name = "gcc_xo_div4_clk",
3814                         .parent_hws = (const struct clk_hw *[]) {
3815                                 &gcc_xo_div4_clk_src.hw
3816                         },
3817                         .num_parents = 1,
3818                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3819                         .ops = &clk_branch2_ops,
3820                 },
3821         },
3822 };
3823
3824 static struct clk_hw *gcc_ipq9574_hws[] = {
3825         &gpll0_out_main_div2.hw,
3826         &gcc_xo_div4_clk_src.hw,
3827         &qdss_dap_sync_clk_src.hw,
3828         &qdss_tsctr_div2_clk_src.hw,
3829         &qdss_tsctr_div8_clk_src.hw,
3830         &qdss_tsctr_div16_clk_src.hw,
3831         &qdss_tsctr_div3_clk_src.hw,
3832         &gcc_eud_at_div_clk_src.hw,
3833 };
3834
3835 static struct clk_regmap *gcc_ipq9574_clks[] = {
3836         [GPLL0_MAIN] = &gpll0_main.clkr,
3837         [GPLL0] = &gpll0.clkr,
3838         [GPLL4_MAIN] = &gpll4_main.clkr,
3839         [GPLL4] = &gpll4.clkr,
3840         [GPLL2_MAIN] = &gpll2_main.clkr,
3841         [GPLL2] = &gpll2.clkr,
3842         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3843         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3844         [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
3845         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3846         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3847         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3848         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3849         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3850         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3851         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3852         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3853         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3854         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3855         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3856         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3857         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3858         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3859         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3860         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3861         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3862         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3863         [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
3864         [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
3865         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3866         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3867         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3868         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3869         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3870         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3871         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3872         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3873         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3874         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3875         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3876         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3877         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3878         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3879         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3880         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3881         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3882         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3883         [PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
3884         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3885         [PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
3886         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3887         [PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
3888         [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
3889         [PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
3890         [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
3891         [PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
3892         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
3893         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3894         [PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
3895         [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
3896         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
3897         [PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
3898         [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
3899         [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
3900         [PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
3901         [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
3902         [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
3903         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
3904         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
3905         [PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
3906         [PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
3907         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3908         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
3909         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
3910         [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
3911         [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
3912         [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
3913         [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
3914         [PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
3915         [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
3916         [PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
3917         [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
3918         [PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
3919         [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
3920         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
3921         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
3922         [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
3923         [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
3924         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
3925         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3926         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
3927         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3928         [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
3929         [GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
3930         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
3931         [USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
3932         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3933         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
3934         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3935         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3936         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3937         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3938         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3939         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3940         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3941         [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
3942         [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
3943         [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
3944         [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
3945         [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3946         [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3947         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3948         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3949         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3950         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
3951         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3952         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
3953         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
3954         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
3955         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
3956         [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
3957         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3958         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
3959         [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
3960         [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3961         [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
3962         [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
3963         [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
3964         [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
3965         [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
3966         [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
3967         [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
3968         [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
3969         [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
3970         [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
3971         [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
3972         [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
3973         [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3974         [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
3975         [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
3976         [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3977         [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3978         [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
3979         [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
3980         [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
3981         [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
3982         [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
3983         [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
3984         [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
3985         [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
3986         [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
3987         [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
3988         [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
3989         [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
3990         [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
3991         [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
3992         [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
3993         [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
3994         [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
3995         [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
3996         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3997         [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
3998         [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
3999         [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
4000         [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
4001         [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4002         [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
4003         [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
4004         [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
4005         [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
4006         [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
4007         [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
4008         [GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
4009         [GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
4010         [GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
4011         [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
4012         [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
4013         [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4014         [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4015         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4016         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4017         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4018         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4019         [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
4020         [GCC_XO_CLK] = &gcc_xo_clk.clkr,
4021         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4022         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4023         [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
4024         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4025         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4026         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4027         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4028         [GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
4029         [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
4030         [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
4031         [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
4032         [GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
4033         [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
4034         [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
4035         [GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
4036         [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
4037         [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
4038         [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
4039 };
4040
4041 static const struct qcom_reset_map gcc_ipq9574_resets[] = {
4042         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4043         [GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
4044         [GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
4045         [GCC_ANOC_BCR] = { 0x2e074, 0 },
4046         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
4047         [GCC_APSS_TCU_BCR] = { 0x12014, 0 },
4048         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4049         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4050         [GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
4051         [GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
4052         [GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
4053         [GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
4054         [GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
4055         [GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
4056         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4057         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4058         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4059         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4060         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4061         [GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
4062         [GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
4063         [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
4064         [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
4065         [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
4066         [GCC_DCC_BCR] = { 0x35000, 0 },
4067         [GCC_DDRSS_BCR] = { 0x11000, 0 },
4068         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4069         [GCC_LPASS_BCR] = { 0x27000, 0 },
4070         [GCC_MDIO_BCR] = { 0x1703c, 0 },
4071         [GCC_MPM_BCR] = { 0x37000, 0 },
4072         [GCC_MSG_RAM_BCR] = { 0x26000, 0 },
4073         [GCC_NSS_BCR] = { 0x17000, 0 },
4074         [GCC_NSS_TBU_BCR] = { 0x12044, 0 },
4075         [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
4076         [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
4077         [GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },
4078         [GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },
4079         [GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
4080         [GCC_NSSCC_ARES] = { 0x17038, 8 },
4081         [GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
4082         [GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
4083         [GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
4084         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
4085         [GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
4086         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
4087         [GCC_NSS_CFG_ARES] = { 0x17038, 1 },
4088         [GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
4089         [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
4090         [GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
4091         [GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
4092         [GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
4093         [GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
4094         [GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
4095         [GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
4096         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
4097         [GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
4098         [GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
4099         [GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
4100         [GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
4101         [GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
4102         [GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
4103         [GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
4104         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
4105         [GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
4106         [GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
4107         [GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
4108         [GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
4109         [GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
4110         [GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
4111         [GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
4112         [GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
4113         [GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
4114         [GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
4115         [GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
4116         [GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
4117         [GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
4118         [GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
4119         [GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
4120         [GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
4121         [GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
4122         [GCC_PCIE0_BCR] = { 0x28000, 0 },
4123         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
4124         [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
4125         [GCC_PCIE1_BCR] = { 0x29000, 0 },
4126         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
4127         [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
4128         [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
4129         [GCC_PCIE2_BCR] = { 0x2a000, 0 },
4130         [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
4131         [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
4132         [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
4133         [GCC_PCIE3_BCR] = { 0x2b000, 0 },
4134         [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
4135         [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
4136         [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
4137         [GCC_PCNOC_BCR] = { 0x31000, 0 },
4138         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
4139         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
4140         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
4141         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
4142         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
4143         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
4144         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
4145         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
4146         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
4147         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
4148         [GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
4149         [GCC_PRNG_BCR] = { 0x13020, 0 },
4150         [GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
4151         [GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
4152         [GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
4153         [GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
4154         [GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
4155         [GCC_QDSS_BCR] = { 0x2d000, 0 },
4156         [GCC_QPIC_BCR] = { 0x32000, 0 },
4157         [GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
4158         [GCC_QPIC_ARES] = { 0x3201c, 0 },
4159         [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
4160         [GCC_RBCPR_BCR] = { 0x39000, 0 },
4161         [GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
4162         [GCC_SDCC_BCR] = { 0x33000, 0 },
4163         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4164         [GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
4165         [GCC_SNOC_BCR] = { 0x2e000, 0 },
4166         [GCC_SPDM_BCR] = { 0x36000, 0 },
4167         [GCC_TCSR_BCR] = { 0x3d000, 0 },
4168         [GCC_TLMM_BCR] = { 0x3e000, 0 },
4169         [GCC_TME_BCR] = { 0x10000, 0 },
4170         [GCC_UNIPHY0_BCR] = { 0x17044, 0 },
4171         [GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
4172         [GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
4173         [GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
4174         [GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
4175         [GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
4176         [GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
4177         [GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
4178         [GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
4179         [GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
4180         [GCC_UNIPHY1_BCR] = { 0x17054, 0 },
4181         [GCC_UNIPHY2_BCR] = { 0x17064, 0 },
4182         [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
4183         [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
4184         [GCC_USB_BCR] = { 0x2c000, 0 },
4185         [GCC_USB_MISC_RESET] = { 0x2c064, 0 },
4186         [GCC_WCSSAON_RESET] = { 0x25074, 0 },
4187         [GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
4188         [GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
4189         [GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
4190         [GCC_WCSS_BCR] = { 0x18004, 0 },
4191         [GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
4192         [GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
4193         [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
4194         [GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
4195         [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
4196 };
4197
4198 static const struct of_device_id gcc_ipq9574_match_table[] = {
4199         { .compatible = "qcom,ipq9574-gcc" },
4200         { }
4201 };
4202 MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
4203
4204 static const struct regmap_config gcc_ipq9574_regmap_config = {
4205         .reg_bits       = 32,
4206         .reg_stride     = 4,
4207         .val_bits       = 32,
4208         .max_register   = 0x7fffc,
4209         .fast_io        = true,
4210 };
4211
4212 static const struct qcom_cc_desc gcc_ipq9574_desc = {
4213         .config = &gcc_ipq9574_regmap_config,
4214         .clks = gcc_ipq9574_clks,
4215         .num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
4216         .resets = gcc_ipq9574_resets,
4217         .num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
4218         .clk_hws = gcc_ipq9574_hws,
4219         .num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
4220 };
4221
4222 static int gcc_ipq9574_probe(struct platform_device *pdev)
4223 {
4224         return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
4225 }
4226
4227 static struct platform_driver gcc_ipq9574_driver = {
4228         .probe = gcc_ipq9574_probe,
4229         .driver = {
4230                 .name   = "qcom,gcc-ipq9574",
4231                 .of_match_table = gcc_ipq9574_match_table,
4232         },
4233 };
4234
4235 static int __init gcc_ipq9574_init(void)
4236 {
4237         return platform_driver_register(&gcc_ipq9574_driver);
4238 }
4239 core_initcall(gcc_ipq9574_init);
4240
4241 static void __exit gcc_ipq9574_exit(void)
4242 {
4243         platform_driver_unregister(&gcc_ipq9574_driver);
4244 }
4245 module_exit(gcc_ipq9574_exit);
4246
4247 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
4248 MODULE_LICENSE("GPL");