drivers/clk/qcom/gcc-apq8084.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
  18 #include <dt-bindings/reset/qcom,gcc-apq8084.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL1,
  32         P_GPLL4,
  33         P_PCIE_0_1_PIPE_CLK,
  34         P_SATA_ASIC0_CLK,
  35         P_SATA_RX_CLK,
  36         P_SLEEP_CLK,
  37 };
  38
  39 static struct clk_pll gpll0 = {
  40         .l_reg = 0x0004,
  41         .m_reg = 0x0008,
  42         .n_reg = 0x000c,
  43         .config_reg = 0x0014,
  44         .mode_reg = 0x0000,
  45         .status_reg = 0x001c,
  46         .status_bit = 17,
  47         .clkr.hw.init = &(struct clk_init_data){
  48                 .name = "gpll0",
  49                 .parent_data = &(const struct clk_parent_data){
  50                         .fw_name = "xo", .name = "xo_board",
  51                 },
  52                 .num_parents = 1,
  53                 .ops = &clk_pll_ops,
  54         },
  55 };
  56
  57 static struct clk_regmap gpll0_vote = {
  58         .enable_reg = 0x1480,
  59         .enable_mask = BIT(0),
  60         .hw.init = &(struct clk_init_data){
  61                 .name = "gpll0_vote",
  62                 .parent_hws = (const struct clk_hw*[]){
  63                         &gpll0.clkr.hw,
  64                 },
  65                 .num_parents = 1,
  66                 .ops = &clk_pll_vote_ops,
  67         },
  68 };
  69
  70 static struct clk_pll gpll1 = {
  71         .l_reg = 0x0044,
  72         .m_reg = 0x0048,
  73         .n_reg = 0x004c,
  74         .config_reg = 0x0054,
  75         .mode_reg = 0x0040,
  76         .status_reg = 0x005c,
  77         .status_bit = 17,
  78         .clkr.hw.init = &(struct clk_init_data){
  79                 .name = "gpll1",
  80                 .parent_data = &(const struct clk_parent_data){
  81                         .fw_name = "xo", .name = "xo_board",
  82                 },
  83                 .num_parents = 1,
  84                 .ops = &clk_pll_ops,
  85         },
  86 };
  87
  88 static struct clk_regmap gpll1_vote = {
  89         .enable_reg = 0x1480,
  90         .enable_mask = BIT(1),
  91         .hw.init = &(struct clk_init_data){
  92                 .name = "gpll1_vote",
  93                 .parent_hws = (const struct clk_hw*[]){
  94                         &gpll1.clkr.hw,
  95                 },
  96                 .num_parents = 1,
  97                 .ops = &clk_pll_vote_ops,
  98         },
  99 };
 100
 101 static struct clk_pll gpll4 = {
 102         .l_reg = 0x1dc4,
 103         .m_reg = 0x1dc8,
 104         .n_reg = 0x1dcc,
 105         .config_reg = 0x1dd4,
 106         .mode_reg = 0x1dc0,
 107         .status_reg = 0x1ddc,
 108         .status_bit = 17,
 109         .clkr.hw.init = &(struct clk_init_data){
 110                 .name = "gpll4",
 111                 .parent_data = &(const struct clk_parent_data){
 112                         .fw_name = "xo", .name = "xo_board",
 113                 },
 114                 .num_parents = 1,
 115                 .ops = &clk_pll_ops,
 116         },
 117 };
 118
 119 static struct clk_regmap gpll4_vote = {
 120         .enable_reg = 0x1480,
 121         .enable_mask = BIT(4),
 122         .hw.init = &(struct clk_init_data){
 123                 .name = "gpll4_vote",
 124                 .parent_hws = (const struct clk_hw*[]){
 125                         &gpll4.clkr.hw,
 126                 },
 127                 .num_parents = 1,
 128                 .ops = &clk_pll_vote_ops,
 129         },
 130 };
 131
 132 static const struct parent_map gcc_xo_gpll0_map[] = {
 133         { P_XO, 0 },
 134         { P_GPLL0, 1 }
 135 };
 136
 137 static const struct clk_parent_data gcc_xo_gpll0[] = {
 138         { .fw_name = "xo", .name = "xo_board" },
 139         { .hw = &gpll0_vote.hw },
 140 };
 141
 142 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 143         { P_XO, 0 },
 144         { P_GPLL0, 1 },
 145         { P_GPLL4, 5 }
 146 };
 147
 148 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 149         { .fw_name = "xo", .name = "xo_board" },
 150         { .hw = &gpll0_vote.hw },
 151         { .hw = &gpll4_vote.hw },
 152 };
 153
 154 static const struct parent_map gcc_xo_sata_asic0_map[] = {
 155         { P_XO, 0 },
 156         { P_SATA_ASIC0_CLK, 2 }
 157 };
 158
 159 static const struct clk_parent_data gcc_xo_sata_asic0[] = {
 160         { .fw_name = "xo", .name = "xo_board" },
 161         { .fw_name = "sata_asic0_clk", .name = "sata_asic0_clk" },
 162 };
 163
 164 static const struct parent_map gcc_xo_sata_rx_map[] = {
 165         { P_XO, 0 },
 166         { P_SATA_RX_CLK, 2}
 167 };
 168
 169 static const struct clk_parent_data gcc_xo_sata_rx[] = {
 170         { .fw_name = "xo", .name = "xo_board" },
 171         { .fw_name = "sata_rx_clk", .name = "sata_rx_clk" },
 172 };
 173
 174 static const struct parent_map gcc_xo_pcie_map[] = {
 175         { P_XO, 0 },
 176         { P_PCIE_0_1_PIPE_CLK, 2 }
 177 };
 178
 179 static const struct clk_parent_data gcc_xo_pcie[] = {
 180         { .fw_name = "xo", .name = "xo_board" },
 181         { .fw_name = "pcie_pipe", .name = "pcie_pipe" },
 182 };
 183
 184 static const struct parent_map gcc_xo_pcie_sleep_map[] = {
 185         { P_XO, 0 },
 186         { P_SLEEP_CLK, 6 }
 187 };
 188
 189 static const struct clk_parent_data gcc_xo_pcie_sleep[] = {
 190         { .fw_name = "xo", .name = "xo_board" },
 191         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 192 };
 193
 194 static struct clk_rcg2 config_noc_clk_src = {
 195         .cmd_rcgr = 0x0150,
 196         .hid_width = 5,
 197         .parent_map = gcc_xo_gpll0_map,
 198         .clkr.hw.init = &(struct clk_init_data){
 199                 .name = "config_noc_clk_src",
 200                 .parent_data = gcc_xo_gpll0,
 201                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 202                 .ops = &clk_rcg2_ops,
 203         },
 204 };
 205
 206 static struct clk_rcg2 periph_noc_clk_src = {
 207         .cmd_rcgr = 0x0190,
 208         .hid_width = 5,
 209         .parent_map = gcc_xo_gpll0_map,
 210         .clkr.hw.init = &(struct clk_init_data){
 211                 .name = "periph_noc_clk_src",
 212                 .parent_data = gcc_xo_gpll0,
 213                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 214                 .ops = &clk_rcg2_ops,
 215         },
 216 };
 217
 218 static struct clk_rcg2 system_noc_clk_src = {
 219         .cmd_rcgr = 0x0120,
 220         .hid_width = 5,
 221         .parent_map = gcc_xo_gpll0_map,
 222         .clkr.hw.init = &(struct clk_init_data){
 223                 .name = "system_noc_clk_src",
 224                 .parent_data = gcc_xo_gpll0,
 225                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 226                 .ops = &clk_rcg2_ops,
 227         },
 228 };
 229
 230 static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
 231         F(100000000, P_GPLL0, 6, 0, 0),
 232         F(200000000, P_GPLL0, 3, 0, 0),
 233         F(240000000, P_GPLL0, 2.5, 0, 0),
 234         { }
 235 };
 236
 237 static struct clk_rcg2 ufs_axi_clk_src = {
 238         .cmd_rcgr = 0x1d64,
 239         .mnd_width = 8,
 240         .hid_width = 5,
 241         .parent_map = gcc_xo_gpll0_map,
 242         .freq_tbl = ftbl_gcc_ufs_axi_clk,
 243         .clkr.hw.init = &(struct clk_init_data){
 244                 .name = "ufs_axi_clk_src",
 245                 .parent_data = gcc_xo_gpll0,
 246                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 247                 .ops = &clk_rcg2_ops,
 248         },
 249 };
 250
 251 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
 252         F(125000000, P_GPLL0, 1, 5, 24),
 253         { }
 254 };
 255
 256 static struct clk_rcg2 usb30_master_clk_src = {
 257         .cmd_rcgr = 0x03d4,
 258         .mnd_width = 8,
 259         .hid_width = 5,
 260         .parent_map = gcc_xo_gpll0_map,
 261         .freq_tbl = ftbl_gcc_usb30_master_clk,
 262         .clkr.hw.init = &(struct clk_init_data){
 263                 .name = "usb30_master_clk_src",
 264                 .parent_data = gcc_xo_gpll0,
 265                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 266                 .ops = &clk_rcg2_ops,
 267         },
 268 };
 269
 270 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
 271         F(125000000, P_GPLL0, 1, 5, 24),
 272         { }
 273 };
 274
 275 static struct clk_rcg2 usb30_sec_master_clk_src = {
 276         .cmd_rcgr = 0x1bd4,
 277         .mnd_width = 8,
 278         .hid_width = 5,
 279         .parent_map = gcc_xo_gpll0_map,
 280         .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
 281         .clkr.hw.init = &(struct clk_init_data){
 282                 .name = "usb30_sec_master_clk_src",
 283                 .parent_data = gcc_xo_gpll0,
 284                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 285                 .ops = &clk_rcg2_ops,
 286         },
 287 };
 288
 289 static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
 290         F(125000000, P_GPLL0, 1, 5, 24),
 291         { }
 292 };
 293
 294 static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
 295         .cmd_rcgr = 0x1be8,
 296         .hid_width = 5,
 297         .parent_map = gcc_xo_gpll0_map,
 298         .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
 299         .clkr.hw.init = &(struct clk_init_data){
 300                 .name = "usb30_sec_mock_utmi_clk_src",
 301                 .parent_data = gcc_xo_gpll0,
 302                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 303                 .ops = &clk_rcg2_ops,
 304         },
 305 };
 306
 307 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
 308         .halt_reg = 0x1bd0,
 309         .clkr = {
 310                 .enable_reg = 0x1bd0,
 311                 .enable_mask = BIT(0),
 312                 .hw.init = &(struct clk_init_data){
 313                         .name = "gcc_usb30_sec_mock_utmi_clk",
 314                         .parent_hws = (const struct clk_hw*[]){
 315                                 &usb30_sec_mock_utmi_clk_src.clkr.hw,
 316                         },
 317                         .num_parents = 1,
 318                         .flags = CLK_SET_RATE_PARENT,
 319                         .ops = &clk_branch2_ops,
 320                 },
 321         },
 322 };
 323
 324 static struct clk_branch gcc_usb30_sec_sleep_clk = {
 325         .halt_reg = 0x1bcc,
 326         .clkr = {
 327                 .enable_reg = 0x1bcc,
 328                 .enable_mask = BIT(0),
 329                 .hw.init = &(struct clk_init_data){
 330                         .name = "gcc_usb30_sec_sleep_clk",
 331                         .parent_data = &(const struct clk_parent_data){
 332                                 .fw_name = "sleep_clk", .name = "sleep_clk",
 333                         },
 334                         .num_parents = 1,
 335                         .flags = CLK_SET_RATE_PARENT,
 336                         .ops = &clk_branch2_ops,
 337                 },
 338         },
 339 };
 340
 341 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
 342         F(19200000, P_XO, 1, 0, 0),
 343         F(50000000, P_GPLL0, 12, 0, 0),
 344         { }
 345 };
 346
 347 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 348         .cmd_rcgr = 0x0660,
 349         .hid_width = 5,
 350         .parent_map = gcc_xo_gpll0_map,
 351         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 352         .clkr.hw.init = &(struct clk_init_data){
 353                 .name = "blsp1_qup1_i2c_apps_clk_src",
 354                 .parent_data = gcc_xo_gpll0,
 355                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 356                 .ops = &clk_rcg2_ops,
 357         },
 358 };
 359
 360 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
 361         F(960000, P_XO, 10, 1, 2),
 362         F(4800000, P_XO, 4, 0, 0),
 363         F(9600000, P_XO, 2, 0, 0),
 364         F(15000000, P_GPLL0, 10, 1, 4),
 365         F(19200000, P_XO, 1, 0, 0),
 366         F(25000000, P_GPLL0, 12, 1, 2),
 367         F(50000000, P_GPLL0, 12, 0, 0),
 368         { }
 369 };
 370
 371 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 372         .cmd_rcgr = 0x064c,
 373         .mnd_width = 8,
 374         .hid_width = 5,
 375         .parent_map = gcc_xo_gpll0_map,
 376         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 377         .clkr.hw.init = &(struct clk_init_data){
 378                 .name = "blsp1_qup1_spi_apps_clk_src",
 379                 .parent_data = gcc_xo_gpll0,
 380                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 381                 .ops = &clk_rcg2_ops,
 382         },
 383 };
 384
 385 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 386         .cmd_rcgr = 0x06e0,
 387         .hid_width = 5,
 388         .parent_map = gcc_xo_gpll0_map,
 389         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 390         .clkr.hw.init = &(struct clk_init_data){
 391                 .name = "blsp1_qup2_i2c_apps_clk_src",
 392                 .parent_data = gcc_xo_gpll0,
 393                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 394                 .ops = &clk_rcg2_ops,
 395         },
 396 };
 397
 398 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 399         .cmd_rcgr = 0x06cc,
 400         .mnd_width = 8,
 401         .hid_width = 5,
 402         .parent_map = gcc_xo_gpll0_map,
 403         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 404         .clkr.hw.init = &(struct clk_init_data){
 405                 .name = "blsp1_qup2_spi_apps_clk_src",
 406                 .parent_data = gcc_xo_gpll0,
 407                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 408                 .ops = &clk_rcg2_ops,
 409         },
 410 };
 411
 412 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 413         .cmd_rcgr = 0x0760,
 414         .hid_width = 5,
 415         .parent_map = gcc_xo_gpll0_map,
 416         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 417         .clkr.hw.init = &(struct clk_init_data){
 418                 .name = "blsp1_qup3_i2c_apps_clk_src",
 419                 .parent_data = gcc_xo_gpll0,
 420                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 421                 .ops = &clk_rcg2_ops,
 422         },
 423 };
 424
 425 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 426         .cmd_rcgr = 0x074c,
 427         .mnd_width = 8,
 428         .hid_width = 5,
 429         .parent_map = gcc_xo_gpll0_map,
 430         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 431         .clkr.hw.init = &(struct clk_init_data){
 432                 .name = "blsp1_qup3_spi_apps_clk_src",
 433                 .parent_data = gcc_xo_gpll0,
 434                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 435                 .ops = &clk_rcg2_ops,
 436         },
 437 };
 438
 439 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 440         .cmd_rcgr = 0x07e0,
 441         .hid_width = 5,
 442         .parent_map = gcc_xo_gpll0_map,
 443         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 444         .clkr.hw.init = &(struct clk_init_data){
 445                 .name = "blsp1_qup4_i2c_apps_clk_src",
 446                 .parent_data = gcc_xo_gpll0,
 447                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 448                 .ops = &clk_rcg2_ops,
 449         },
 450 };
 451
 452 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 453         .cmd_rcgr = 0x07cc,
 454         .mnd_width = 8,
 455         .hid_width = 5,
 456         .parent_map = gcc_xo_gpll0_map,
 457         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 458         .clkr.hw.init = &(struct clk_init_data){
 459                 .name = "blsp1_qup4_spi_apps_clk_src",
 460                 .parent_data = gcc_xo_gpll0,
 461                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 462                 .ops = &clk_rcg2_ops,
 463         },
 464 };
 465
 466 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 467         .cmd_rcgr = 0x0860,
 468         .hid_width = 5,
 469         .parent_map = gcc_xo_gpll0_map,
 470         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 471         .clkr.hw.init = &(struct clk_init_data){
 472                 .name = "blsp1_qup5_i2c_apps_clk_src",
 473                 .parent_data = gcc_xo_gpll0,
 474                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 475                 .ops = &clk_rcg2_ops,
 476         },
 477 };
 478
 479 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 480         .cmd_rcgr = 0x084c,
 481         .mnd_width = 8,
 482         .hid_width = 5,
 483         .parent_map = gcc_xo_gpll0_map,
 484         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 485         .clkr.hw.init = &(struct clk_init_data){
 486                 .name = "blsp1_qup5_spi_apps_clk_src",
 487                 .parent_data = gcc_xo_gpll0,
 488                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 489                 .ops = &clk_rcg2_ops,
 490         },
 491 };
 492
 493 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 494         .cmd_rcgr = 0x08e0,
 495         .hid_width = 5,
 496         .parent_map = gcc_xo_gpll0_map,
 497         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 498         .clkr.hw.init = &(struct clk_init_data){
 499                 .name = "blsp1_qup6_i2c_apps_clk_src",
 500                 .parent_data = gcc_xo_gpll0,
 501                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 502                 .ops = &clk_rcg2_ops,
 503         },
 504 };
 505
 506 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 507         .cmd_rcgr = 0x08cc,
 508         .mnd_width = 8,
 509         .hid_width = 5,
 510         .parent_map = gcc_xo_gpll0_map,
 511         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 512         .clkr.hw.init = &(struct clk_init_data){
 513                 .name = "blsp1_qup6_spi_apps_clk_src",
 514                 .parent_data = gcc_xo_gpll0,
 515                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 516                 .ops = &clk_rcg2_ops,
 517         },
 518 };
 519
 520 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
 521         F(3686400, P_GPLL0, 1, 96, 15625),
 522         F(7372800, P_GPLL0, 1, 192, 15625),
 523         F(14745600, P_GPLL0, 1, 384, 15625),
 524         F(16000000, P_GPLL0, 5, 2, 15),
 525         F(19200000, P_XO, 1, 0, 0),
 526         F(24000000, P_GPLL0, 5, 1, 5),
 527         F(32000000, P_GPLL0, 1, 4, 75),
 528         F(40000000, P_GPLL0, 15, 0, 0),
 529         F(46400000, P_GPLL0, 1, 29, 375),
 530         F(48000000, P_GPLL0, 12.5, 0, 0),
 531         F(51200000, P_GPLL0, 1, 32, 375),
 532         F(56000000, P_GPLL0, 1, 7, 75),
 533         F(58982400, P_GPLL0, 1, 1536, 15625),
 534         F(60000000, P_GPLL0, 10, 0, 0),
 535         F(63160000, P_GPLL0, 9.5, 0, 0),
 536         { }
 537 };
 538
 539 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 540         .cmd_rcgr = 0x068c,
 541         .mnd_width = 16,
 542         .hid_width = 5,
 543         .parent_map = gcc_xo_gpll0_map,
 544         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 545         .clkr.hw.init = &(struct clk_init_data){
 546                 .name = "blsp1_uart1_apps_clk_src",
 547                 .parent_data = gcc_xo_gpll0,
 548                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 549                 .ops = &clk_rcg2_ops,
 550         },
 551 };
 552
 553 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 554         .cmd_rcgr = 0x070c,
 555         .mnd_width = 16,
 556         .hid_width = 5,
 557         .parent_map = gcc_xo_gpll0_map,
 558         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 559         .clkr.hw.init = &(struct clk_init_data){
 560                 .name = "blsp1_uart2_apps_clk_src",
 561                 .parent_data = gcc_xo_gpll0,
 562                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 563                 .ops = &clk_rcg2_ops,
 564         },
 565 };
 566
 567 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 568         .cmd_rcgr = 0x078c,
 569         .mnd_width = 16,
 570         .hid_width = 5,
 571         .parent_map = gcc_xo_gpll0_map,
 572         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 573         .clkr.hw.init = &(struct clk_init_data){
 574                 .name = "blsp1_uart3_apps_clk_src",
 575                 .parent_data = gcc_xo_gpll0,
 576                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 577                 .ops = &clk_rcg2_ops,
 578         },
 579 };
 580
 581 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 582         .cmd_rcgr = 0x080c,
 583         .mnd_width = 16,
 584         .hid_width = 5,
 585         .parent_map = gcc_xo_gpll0_map,
 586         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 587         .clkr.hw.init = &(struct clk_init_data){
 588                 .name = "blsp1_uart4_apps_clk_src",
 589                 .parent_data = gcc_xo_gpll0,
 590                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 591                 .ops = &clk_rcg2_ops,
 592         },
 593 };
 594
 595 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 596         .cmd_rcgr = 0x088c,
 597         .mnd_width = 16,
 598         .hid_width = 5,
 599         .parent_map = gcc_xo_gpll0_map,
 600         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 601         .clkr.hw.init = &(struct clk_init_data){
 602                 .name = "blsp1_uart5_apps_clk_src",
 603                 .parent_data = gcc_xo_gpll0,
 604                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 605                 .ops = &clk_rcg2_ops,
 606         },
 607 };
 608
 609 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 610         .cmd_rcgr = 0x090c,
 611         .mnd_width = 16,
 612         .hid_width = 5,
 613         .parent_map = gcc_xo_gpll0_map,
 614         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 615         .clkr.hw.init = &(struct clk_init_data){
 616                 .name = "blsp1_uart6_apps_clk_src",
 617                 .parent_data = gcc_xo_gpll0,
 618                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 619                 .ops = &clk_rcg2_ops,
 620         },
 621 };
 622
 623 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 624         .cmd_rcgr = 0x09a0,
 625         .hid_width = 5,
 626         .parent_map = gcc_xo_gpll0_map,
 627         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 628         .clkr.hw.init = &(struct clk_init_data){
 629                 .name = "blsp2_qup1_i2c_apps_clk_src",
 630                 .parent_data = gcc_xo_gpll0,
 631                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 632                 .ops = &clk_rcg2_ops,
 633         },
 634 };
 635
 636 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 637         .cmd_rcgr = 0x098c,
 638         .mnd_width = 8,
 639         .hid_width = 5,
 640         .parent_map = gcc_xo_gpll0_map,
 641         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 642         .clkr.hw.init = &(struct clk_init_data){
 643                 .name = "blsp2_qup1_spi_apps_clk_src",
 644                 .parent_data = gcc_xo_gpll0,
 645                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 646                 .ops = &clk_rcg2_ops,
 647         },
 648 };
 649
 650 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 651         .cmd_rcgr = 0x0a20,
 652         .hid_width = 5,
 653         .parent_map = gcc_xo_gpll0_map,
 654         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 655         .clkr.hw.init = &(struct clk_init_data){
 656                 .name = "blsp2_qup2_i2c_apps_clk_src",
 657                 .parent_data = gcc_xo_gpll0,
 658                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 659                 .ops = &clk_rcg2_ops,
 660         },
 661 };
 662
 663 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 664         .cmd_rcgr = 0x0a0c,
 665         .mnd_width = 8,
 666         .hid_width = 5,
 667         .parent_map = gcc_xo_gpll0_map,
 668         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 669         .clkr.hw.init = &(struct clk_init_data){
 670                 .name = "blsp2_qup2_spi_apps_clk_src",
 671                 .parent_data = gcc_xo_gpll0,
 672                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 673                 .ops = &clk_rcg2_ops,
 674         },
 675 };
 676
 677 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 678         .cmd_rcgr = 0x0aa0,
 679         .hid_width = 5,
 680         .parent_map = gcc_xo_gpll0_map,
 681         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 682         .clkr.hw.init = &(struct clk_init_data){
 683                 .name = "blsp2_qup3_i2c_apps_clk_src",
 684                 .parent_data = gcc_xo_gpll0,
 685                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 686                 .ops = &clk_rcg2_ops,
 687         },
 688 };
 689
 690 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 691         .cmd_rcgr = 0x0a8c,
 692         .mnd_width = 8,
 693         .hid_width = 5,
 694         .parent_map = gcc_xo_gpll0_map,
 695         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 696         .clkr.hw.init = &(struct clk_init_data){
 697                 .name = "blsp2_qup3_spi_apps_clk_src",
 698                 .parent_data = gcc_xo_gpll0,
 699                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 700                 .ops = &clk_rcg2_ops,
 701         },
 702 };
 703
 704 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 705         .cmd_rcgr = 0x0b20,
 706         .hid_width = 5,
 707         .parent_map = gcc_xo_gpll0_map,
 708         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 709         .clkr.hw.init = &(struct clk_init_data){
 710                 .name = "blsp2_qup4_i2c_apps_clk_src",
 711                 .parent_data = gcc_xo_gpll0,
 712                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 713                 .ops = &clk_rcg2_ops,
 714         },
 715 };
 716
 717 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 718         .cmd_rcgr = 0x0b0c,
 719         .mnd_width = 8,
 720         .hid_width = 5,
 721         .parent_map = gcc_xo_gpll0_map,
 722         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 723         .clkr.hw.init = &(struct clk_init_data){
 724                 .name = "blsp2_qup4_spi_apps_clk_src",
 725                 .parent_data = gcc_xo_gpll0,
 726                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 727                 .ops = &clk_rcg2_ops,
 728         },
 729 };
 730
 731 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 732         .cmd_rcgr = 0x0ba0,
 733         .hid_width = 5,
 734         .parent_map = gcc_xo_gpll0_map,
 735         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 736         .clkr.hw.init = &(struct clk_init_data){
 737                 .name = "blsp2_qup5_i2c_apps_clk_src",
 738                 .parent_data = gcc_xo_gpll0,
 739                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 740                 .ops = &clk_rcg2_ops,
 741         },
 742 };
 743
 744 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 745         .cmd_rcgr = 0x0b8c,
 746         .mnd_width = 8,
 747         .hid_width = 5,
 748         .parent_map = gcc_xo_gpll0_map,
 749         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 750         .clkr.hw.init = &(struct clk_init_data){
 751                 .name = "blsp2_qup5_spi_apps_clk_src",
 752                 .parent_data = gcc_xo_gpll0,
 753                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 754                 .ops = &clk_rcg2_ops,
 755         },
 756 };
 757
 758 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 759         .cmd_rcgr = 0x0c20,
 760         .hid_width = 5,
 761         .parent_map = gcc_xo_gpll0_map,
 762         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 763         .clkr.hw.init = &(struct clk_init_data){
 764                 .name = "blsp2_qup6_i2c_apps_clk_src",
 765                 .parent_data = gcc_xo_gpll0,
 766                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 767                 .ops = &clk_rcg2_ops,
 768         },
 769 };
 770
 771 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 772         .cmd_rcgr = 0x0c0c,
 773         .mnd_width = 8,
 774         .hid_width = 5,
 775         .parent_map = gcc_xo_gpll0_map,
 776         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 777         .clkr.hw.init = &(struct clk_init_data){
 778                 .name = "blsp2_qup6_spi_apps_clk_src",
 779                 .parent_data = gcc_xo_gpll0,
 780                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 781                 .ops = &clk_rcg2_ops,
 782         },
 783 };
 784
 785 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 786         .cmd_rcgr = 0x09cc,
 787         .mnd_width = 16,
 788         .hid_width = 5,
 789         .parent_map = gcc_xo_gpll0_map,
 790         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 791         .clkr.hw.init = &(struct clk_init_data){
 792                 .name = "blsp2_uart1_apps_clk_src",
 793                 .parent_data = gcc_xo_gpll0,
 794                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 795                 .ops = &clk_rcg2_ops,
 796         },
 797 };
 798
 799 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 800         .cmd_rcgr = 0x0a4c,
 801         .mnd_width = 16,
 802         .hid_width = 5,
 803         .parent_map = gcc_xo_gpll0_map,
 804         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 805         .clkr.hw.init = &(struct clk_init_data){
 806                 .name = "blsp2_uart2_apps_clk_src",
 807                 .parent_data = gcc_xo_gpll0,
 808                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 809                 .ops = &clk_rcg2_ops,
 810         },
 811 };
 812
 813 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 814         .cmd_rcgr = 0x0acc,
 815         .mnd_width = 16,
 816         .hid_width = 5,
 817         .parent_map = gcc_xo_gpll0_map,
 818         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 819         .clkr.hw.init = &(struct clk_init_data){
 820                 .name = "blsp2_uart3_apps_clk_src",
 821                 .parent_data = gcc_xo_gpll0,
 822                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 823                 .ops = &clk_rcg2_ops,
 824         },
 825 };
 826
 827 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 828         .cmd_rcgr = 0x0b4c,
 829         .mnd_width = 16,
 830         .hid_width = 5,
 831         .parent_map = gcc_xo_gpll0_map,
 832         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 833         .clkr.hw.init = &(struct clk_init_data){
 834                 .name = "blsp2_uart4_apps_clk_src",
 835                 .parent_data = gcc_xo_gpll0,
 836                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 837                 .ops = &clk_rcg2_ops,
 838         },
 839 };
 840
 841 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 842         .cmd_rcgr = 0x0bcc,
 843         .mnd_width = 16,
 844         .hid_width = 5,
 845         .parent_map = gcc_xo_gpll0_map,
 846         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 847         .clkr.hw.init = &(struct clk_init_data){
 848                 .name = "blsp2_uart5_apps_clk_src",
 849                 .parent_data = gcc_xo_gpll0,
 850                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 851                 .ops = &clk_rcg2_ops,
 852         },
 853 };
 854
 855 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 856         .cmd_rcgr = 0x0c4c,
 857         .mnd_width = 16,
 858         .hid_width = 5,
 859         .parent_map = gcc_xo_gpll0_map,
 860         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 861         .clkr.hw.init = &(struct clk_init_data){
 862                 .name = "blsp2_uart6_apps_clk_src",
 863                 .parent_data = gcc_xo_gpll0,
 864                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 865                 .ops = &clk_rcg2_ops,
 866         },
 867 };
 868
 869 static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
 870         F(50000000, P_GPLL0, 12, 0, 0),
 871         F(85710000, P_GPLL0, 7, 0, 0),
 872         F(100000000, P_GPLL0, 6, 0, 0),
 873         F(171430000, P_GPLL0, 3.5, 0, 0),
 874         { }
 875 };
 876
 877 static struct clk_rcg2 ce1_clk_src = {
 878         .cmd_rcgr = 0x1050,
 879         .hid_width = 5,
 880         .parent_map = gcc_xo_gpll0_map,
 881         .freq_tbl = ftbl_gcc_ce1_clk,
 882         .clkr.hw.init = &(struct clk_init_data){
 883                 .name = "ce1_clk_src",
 884                 .parent_data = gcc_xo_gpll0,
 885                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 886                 .ops = &clk_rcg2_ops,
 887         },
 888 };
 889
 890 static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
 891         F(50000000, P_GPLL0, 12, 0, 0),
 892         F(85710000, P_GPLL0, 7, 0, 0),
 893         F(100000000, P_GPLL0, 6, 0, 0),
 894         F(171430000, P_GPLL0, 3.5, 0, 0),
 895         { }
 896 };
 897
 898 static struct clk_rcg2 ce2_clk_src = {
 899         .cmd_rcgr = 0x1090,
 900         .hid_width = 5,
 901         .parent_map = gcc_xo_gpll0_map,
 902         .freq_tbl = ftbl_gcc_ce2_clk,
 903         .clkr.hw.init = &(struct clk_init_data){
 904                 .name = "ce2_clk_src",
 905                 .parent_data = gcc_xo_gpll0,
 906                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 907                 .ops = &clk_rcg2_ops,
 908         },
 909 };
 910
 911 static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
 912         F(50000000, P_GPLL0, 12, 0, 0),
 913         F(85710000, P_GPLL0, 7, 0, 0),
 914         F(100000000, P_GPLL0, 6, 0, 0),
 915         F(171430000, P_GPLL0, 3.5, 0, 0),
 916         { }
 917 };
 918
 919 static struct clk_rcg2 ce3_clk_src = {
 920         .cmd_rcgr = 0x1d10,
 921         .hid_width = 5,
 922         .parent_map = gcc_xo_gpll0_map,
 923         .freq_tbl = ftbl_gcc_ce3_clk,
 924         .clkr.hw.init = &(struct clk_init_data){
 925                 .name = "ce3_clk_src",
 926                 .parent_data = gcc_xo_gpll0,
 927                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 928                 .ops = &clk_rcg2_ops,
 929         },
 930 };
 931
 932 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 933         F(19200000, P_XO, 1, 0, 0),
 934         F(100000000, P_GPLL0, 6, 0, 0),
 935         F(200000000, P_GPLL0, 3, 0, 0),
 936         { }
 937 };
 938
 939 static struct clk_rcg2 gp1_clk_src = {
 940         .cmd_rcgr = 0x1904,
 941         .mnd_width = 8,
 942         .hid_width = 5,
 943         .parent_map = gcc_xo_gpll0_map,
 944         .freq_tbl = ftbl_gcc_gp_clk,
 945         .clkr.hw.init = &(struct clk_init_data){
 946                 .name = "gp1_clk_src",
 947                 .parent_data = gcc_xo_gpll0,
 948                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 949                 .ops = &clk_rcg2_ops,
 950         },
 951 };
 952
 953 static struct clk_rcg2 gp2_clk_src = {
 954         .cmd_rcgr = 0x1944,
 955         .mnd_width = 8,
 956         .hid_width = 5,
 957         .parent_map = gcc_xo_gpll0_map,
 958         .freq_tbl = ftbl_gcc_gp_clk,
 959         .clkr.hw.init = &(struct clk_init_data){
 960                 .name = "gp2_clk_src",
 961                 .parent_data = gcc_xo_gpll0,
 962                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 963                 .ops = &clk_rcg2_ops,
 964         },
 965 };
 966
 967 static struct clk_rcg2 gp3_clk_src = {
 968         .cmd_rcgr = 0x1984,
 969         .mnd_width = 8,
 970         .hid_width = 5,
 971         .parent_map = gcc_xo_gpll0_map,
 972         .freq_tbl = ftbl_gcc_gp_clk,
 973         .clkr.hw.init = &(struct clk_init_data){
 974                 .name = "gp3_clk_src",
 975                 .parent_data = gcc_xo_gpll0,
 976                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 977                 .ops = &clk_rcg2_ops,
 978         },
 979 };
 980
 981 static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = {
 982         F(1010000, P_XO, 1, 1, 19),
 983         { }
 984 };
 985
 986 static struct clk_rcg2 pcie_0_aux_clk_src = {
 987         .cmd_rcgr = 0x1b2c,
 988         .mnd_width = 16,
 989         .hid_width = 5,
 990         .parent_map = gcc_xo_pcie_sleep_map,
 991         .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
 992         .clkr.hw.init = &(struct clk_init_data){
 993                 .name = "pcie_0_aux_clk_src",
 994                 .parent_data = gcc_xo_pcie_sleep,
 995                 .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
 996                 .ops = &clk_rcg2_ops,
 997         },
 998 };
 999
1000 static struct clk_rcg2 pcie_1_aux_clk_src = {
1001         .cmd_rcgr = 0x1bac,
1002         .mnd_width = 16,
1003         .hid_width = 5,
1004         .parent_map = gcc_xo_pcie_sleep_map,
1005         .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
1006         .clkr.hw.init = &(struct clk_init_data){
1007                 .name = "pcie_1_aux_clk_src",
1008                 .parent_data = gcc_xo_pcie_sleep,
1009                 .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
1010                 .ops = &clk_rcg2_ops,
1011         },
1012 };
1013
1014 static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
1015         F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
1016         F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
1017         { }
1018 };
1019
1020 static struct clk_rcg2 pcie_0_pipe_clk_src = {
1021         .cmd_rcgr = 0x1b18,
1022         .hid_width = 5,
1023         .parent_map = gcc_xo_pcie_map,
1024         .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1025         .clkr.hw.init = &(struct clk_init_data){
1026                 .name = "pcie_0_pipe_clk_src",
1027                 .parent_data = gcc_xo_pcie,
1028                 .num_parents = ARRAY_SIZE(gcc_xo_pcie),
1029                 .ops = &clk_rcg2_ops,
1030         },
1031 };
1032
1033 static struct clk_rcg2 pcie_1_pipe_clk_src = {
1034         .cmd_rcgr = 0x1b98,
1035         .hid_width = 5,
1036         .parent_map = gcc_xo_pcie_map,
1037         .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1038         .clkr.hw.init = &(struct clk_init_data){
1039                 .name = "pcie_1_pipe_clk_src",
1040                 .parent_data = gcc_xo_pcie,
1041                 .num_parents = ARRAY_SIZE(gcc_xo_pcie),
1042                 .ops = &clk_rcg2_ops,
1043         },
1044 };
1045
1046 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1047         F(60000000, P_GPLL0, 10, 0, 0),
1048         { }
1049 };
1050
1051 static struct clk_rcg2 pdm2_clk_src = {
1052         .cmd_rcgr = 0x0cd0,
1053         .hid_width = 5,
1054         .parent_map = gcc_xo_gpll0_map,
1055         .freq_tbl = ftbl_gcc_pdm2_clk,
1056         .clkr.hw.init = &(struct clk_init_data){
1057                 .name = "pdm2_clk_src",
1058                 .parent_data = gcc_xo_gpll0,
1059                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1060                 .ops = &clk_rcg2_ops,
1061         },
1062 };
1063
1064 static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = {
1065         F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1066         F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1067         F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1068         { }
1069 };
1070
1071 static struct clk_rcg2 sata_asic0_clk_src = {
1072         .cmd_rcgr = 0x1c94,
1073         .hid_width = 5,
1074         .parent_map = gcc_xo_sata_asic0_map,
1075         .freq_tbl = ftbl_gcc_sata_asic0_clk,
1076         .clkr.hw.init = &(struct clk_init_data){
1077                 .name = "sata_asic0_clk_src",
1078                 .parent_data = gcc_xo_sata_asic0,
1079                 .num_parents = ARRAY_SIZE(gcc_xo_sata_asic0),
1080                 .ops = &clk_rcg2_ops,
1081         },
1082 };
1083
1084 static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = {
1085         F(19200000, P_XO, 1, 0, 0),
1086         F(50000000, P_GPLL0, 12, 0, 0),
1087         F(100000000, P_GPLL0, 6, 0, 0),
1088         { }
1089 };
1090
1091 static struct clk_rcg2 sata_pmalive_clk_src = {
1092         .cmd_rcgr = 0x1c80,
1093         .hid_width = 5,
1094         .parent_map = gcc_xo_gpll0_map,
1095         .freq_tbl = ftbl_gcc_sata_pmalive_clk,
1096         .clkr.hw.init = &(struct clk_init_data){
1097                 .name = "sata_pmalive_clk_src",
1098                 .parent_data = gcc_xo_gpll0,
1099                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1100                 .ops = &clk_rcg2_ops,
1101         },
1102 };
1103
1104 static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = {
1105         F(75000000, P_SATA_RX_CLK, 1, 0, 0),
1106         F(150000000, P_SATA_RX_CLK, 1, 0, 0),
1107         F(300000000, P_SATA_RX_CLK, 1, 0, 0),
1108         { }
1109 };
1110
1111 static struct clk_rcg2 sata_rx_clk_src = {
1112         .cmd_rcgr = 0x1ca8,
1113         .hid_width = 5,
1114         .parent_map = gcc_xo_sata_rx_map,
1115         .freq_tbl = ftbl_gcc_sata_rx_clk,
1116         .clkr.hw.init = &(struct clk_init_data){
1117                 .name = "sata_rx_clk_src",
1118                 .parent_data = gcc_xo_sata_rx,
1119                 .num_parents = ARRAY_SIZE(gcc_xo_sata_rx),
1120                 .ops = &clk_rcg2_ops,
1121         },
1122 };
1123
1124 static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = {
1125         F(100000000, P_GPLL0, 6, 0, 0),
1126         { }
1127 };
1128
1129 static struct clk_rcg2 sata_rx_oob_clk_src = {
1130         .cmd_rcgr = 0x1c5c,
1131         .hid_width = 5,
1132         .parent_map = gcc_xo_gpll0_map,
1133         .freq_tbl = ftbl_gcc_sata_rx_oob_clk,
1134         .clkr.hw.init = &(struct clk_init_data){
1135                 .name = "sata_rx_oob_clk_src",
1136                 .parent_data = gcc_xo_gpll0,
1137                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1138                 .ops = &clk_rcg2_ops,
1139         },
1140 };
1141
1142 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
1143         F(144000, P_XO, 16, 3, 25),
1144         F(400000, P_XO, 12, 1, 4),
1145         F(20000000, P_GPLL0, 15, 1, 2),
1146         F(25000000, P_GPLL0, 12, 1, 2),
1147         F(50000000, P_GPLL0, 12, 0, 0),
1148         F(100000000, P_GPLL0, 6, 0, 0),
1149         F(192000000, P_GPLL4, 4, 0, 0),
1150         F(200000000, P_GPLL0, 3, 0, 0),
1151         F(384000000, P_GPLL4, 2, 0, 0),
1152         { }
1153 };
1154
1155 static struct clk_rcg2 sdcc1_apps_clk_src = {
1156         .cmd_rcgr = 0x04d0,
1157         .mnd_width = 8,
1158         .hid_width = 5,
1159         .parent_map = gcc_xo_gpll0_gpll4_map,
1160         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1161         .clkr.hw.init = &(struct clk_init_data){
1162                 .name = "sdcc1_apps_clk_src",
1163                 .parent_data = gcc_xo_gpll0_gpll4,
1164                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1165                 .ops = &clk_rcg2_floor_ops,
1166         },
1167 };
1168
1169 static struct clk_rcg2 sdcc2_apps_clk_src = {
1170         .cmd_rcgr = 0x0510,
1171         .mnd_width = 8,
1172         .hid_width = 5,
1173         .parent_map = gcc_xo_gpll0_map,
1174         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1175         .clkr.hw.init = &(struct clk_init_data){
1176                 .name = "sdcc2_apps_clk_src",
1177                 .parent_data = gcc_xo_gpll0,
1178                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1179                 .ops = &clk_rcg2_floor_ops,
1180         },
1181 };
1182
1183 static struct clk_rcg2 sdcc3_apps_clk_src = {
1184         .cmd_rcgr = 0x0550,
1185         .mnd_width = 8,
1186         .hid_width = 5,
1187         .parent_map = gcc_xo_gpll0_map,
1188         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1189         .clkr.hw.init = &(struct clk_init_data){
1190                 .name = "sdcc3_apps_clk_src",
1191                 .parent_data = gcc_xo_gpll0,
1192                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1193                 .ops = &clk_rcg2_floor_ops,
1194         },
1195 };
1196
1197 static struct clk_rcg2 sdcc4_apps_clk_src = {
1198         .cmd_rcgr = 0x0590,
1199         .mnd_width = 8,
1200         .hid_width = 5,
1201         .parent_map = gcc_xo_gpll0_map,
1202         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1203         .clkr.hw.init = &(struct clk_init_data){
1204                 .name = "sdcc4_apps_clk_src",
1205                 .parent_data = gcc_xo_gpll0,
1206                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1207                 .ops = &clk_rcg2_floor_ops,
1208         },
1209 };
1210
1211 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
1212         F(105000, P_XO, 2, 1, 91),
1213         { }
1214 };
1215
1216 static struct clk_rcg2 tsif_ref_clk_src = {
1217         .cmd_rcgr = 0x0d90,
1218         .mnd_width = 8,
1219         .hid_width = 5,
1220         .parent_map = gcc_xo_gpll0_map,
1221         .freq_tbl = ftbl_gcc_tsif_ref_clk,
1222         .clkr.hw.init = &(struct clk_init_data){
1223                 .name = "tsif_ref_clk_src",
1224                 .parent_data = gcc_xo_gpll0,
1225                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1226                 .ops = &clk_rcg2_ops,
1227         },
1228 };
1229
1230 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
1231         F(60000000, P_GPLL0, 10, 0, 0),
1232         { }
1233 };
1234
1235 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1236         .cmd_rcgr = 0x03e8,
1237         .hid_width = 5,
1238         .parent_map = gcc_xo_gpll0_map,
1239         .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
1240         .clkr.hw.init = &(struct clk_init_data){
1241                 .name = "usb30_mock_utmi_clk_src",
1242                 .parent_data = gcc_xo_gpll0,
1243                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1244                 .ops = &clk_rcg2_ops,
1245         },
1246 };
1247
1248 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1249         F(75000000, P_GPLL0, 8, 0, 0),
1250         { }
1251 };
1252
1253 static struct clk_rcg2 usb_hs_system_clk_src = {
1254         .cmd_rcgr = 0x0490,
1255         .hid_width = 5,
1256         .parent_map = gcc_xo_gpll0_map,
1257         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1258         .clkr.hw.init = &(struct clk_init_data){
1259                 .name = "usb_hs_system_clk_src",
1260                 .parent_data = gcc_xo_gpll0,
1261                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1262                 .ops = &clk_rcg2_ops,
1263         },
1264 };
1265
1266 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1267         F(480000000, P_GPLL1, 1, 0, 0),
1268         { }
1269 };
1270
1271 static const struct parent_map usb_hsic_clk_src_map[] = {
1272         { P_XO, 0 },
1273         { P_GPLL1, 4 }
1274 };
1275
1276 static struct clk_rcg2 usb_hsic_clk_src = {
1277         .cmd_rcgr = 0x0440,
1278         .hid_width = 5,
1279         .parent_map = usb_hsic_clk_src_map,
1280         .freq_tbl = ftbl_gcc_usb_hsic_clk,
1281         .clkr.hw.init = &(struct clk_init_data){
1282                 .name = "usb_hsic_clk_src",
1283                 .parent_data = (const struct clk_parent_data[]){
1284                         { .fw_name = "xo", .name = "xo_board" },
1285                         { .hw = &gpll1_vote.hw },
1286                 },
1287                 .num_parents = 2,
1288                 .ops = &clk_rcg2_ops,
1289         },
1290 };
1291
1292 static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
1293         F(60000000, P_GPLL1, 8, 0, 0),
1294         { }
1295 };
1296
1297 static struct clk_rcg2 usb_hsic_ahb_clk_src = {
1298         .cmd_rcgr = 0x046c,
1299         .mnd_width = 8,
1300         .hid_width = 5,
1301         .parent_map = usb_hsic_clk_src_map,
1302         .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
1303         .clkr.hw.init = &(struct clk_init_data){
1304                 .name = "usb_hsic_ahb_clk_src",
1305                 .parent_data = (const struct clk_parent_data[]){
1306                         { .fw_name = "xo", .name = "xo_board" },
1307                         { .hw = &gpll1_vote.hw },
1308                 },
1309                 .num_parents = 2,
1310                 .ops = &clk_rcg2_ops,
1311         },
1312 };
1313
1314 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1315         F(9600000, P_XO, 2, 0, 0),
1316         { }
1317 };
1318
1319 static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1320         .cmd_rcgr = 0x0458,
1321         .hid_width = 5,
1322         .parent_map = gcc_xo_gpll0_map,
1323         .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1324         .clkr.hw.init = &(struct clk_init_data){
1325                 .name = "usb_hsic_io_cal_clk_src",
1326                 .parent_data = gcc_xo_gpll0,
1327                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1328                 .ops = &clk_rcg2_ops,
1329         },
1330 };
1331
1332 static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
1333         F(60000000, P_GPLL0, 10, 0, 0),
1334         { }
1335 };
1336
1337 static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
1338         .cmd_rcgr = 0x1f00,
1339         .hid_width = 5,
1340         .parent_map = gcc_xo_gpll0_map,
1341         .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
1342         .clkr.hw.init = &(struct clk_init_data){
1343                 .name = "usb_hsic_mock_utmi_clk_src",
1344                 .parent_data = gcc_xo_gpll0,
1345                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1346                 .ops = &clk_rcg2_ops,
1347         },
1348 };
1349
1350 static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
1351         .halt_reg = 0x1f14,
1352         .clkr = {
1353                 .enable_reg = 0x1f14,
1354                 .enable_mask = BIT(0),
1355                 .hw.init = &(struct clk_init_data){
1356                         .name = "gcc_usb_hsic_mock_utmi_clk",
1357                         .parent_hws = (const struct clk_hw*[]){
1358                                 &usb_hsic_mock_utmi_clk_src.clkr.hw,
1359                         },
1360                         .num_parents = 1,
1361                         .flags = CLK_SET_RATE_PARENT,
1362                         .ops = &clk_branch2_ops,
1363                 },
1364         },
1365 };
1366
1367 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1368         F(75000000, P_GPLL0, 8, 0, 0),
1369         { }
1370 };
1371
1372 static struct clk_rcg2 usb_hsic_system_clk_src = {
1373         .cmd_rcgr = 0x041c,
1374         .hid_width = 5,
1375         .parent_map = gcc_xo_gpll0_map,
1376         .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1377         .clkr.hw.init = &(struct clk_init_data){
1378                 .name = "usb_hsic_system_clk_src",
1379                 .parent_data = gcc_xo_gpll0,
1380                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1381                 .ops = &clk_rcg2_ops,
1382         },
1383 };
1384
1385 static struct clk_regmap gcc_mmss_gpll0_clk_src = {
1386         .enable_reg = 0x1484,
1387         .enable_mask = BIT(26),
1388         .hw.init = &(struct clk_init_data){
1389                 .name = "mmss_gpll0_vote",
1390                 .parent_hws = (const struct clk_hw*[]){
1391                         &gpll0_vote.hw,
1392                 },
1393                 .num_parents = 1,
1394                 .ops = &clk_branch_simple_ops,
1395         },
1396 };
1397
1398 static struct clk_branch gcc_bam_dma_ahb_clk = {
1399         .halt_reg = 0x0d44,
1400         .halt_check = BRANCH_HALT_VOTED,
1401         .clkr = {
1402                 .enable_reg = 0x1484,
1403                 .enable_mask = BIT(12),
1404                 .hw.init = &(struct clk_init_data){
1405                         .name = "gcc_bam_dma_ahb_clk",
1406                         .parent_hws = (const struct clk_hw*[]){
1407                                 &periph_noc_clk_src.clkr.hw,
1408                         },
1409                         .num_parents = 1,
1410                         .ops = &clk_branch2_ops,
1411                 },
1412         },
1413 };
1414
1415 static struct clk_branch gcc_blsp1_ahb_clk = {
1416         .halt_reg = 0x05c4,
1417         .halt_check = BRANCH_HALT_VOTED,
1418         .clkr = {
1419                 .enable_reg = 0x1484,
1420                 .enable_mask = BIT(17),
1421                 .hw.init = &(struct clk_init_data){
1422                         .name = "gcc_blsp1_ahb_clk",
1423                         .parent_hws = (const struct clk_hw*[]){
1424                                 &periph_noc_clk_src.clkr.hw,
1425                         },
1426                         .num_parents = 1,
1427                         .ops = &clk_branch2_ops,
1428                 },
1429         },
1430 };
1431
1432 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1433         .halt_reg = 0x0648,
1434         .clkr = {
1435                 .enable_reg = 0x0648,
1436                 .enable_mask = BIT(0),
1437                 .hw.init = &(struct clk_init_data){
1438                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1439                         .parent_hws = (const struct clk_hw*[]){
1440                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1441                         },
1442                         .num_parents = 1,
1443                         .flags = CLK_SET_RATE_PARENT,
1444                         .ops = &clk_branch2_ops,
1445                 },
1446         },
1447 };
1448
1449 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1450         .halt_reg = 0x0644,
1451         .clkr = {
1452                 .enable_reg = 0x0644,
1453                 .enable_mask = BIT(0),
1454                 .hw.init = &(struct clk_init_data){
1455                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1456                         .parent_hws = (const struct clk_hw*[]){
1457                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1458                         },
1459                         .num_parents = 1,
1460                         .flags = CLK_SET_RATE_PARENT,
1461                         .ops = &clk_branch2_ops,
1462                 },
1463         },
1464 };
1465
1466 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1467         .halt_reg = 0x06c8,
1468         .clkr = {
1469                 .enable_reg = 0x06c8,
1470                 .enable_mask = BIT(0),
1471                 .hw.init = &(struct clk_init_data){
1472                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1473                         .parent_hws = (const struct clk_hw*[]){
1474                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1475                         },
1476                         .num_parents = 1,
1477                         .flags = CLK_SET_RATE_PARENT,
1478                         .ops = &clk_branch2_ops,
1479                 },
1480         },
1481 };
1482
1483 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1484         .halt_reg = 0x06c4,
1485         .clkr = {
1486                 .enable_reg = 0x06c4,
1487                 .enable_mask = BIT(0),
1488                 .hw.init = &(struct clk_init_data){
1489                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1490                         .parent_hws = (const struct clk_hw*[]){
1491                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1492                         },
1493                         .num_parents = 1,
1494                         .flags = CLK_SET_RATE_PARENT,
1495                         .ops = &clk_branch2_ops,
1496                 },
1497         },
1498 };
1499
1500 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1501         .halt_reg = 0x0748,
1502         .clkr = {
1503                 .enable_reg = 0x0748,
1504                 .enable_mask = BIT(0),
1505                 .hw.init = &(struct clk_init_data){
1506                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1507                         .parent_hws = (const struct clk_hw*[]){
1508                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1509                         },
1510                         .num_parents = 1,
1511                         .flags = CLK_SET_RATE_PARENT,
1512                         .ops = &clk_branch2_ops,
1513                 },
1514         },
1515 };
1516
1517 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1518         .halt_reg = 0x0744,
1519         .clkr = {
1520                 .enable_reg = 0x0744,
1521                 .enable_mask = BIT(0),
1522                 .hw.init = &(struct clk_init_data){
1523                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1524                         .parent_hws = (const struct clk_hw*[]){
1525                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1526                         },
1527                         .num_parents = 1,
1528                         .flags = CLK_SET_RATE_PARENT,
1529                         .ops = &clk_branch2_ops,
1530                 },
1531         },
1532 };
1533
1534 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1535         .halt_reg = 0x07c8,
1536         .clkr = {
1537                 .enable_reg = 0x07c8,
1538                 .enable_mask = BIT(0),
1539                 .hw.init = &(struct clk_init_data){
1540                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1541                         .parent_hws = (const struct clk_hw*[]){
1542                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1543                         },
1544                         .num_parents = 1,
1545                         .flags = CLK_SET_RATE_PARENT,
1546                         .ops = &clk_branch2_ops,
1547                 },
1548         },
1549 };
1550
1551 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1552         .halt_reg = 0x07c4,
1553         .clkr = {
1554                 .enable_reg = 0x07c4,
1555                 .enable_mask = BIT(0),
1556                 .hw.init = &(struct clk_init_data){
1557                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1558                         .parent_hws = (const struct clk_hw*[]){
1559                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
1560                         },
1561                         .num_parents = 1,
1562                         .flags = CLK_SET_RATE_PARENT,
1563                         .ops = &clk_branch2_ops,
1564                 },
1565         },
1566 };
1567
1568 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1569         .halt_reg = 0x0848,
1570         .clkr = {
1571                 .enable_reg = 0x0848,
1572                 .enable_mask = BIT(0),
1573                 .hw.init = &(struct clk_init_data){
1574                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1575                         .parent_hws = (const struct clk_hw*[]){
1576                                 &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
1577                         },
1578                         .num_parents = 1,
1579                         .flags = CLK_SET_RATE_PARENT,
1580                         .ops = &clk_branch2_ops,
1581                 },
1582         },
1583 };
1584
1585 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1586         .halt_reg = 0x0844,
1587         .clkr = {
1588                 .enable_reg = 0x0844,
1589                 .enable_mask = BIT(0),
1590                 .hw.init = &(struct clk_init_data){
1591                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1592                         .parent_hws = (const struct clk_hw*[]){
1593                                 &blsp1_qup5_spi_apps_clk_src.clkr.hw,
1594                         },
1595                         .num_parents = 1,
1596                         .flags = CLK_SET_RATE_PARENT,
1597                         .ops = &clk_branch2_ops,
1598                 },
1599         },
1600 };
1601
1602 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1603         .halt_reg = 0x08c8,
1604         .clkr = {
1605                 .enable_reg = 0x08c8,
1606                 .enable_mask = BIT(0),
1607                 .hw.init = &(struct clk_init_data){
1608                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1609                         .parent_hws = (const struct clk_hw*[]){
1610                                 &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
1611                         },
1612                         .num_parents = 1,
1613                         .flags = CLK_SET_RATE_PARENT,
1614                         .ops = &clk_branch2_ops,
1615                 },
1616         },
1617 };
1618
1619 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1620         .halt_reg = 0x08c4,
1621         .clkr = {
1622                 .enable_reg = 0x08c4,
1623                 .enable_mask = BIT(0),
1624                 .hw.init = &(struct clk_init_data){
1625                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1626                         .parent_hws = (const struct clk_hw*[]){
1627                                 &blsp1_qup6_spi_apps_clk_src.clkr.hw,
1628                         },
1629                         .num_parents = 1,
1630                         .flags = CLK_SET_RATE_PARENT,
1631                         .ops = &clk_branch2_ops,
1632                 },
1633         },
1634 };
1635
1636 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1637         .halt_reg = 0x0684,
1638         .clkr = {
1639                 .enable_reg = 0x0684,
1640                 .enable_mask = BIT(0),
1641                 .hw.init = &(struct clk_init_data){
1642                         .name = "gcc_blsp1_uart1_apps_clk",
1643                         .parent_hws = (const struct clk_hw*[]){
1644                                 &blsp1_uart1_apps_clk_src.clkr.hw,
1645                         },
1646                         .num_parents = 1,
1647                         .flags = CLK_SET_RATE_PARENT,
1648                         .ops = &clk_branch2_ops,
1649                 },
1650         },
1651 };
1652
1653 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1654         .halt_reg = 0x0704,
1655         .clkr = {
1656                 .enable_reg = 0x0704,
1657                 .enable_mask = BIT(0),
1658                 .hw.init = &(struct clk_init_data){
1659                         .name = "gcc_blsp1_uart2_apps_clk",
1660                         .parent_hws = (const struct clk_hw*[]){
1661                                 &blsp1_uart2_apps_clk_src.clkr.hw,
1662                         },
1663                         .num_parents = 1,
1664                         .flags = CLK_SET_RATE_PARENT,
1665                         .ops = &clk_branch2_ops,
1666                 },
1667         },
1668 };
1669
1670 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1671         .halt_reg = 0x0784,
1672         .clkr = {
1673                 .enable_reg = 0x0784,
1674                 .enable_mask = BIT(0),
1675                 .hw.init = &(struct clk_init_data){
1676                         .name = "gcc_blsp1_uart3_apps_clk",
1677                         .parent_hws = (const struct clk_hw*[]){
1678                                 &blsp1_uart3_apps_clk_src.clkr.hw,
1679                         },
1680                         .num_parents = 1,
1681                         .flags = CLK_SET_RATE_PARENT,
1682                         .ops = &clk_branch2_ops,
1683                 },
1684         },
1685 };
1686
1687 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1688         .halt_reg = 0x0804,
1689         .clkr = {
1690                 .enable_reg = 0x0804,
1691                 .enable_mask = BIT(0),
1692                 .hw.init = &(struct clk_init_data){
1693                         .name = "gcc_blsp1_uart4_apps_clk",
1694                         .parent_hws = (const struct clk_hw*[]){
1695                                 &blsp1_uart4_apps_clk_src.clkr.hw,
1696                         },
1697                         .num_parents = 1,
1698                         .flags = CLK_SET_RATE_PARENT,
1699                         .ops = &clk_branch2_ops,
1700                 },
1701         },
1702 };
1703
1704 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1705         .halt_reg = 0x0884,
1706         .clkr = {
1707                 .enable_reg = 0x0884,
1708                 .enable_mask = BIT(0),
1709                 .hw.init = &(struct clk_init_data){
1710                         .name = "gcc_blsp1_uart5_apps_clk",
1711                         .parent_hws = (const struct clk_hw*[]){
1712                                 &blsp1_uart5_apps_clk_src.clkr.hw,
1713                         },
1714                         .num_parents = 1,
1715                         .flags = CLK_SET_RATE_PARENT,
1716                         .ops = &clk_branch2_ops,
1717                 },
1718         },
1719 };
1720
1721 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1722         .halt_reg = 0x0904,
1723         .clkr = {
1724                 .enable_reg = 0x0904,
1725                 .enable_mask = BIT(0),
1726                 .hw.init = &(struct clk_init_data){
1727                         .name = "gcc_blsp1_uart6_apps_clk",
1728                         .parent_hws = (const struct clk_hw*[]){
1729                                 &blsp1_uart6_apps_clk_src.clkr.hw,
1730                         },
1731                         .num_parents = 1,
1732                         .flags = CLK_SET_RATE_PARENT,
1733                         .ops = &clk_branch2_ops,
1734                 },
1735         },
1736 };
1737
1738 static struct clk_branch gcc_blsp2_ahb_clk = {
1739         .halt_reg = 0x0944,
1740         .halt_check = BRANCH_HALT_VOTED,
1741         .clkr = {
1742                 .enable_reg = 0x1484,
1743                 .enable_mask = BIT(15),
1744                 .hw.init = &(struct clk_init_data){
1745                         .name = "gcc_blsp2_ahb_clk",
1746                         .parent_hws = (const struct clk_hw*[]){
1747                                 &periph_noc_clk_src.clkr.hw,
1748                         },
1749                         .num_parents = 1,
1750                         .ops = &clk_branch2_ops,
1751                 },
1752         },
1753 };
1754
1755 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1756         .halt_reg = 0x0988,
1757         .clkr = {
1758                 .enable_reg = 0x0988,
1759                 .enable_mask = BIT(0),
1760                 .hw.init = &(struct clk_init_data){
1761                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1762                         .parent_hws = (const struct clk_hw*[]){
1763                                 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1764                         },
1765                         .num_parents = 1,
1766                         .flags = CLK_SET_RATE_PARENT,
1767                         .ops = &clk_branch2_ops,
1768                 },
1769         },
1770 };
1771
1772 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1773         .halt_reg = 0x0984,
1774         .clkr = {
1775                 .enable_reg = 0x0984,
1776                 .enable_mask = BIT(0),
1777                 .hw.init = &(struct clk_init_data){
1778                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1779                         .parent_hws = (const struct clk_hw*[]){
1780                                 &blsp2_qup1_spi_apps_clk_src.clkr.hw,
1781                         },
1782                         .num_parents = 1,
1783                         .flags = CLK_SET_RATE_PARENT,
1784                         .ops = &clk_branch2_ops,
1785                 },
1786         },
1787 };
1788
1789 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1790         .halt_reg = 0x0a08,
1791         .clkr = {
1792                 .enable_reg = 0x0a08,
1793                 .enable_mask = BIT(0),
1794                 .hw.init = &(struct clk_init_data){
1795                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1796                         .parent_hws = (const struct clk_hw*[]){
1797                                 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1798                         },
1799                         .num_parents = 1,
1800                         .flags = CLK_SET_RATE_PARENT,
1801                         .ops = &clk_branch2_ops,
1802                 },
1803         },
1804 };
1805
1806 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1807         .halt_reg = 0x0a04,
1808         .clkr = {
1809                 .enable_reg = 0x0a04,
1810                 .enable_mask = BIT(0),
1811                 .hw.init = &(struct clk_init_data){
1812                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1813                         .parent_hws = (const struct clk_hw*[]){
1814                                 &blsp2_qup2_spi_apps_clk_src.clkr.hw,
1815                         },
1816                         .num_parents = 1,
1817                         .flags = CLK_SET_RATE_PARENT,
1818                         .ops = &clk_branch2_ops,
1819                 },
1820         },
1821 };
1822
1823 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1824         .halt_reg = 0x0a88,
1825         .clkr = {
1826                 .enable_reg = 0x0a88,
1827                 .enable_mask = BIT(0),
1828                 .hw.init = &(struct clk_init_data){
1829                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1830                         .parent_hws = (const struct clk_hw*[]){
1831                                 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1832                         },
1833                         .num_parents = 1,
1834                         .flags = CLK_SET_RATE_PARENT,
1835                         .ops = &clk_branch2_ops,
1836                 },
1837         },
1838 };
1839
1840 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1841         .halt_reg = 0x0a84,
1842         .clkr = {
1843                 .enable_reg = 0x0a84,
1844                 .enable_mask = BIT(0),
1845                 .hw.init = &(struct clk_init_data){
1846                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1847                         .parent_hws = (const struct clk_hw*[]){
1848                                 &blsp2_qup3_spi_apps_clk_src.clkr.hw,
1849                         },
1850                         .num_parents = 1,
1851                         .flags = CLK_SET_RATE_PARENT,
1852                         .ops = &clk_branch2_ops,
1853                 },
1854         },
1855 };
1856
1857 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1858         .halt_reg = 0x0b08,
1859         .clkr = {
1860                 .enable_reg = 0x0b08,
1861                 .enable_mask = BIT(0),
1862                 .hw.init = &(struct clk_init_data){
1863                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1864                         .parent_hws = (const struct clk_hw*[]){
1865                                 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
1866                         },
1867                         .num_parents = 1,
1868                         .flags = CLK_SET_RATE_PARENT,
1869                         .ops = &clk_branch2_ops,
1870                 },
1871         },
1872 };
1873
1874 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1875         .halt_reg = 0x0b04,
1876         .clkr = {
1877                 .enable_reg = 0x0b04,
1878                 .enable_mask = BIT(0),
1879                 .hw.init = &(struct clk_init_data){
1880                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1881                         .parent_hws = (const struct clk_hw*[]){
1882                                 &blsp2_qup4_spi_apps_clk_src.clkr.hw,
1883                         },
1884                         .num_parents = 1,
1885                         .flags = CLK_SET_RATE_PARENT,
1886                         .ops = &clk_branch2_ops,
1887                 },
1888         },
1889 };
1890
1891 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1892         .halt_reg = 0x0b88,
1893         .clkr = {
1894                 .enable_reg = 0x0b88,
1895                 .enable_mask = BIT(0),
1896                 .hw.init = &(struct clk_init_data){
1897                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1898                         .parent_hws = (const struct clk_hw*[]){
1899                                 &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
1900                         },
1901                         .num_parents = 1,
1902                         .flags = CLK_SET_RATE_PARENT,
1903                         .ops = &clk_branch2_ops,
1904                 },
1905         },
1906 };
1907
1908 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1909         .halt_reg = 0x0b84,
1910         .clkr = {
1911                 .enable_reg = 0x0b84,
1912                 .enable_mask = BIT(0),
1913                 .hw.init = &(struct clk_init_data){
1914                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1915                         .parent_hws = (const struct clk_hw*[]){
1916                                 &blsp2_qup5_spi_apps_clk_src.clkr.hw,
1917                         },
1918                         .num_parents = 1,
1919                         .flags = CLK_SET_RATE_PARENT,
1920                         .ops = &clk_branch2_ops,
1921                 },
1922         },
1923 };
1924
1925 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1926         .halt_reg = 0x0c08,
1927         .clkr = {
1928                 .enable_reg = 0x0c08,
1929                 .enable_mask = BIT(0),
1930                 .hw.init = &(struct clk_init_data){
1931                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1932                         .parent_hws = (const struct clk_hw*[]){
1933                                 &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
1934                         },
1935                         .num_parents = 1,
1936                         .flags = CLK_SET_RATE_PARENT,
1937                         .ops = &clk_branch2_ops,
1938                 },
1939         },
1940 };
1941
1942 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1943         .halt_reg = 0x0c04,
1944         .clkr = {
1945                 .enable_reg = 0x0c04,
1946                 .enable_mask = BIT(0),
1947                 .hw.init = &(struct clk_init_data){
1948                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1949                         .parent_hws = (const struct clk_hw*[]){
1950                                 &blsp2_qup6_spi_apps_clk_src.clkr.hw,
1951                         },
1952                         .num_parents = 1,
1953                         .flags = CLK_SET_RATE_PARENT,
1954                         .ops = &clk_branch2_ops,
1955                 },
1956         },
1957 };
1958
1959 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1960         .halt_reg = 0x09c4,
1961         .clkr = {
1962                 .enable_reg = 0x09c4,
1963                 .enable_mask = BIT(0),
1964                 .hw.init = &(struct clk_init_data){
1965                         .name = "gcc_blsp2_uart1_apps_clk",
1966                         .parent_hws = (const struct clk_hw*[]){
1967                                 &blsp2_uart1_apps_clk_src.clkr.hw,
1968                         },
1969                         .num_parents = 1,
1970                         .flags = CLK_SET_RATE_PARENT,
1971                         .ops = &clk_branch2_ops,
1972                 },
1973         },
1974 };
1975
1976 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1977         .halt_reg = 0x0a44,
1978         .clkr = {
1979                 .enable_reg = 0x0a44,
1980                 .enable_mask = BIT(0),
1981                 .hw.init = &(struct clk_init_data){
1982                         .name = "gcc_blsp2_uart2_apps_clk",
1983                         .parent_hws = (const struct clk_hw*[]){
1984                                 &blsp2_uart2_apps_clk_src.clkr.hw,
1985                         },
1986                         .num_parents = 1,
1987                         .flags = CLK_SET_RATE_PARENT,
1988                         .ops = &clk_branch2_ops,
1989                 },
1990         },
1991 };
1992
1993 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1994         .halt_reg = 0x0ac4,
1995         .clkr = {
1996                 .enable_reg = 0x0ac4,
1997                 .enable_mask = BIT(0),
1998                 .hw.init = &(struct clk_init_data){
1999                         .name = "gcc_blsp2_uart3_apps_clk",
2000                         .parent_hws = (const struct clk_hw*[]){
2001                                 &blsp2_uart3_apps_clk_src.clkr.hw,
2002                         },
2003                         .num_parents = 1,
2004                         .flags = CLK_SET_RATE_PARENT,
2005                         .ops = &clk_branch2_ops,
2006                 },
2007         },
2008 };
2009
2010 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2011         .halt_reg = 0x0b44,
2012         .clkr = {
2013                 .enable_reg = 0x0b44,
2014                 .enable_mask = BIT(0),
2015                 .hw.init = &(struct clk_init_data){
2016                         .name = "gcc_blsp2_uart4_apps_clk",
2017                         .parent_hws = (const struct clk_hw*[]){
2018                                 &blsp2_uart4_apps_clk_src.clkr.hw,
2019                         },
2020                         .num_parents = 1,
2021                         .flags = CLK_SET_RATE_PARENT,
2022                         .ops = &clk_branch2_ops,
2023                 },
2024         },
2025 };
2026
2027 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2028         .halt_reg = 0x0bc4,
2029         .clkr = {
2030                 .enable_reg = 0x0bc4,
2031                 .enable_mask = BIT(0),
2032                 .hw.init = &(struct clk_init_data){
2033                         .name = "gcc_blsp2_uart5_apps_clk",
2034                         .parent_hws = (const struct clk_hw*[]){
2035                                 &blsp2_uart5_apps_clk_src.clkr.hw,
2036                         },
2037                         .num_parents = 1,
2038                         .flags = CLK_SET_RATE_PARENT,
2039                         .ops = &clk_branch2_ops,
2040                 },
2041         },
2042 };
2043
2044 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2045         .halt_reg = 0x0c44,
2046         .clkr = {
2047                 .enable_reg = 0x0c44,
2048                 .enable_mask = BIT(0),
2049                 .hw.init = &(struct clk_init_data){
2050                         .name = "gcc_blsp2_uart6_apps_clk",
2051                         .parent_hws = (const struct clk_hw*[]){
2052                                 &blsp2_uart6_apps_clk_src.clkr.hw,
2053                         },
2054                         .num_parents = 1,
2055                         .flags = CLK_SET_RATE_PARENT,
2056                         .ops = &clk_branch2_ops,
2057                 },
2058         },
2059 };
2060
2061 static struct clk_branch gcc_boot_rom_ahb_clk = {
2062         .halt_reg = 0x0e04,
2063         .halt_check = BRANCH_HALT_VOTED,
2064         .clkr = {
2065                 .enable_reg = 0x1484,
2066                 .enable_mask = BIT(10),
2067                 .hw.init = &(struct clk_init_data){
2068                         .name = "gcc_boot_rom_ahb_clk",
2069                         .parent_hws = (const struct clk_hw*[]){
2070                                 &config_noc_clk_src.clkr.hw,
2071                         },
2072                         .num_parents = 1,
2073                         .ops = &clk_branch2_ops,
2074                 },
2075         },
2076 };
2077
2078 static struct clk_branch gcc_ce1_ahb_clk = {
2079         .halt_reg = 0x104c,
2080         .halt_check = BRANCH_HALT_VOTED,
2081         .clkr = {
2082                 .enable_reg = 0x1484,
2083                 .enable_mask = BIT(3),
2084                 .hw.init = &(struct clk_init_data){
2085                         .name = "gcc_ce1_ahb_clk",
2086                         .parent_hws = (const struct clk_hw*[]){
2087                                 &config_noc_clk_src.clkr.hw,
2088                         },
2089                         .num_parents = 1,
2090                         .ops = &clk_branch2_ops,
2091                 },
2092         },
2093 };
2094
2095 static struct clk_branch gcc_ce1_axi_clk = {
2096         .halt_reg = 0x1048,
2097         .halt_check = BRANCH_HALT_VOTED,
2098         .clkr = {
2099                 .enable_reg = 0x1484,
2100                 .enable_mask = BIT(4),
2101                 .hw.init = &(struct clk_init_data){
2102                         .name = "gcc_ce1_axi_clk",
2103                         .parent_hws = (const struct clk_hw*[]){
2104                                 &system_noc_clk_src.clkr.hw,
2105                         },
2106                         .num_parents = 1,
2107                         .ops = &clk_branch2_ops,
2108                 },
2109         },
2110 };
2111
2112 static struct clk_branch gcc_ce1_clk = {
2113         .halt_reg = 0x1050,
2114         .halt_check = BRANCH_HALT_VOTED,
2115         .clkr = {
2116                 .enable_reg = 0x1484,
2117                 .enable_mask = BIT(5),
2118                 .hw.init = &(struct clk_init_data){
2119                         .name = "gcc_ce1_clk",
2120                         .parent_hws = (const struct clk_hw*[]){
2121                                 &ce1_clk_src.clkr.hw,
2122                         },
2123                         .num_parents = 1,
2124                         .flags = CLK_SET_RATE_PARENT,
2125                         .ops = &clk_branch2_ops,
2126                 },
2127         },
2128 };
2129
2130 static struct clk_branch gcc_ce2_ahb_clk = {
2131         .halt_reg = 0x108c,
2132         .halt_check = BRANCH_HALT_VOTED,
2133         .clkr = {
2134                 .enable_reg = 0x1484,
2135                 .enable_mask = BIT(0),
2136                 .hw.init = &(struct clk_init_data){
2137                         .name = "gcc_ce2_ahb_clk",
2138                         .parent_hws = (const struct clk_hw*[]){
2139                                 &config_noc_clk_src.clkr.hw,
2140                         },
2141                         .num_parents = 1,
2142                         .ops = &clk_branch2_ops,
2143                 },
2144         },
2145 };
2146
2147 static struct clk_branch gcc_ce2_axi_clk = {
2148         .halt_reg = 0x1088,
2149         .halt_check = BRANCH_HALT_VOTED,
2150         .clkr = {
2151                 .enable_reg = 0x1484,
2152                 .enable_mask = BIT(1),
2153                 .hw.init = &(struct clk_init_data){
2154                         .name = "gcc_ce2_axi_clk",
2155                         .parent_hws = (const struct clk_hw*[]){
2156                                 &system_noc_clk_src.clkr.hw,
2157                         },
2158                         .num_parents = 1,
2159                         .ops = &clk_branch2_ops,
2160                 },
2161         },
2162 };
2163
2164 static struct clk_branch gcc_ce2_clk = {
2165         .halt_reg = 0x1090,
2166         .halt_check = BRANCH_HALT_VOTED,
2167         .clkr = {
2168                 .enable_reg = 0x1484,
2169                 .enable_mask = BIT(2),
2170                 .hw.init = &(struct clk_init_data){
2171                         .name = "gcc_ce2_clk",
2172                         .parent_hws = (const struct clk_hw*[]){
2173                                 &ce2_clk_src.clkr.hw,
2174                         },
2175                         .num_parents = 1,
2176                         .flags = CLK_SET_RATE_PARENT,
2177                         .ops = &clk_branch2_ops,
2178                 },
2179         },
2180 };
2181
2182 static struct clk_branch gcc_ce3_ahb_clk = {
2183         .halt_reg = 0x1d0c,
2184         .halt_check = BRANCH_HALT_VOTED,
2185         .clkr = {
2186                 .enable_reg = 0x1d0c,
2187                 .enable_mask = BIT(0),
2188                 .hw.init = &(struct clk_init_data){
2189                         .name = "gcc_ce3_ahb_clk",
2190                         .parent_hws = (const struct clk_hw*[]){
2191                                 &config_noc_clk_src.clkr.hw,
2192                         },
2193                         .num_parents = 1,
2194                         .ops = &clk_branch2_ops,
2195                 },
2196         },
2197 };
2198
2199 static struct clk_branch gcc_ce3_axi_clk = {
2200         .halt_reg = 0x1088,
2201         .halt_check = BRANCH_HALT_VOTED,
2202         .clkr = {
2203                 .enable_reg = 0x1d08,
2204                 .enable_mask = BIT(0),
2205                 .hw.init = &(struct clk_init_data){
2206                         .name = "gcc_ce3_axi_clk",
2207                         .parent_hws = (const struct clk_hw*[]){
2208                                 &system_noc_clk_src.clkr.hw,
2209                         },
2210                         .num_parents = 1,
2211                         .ops = &clk_branch2_ops,
2212                 },
2213         },
2214 };
2215
2216 static struct clk_branch gcc_ce3_clk = {
2217         .halt_reg = 0x1090,
2218         .halt_check = BRANCH_HALT_VOTED,
2219         .clkr = {
2220                 .enable_reg = 0x1d04,
2221                 .enable_mask = BIT(0),
2222                 .hw.init = &(struct clk_init_data){
2223                         .name = "gcc_ce3_clk",
2224                         .parent_hws = (const struct clk_hw*[]){
2225                                 &ce3_clk_src.clkr.hw,
2226                         },
2227                         .num_parents = 1,
2228                         .flags = CLK_SET_RATE_PARENT,
2229                         .ops = &clk_branch2_ops,
2230                 },
2231         },
2232 };
2233
2234 static struct clk_branch gcc_gp1_clk = {
2235         .halt_reg = 0x1900,
2236         .clkr = {
2237                 .enable_reg = 0x1900,
2238                 .enable_mask = BIT(0),
2239                 .hw.init = &(struct clk_init_data){
2240                         .name = "gcc_gp1_clk",
2241                         .parent_hws = (const struct clk_hw*[]){
2242                                 &gp1_clk_src.clkr.hw,
2243                         },
2244                         .num_parents = 1,
2245                         .flags = CLK_SET_RATE_PARENT,
2246                         .ops = &clk_branch2_ops,
2247                 },
2248         },
2249 };
2250
2251 static struct clk_branch gcc_gp2_clk = {
2252         .halt_reg = 0x1940,
2253         .clkr = {
2254                 .enable_reg = 0x1940,
2255                 .enable_mask = BIT(0),
2256                 .hw.init = &(struct clk_init_data){
2257                         .name = "gcc_gp2_clk",
2258                         .parent_hws = (const struct clk_hw*[]){
2259                                 &gp2_clk_src.clkr.hw,
2260                         },
2261                         .num_parents = 1,
2262                         .flags = CLK_SET_RATE_PARENT,
2263                         .ops = &clk_branch2_ops,
2264                 },
2265         },
2266 };
2267
2268 static struct clk_branch gcc_gp3_clk = {
2269         .halt_reg = 0x1980,
2270         .clkr = {
2271                 .enable_reg = 0x1980,
2272                 .enable_mask = BIT(0),
2273                 .hw.init = &(struct clk_init_data){
2274                         .name = "gcc_gp3_clk",
2275                         .parent_hws = (const struct clk_hw*[]){
2276                                 &gp3_clk_src.clkr.hw,
2277                         },
2278                         .num_parents = 1,
2279                         .flags = CLK_SET_RATE_PARENT,
2280                         .ops = &clk_branch2_ops,
2281                 },
2282         },
2283 };
2284
2285 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
2286         .halt_reg = 0x0248,
2287         .clkr = {
2288                 .enable_reg = 0x0248,
2289                 .enable_mask = BIT(0),
2290                 .hw.init = &(struct clk_init_data){
2291                         .name = "gcc_ocmem_noc_cfg_ahb_clk",
2292                         .parent_hws = (const struct clk_hw*[]){
2293                                 &config_noc_clk_src.clkr.hw,
2294                         },
2295                         .num_parents = 1,
2296                         .ops = &clk_branch2_ops,
2297                 },
2298         },
2299 };
2300
2301 static struct clk_branch gcc_pcie_0_aux_clk = {
2302         .halt_reg = 0x1b10,
2303         .clkr = {
2304                 .enable_reg = 0x1b10,
2305                 .enable_mask = BIT(0),
2306                 .hw.init = &(struct clk_init_data){
2307                         .name = "gcc_pcie_0_aux_clk",
2308                         .parent_hws = (const struct clk_hw*[]){
2309                                 &pcie_0_aux_clk_src.clkr.hw,
2310                         },
2311                         .num_parents = 1,
2312                         .flags = CLK_SET_RATE_PARENT,
2313                         .ops = &clk_branch2_ops,
2314                 },
2315         },
2316 };
2317
2318 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2319         .halt_reg = 0x1b0c,
2320         .clkr = {
2321                 .enable_reg = 0x1b0c,
2322                 .enable_mask = BIT(0),
2323                 .hw.init = &(struct clk_init_data){
2324                         .name = "gcc_pcie_0_cfg_ahb_clk",
2325                         .parent_hws = (const struct clk_hw*[]){
2326                                 &config_noc_clk_src.clkr.hw,
2327                         },
2328                         .num_parents = 1,
2329                         .flags = CLK_SET_RATE_PARENT,
2330                         .ops = &clk_branch2_ops,
2331                 },
2332         },
2333 };
2334
2335 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2336         .halt_reg = 0x1b08,
2337         .clkr = {
2338                 .enable_reg = 0x1b08,
2339                 .enable_mask = BIT(0),
2340                 .hw.init = &(struct clk_init_data){
2341                         .name = "gcc_pcie_0_mstr_axi_clk",
2342                         .parent_hws = (const struct clk_hw*[]){
2343                                 &config_noc_clk_src.clkr.hw,
2344                         },
2345                         .num_parents = 1,
2346                         .flags = CLK_SET_RATE_PARENT,
2347                         .ops = &clk_branch2_ops,
2348                 },
2349         },
2350 };
2351
2352 static struct clk_branch gcc_pcie_0_pipe_clk = {
2353         .halt_reg = 0x1b14,
2354         .clkr = {
2355                 .enable_reg = 0x1b14,
2356                 .enable_mask = BIT(0),
2357                 .hw.init = &(struct clk_init_data){
2358                         .name = "gcc_pcie_0_pipe_clk",
2359                         .parent_data = &(const struct clk_parent_data){
2360                                 .hw = &pcie_0_pipe_clk_src.clkr.hw,
2361                         },
2362                         .num_parents = 1,
2363                         .flags = CLK_SET_RATE_PARENT,
2364                         .ops = &clk_branch2_ops,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2370         .halt_reg = 0x1b04,
2371         .clkr = {
2372                 .enable_reg = 0x1b04,
2373                 .enable_mask = BIT(0),
2374                 .hw.init = &(struct clk_init_data){
2375                         .name = "gcc_pcie_0_slv_axi_clk",
2376                         .parent_hws = (const struct clk_hw*[]){
2377                                 &config_noc_clk_src.clkr.hw,
2378                         },
2379                         .num_parents = 1,
2380                         .flags = CLK_SET_RATE_PARENT,
2381                         .ops = &clk_branch2_ops,
2382                 },
2383         },
2384 };
2385
2386 static struct clk_branch gcc_pcie_1_aux_clk = {
2387         .halt_reg = 0x1b90,
2388         .clkr = {
2389                 .enable_reg = 0x1b90,
2390                 .enable_mask = BIT(0),
2391                 .hw.init = &(struct clk_init_data){
2392                         .name = "gcc_pcie_1_aux_clk",
2393                         .parent_hws = (const struct clk_hw*[]){
2394                                 &pcie_1_aux_clk_src.clkr.hw,
2395                         },
2396                         .num_parents = 1,
2397                         .flags = CLK_SET_RATE_PARENT,
2398                         .ops = &clk_branch2_ops,
2399                 },
2400         },
2401 };
2402
2403 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2404         .halt_reg = 0x1b8c,
2405         .clkr = {
2406                 .enable_reg = 0x1b8c,
2407                 .enable_mask = BIT(0),
2408                 .hw.init = &(struct clk_init_data){
2409                         .name = "gcc_pcie_1_cfg_ahb_clk",
2410                         .parent_hws = (const struct clk_hw*[]){
2411                                 &config_noc_clk_src.clkr.hw,
2412                         },
2413                         .num_parents = 1,
2414                         .flags = CLK_SET_RATE_PARENT,
2415                         .ops = &clk_branch2_ops,
2416                 },
2417         },
2418 };
2419
2420 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2421         .halt_reg = 0x1b88,
2422         .clkr = {
2423                 .enable_reg = 0x1b88,
2424                 .enable_mask = BIT(0),
2425                 .hw.init = &(struct clk_init_data){
2426                         .name = "gcc_pcie_1_mstr_axi_clk",
2427                         .parent_hws = (const struct clk_hw*[]){
2428                                 &config_noc_clk_src.clkr.hw,
2429                         },
2430                         .num_parents = 1,
2431                         .flags = CLK_SET_RATE_PARENT,
2432                         .ops = &clk_branch2_ops,
2433                 },
2434         },
2435 };
2436
2437 static struct clk_branch gcc_pcie_1_pipe_clk = {
2438         .halt_reg = 0x1b94,
2439         .clkr = {
2440                 .enable_reg = 0x1b94,
2441                 .enable_mask = BIT(0),
2442                 .hw.init = &(struct clk_init_data){
2443                         .name = "gcc_pcie_1_pipe_clk",
2444                         .parent_data = &(const struct clk_parent_data){
2445                                 .hw = &pcie_1_pipe_clk_src.clkr.hw,
2446                         },
2447                         .num_parents = 1,
2448                         .flags = CLK_SET_RATE_PARENT,
2449                         .ops = &clk_branch2_ops,
2450                 },
2451         },
2452 };
2453
2454 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2455         .halt_reg = 0x1b84,
2456         .clkr = {
2457                 .enable_reg = 0x1b84,
2458                 .enable_mask = BIT(0),
2459                 .hw.init = &(struct clk_init_data){
2460                         .name = "gcc_pcie_1_slv_axi_clk",
2461                         .parent_hws = (const struct clk_hw*[]){
2462                                 &config_noc_clk_src.clkr.hw,
2463                         },
2464                         .num_parents = 1,
2465                         .flags = CLK_SET_RATE_PARENT,
2466                         .ops = &clk_branch2_ops,
2467                 },
2468         },
2469 };
2470
2471 static struct clk_branch gcc_pdm2_clk = {
2472         .halt_reg = 0x0ccc,
2473         .clkr = {
2474                 .enable_reg = 0x0ccc,
2475                 .enable_mask = BIT(0),
2476                 .hw.init = &(struct clk_init_data){
2477                         .name = "gcc_pdm2_clk",
2478                         .parent_hws = (const struct clk_hw*[]){
2479                                 &pdm2_clk_src.clkr.hw,
2480                         },
2481                         .num_parents = 1,
2482                         .flags = CLK_SET_RATE_PARENT,
2483                         .ops = &clk_branch2_ops,
2484                 },
2485         },
2486 };
2487
2488 static struct clk_branch gcc_pdm_ahb_clk = {
2489         .halt_reg = 0x0cc4,
2490         .clkr = {
2491                 .enable_reg = 0x0cc4,
2492                 .enable_mask = BIT(0),
2493                 .hw.init = &(struct clk_init_data){
2494                         .name = "gcc_pdm_ahb_clk",
2495                         .parent_hws = (const struct clk_hw*[]){
2496                                 &periph_noc_clk_src.clkr.hw,
2497                         },
2498                         .num_parents = 1,
2499                         .ops = &clk_branch2_ops,
2500                 },
2501         },
2502 };
2503
2504 static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
2505         .halt_reg = 0x01a4,
2506         .clkr = {
2507                 .enable_reg = 0x01a4,
2508                 .enable_mask = BIT(0),
2509                 .hw.init = &(struct clk_init_data){
2510                         .name = "gcc_periph_noc_usb_hsic_ahb_clk",
2511                         .parent_hws = (const struct clk_hw*[]){
2512                                 &usb_hsic_ahb_clk_src.clkr.hw,
2513                         },
2514                         .num_parents = 1,
2515                         .flags = CLK_SET_RATE_PARENT,
2516                         .ops = &clk_branch2_ops,
2517                 },
2518         },
2519 };
2520
2521 static struct clk_branch gcc_prng_ahb_clk = {
2522         .halt_reg = 0x0d04,
2523         .halt_check = BRANCH_HALT_VOTED,
2524         .clkr = {
2525                 .enable_reg = 0x1484,
2526                 .enable_mask = BIT(13),
2527                 .hw.init = &(struct clk_init_data){
2528                         .name = "gcc_prng_ahb_clk",
2529                         .parent_hws = (const struct clk_hw*[]){
2530                                 &periph_noc_clk_src.clkr.hw,
2531                         },
2532                         .num_parents = 1,
2533                         .ops = &clk_branch2_ops,
2534                 },
2535         },
2536 };
2537
2538 static struct clk_branch gcc_sata_asic0_clk = {
2539         .halt_reg = 0x1c54,
2540         .clkr = {
2541                 .enable_reg = 0x1c54,
2542                 .enable_mask = BIT(0),
2543                 .hw.init = &(struct clk_init_data){
2544                         .name = "gcc_sata_asic0_clk",
2545                         .parent_hws = (const struct clk_hw*[]){
2546                                 &sata_asic0_clk_src.clkr.hw,
2547                         },
2548                         .num_parents = 1,
2549                         .flags = CLK_SET_RATE_PARENT,
2550                         .ops = &clk_branch2_ops,
2551                 },
2552         },
2553 };
2554
2555 static struct clk_branch gcc_sata_axi_clk = {
2556         .halt_reg = 0x1c44,
2557         .clkr = {
2558                 .enable_reg = 0x1c44,
2559                 .enable_mask = BIT(0),
2560                 .hw.init = &(struct clk_init_data){
2561                         .name = "gcc_sata_axi_clk",
2562                         .parent_hws = (const struct clk_hw*[]){
2563                                 &config_noc_clk_src.clkr.hw,
2564                         },
2565                         .num_parents = 1,
2566                         .flags = CLK_SET_RATE_PARENT,
2567                         .ops = &clk_branch2_ops,
2568                 },
2569         },
2570 };
2571
2572 static struct clk_branch gcc_sata_cfg_ahb_clk = {
2573         .halt_reg = 0x1c48,
2574         .clkr = {
2575                 .enable_reg = 0x1c48,
2576                 .enable_mask = BIT(0),
2577                 .hw.init = &(struct clk_init_data){
2578                         .name = "gcc_sata_cfg_ahb_clk",
2579                         .parent_hws = (const struct clk_hw*[]){
2580                                 &config_noc_clk_src.clkr.hw,
2581                         },
2582                         .num_parents = 1,
2583                         .flags = CLK_SET_RATE_PARENT,
2584                         .ops = &clk_branch2_ops,
2585                 },
2586         },
2587 };
2588
2589 static struct clk_branch gcc_sata_pmalive_clk = {
2590         .halt_reg = 0x1c50,
2591         .clkr = {
2592                 .enable_reg = 0x1c50,
2593                 .enable_mask = BIT(0),
2594                 .hw.init = &(struct clk_init_data){
2595                         .name = "gcc_sata_pmalive_clk",
2596                         .parent_hws = (const struct clk_hw*[]){
2597                                 &sata_pmalive_clk_src.clkr.hw,
2598                         },
2599                         .num_parents = 1,
2600                         .flags = CLK_SET_RATE_PARENT,
2601                         .ops = &clk_branch2_ops,
2602                 },
2603         },
2604 };
2605
2606 static struct clk_branch gcc_sata_rx_clk = {
2607         .halt_reg = 0x1c58,
2608         .clkr = {
2609                 .enable_reg = 0x1c58,
2610                 .enable_mask = BIT(0),
2611                 .hw.init = &(struct clk_init_data){
2612                         .name = "gcc_sata_rx_clk",
2613                         .parent_hws = (const struct clk_hw*[]){
2614                                 &sata_rx_clk_src.clkr.hw,
2615                         },
2616                         .num_parents = 1,
2617                         .flags = CLK_SET_RATE_PARENT,
2618                         .ops = &clk_branch2_ops,
2619                 },
2620         },
2621 };
2622
2623 static struct clk_branch gcc_sata_rx_oob_clk = {
2624         .halt_reg = 0x1c4c,
2625         .clkr = {
2626                 .enable_reg = 0x1c4c,
2627                 .enable_mask = BIT(0),
2628                 .hw.init = &(struct clk_init_data){
2629                         .name = "gcc_sata_rx_oob_clk",
2630                         .parent_hws = (const struct clk_hw*[]){
2631                                 &sata_rx_oob_clk_src.clkr.hw,
2632                         },
2633                         .num_parents = 1,
2634                         .flags = CLK_SET_RATE_PARENT,
2635                         .ops = &clk_branch2_ops,
2636                 },
2637         },
2638 };
2639
2640 static struct clk_branch gcc_sdcc1_ahb_clk = {
2641         .halt_reg = 0x04c8,
2642         .clkr = {
2643                 .enable_reg = 0x04c8,
2644                 .enable_mask = BIT(0),
2645                 .hw.init = &(struct clk_init_data){
2646                         .name = "gcc_sdcc1_ahb_clk",
2647                         .parent_hws = (const struct clk_hw*[]){
2648                                 &periph_noc_clk_src.clkr.hw,
2649                         },
2650                         .num_parents = 1,
2651                         .ops = &clk_branch2_ops,
2652                 },
2653         },
2654 };
2655
2656 static struct clk_branch gcc_sdcc1_apps_clk = {
2657         .halt_reg = 0x04c4,
2658         .clkr = {
2659                 .enable_reg = 0x04c4,
2660                 .enable_mask = BIT(0),
2661                 .hw.init = &(struct clk_init_data){
2662                         .name = "gcc_sdcc1_apps_clk",
2663                         .parent_hws = (const struct clk_hw*[]){
2664                                 &sdcc1_apps_clk_src.clkr.hw,
2665                         },
2666                         .num_parents = 1,
2667                         .flags = CLK_SET_RATE_PARENT,
2668                         .ops = &clk_branch2_ops,
2669                 },
2670         },
2671 };
2672
2673 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2674         .halt_reg = 0x04e8,
2675         .clkr = {
2676                 .enable_reg = 0x04e8,
2677                 .enable_mask = BIT(0),
2678                 .hw.init = &(struct clk_init_data){
2679                         .name = "gcc_sdcc1_cdccal_ff_clk",
2680                         .parent_data = (const struct clk_parent_data[]){
2681                                 { .fw_name = "xo", .name = "xo_board" }
2682                         },
2683                         .num_parents = 1,
2684                         .ops = &clk_branch2_ops,
2685                 },
2686         },
2687 };
2688
2689 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2690         .halt_reg = 0x04e4,
2691         .clkr = {
2692                 .enable_reg = 0x04e4,
2693                 .enable_mask = BIT(0),
2694                 .hw.init = &(struct clk_init_data){
2695                         .name = "gcc_sdcc1_cdccal_sleep_clk",
2696                         .parent_data = (const struct clk_parent_data[]){
2697                                 { .fw_name = "sleep_clk", .name = "sleep_clk" }
2698                         },
2699                         .num_parents = 1,
2700                         .ops = &clk_branch2_ops,
2701                 },
2702         },
2703 };
2704
2705 static struct clk_branch gcc_sdcc2_ahb_clk = {
2706         .halt_reg = 0x0508,
2707         .clkr = {
2708                 .enable_reg = 0x0508,
2709                 .enable_mask = BIT(0),
2710                 .hw.init = &(struct clk_init_data){
2711                         .name = "gcc_sdcc2_ahb_clk",
2712                         .parent_hws = (const struct clk_hw*[]){
2713                                 &periph_noc_clk_src.clkr.hw,
2714                         },
2715                         .num_parents = 1,
2716                         .ops = &clk_branch2_ops,
2717                 },
2718         },
2719 };
2720
2721 static struct clk_branch gcc_sdcc2_apps_clk = {
2722         .halt_reg = 0x0504,
2723         .clkr = {
2724                 .enable_reg = 0x0504,
2725                 .enable_mask = BIT(0),
2726                 .hw.init = &(struct clk_init_data){
2727                         .name = "gcc_sdcc2_apps_clk",
2728                         .parent_hws = (const struct clk_hw*[]){
2729                                 &sdcc2_apps_clk_src.clkr.hw,
2730                         },
2731                         .num_parents = 1,
2732                         .flags = CLK_SET_RATE_PARENT,
2733                         .ops = &clk_branch2_ops,
2734                 },
2735         },
2736 };
2737
2738 static struct clk_branch gcc_sdcc3_ahb_clk = {
2739         .halt_reg = 0x0548,
2740         .clkr = {
2741                 .enable_reg = 0x0548,
2742                 .enable_mask = BIT(0),
2743                 .hw.init = &(struct clk_init_data){
2744                         .name = "gcc_sdcc3_ahb_clk",
2745                         .parent_hws = (const struct clk_hw*[]){
2746                                 &periph_noc_clk_src.clkr.hw,
2747                         },
2748                         .num_parents = 1,
2749                         .ops = &clk_branch2_ops,
2750                 },
2751         },
2752 };
2753
2754 static struct clk_branch gcc_sdcc3_apps_clk = {
2755         .halt_reg = 0x0544,
2756         .clkr = {
2757                 .enable_reg = 0x0544,
2758                 .enable_mask = BIT(0),
2759                 .hw.init = &(struct clk_init_data){
2760                         .name = "gcc_sdcc3_apps_clk",
2761                         .parent_hws = (const struct clk_hw*[]){
2762                                 &sdcc3_apps_clk_src.clkr.hw,
2763                         },
2764                         .num_parents = 1,
2765                         .flags = CLK_SET_RATE_PARENT,
2766                         .ops = &clk_branch2_ops,
2767                 },
2768         },
2769 };
2770
2771 static struct clk_branch gcc_sdcc4_ahb_clk = {
2772         .halt_reg = 0x0588,
2773         .clkr = {
2774                 .enable_reg = 0x0588,
2775                 .enable_mask = BIT(0),
2776                 .hw.init = &(struct clk_init_data){
2777                         .name = "gcc_sdcc4_ahb_clk",
2778                         .parent_hws = (const struct clk_hw*[]){
2779                                 &periph_noc_clk_src.clkr.hw,
2780                         },
2781                         .num_parents = 1,
2782                         .ops = &clk_branch2_ops,
2783                 },
2784         },
2785 };
2786
2787 static struct clk_branch gcc_sdcc4_apps_clk = {
2788         .halt_reg = 0x0584,
2789         .clkr = {
2790                 .enable_reg = 0x0584,
2791                 .enable_mask = BIT(0),
2792                 .hw.init = &(struct clk_init_data){
2793                         .name = "gcc_sdcc4_apps_clk",
2794                         .parent_hws = (const struct clk_hw*[]){
2795                                 &sdcc4_apps_clk_src.clkr.hw,
2796                         },
2797                         .num_parents = 1,
2798                         .flags = CLK_SET_RATE_PARENT,
2799                         .ops = &clk_branch2_ops,
2800                 },
2801         },
2802 };
2803
2804 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2805         .halt_reg = 0x013c,
2806         .clkr = {
2807                 .enable_reg = 0x013c,
2808                 .enable_mask = BIT(0),
2809                 .hw.init = &(struct clk_init_data){
2810                         .name = "gcc_sys_noc_ufs_axi_clk",
2811                         .parent_hws = (const struct clk_hw*[]){
2812                                 &ufs_axi_clk_src.clkr.hw,
2813                         },
2814                         .num_parents = 1,
2815                         .flags = CLK_SET_RATE_PARENT,
2816                         .ops = &clk_branch2_ops,
2817                 },
2818         },
2819 };
2820
2821 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2822         .halt_reg = 0x0108,
2823         .clkr = {
2824                 .enable_reg = 0x0108,
2825                 .enable_mask = BIT(0),
2826                 .hw.init = &(struct clk_init_data){
2827                         .name = "gcc_sys_noc_usb3_axi_clk",
2828                         .parent_hws = (const struct clk_hw*[]){
2829                                 &usb30_master_clk_src.clkr.hw,
2830                         },
2831                         .num_parents = 1,
2832                         .flags = CLK_SET_RATE_PARENT,
2833                         .ops = &clk_branch2_ops,
2834                 },
2835         },
2836 };
2837
2838 static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
2839         .halt_reg = 0x0138,
2840         .clkr = {
2841                 .enable_reg = 0x0138,
2842                 .enable_mask = BIT(0),
2843                 .hw.init = &(struct clk_init_data){
2844                         .name = "gcc_sys_noc_usb3_sec_axi_clk",
2845                         .parent_hws = (const struct clk_hw*[]){
2846                                 &usb30_sec_master_clk_src.clkr.hw,
2847                         },
2848                         .num_parents = 1,
2849                         .flags = CLK_SET_RATE_PARENT,
2850                         .ops = &clk_branch2_ops,
2851                 },
2852         },
2853 };
2854
2855 static struct clk_branch gcc_tsif_ahb_clk = {
2856         .halt_reg = 0x0d84,
2857         .clkr = {
2858                 .enable_reg = 0x0d84,
2859                 .enable_mask = BIT(0),
2860                 .hw.init = &(struct clk_init_data){
2861                         .name = "gcc_tsif_ahb_clk",
2862                         .parent_hws = (const struct clk_hw*[]){
2863                                 &periph_noc_clk_src.clkr.hw,
2864                         },
2865                         .num_parents = 1,
2866                         .ops = &clk_branch2_ops,
2867                 },
2868         },
2869 };
2870
2871 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2872         .halt_reg = 0x0d8c,
2873         .clkr = {
2874                 .enable_reg = 0x0d8c,
2875                 .enable_mask = BIT(0),
2876                 .hw.init = &(struct clk_init_data){
2877                         .name = "gcc_tsif_inactivity_timers_clk",
2878                         .parent_data = &(const struct clk_parent_data){
2879                                 .fw_name = "sleep_clk", .name = "sleep_clk",
2880                         },
2881                         .num_parents = 1,
2882                         .flags = CLK_SET_RATE_PARENT,
2883                         .ops = &clk_branch2_ops,
2884                 },
2885         },
2886 };
2887
2888 static struct clk_branch gcc_tsif_ref_clk = {
2889         .halt_reg = 0x0d88,
2890         .clkr = {
2891                 .enable_reg = 0x0d88,
2892                 .enable_mask = BIT(0),
2893                 .hw.init = &(struct clk_init_data){
2894                         .name = "gcc_tsif_ref_clk",
2895                         .parent_hws = (const struct clk_hw*[]){
2896                                 &tsif_ref_clk_src.clkr.hw,
2897                         },
2898                         .num_parents = 1,
2899                         .flags = CLK_SET_RATE_PARENT,
2900                         .ops = &clk_branch2_ops,
2901                 },
2902         },
2903 };
2904
2905 static struct clk_branch gcc_ufs_ahb_clk = {
2906         .halt_reg = 0x1d48,
2907         .clkr = {
2908                 .enable_reg = 0x1d48,
2909                 .enable_mask = BIT(0),
2910                 .hw.init = &(struct clk_init_data){
2911                         .name = "gcc_ufs_ahb_clk",
2912                         .parent_hws = (const struct clk_hw*[]){
2913                                 &config_noc_clk_src.clkr.hw,
2914                         },
2915                         .num_parents = 1,
2916                         .flags = CLK_SET_RATE_PARENT,
2917                         .ops = &clk_branch2_ops,
2918                 },
2919         },
2920 };
2921
2922 static struct clk_branch gcc_ufs_axi_clk = {
2923         .halt_reg = 0x1d44,
2924         .clkr = {
2925                 .enable_reg = 0x1d44,
2926                 .enable_mask = BIT(0),
2927                 .hw.init = &(struct clk_init_data){
2928                         .name = "gcc_ufs_axi_clk",
2929                         .parent_hws = (const struct clk_hw*[]){
2930                                 &ufs_axi_clk_src.clkr.hw,
2931                         },
2932                         .num_parents = 1,
2933                         .flags = CLK_SET_RATE_PARENT,
2934                         .ops = &clk_branch2_ops,
2935                 },
2936         },
2937 };
2938
2939 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2940         .halt_reg = 0x1d50,
2941         .clkr = {
2942                 .enable_reg = 0x1d50,
2943                 .enable_mask = BIT(0),
2944                 .hw.init = &(struct clk_init_data){
2945                         .name = "gcc_ufs_rx_cfg_clk",
2946                         .parent_hws = (const struct clk_hw*[]){
2947                                 &ufs_axi_clk_src.clkr.hw,
2948                         },
2949                         .num_parents = 1,
2950                         .flags = CLK_SET_RATE_PARENT,
2951                         .ops = &clk_branch2_ops,
2952                 },
2953         },
2954 };
2955
2956 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2957         .halt_reg = 0x1d5c,
2958         .clkr = {
2959                 .enable_reg = 0x1d5c,
2960                 .enable_mask = BIT(0),
2961                 .hw.init = &(struct clk_init_data){
2962                         .name = "gcc_ufs_rx_symbol_0_clk",
2963                         .parent_data = &(const struct clk_parent_data){
2964                                 .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
2965                         },
2966                         .num_parents = 1,
2967                         .flags = CLK_SET_RATE_PARENT,
2968                         .ops = &clk_branch2_ops,
2969                 },
2970         },
2971 };
2972
2973 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2974         .halt_reg = 0x1d60,
2975         .clkr = {
2976                 .enable_reg = 0x1d60,
2977                 .enable_mask = BIT(0),
2978                 .hw.init = &(struct clk_init_data){
2979                         .name = "gcc_ufs_rx_symbol_1_clk",
2980                         .parent_data = &(const struct clk_parent_data){
2981                                 .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
2982                         },
2983                         .num_parents = 1,
2984                         .flags = CLK_SET_RATE_PARENT,
2985                         .ops = &clk_branch2_ops,
2986                 },
2987         },
2988 };
2989
2990 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2991         .halt_reg = 0x1d4c,
2992         .clkr = {
2993                 .enable_reg = 0x1d4c,
2994                 .enable_mask = BIT(0),
2995                 .hw.init = &(struct clk_init_data){
2996                         .name = "gcc_ufs_tx_cfg_clk",
2997                         .parent_hws = (const struct clk_hw*[]){
2998                                 &ufs_axi_clk_src.clkr.hw,
2999                         },
3000                         .num_parents = 1,
3001                         .flags = CLK_SET_RATE_PARENT,
3002                         .ops = &clk_branch2_ops,
3003                 },
3004         },
3005 };
3006
3007 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
3008         .halt_reg = 0x1d54,
3009         .clkr = {
3010                 .enable_reg = 0x1d54,
3011                 .enable_mask = BIT(0),
3012                 .hw.init = &(struct clk_init_data){
3013                         .name = "gcc_ufs_tx_symbol_0_clk",
3014                         .parent_data = &(const struct clk_parent_data){
3015                                 .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
3016                         },
3017                         .num_parents = 1,
3018                         .flags = CLK_SET_RATE_PARENT,
3019                         .ops = &clk_branch2_ops,
3020                 },
3021         },
3022 };
3023
3024 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
3025         .halt_reg = 0x1d58,
3026         .clkr = {
3027                 .enable_reg = 0x1d58,
3028                 .enable_mask = BIT(0),
3029                 .hw.init = &(struct clk_init_data){
3030                         .name = "gcc_ufs_tx_symbol_1_clk",
3031                         .parent_data = &(const struct clk_parent_data){
3032                                 .fw_name = "ufs_tx_symbol_1_clk_src", .name = "ufs_tx_symbol_1_clk_src",
3033                         },
3034                         .num_parents = 1,
3035                         .flags = CLK_SET_RATE_PARENT,
3036                         .ops = &clk_branch2_ops,
3037                 },
3038         },
3039 };
3040
3041 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3042         .halt_reg = 0x04ac,
3043         .clkr = {
3044                 .enable_reg = 0x04ac,
3045                 .enable_mask = BIT(0),
3046                 .hw.init = &(struct clk_init_data){
3047                         .name = "gcc_usb2a_phy_sleep_clk",
3048                         .parent_data = &(const struct clk_parent_data){
3049                                 .fw_name = "sleep_clk", .name = "sleep_clk",
3050                         },
3051                         .num_parents = 1,
3052                         .ops = &clk_branch2_ops,
3053                 },
3054         },
3055 };
3056
3057 static struct clk_branch gcc_usb2b_phy_sleep_clk = {
3058         .halt_reg = 0x04b4,
3059         .clkr = {
3060                 .enable_reg = 0x04b4,
3061                 .enable_mask = BIT(0),
3062                 .hw.init = &(struct clk_init_data){
3063                         .name = "gcc_usb2b_phy_sleep_clk",
3064                         .parent_data = &(const struct clk_parent_data){
3065                                 .fw_name = "sleep_clk", .name = "sleep_clk",
3066                         },
3067                         .num_parents = 1,
3068                         .ops = &clk_branch2_ops,
3069                 },
3070         },
3071 };
3072
3073 static struct clk_branch gcc_usb30_master_clk = {
3074         .halt_reg = 0x03c8,
3075         .clkr = {
3076                 .enable_reg = 0x03c8,
3077                 .enable_mask = BIT(0),
3078                 .hw.init = &(struct clk_init_data){
3079                         .name = "gcc_usb30_master_clk",
3080                         .parent_hws = (const struct clk_hw*[]){
3081                                 &usb30_master_clk_src.clkr.hw,
3082                         },
3083                         .num_parents = 1,
3084                         .flags = CLK_SET_RATE_PARENT,
3085                         .ops = &clk_branch2_ops,
3086                 },
3087         },
3088 };
3089
3090 static struct clk_branch gcc_usb30_sec_master_clk = {
3091         .halt_reg = 0x1bc8,
3092         .clkr = {
3093                 .enable_reg = 0x1bc8,
3094                 .enable_mask = BIT(0),
3095                 .hw.init = &(struct clk_init_data){
3096                         .name = "gcc_usb30_sec_master_clk",
3097                         .parent_hws = (const struct clk_hw*[]){
3098                                 &usb30_sec_master_clk_src.clkr.hw,
3099                         },
3100                         .num_parents = 1,
3101                         .flags = CLK_SET_RATE_PARENT,
3102                         .ops = &clk_branch2_ops,
3103                 },
3104         },
3105 };
3106
3107 static struct clk_branch gcc_usb30_mock_utmi_clk = {
3108         .halt_reg = 0x03d0,
3109         .clkr = {
3110                 .enable_reg = 0x03d0,
3111                 .enable_mask = BIT(0),
3112                 .hw.init = &(struct clk_init_data){
3113                         .name = "gcc_usb30_mock_utmi_clk",
3114                         .parent_hws = (const struct clk_hw*[]){
3115                                 &usb30_mock_utmi_clk_src.clkr.hw,
3116                         },
3117                         .num_parents = 1,
3118                         .flags = CLK_SET_RATE_PARENT,
3119                         .ops = &clk_branch2_ops,
3120                 },
3121         },
3122 };
3123
3124 static struct clk_branch gcc_usb30_sleep_clk = {
3125         .halt_reg = 0x03cc,
3126         .clkr = {
3127                 .enable_reg = 0x03cc,
3128                 .enable_mask = BIT(0),
3129                 .hw.init = &(struct clk_init_data){
3130                         .name = "gcc_usb30_sleep_clk",
3131                         .parent_data = &(const struct clk_parent_data){
3132                                 .fw_name = "sleep_clk", .name = "sleep_clk",
3133                         },
3134                         .num_parents = 1,
3135                         .ops = &clk_branch2_ops,
3136                 },
3137         },
3138 };
3139
3140 static struct clk_branch gcc_usb_hs_ahb_clk = {
3141         .halt_reg = 0x0488,
3142         .clkr = {
3143                 .enable_reg = 0x0488,
3144                 .enable_mask = BIT(0),
3145                 .hw.init = &(struct clk_init_data){
3146                         .name = "gcc_usb_hs_ahb_clk",
3147                         .parent_hws = (const struct clk_hw*[]){
3148                                 &periph_noc_clk_src.clkr.hw,
3149                         },
3150                         .num_parents = 1,
3151                         .ops = &clk_branch2_ops,
3152                 },
3153         },
3154 };
3155
3156 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
3157         .halt_reg = 0x048c,
3158         .clkr = {
3159                 .enable_reg = 0x048c,
3160                 .enable_mask = BIT(0),
3161                 .hw.init = &(struct clk_init_data){
3162                         .name = "gcc_usb_hs_inactivity_timers_clk",
3163                         .parent_data = &(const struct clk_parent_data){
3164                                 .fw_name = "sleep_clk", .name = "sleep_clk",
3165                         },
3166                         .num_parents = 1,
3167                         .flags = CLK_SET_RATE_PARENT,
3168                         .ops = &clk_branch2_ops,
3169                 },
3170         },
3171 };
3172
3173 static struct clk_branch gcc_usb_hs_system_clk = {
3174         .halt_reg = 0x0484,
3175         .clkr = {
3176                 .enable_reg = 0x0484,
3177                 .enable_mask = BIT(0),
3178                 .hw.init = &(struct clk_init_data){
3179                         .name = "gcc_usb_hs_system_clk",
3180                         .parent_hws = (const struct clk_hw*[]){
3181                                 &usb_hs_system_clk_src.clkr.hw,
3182                         },
3183                         .num_parents = 1,
3184                         .flags = CLK_SET_RATE_PARENT,
3185                         .ops = &clk_branch2_ops,
3186                 },
3187         },
3188 };
3189
3190 static struct clk_branch gcc_usb_hsic_ahb_clk = {
3191         .halt_reg = 0x0408,
3192         .clkr = {
3193                 .enable_reg = 0x0408,
3194                 .enable_mask = BIT(0),
3195                 .hw.init = &(struct clk_init_data){
3196                         .name = "gcc_usb_hsic_ahb_clk",
3197                         .parent_hws = (const struct clk_hw*[]) {
3198                                 &periph_noc_clk_src.clkr.hw,
3199                         },
3200                         .num_parents = 1,
3201                         .ops = &clk_branch2_ops,
3202                 },
3203         },
3204 };
3205
3206 static struct clk_branch gcc_usb_hsic_clk = {
3207         .halt_reg = 0x0410,
3208         .clkr = {
3209                 .enable_reg = 0x0410,
3210                 .enable_mask = BIT(0),
3211                 .hw.init = &(struct clk_init_data){
3212                         .name = "gcc_usb_hsic_clk",
3213                         .parent_hws = (const struct clk_hw*[]){
3214                                 &usb_hsic_clk_src.clkr.hw,
3215                         },
3216                         .num_parents = 1,
3217                         .flags = CLK_SET_RATE_PARENT,
3218                         .ops = &clk_branch2_ops,
3219                 },
3220         },
3221 };
3222
3223 static struct clk_branch gcc_usb_hsic_io_cal_clk = {
3224         .halt_reg = 0x0414,
3225         .clkr = {
3226                 .enable_reg = 0x0414,
3227                 .enable_mask = BIT(0),
3228                 .hw.init = &(struct clk_init_data){
3229                         .name = "gcc_usb_hsic_io_cal_clk",
3230                         .parent_hws = (const struct clk_hw*[]){
3231                                 &usb_hsic_io_cal_clk_src.clkr.hw,
3232                         },
3233                         .num_parents = 1,
3234                         .flags = CLK_SET_RATE_PARENT,
3235                         .ops = &clk_branch2_ops,
3236                 },
3237         },
3238 };
3239
3240 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
3241         .halt_reg = 0x0418,
3242         .clkr = {
3243                 .enable_reg = 0x0418,
3244                 .enable_mask = BIT(0),
3245                 .hw.init = &(struct clk_init_data){
3246                         .name = "gcc_usb_hsic_io_cal_sleep_clk",
3247                         .parent_data = &(const struct clk_parent_data){
3248                                 .fw_name = "sleep_clk", .name = "sleep_clk",
3249                         },
3250                         .num_parents = 1,
3251                         .ops = &clk_branch2_ops,
3252                 },
3253         },
3254 };
3255
3256 static struct clk_branch gcc_usb_hsic_system_clk = {
3257         .halt_reg = 0x040c,
3258         .clkr = {
3259                 .enable_reg = 0x040c,
3260                 .enable_mask = BIT(0),
3261                 .hw.init = &(struct clk_init_data){
3262                         .name = "gcc_usb_hsic_system_clk",
3263                         .parent_hws = (const struct clk_hw*[]){
3264                                 &usb_hsic_system_clk_src.clkr.hw,
3265                         },
3266                         .num_parents = 1,
3267                         .flags = CLK_SET_RATE_PARENT,
3268                         .ops = &clk_branch2_ops,
3269                 },
3270         },
3271 };
3272
3273 static struct gdsc usb_hs_hsic_gdsc = {
3274         .gdscr = 0x404,
3275         .pd = {
3276                 .name = "usb_hs_hsic",
3277         },
3278         .pwrsts = PWRSTS_OFF_ON,
3279 };
3280
3281 static struct gdsc pcie0_gdsc = {
3282         .gdscr = 0x1ac4,
3283         .pd = {
3284                 .name = "pcie0",
3285         },
3286         .pwrsts = PWRSTS_OFF_ON,
3287 };
3288
3289 static struct gdsc pcie1_gdsc = {
3290         .gdscr = 0x1b44,
3291         .pd = {
3292                 .name = "pcie1",
3293         },
3294         .pwrsts = PWRSTS_OFF_ON,
3295 };
3296
3297 static struct gdsc usb30_gdsc = {
3298         .gdscr = 0x1e84,
3299         .pd = {
3300                 .name = "usb30",
3301         },
3302         .pwrsts = PWRSTS_OFF_ON,
3303 };
3304
3305 static struct clk_regmap *gcc_apq8084_clocks[] = {
3306         [GPLL0] = &gpll0.clkr,
3307         [GPLL0_VOTE] = &gpll0_vote,
3308         [GPLL1] = &gpll1.clkr,
3309         [GPLL1_VOTE] = &gpll1_vote,
3310         [GPLL4] = &gpll4.clkr,
3311         [GPLL4_VOTE] = &gpll4_vote,
3312         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3313         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3314         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3315         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3316         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3317         [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
3318         [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
3319         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3320         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3321         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3322         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3323         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3324         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3325         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3326         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3327         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3328         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3329         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3330         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3331         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3332         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3333         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3334         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3335         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3336         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3337         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3338         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3339         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3340         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3341         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3342         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3343         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3344         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3345         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3346         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3347         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3348         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3349         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3350         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3351         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3352         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3353         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3354         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3355         [CE1_CLK_SRC] = &ce1_clk_src.clkr,
3356         [CE2_CLK_SRC] = &ce2_clk_src.clkr,
3357         [CE3_CLK_SRC] = &ce3_clk_src.clkr,
3358         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3359         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3360         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3361         [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
3362         [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
3363         [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
3364         [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
3365         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3366         [SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr,
3367         [SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr,
3368         [SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr,
3369         [SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr,
3370         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3371         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3372         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3373         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3374         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3375         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3376         [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
3377         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3378         [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
3379         [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
3380         [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
3381         [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
3382         [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
3383         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3384         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3385         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3386         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3387         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3388         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3389         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3390         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3391         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3392         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3393         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3394         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3395         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3396         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3397         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3398         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3399         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3400         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3401         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3402         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3403         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3404         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3405         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3406         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3407         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3408         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3409         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3410         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3411         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3412         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3413         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3414         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3415         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3416         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3417         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3418         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3419         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3420         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3421         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3422         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3423         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3424         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3425         [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
3426         [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
3427         [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
3428         [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
3429         [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
3430         [GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
3431         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3432         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3433         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3434         [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
3435         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3436         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3437         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3438         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3439         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3440         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3441         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3442         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3443         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3444         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3445         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3446         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3447         [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
3448         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3449         [GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr,
3450         [GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr,
3451         [GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr,
3452         [GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr,
3453         [GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr,
3454         [GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr,
3455         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3456         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3457         [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
3458         [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
3459         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3460         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3461         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3462         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3463         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3464         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3465         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3466         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3467         [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
3468         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3469         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3470         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3471         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3472         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3473         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3474         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3475         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3476         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3477         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3478         [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
3479         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3480         [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
3481         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3482         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3483         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3484         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3485         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3486         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3487         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3488         [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
3489         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3490         [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
3491         [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
3492         [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
3493         [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
3494         [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
3495         [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
3496         [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
3497 };
3498
3499 static struct gdsc *gcc_apq8084_gdscs[] = {
3500         [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
3501         [PCIE0_GDSC] = &pcie0_gdsc,
3502         [PCIE1_GDSC] = &pcie1_gdsc,
3503         [USB30_GDSC] = &usb30_gdsc,
3504 };
3505
3506 static const struct qcom_reset_map gcc_apq8084_resets[] = {
3507         [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
3508         [GCC_CONFIG_NOC_BCR] = { 0x0140 },
3509         [GCC_PERIPH_NOC_BCR] = { 0x0180 },
3510         [GCC_IMEM_BCR] = { 0x0200 },
3511         [GCC_MMSS_BCR] = { 0x0240 },
3512         [GCC_QDSS_BCR] = { 0x0300 },
3513         [GCC_USB_30_BCR] = { 0x03c0 },
3514         [GCC_USB3_PHY_BCR] = { 0x03fc },
3515         [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
3516         [GCC_USB_HS_BCR] = { 0x0480 },
3517         [GCC_USB2A_PHY_BCR] = { 0x04a8 },
3518         [GCC_USB2B_PHY_BCR] = { 0x04b0 },
3519         [GCC_SDCC1_BCR] = { 0x04c0 },
3520         [GCC_SDCC2_BCR] = { 0x0500 },
3521         [GCC_SDCC3_BCR] = { 0x0540 },
3522         [GCC_SDCC4_BCR] = { 0x0580 },
3523         [GCC_BLSP1_BCR] = { 0x05c0 },
3524         [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
3525         [GCC_BLSP1_UART1_BCR] = { 0x0680 },
3526         [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
3527         [GCC_BLSP1_UART2_BCR] = { 0x0700 },
3528         [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
3529         [GCC_BLSP1_UART3_BCR] = { 0x0780 },
3530         [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
3531         [GCC_BLSP1_UART4_BCR] = { 0x0800 },
3532         [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
3533         [GCC_BLSP1_UART5_BCR] = { 0x0880 },
3534         [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
3535         [GCC_BLSP1_UART6_BCR] = { 0x0900 },
3536         [GCC_BLSP2_BCR] = { 0x0940 },
3537         [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
3538         [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
3539         [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
3540         [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
3541         [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
3542         [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
3543         [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
3544         [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
3545         [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
3546         [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
3547         [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
3548         [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
3549         [GCC_PDM_BCR] = { 0x0cc0 },
3550         [GCC_PRNG_BCR] = { 0x0d00 },
3551         [GCC_BAM_DMA_BCR] = { 0x0d40 },
3552         [GCC_TSIF_BCR] = { 0x0d80 },
3553         [GCC_TCSR_BCR] = { 0x0dc0 },
3554         [GCC_BOOT_ROM_BCR] = { 0x0e00 },
3555         [GCC_MSG_RAM_BCR] = { 0x0e40 },
3556         [GCC_TLMM_BCR] = { 0x0e80 },
3557         [GCC_MPM_BCR] = { 0x0ec0 },
3558         [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
3559         [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
3560         [GCC_SEC_CTRL_BCR] = { 0x0f40 },
3561         [GCC_SPMI_BCR] = { 0x0fc0 },
3562         [GCC_SPDM_BCR] = { 0x1000 },
3563         [GCC_CE1_BCR] = { 0x1040 },
3564         [GCC_CE2_BCR] = { 0x1080 },
3565         [GCC_BIMC_BCR] = { 0x1100 },
3566         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
3567         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
3568         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
3569         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
3570         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
3571         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
3572         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
3573         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
3574         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
3575         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
3576         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
3577         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
3578         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
3579         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
3580         [GCC_DEHR_BCR] = { 0x1300 },
3581         [GCC_RBCPR_BCR] = { 0x1380 },
3582         [GCC_MSS_RESTART] = { 0x1680 },
3583         [GCC_LPASS_RESTART] = { 0x16c0 },
3584         [GCC_WCSS_RESTART] = { 0x1700 },
3585         [GCC_VENUS_RESTART] = { 0x1740 },
3586         [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
3587         [GCC_SPSS_BCR] = { 0x1a80 },
3588         [GCC_PCIE_0_BCR] = { 0x1ac0 },
3589         [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
3590         [GCC_PCIE_1_BCR] = { 0x1b40 },
3591         [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
3592         [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
3593         [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
3594         [GCC_SATA_BCR] = { 0x1c40 },
3595         [GCC_CE3_BCR] = { 0x1d00 },
3596         [GCC_UFS_BCR] = { 0x1d40 },
3597         [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
3598 };
3599
3600 static const struct regmap_config gcc_apq8084_regmap_config = {
3601         .reg_bits       = 32,
3602         .reg_stride     = 4,
3603         .val_bits       = 32,
3604         .max_register   = 0x1fc0,
3605         .fast_io        = true,
3606 };
3607
3608 static const struct qcom_cc_desc gcc_apq8084_desc = {
3609         .config = &gcc_apq8084_regmap_config,
3610         .clks = gcc_apq8084_clocks,
3611         .num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
3612         .resets = gcc_apq8084_resets,
3613         .num_resets = ARRAY_SIZE(gcc_apq8084_resets),
3614         .gdscs = gcc_apq8084_gdscs,
3615         .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
3616 };
3617
3618 static const struct of_device_id gcc_apq8084_match_table[] = {
3619         { .compatible = "qcom,gcc-apq8084" },
3620         { }
3621 };
3622 MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
3623
3624 static int gcc_apq8084_probe(struct platform_device *pdev)
3625 {
3626         int ret;
3627         struct device *dev = &pdev->dev;
3628
3629         ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3630         if (ret)
3631                 return ret;
3632
3633         ret = qcom_cc_register_sleep_clk(dev);
3634         if (ret)
3635                 return ret;
3636
3637         return qcom_cc_probe(pdev, &gcc_apq8084_desc);
3638 }
3639
3640 static struct platform_driver gcc_apq8084_driver = {
3641         .probe          = gcc_apq8084_probe,
3642         .driver         = {
3643                 .name   = "gcc-apq8084",
3644                 .of_match_table = gcc_apq8084_match_table,
3645         },
3646 };
3647
3648 static int __init gcc_apq8084_init(void)
3649 {
3650         return platform_driver_register(&gcc_apq8084_driver);
3651 }
3652 core_initcall(gcc_apq8084_init);
3653
3654 static void __exit gcc_apq8084_exit(void)
3655 {
3656         platform_driver_unregister(&gcc_apq8084_driver);
3657 }
3658 module_exit(gcc_apq8084_exit);
3659
3660 MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
3661 MODULE_LICENSE("GPL v2");
3662 MODULE_ALIAS("platform:gcc-apq8084");