drivers/clk/qcom/apss-ipq-pll.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018, The Linux Foundation. All rights reserved.
   3 #include <linux/clk-provider.h>
   4 #include <linux/module.h>
   5 #include <linux/of_device.h>
   6 #include <linux/platform_device.h>
   7 #include <linux/regmap.h>
   8
   9 #include "clk-alpha-pll.h"
  10
  11 /*
  12  * Even though APSS PLL type is of existing one (like Huayra), its offsets
  13  * are different from the one mentioned in the clk-alpha-pll.c, since the
  14  * PLL is specific to APSS, so lets the define the same.
  15  */
  16 static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
  17         [CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
  18                 [PLL_OFF_L_VAL] = 0x08,
  19                 [PLL_OFF_ALPHA_VAL] = 0x10,
  20                 [PLL_OFF_USER_CTL] = 0x18,
  21                 [PLL_OFF_CONFIG_CTL] = 0x20,
  22                 [PLL_OFF_CONFIG_CTL_U] = 0x24,
  23                 [PLL_OFF_STATUS] = 0x28,
  24                 [PLL_OFF_TEST_CTL] = 0x30,
  25                 [PLL_OFF_TEST_CTL_U] = 0x34,
  26         },
  27         [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
  28                 [PLL_OFF_L_VAL] = 0x08,
  29                 [PLL_OFF_ALPHA_VAL] = 0x10,
  30                 [PLL_OFF_ALPHA_VAL_U] = 0x14,
  31                 [PLL_OFF_USER_CTL] = 0x18,
  32                 [PLL_OFF_USER_CTL_U] = 0x1c,
  33                 [PLL_OFF_CONFIG_CTL] = 0x20,
  34                 [PLL_OFF_STATUS] = 0x28,
  35                 [PLL_OFF_TEST_CTL] = 0x30,
  36                 [PLL_OFF_TEST_CTL_U] = 0x34,
  37         },
  38 };
  39
  40 static struct clk_alpha_pll ipq_pll_huayra = {
  41         .offset = 0x0,
  42         .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA],
  43         .flags = SUPPORTS_DYNAMIC_UPDATE,
  44         .clkr = {
  45                 .enable_reg = 0x0,
  46                 .enable_mask = BIT(0),
  47                 .hw.init = &(struct clk_init_data){
  48                         .name = "a53pll",
  49                         .parent_data = &(const struct clk_parent_data) {
  50                                 .fw_name = "xo",
  51                         },
  52                         .num_parents = 1,
  53                         .ops = &clk_alpha_pll_huayra_ops,
  54                 },
  55         },
  56 };
  57
  58 static struct clk_alpha_pll ipq_pll_stromer_plus = {
  59         .offset = 0x0,
  60         .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
  61         .flags = SUPPORTS_DYNAMIC_UPDATE,
  62         .clkr = {
  63                 .enable_reg = 0x0,
  64                 .enable_mask = BIT(0),
  65                 .hw.init = &(struct clk_init_data){
  66                         .name = "a53pll",
  67                         .parent_data = &(const struct clk_parent_data) {
  68                                 .fw_name = "xo",
  69                         },
  70                         .num_parents = 1,
  71                         .ops = &clk_alpha_pll_stromer_ops,
  72                 },
  73         },
  74 };
  75
  76 static const struct alpha_pll_config ipq5332_pll_config = {
  77         .l = 0x3e,
  78         .config_ctl_val = 0x4001075b,
  79         .config_ctl_hi_val = 0x304,
  80         .main_output_mask = BIT(0),
  81         .aux_output_mask = BIT(1),
  82         .early_output_mask = BIT(3),
  83         .alpha_en_mask = BIT(24),
  84         .status_val = 0x3,
  85         .status_mask = GENMASK(10, 8),
  86         .lock_det = BIT(2),
  87         .test_ctl_hi_val = 0x00400003,
  88 };
  89
  90 static const struct alpha_pll_config ipq6018_pll_config = {
  91         .l = 0x37,
  92         .config_ctl_val = 0x240d4828,
  93         .config_ctl_hi_val = 0x6,
  94         .early_output_mask = BIT(3),
  95         .aux2_output_mask = BIT(2),
  96         .aux_output_mask = BIT(1),
  97         .main_output_mask = BIT(0),
  98         .test_ctl_val = 0x1c0000C0,
  99         .test_ctl_hi_val = 0x4000,
 100 };
 101
 102 static const struct alpha_pll_config ipq8074_pll_config = {
 103         .l = 0x48,
 104         .config_ctl_val = 0x200d4828,
 105         .config_ctl_hi_val = 0x6,
 106         .early_output_mask = BIT(3),
 107         .aux2_output_mask = BIT(2),
 108         .aux_output_mask = BIT(1),
 109         .main_output_mask = BIT(0),
 110         .test_ctl_val = 0x1c000000,
 111         .test_ctl_hi_val = 0x4000,
 112 };
 113
 114 struct apss_pll_data {
 115         int pll_type;
 116         struct clk_alpha_pll *pll;
 117         const struct alpha_pll_config *pll_config;
 118 };
 119
 120 static struct apss_pll_data ipq5332_pll_data = {
 121         .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
 122         .pll = &ipq_pll_stromer_plus,
 123         .pll_config = &ipq5332_pll_config,
 124 };
 125
 126 static struct apss_pll_data ipq8074_pll_data = {
 127         .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
 128         .pll = &ipq_pll_huayra,
 129         .pll_config = &ipq8074_pll_config,
 130 };
 131
 132 static struct apss_pll_data ipq6018_pll_data = {
 133         .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
 134         .pll = &ipq_pll_huayra,
 135         .pll_config = &ipq6018_pll_config,
 136 };
 137
 138 static const struct regmap_config ipq_pll_regmap_config = {
 139         .reg_bits               = 32,
 140         .reg_stride             = 4,
 141         .val_bits               = 32,
 142         .max_register           = 0x40,
 143         .fast_io                = true,
 144 };
 145
 146 static int apss_ipq_pll_probe(struct platform_device *pdev)
 147 {
 148         const struct apss_pll_data *data;
 149         struct device *dev = &pdev->dev;
 150         struct regmap *regmap;
 151         void __iomem *base;
 152         int ret;
 153
 154         base = devm_platform_ioremap_resource(pdev, 0);
 155         if (IS_ERR(base))
 156                 return PTR_ERR(base);
 157
 158         regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);
 159         if (IS_ERR(regmap))
 160                 return PTR_ERR(regmap);
 161
 162         data = of_device_get_match_data(&pdev->dev);
 163         if (!data)
 164                 return -ENODEV;
 165
 166         if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
 167                 clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
 168         else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
 169                 clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
 170
 171         ret = devm_clk_register_regmap(dev, &data->pll->clkr);
 172         if (ret)
 173                 return ret;
 174
 175         return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
 176                                            &data->pll->clkr.hw);
 177 }
 178
 179 static const struct of_device_id apss_ipq_pll_match_table[] = {
 180         { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
 181         { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
 182         { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
 183         { }
 184 };
 185 MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
 186
 187 static struct platform_driver apss_ipq_pll_driver = {
 188         .probe = apss_ipq_pll_probe,
 189         .driver = {
 190                 .name = "qcom-ipq-apss-pll",
 191                 .of_match_table = apss_ipq_pll_match_table,
 192         },
 193 };
 194 module_platform_driver(apss_ipq_pll_driver);
 195
 196 MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
 197 MODULE_LICENSE("GPL v2");