drivers/i2c/busses/i2c-cadence.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * I2C bus driver for the Cadence I2C controller.
   4  *
   5  * Copyright (C) 2009 - 2014 Xilinx, Inc.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/i2c.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/pinctrl/consumer.h>
  19
  20 /* Register offsets for the I2C device. */
  21 #define CDNS_I2C_CR_OFFSET              0x00 /* Control Register, RW */
  22 #define CDNS_I2C_SR_OFFSET              0x04 /* Status Register, RO */
  23 #define CDNS_I2C_ADDR_OFFSET            0x08 /* I2C Address Register, RW */
  24 #define CDNS_I2C_DATA_OFFSET            0x0C /* I2C Data Register, RW */
  25 #define CDNS_I2C_ISR_OFFSET             0x10 /* IRQ Status Register, RW */
  26 #define CDNS_I2C_XFER_SIZE_OFFSET       0x14 /* Transfer Size Register, RW */
  27 #define CDNS_I2C_TIME_OUT_OFFSET        0x1C /* Time Out Register, RW */
  28 #define CDNS_I2C_IMR_OFFSET             0x20 /* IRQ Mask Register, RO */
  29 #define CDNS_I2C_IER_OFFSET             0x24 /* IRQ Enable Register, WO */
  30 #define CDNS_I2C_IDR_OFFSET             0x28 /* IRQ Disable Register, WO */
  31
  32 /* Control Register Bit mask definitions */
  33 #define CDNS_I2C_CR_HOLD                BIT(4) /* Hold Bus bit */
  34 #define CDNS_I2C_CR_ACK_EN              BIT(3)
  35 #define CDNS_I2C_CR_NEA                 BIT(2)
  36 #define CDNS_I2C_CR_MS                  BIT(1)
  37 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
  38 #define CDNS_I2C_CR_RW                  BIT(0)
  39 /* 1 = Auto init FIFO to zeroes */
  40 #define CDNS_I2C_CR_CLR_FIFO            BIT(6)
  41 #define CDNS_I2C_CR_DIVA_SHIFT          14
  42 #define CDNS_I2C_CR_DIVA_MASK           (3 << CDNS_I2C_CR_DIVA_SHIFT)
  43 #define CDNS_I2C_CR_DIVB_SHIFT          8
  44 #define CDNS_I2C_CR_DIVB_MASK           (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
  45
  46 #define CDNS_I2C_CR_MASTER_EN_MASK      (CDNS_I2C_CR_NEA | \
  47                                          CDNS_I2C_CR_ACK_EN | \
  48                                          CDNS_I2C_CR_MS)
  49
  50 #define CDNS_I2C_CR_SLAVE_EN_MASK       ~CDNS_I2C_CR_MASTER_EN_MASK
  51
  52 /* Status Register Bit mask definitions */
  53 #define CDNS_I2C_SR_BA          BIT(8)
  54 #define CDNS_I2C_SR_TXDV        BIT(6)
  55 #define CDNS_I2C_SR_RXDV        BIT(5)
  56 #define CDNS_I2C_SR_RXRW        BIT(3)
  57
  58 /*
  59  * I2C Address Register Bit mask definitions
  60  * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
  61  * bits. A write access to this register always initiates a transfer if the I2C
  62  * is in master mode.
  63  */
  64 #define CDNS_I2C_ADDR_MASK      0x000003FF /* I2C Address Mask */
  65
  66 /*
  67  * I2C Interrupt Registers Bit mask definitions
  68  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  69  * bit definitions.
  70  */
  71 #define CDNS_I2C_IXR_ARB_LOST           BIT(9)
  72 #define CDNS_I2C_IXR_RX_UNF             BIT(7)
  73 #define CDNS_I2C_IXR_TX_OVF             BIT(6)
  74 #define CDNS_I2C_IXR_RX_OVF             BIT(5)
  75 #define CDNS_I2C_IXR_SLV_RDY            BIT(4)
  76 #define CDNS_I2C_IXR_TO                 BIT(3)
  77 #define CDNS_I2C_IXR_NACK               BIT(2)
  78 #define CDNS_I2C_IXR_DATA               BIT(1)
  79 #define CDNS_I2C_IXR_COMP               BIT(0)
  80
  81 #define CDNS_I2C_IXR_ALL_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  82                                          CDNS_I2C_IXR_RX_UNF | \
  83                                          CDNS_I2C_IXR_TX_OVF | \
  84                                          CDNS_I2C_IXR_RX_OVF | \
  85                                          CDNS_I2C_IXR_SLV_RDY | \
  86                                          CDNS_I2C_IXR_TO | \
  87                                          CDNS_I2C_IXR_NACK | \
  88                                          CDNS_I2C_IXR_DATA | \
  89                                          CDNS_I2C_IXR_COMP)
  90
  91 #define CDNS_I2C_IXR_ERR_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  92                                          CDNS_I2C_IXR_RX_UNF | \
  93                                          CDNS_I2C_IXR_TX_OVF | \
  94                                          CDNS_I2C_IXR_RX_OVF | \
  95                                          CDNS_I2C_IXR_NACK)
  96
  97 #define CDNS_I2C_ENABLED_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  98                                          CDNS_I2C_IXR_RX_UNF | \
  99                                          CDNS_I2C_IXR_TX_OVF | \
 100                                          CDNS_I2C_IXR_RX_OVF | \
 101                                          CDNS_I2C_IXR_NACK | \
 102                                          CDNS_I2C_IXR_DATA | \
 103                                          CDNS_I2C_IXR_COMP)
 104
 105 #define CDNS_I2C_IXR_SLAVE_INTR_MASK    (CDNS_I2C_IXR_RX_UNF | \
 106                                          CDNS_I2C_IXR_TX_OVF | \
 107                                          CDNS_I2C_IXR_RX_OVF | \
 108                                          CDNS_I2C_IXR_TO | \
 109                                          CDNS_I2C_IXR_NACK | \
 110                                          CDNS_I2C_IXR_DATA | \
 111                                          CDNS_I2C_IXR_COMP)
 112
 113 #define CDNS_I2C_TIMEOUT                msecs_to_jiffies(1000)
 114 /* timeout for pm runtime autosuspend */
 115 #define CNDS_I2C_PM_TIMEOUT             1000    /* ms */
 116
 117 #define CDNS_I2C_FIFO_DEPTH             16
 118 /* FIFO depth at which the DATA interrupt occurs */
 119 #define CDNS_I2C_DATA_INTR_DEPTH        (CDNS_I2C_FIFO_DEPTH - 2)
 120 #define CDNS_I2C_MAX_TRANSFER_SIZE      255
 121 /* Transfer size in multiples of data interrupt depth */
 122 #define CDNS_I2C_TRANSFER_SIZE  (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
 123
 124 #define DRIVER_NAME             "cdns-i2c"
 125
 126 #define CDNS_I2C_DIVA_MAX       4
 127 #define CDNS_I2C_DIVB_MAX       64
 128
 129 #define CDNS_I2C_TIMEOUT_MAX    0xFF
 130
 131 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
 132 #define CDNS_I2C_POLL_US        100000
 133 #define CDNS_I2C_TIMEOUT_US     500000
 134
 135 #define cdns_i2c_readreg(offset)       readl_relaxed(id->membase + offset)
 136 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
 137
 138 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 139 /**
 140  * enum cdns_i2c_mode - I2C Controller current operating mode
 141  *
 142  * @CDNS_I2C_MODE_SLAVE:       I2C controller operating in slave mode
 143  * @CDNS_I2C_MODE_MASTER:      I2C Controller operating in master mode
 144  */
 145 enum cdns_i2c_mode {
 146         CDNS_I2C_MODE_SLAVE,
 147         CDNS_I2C_MODE_MASTER,
 148 };
 149
 150 /**
 151  * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode
 152  *
 153  * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
 154  * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
 155  * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
 156  */
 157 enum cdns_i2c_slave_state {
 158         CDNS_I2C_SLAVE_STATE_IDLE,
 159         CDNS_I2C_SLAVE_STATE_SEND,
 160         CDNS_I2C_SLAVE_STATE_RECV,
 161 };
 162 #endif
 163
 164 /**
 165  * struct cdns_i2c - I2C device private data structure
 166  *
 167  * @dev:                Pointer to device structure
 168  * @membase:            Base address of the I2C device
 169  * @adap:               I2C adapter instance
 170  * @p_msg:              Message pointer
 171  * @err_status:         Error status in Interrupt Status Register
 172  * @xfer_done:          Transfer complete status
 173  * @p_send_buf:         Pointer to transmit buffer
 174  * @p_recv_buf:         Pointer to receive buffer
 175  * @send_count:         Number of bytes still expected to send
 176  * @recv_count:         Number of bytes still expected to receive
 177  * @curr_recv_count:    Number of bytes to be received in current transfer
 178  * @irq:                IRQ number
 179  * @input_clk:          Input clock to I2C controller
 180  * @i2c_clk:            Maximum I2C clock speed
 181  * @bus_hold_flag:      Flag used in repeated start for clearing HOLD bit
 182  * @clk:                Pointer to struct clk
 183  * @clk_rate_change_nb: Notifier block for clock rate changes
 184  * @quirks:             flag for broken hold bit usage in r1p10
 185  * @ctrl_reg:           Cached value of the control register.
 186  * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
 187  * @slave:              Registered slave instance.
 188  * @dev_mode:           I2C operating role(master/slave).
 189  * @slave_state:        I2C Slave state(idle/read/write).
 190  */
 191 struct cdns_i2c {
 192         struct device           *dev;
 193         void __iomem *membase;
 194         struct i2c_adapter adap;
 195         struct i2c_msg *p_msg;
 196         int err_status;
 197         struct completion xfer_done;
 198         unsigned char *p_send_buf;
 199         unsigned char *p_recv_buf;
 200         unsigned int send_count;
 201         unsigned int recv_count;
 202         unsigned int curr_recv_count;
 203         int irq;
 204         unsigned long input_clk;
 205         unsigned int i2c_clk;
 206         unsigned int bus_hold_flag;
 207         struct clk *clk;
 208         struct notifier_block clk_rate_change_nb;
 209         u32 quirks;
 210         u32 ctrl_reg;
 211         struct i2c_bus_recovery_info rinfo;
 212 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 213         u16 ctrl_reg_diva_divb;
 214         struct i2c_client *slave;
 215         enum cdns_i2c_mode dev_mode;
 216         enum cdns_i2c_slave_state slave_state;
 217 #endif
 218 };
 219
 220 struct cdns_platform_data {
 221         u32 quirks;
 222 };
 223
 224 #define to_cdns_i2c(_nb)        container_of(_nb, struct cdns_i2c, \
 225                                              clk_rate_change_nb)
 226
 227 /**
 228  * cdns_i2c_clear_bus_hold - Clear bus hold bit
 229  * @id: Pointer to driver data struct
 230  *
 231  * Helper to clear the controller's bus hold bit.
 232  */
 233 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
 234 {
 235         u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 236         if (reg & CDNS_I2C_CR_HOLD)
 237                 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
 238 }
 239
 240 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
 241 {
 242         return (hold_wrkaround &&
 243                 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
 244 }
 245
 246 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 247 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
 248 {
 249         /* Disable all interrupts */
 250         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
 251
 252         /* Clear FIFO and transfer size */
 253         cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
 254
 255         /* Update device mode and state */
 256         id->dev_mode = mode;
 257         id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
 258
 259         switch (mode) {
 260         case CDNS_I2C_MODE_MASTER:
 261                 /* Enable i2c master */
 262                 cdns_i2c_writereg(id->ctrl_reg_diva_divb |
 263                                   CDNS_I2C_CR_MASTER_EN_MASK,
 264                                   CDNS_I2C_CR_OFFSET);
 265                 /*
 266                  * This delay is needed to give the IP some time to switch to
 267                  * the master mode. With lower values(like 110 us) i2cdetect
 268                  * will not detect any slave and without this delay, the IP will
 269                  * trigger a timeout interrupt.
 270                  */
 271                 usleep_range(115, 125);
 272                 break;
 273         case CDNS_I2C_MODE_SLAVE:
 274                 /* Enable i2c slave */
 275                 cdns_i2c_writereg(id->ctrl_reg_diva_divb &
 276                                   CDNS_I2C_CR_SLAVE_EN_MASK,
 277                                   CDNS_I2C_CR_OFFSET);
 278
 279                 /* Setting slave address */
 280                 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
 281                                   CDNS_I2C_ADDR_OFFSET);
 282
 283                 /* Enable slave send/receive interrupts */
 284                 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
 285                                   CDNS_I2C_IER_OFFSET);
 286                 break;
 287         }
 288 }
 289
 290 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
 291 {
 292         u8 bytes;
 293         unsigned char data;
 294
 295         /* Prepare backend for data reception */
 296         if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
 297                 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
 298                 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
 299         }
 300
 301         /* Fetch number of bytes to receive */
 302         bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 303
 304         /* Read data and send to backend */
 305         while (bytes--) {
 306                 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
 307                 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
 308         }
 309 }
 310
 311 static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
 312 {
 313         u8 data;
 314
 315         /* Prepare backend for data transmission */
 316         if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
 317                 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
 318                 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
 319         } else {
 320                 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
 321         }
 322
 323         /* Send data over bus */
 324         cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
 325 }
 326
 327 /**
 328  * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
 329  * @ptr:       Pointer to I2C device private data
 330  *
 331  * This function handles the data interrupt and transfer complete interrupt of
 332  * the I2C device in slave role.
 333  *
 334  * Return: IRQ_HANDLED always
 335  */
 336 static irqreturn_t cdns_i2c_slave_isr(void *ptr)
 337 {
 338         struct cdns_i2c *id = ptr;
 339         unsigned int isr_status, i2c_status;
 340
 341         /* Fetch the interrupt status */
 342         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 343         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 344
 345         /* Ignore masked interrupts */
 346         isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
 347
 348         /* Fetch transfer mode (send/receive) */
 349         i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
 350
 351         /* Handle data send/receive */
 352         if (i2c_status & CDNS_I2C_SR_RXRW) {
 353                 /* Send data to master */
 354                 if (isr_status & CDNS_I2C_IXR_DATA)
 355                         cdns_i2c_slave_send_data(id);
 356
 357                 if (isr_status & CDNS_I2C_IXR_COMP) {
 358                         id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
 359                         i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
 360                 }
 361         } else {
 362                 /* Receive data from master */
 363                 if (isr_status & CDNS_I2C_IXR_DATA)
 364                         cdns_i2c_slave_rcv_data(id);
 365
 366                 if (isr_status & CDNS_I2C_IXR_COMP) {
 367                         cdns_i2c_slave_rcv_data(id);
 368                         id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
 369                         i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
 370                 }
 371         }
 372
 373         /* Master indicated xfer stop or fifo underflow/overflow */
 374         if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
 375                           CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
 376                 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
 377                 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
 378                 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
 379         }
 380
 381         return IRQ_HANDLED;
 382 }
 383 #endif
 384
 385 /**
 386  * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
 387  * @ptr:       Pointer to I2C device private data
 388  *
 389  * This function handles the data interrupt, transfer complete interrupt and
 390  * the error interrupts of the I2C device in master role.
 391  *
 392  * Return: IRQ_HANDLED always
 393  */
 394 static irqreturn_t cdns_i2c_master_isr(void *ptr)
 395 {
 396         unsigned int isr_status, avail_bytes;
 397         unsigned int bytes_to_send;
 398         bool updatetx;
 399         struct cdns_i2c *id = ptr;
 400         /* Signal completion only after everything is updated */
 401         int done_flag = 0;
 402         irqreturn_t status = IRQ_NONE;
 403
 404         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 405         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 406         id->err_status = 0;
 407
 408         /* Handling nack and arbitration lost interrupt */
 409         if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
 410                 done_flag = 1;
 411                 status = IRQ_HANDLED;
 412         }
 413
 414         /*
 415          * Check if transfer size register needs to be updated again for a
 416          * large data receive operation.
 417          */
 418         updatetx = id->recv_count > id->curr_recv_count;
 419
 420         /* When receiving, handle data interrupt and completion interrupt */
 421         if (id->p_recv_buf &&
 422             ((isr_status & CDNS_I2C_IXR_COMP) ||
 423              (isr_status & CDNS_I2C_IXR_DATA))) {
 424                 /* Read data if receive data valid is set */
 425                 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
 426                        CDNS_I2C_SR_RXDV) {
 427                         if (id->recv_count > 0) {
 428                                 *(id->p_recv_buf)++ =
 429                                         cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
 430                                 id->recv_count--;
 431                                 id->curr_recv_count--;
 432
 433                                 /*
 434                                  * Clear hold bit that was set for FIFO control
 435                                  * if RX data left is less than or equal to
 436                                  * FIFO DEPTH unless repeated start is selected
 437                                  */
 438                                 if (id->recv_count <= CDNS_I2C_FIFO_DEPTH &&
 439                                     !id->bus_hold_flag)
 440                                         cdns_i2c_clear_bus_hold(id);
 441
 442                         } else {
 443                                 dev_err(id->adap.dev.parent,
 444                                         "xfer_size reg rollover. xfer aborted!\n");
 445                                 id->err_status |= CDNS_I2C_IXR_TO;
 446                                 break;
 447                         }
 448
 449                         if (cdns_is_holdquirk(id, updatetx))
 450                                 break;
 451                 }
 452
 453                 /*
 454                  * The controller sends NACK to the slave when transfer size
 455                  * register reaches zero without considering the HOLD bit.
 456                  * This workaround is implemented for large data transfers to
 457                  * maintain transfer size non-zero while performing a large
 458                  * receive operation.
 459                  */
 460                 if (cdns_is_holdquirk(id, updatetx)) {
 461                         /* wait while fifo is full */
 462                         while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
 463                                (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 464                                 ;
 465
 466                         /*
 467                          * Check number of bytes to be received against maximum
 468                          * transfer size and update register accordingly.
 469                          */
 470                         if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
 471                             CDNS_I2C_TRANSFER_SIZE) {
 472                                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 473                                                   CDNS_I2C_XFER_SIZE_OFFSET);
 474                                 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 475                                                       CDNS_I2C_FIFO_DEPTH;
 476                         } else {
 477                                 cdns_i2c_writereg(id->recv_count -
 478                                                   CDNS_I2C_FIFO_DEPTH,
 479                                                   CDNS_I2C_XFER_SIZE_OFFSET);
 480                                 id->curr_recv_count = id->recv_count;
 481                         }
 482                 }
 483
 484                 /* Clear hold (if not repeated start) and signal completion */
 485                 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
 486                         if (!id->bus_hold_flag)
 487                                 cdns_i2c_clear_bus_hold(id);
 488                         done_flag = 1;
 489                 }
 490
 491                 status = IRQ_HANDLED;
 492         }
 493
 494         /* When sending, handle transfer complete interrupt */
 495         if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
 496                 /*
 497                  * If there is more data to be sent, calculate the
 498                  * space available in FIFO and fill with that many bytes.
 499                  */
 500                 if (id->send_count) {
 501                         avail_bytes = CDNS_I2C_FIFO_DEPTH -
 502                             cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 503                         if (id->send_count > avail_bytes)
 504                                 bytes_to_send = avail_bytes;
 505                         else
 506                                 bytes_to_send = id->send_count;
 507
 508                         while (bytes_to_send--) {
 509                                 cdns_i2c_writereg(
 510                                         (*(id->p_send_buf)++),
 511                                          CDNS_I2C_DATA_OFFSET);
 512                                 id->send_count--;
 513                         }
 514                 } else {
 515                         /*
 516                          * Signal the completion of transaction and
 517                          * clear the hold bus bit if there are no
 518                          * further messages to be processed.
 519                          */
 520                         done_flag = 1;
 521                 }
 522                 if (!id->send_count && !id->bus_hold_flag)
 523                         cdns_i2c_clear_bus_hold(id);
 524
 525                 status = IRQ_HANDLED;
 526         }
 527
 528         /* Update the status for errors */
 529         id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
 530         if (id->err_status)
 531                 status = IRQ_HANDLED;
 532
 533         if (done_flag)
 534                 complete(&id->xfer_done);
 535
 536         return status;
 537 }
 538
 539 /**
 540  * cdns_i2c_isr - Interrupt handler for the I2C device
 541  * @irq:        irq number for the I2C device
 542  * @ptr:        void pointer to cdns_i2c structure
 543  *
 544  * This function passes the control to slave/master based on current role of
 545  * i2c controller.
 546  *
 547  * Return: IRQ_HANDLED always
 548  */
 549 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
 550 {
 551 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 552         struct cdns_i2c *id = ptr;
 553
 554         if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
 555                 return cdns_i2c_slave_isr(ptr);
 556 #endif
 557         return cdns_i2c_master_isr(ptr);
 558 }
 559
 560 /**
 561  * cdns_i2c_mrecv - Prepare and start a master receive operation
 562  * @id:         pointer to the i2c device structure
 563  */
 564 static void cdns_i2c_mrecv(struct cdns_i2c *id)
 565 {
 566         unsigned int ctrl_reg;
 567         unsigned int isr_status;
 568         unsigned long flags;
 569         bool hold_clear = false;
 570         bool irq_save = false;
 571
 572         u32 addr;
 573
 574         id->p_recv_buf = id->p_msg->buf;
 575         id->recv_count = id->p_msg->len;
 576
 577         /* Put the controller in master receive mode and clear the FIFO */
 578         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 579         ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
 580
 581         /*
 582          * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length
 583          * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if
 584          * PEC is enabled, otherwise 1.
 585          */
 586         if (id->p_msg->flags & I2C_M_RECV_LEN)
 587                 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len;
 588
 589         id->curr_recv_count = id->recv_count;
 590
 591         /*
 592          * Check for the message size against FIFO depth and set the
 593          * 'hold bus' bit if it is greater than FIFO depth.
 594          */
 595         if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
 596                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 597
 598         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 599
 600         /* Clear the interrupts in interrupt status register */
 601         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 602         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 603
 604         /*
 605          * The no. of bytes to receive is checked against the limit of
 606          * max transfer size. Set transfer size register with no of bytes
 607          * receive if it is less than transfer size and transfer size if
 608          * it is more. Enable the interrupts.
 609          */
 610         if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
 611                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 612                                   CDNS_I2C_XFER_SIZE_OFFSET);
 613                 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 614         } else {
 615                 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
 616         }
 617
 618         /* Determine hold_clear based on number of bytes to receive and hold flag */
 619         if (!id->bus_hold_flag &&
 620             ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
 621             (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) {
 622                 if (cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & CDNS_I2C_CR_HOLD) {
 623                         hold_clear = true;
 624                         if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT)
 625                                 irq_save = true;
 626                 }
 627         }
 628
 629         addr = id->p_msg->addr;
 630         addr &= CDNS_I2C_ADDR_MASK;
 631
 632         if (hold_clear) {
 633                 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & ~CDNS_I2C_CR_HOLD;
 634                 /*
 635                  * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
 636                  * register reaches '0'. This is an IP bug which causes transfer size
 637                  * register overflow to 0xFF. To satisfy this timing requirement,
 638                  * disable the interrupts on current processor core between register
 639                  * writes to slave address register and control register.
 640                  */
 641                 if (irq_save)
 642                         local_irq_save(flags);
 643
 644                 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET);
 645                 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 646                 /* Read it back to avoid bufferring and make sure write happens */
 647                 cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 648
 649                 if (irq_save)
 650                         local_irq_restore(flags);
 651         } else {
 652                 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET);
 653         }
 654
 655         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 656 }
 657
 658 /**
 659  * cdns_i2c_msend - Prepare and start a master send operation
 660  * @id:         pointer to the i2c device
 661  */
 662 static void cdns_i2c_msend(struct cdns_i2c *id)
 663 {
 664         unsigned int avail_bytes;
 665         unsigned int bytes_to_send;
 666         unsigned int ctrl_reg;
 667         unsigned int isr_status;
 668
 669         id->p_recv_buf = NULL;
 670         id->p_send_buf = id->p_msg->buf;
 671         id->send_count = id->p_msg->len;
 672
 673         /* Set the controller in Master transmit mode and clear the FIFO. */
 674         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 675         ctrl_reg &= ~CDNS_I2C_CR_RW;
 676         ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
 677
 678         /*
 679          * Check for the message size against FIFO depth and set the
 680          * 'hold bus' bit if it is greater than FIFO depth.
 681          */
 682         if (id->send_count > CDNS_I2C_FIFO_DEPTH)
 683                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 684         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 685
 686         /* Clear the interrupts in interrupt status register. */
 687         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 688         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 689
 690         /*
 691          * Calculate the space available in FIFO. Check the message length
 692          * against the space available, and fill the FIFO accordingly.
 693          * Enable the interrupts.
 694          */
 695         avail_bytes = CDNS_I2C_FIFO_DEPTH -
 696                                 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 697
 698         if (id->send_count > avail_bytes)
 699                 bytes_to_send = avail_bytes;
 700         else
 701                 bytes_to_send = id->send_count;
 702
 703         while (bytes_to_send--) {
 704                 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
 705                 id->send_count--;
 706         }
 707
 708         /*
 709          * Clear the bus hold flag if there is no more data
 710          * and if it is the last message.
 711          */
 712         if (!id->bus_hold_flag && !id->send_count)
 713                 cdns_i2c_clear_bus_hold(id);
 714         /* Set the slave address in address register - triggers operation. */
 715         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 716                                                 CDNS_I2C_ADDR_OFFSET);
 717
 718         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 719 }
 720
 721 /**
 722  * cdns_i2c_master_reset - Reset the interface
 723  * @adap:       pointer to the i2c adapter driver instance
 724  *
 725  * This function cleanup the fifos, clear the hold bit and status
 726  * and disable the interrupts.
 727  */
 728 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
 729 {
 730         struct cdns_i2c *id = adap->algo_data;
 731         u32 regval;
 732
 733         /* Disable the interrupts */
 734         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
 735         /* Clear the hold bit and fifos */
 736         regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 737         regval &= ~CDNS_I2C_CR_HOLD;
 738         regval |= CDNS_I2C_CR_CLR_FIFO;
 739         cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
 740         /* Update the transfercount register to zero */
 741         cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
 742         /* Clear the interrupt status register */
 743         regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 744         cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
 745         /* Clear the status register */
 746         regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
 747         cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
 748 }
 749
 750 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
 751                 struct i2c_adapter *adap)
 752 {
 753         unsigned long time_left, msg_timeout;
 754         u32 reg;
 755
 756         id->p_msg = msg;
 757         id->err_status = 0;
 758         reinit_completion(&id->xfer_done);
 759
 760         /* Check for the TEN Bit mode on each msg */
 761         reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 762         if (msg->flags & I2C_M_TEN) {
 763                 if (reg & CDNS_I2C_CR_NEA)
 764                         cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
 765                                         CDNS_I2C_CR_OFFSET);
 766         } else {
 767                 if (!(reg & CDNS_I2C_CR_NEA))
 768                         cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
 769                                         CDNS_I2C_CR_OFFSET);
 770         }
 771
 772         /* Check for the R/W flag on each msg */
 773         if (msg->flags & I2C_M_RD)
 774                 cdns_i2c_mrecv(id);
 775         else
 776                 cdns_i2c_msend(id);
 777
 778         /* Minimal time to execute this message */
 779         msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk);
 780         /* Plus some wiggle room */
 781         msg_timeout += msecs_to_jiffies(500);
 782
 783         if (msg_timeout < adap->timeout)
 784                 msg_timeout = adap->timeout;
 785
 786         /* Wait for the signal of completion */
 787         time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout);
 788         if (time_left == 0) {
 789                 cdns_i2c_master_reset(adap);
 790                 dev_err(id->adap.dev.parent,
 791                                 "timeout waiting on completion\n");
 792                 return -ETIMEDOUT;
 793         }
 794
 795         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
 796                           CDNS_I2C_IDR_OFFSET);
 797
 798         /* If it is bus arbitration error, try again */
 799         if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
 800                 return -EAGAIN;
 801
 802         if (msg->flags & I2C_M_RECV_LEN)
 803                 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
 804
 805         return 0;
 806 }
 807
 808 /**
 809  * cdns_i2c_master_xfer - The main i2c transfer function
 810  * @adap:       pointer to the i2c adapter driver instance
 811  * @msgs:       pointer to the i2c message structure
 812  * @num:        the number of messages to transfer
 813  *
 814  * Initiates the send/recv activity based on the transfer message received.
 815  *
 816  * Return: number of msgs processed on success, negative error otherwise
 817  */
 818 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 819                                 int num)
 820 {
 821         int ret, count;
 822         u32 reg;
 823         struct cdns_i2c *id = adap->algo_data;
 824         bool hold_quirk;
 825 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 826         bool change_role = false;
 827 #endif
 828
 829         ret = pm_runtime_resume_and_get(id->dev);
 830         if (ret < 0)
 831                 return ret;
 832
 833 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 834         /* Check i2c operating mode and switch if possible */
 835         if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
 836                 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE)
 837                         return -EAGAIN;
 838
 839                 /* Set mode to master */
 840                 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
 841
 842                 /* Mark flag to change role once xfer is completed */
 843                 change_role = true;
 844         }
 845 #endif
 846
 847         /* Check if the bus is free */
 848
 849         ret = readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET,
 850                                          reg,
 851                                          !(reg & CDNS_I2C_SR_BA),
 852                                          CDNS_I2C_POLL_US, CDNS_I2C_TIMEOUT_US);
 853         if (ret) {
 854                 ret = -EAGAIN;
 855                 if (id->adap.bus_recovery_info)
 856                         i2c_recover_bus(adap);
 857                 goto out;
 858         }
 859
 860         hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 861         /*
 862          * Set the flag to one when multiple messages are to be
 863          * processed with a repeated start.
 864          */
 865         if (num > 1) {
 866                 /*
 867                  * This controller does not give completion interrupt after a
 868                  * master receive message if HOLD bit is set (repeated start),
 869                  * resulting in SW timeout. Hence, if a receive message is
 870                  * followed by any other message, an error is returned
 871                  * indicating that this sequence is not supported.
 872                  */
 873                 for (count = 0; (count < num - 1 && hold_quirk); count++) {
 874                         if (msgs[count].flags & I2C_M_RD) {
 875                                 dev_warn(adap->dev.parent,
 876                                          "Can't do repeated start after a receive message\n");
 877                                 ret = -EOPNOTSUPP;
 878                                 goto out;
 879                         }
 880                 }
 881                 id->bus_hold_flag = 1;
 882                 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 883                 reg |= CDNS_I2C_CR_HOLD;
 884                 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
 885         } else {
 886                 id->bus_hold_flag = 0;
 887         }
 888
 889         /* Process the msg one by one */
 890         for (count = 0; count < num; count++, msgs++) {
 891                 if (count == (num - 1))
 892                         id->bus_hold_flag = 0;
 893
 894                 ret = cdns_i2c_process_msg(id, msgs, adap);
 895                 if (ret)
 896                         goto out;
 897
 898                 /* Report the other error interrupts to application */
 899                 if (id->err_status) {
 900                         cdns_i2c_master_reset(adap);
 901
 902                         if (id->err_status & CDNS_I2C_IXR_NACK) {
 903                                 ret = -ENXIO;
 904                                 goto out;
 905                         }
 906                         ret = -EIO;
 907                         goto out;
 908                 }
 909         }
 910
 911         ret = num;
 912
 913 out:
 914
 915 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 916         /* Switch i2c mode to slave */
 917         if (change_role)
 918                 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
 919 #endif
 920
 921         pm_runtime_mark_last_busy(id->dev);
 922         pm_runtime_put_autosuspend(id->dev);
 923         return ret;
 924 }
 925
 926 /**
 927  * cdns_i2c_func - Returns the supported features of the I2C driver
 928  * @adap:       pointer to the i2c adapter structure
 929  *
 930  * Return: 32 bit value, each bit corresponding to a feature
 931  */
 932 static u32 cdns_i2c_func(struct i2c_adapter *adap)
 933 {
 934         u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
 935                         (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 936                         I2C_FUNC_SMBUS_BLOCK_DATA;
 937
 938 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 939         func |= I2C_FUNC_SLAVE;
 940 #endif
 941
 942         return func;
 943 }
 944
 945 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 946 static int cdns_reg_slave(struct i2c_client *slave)
 947 {
 948         int ret;
 949         struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
 950                                                                         adap);
 951
 952         if (id->slave)
 953                 return -EBUSY;
 954
 955         if (slave->flags & I2C_CLIENT_TEN)
 956                 return -EAFNOSUPPORT;
 957
 958         ret = pm_runtime_resume_and_get(id->dev);
 959         if (ret < 0)
 960                 return ret;
 961
 962         /* Store slave information */
 963         id->slave = slave;
 964
 965         /* Enable I2C slave */
 966         cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
 967
 968         return 0;
 969 }
 970
 971 static int cdns_unreg_slave(struct i2c_client *slave)
 972 {
 973         struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
 974                                                                         adap);
 975
 976         pm_runtime_put(id->dev);
 977
 978         /* Remove slave information */
 979         id->slave = NULL;
 980
 981         /* Enable I2C master */
 982         cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
 983
 984         return 0;
 985 }
 986 #endif
 987
 988 static const struct i2c_algorithm cdns_i2c_algo = {
 989         .master_xfer    = cdns_i2c_master_xfer,
 990         .functionality  = cdns_i2c_func,
 991 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 992         .reg_slave      = cdns_reg_slave,
 993         .unreg_slave    = cdns_unreg_slave,
 994 #endif
 995 };
 996
 997 /**
 998  * cdns_i2c_calc_divs - Calculate clock dividers
 999  * @f:          I2C clock frequency
1000  * @input_clk:  Input clock frequency
1001  * @a:          First divider (return value)
1002  * @b:          Second divider (return value)
1003  *
1004  * f is used as input and output variable. As input it is used as target I2C
1005  * frequency. On function exit f holds the actually resulting I2C frequency.
1006  *
1007  * Return: 0 on success, negative errno otherwise.
1008  */
1009 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
1010                 unsigned int *a, unsigned int *b)
1011 {
1012         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
1013         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
1014         unsigned int last_error, current_error;
1015
1016         /* calculate (divisor_a+1) x (divisor_b+1) */
1017         temp = input_clk / (22 * fscl);
1018
1019         /*
1020          * If the calculated value is negative or 0, the fscl input is out of
1021          * range. Return error.
1022          */
1023         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
1024                 return -EINVAL;
1025
1026         last_error = -1;
1027         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
1028                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
1029
1030                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
1031                         continue;
1032                 div_b--;
1033
1034                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
1035
1036                 if (actual_fscl > fscl)
1037                         continue;
1038
1039                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
1040                                                         (fscl - actual_fscl));
1041
1042                 if (last_error > current_error) {
1043                         calc_div_a = div_a;
1044                         calc_div_b = div_b;
1045                         best_fscl = actual_fscl;
1046                         last_error = current_error;
1047                 }
1048         }
1049
1050         *a = calc_div_a;
1051         *b = calc_div_b;
1052         *f = best_fscl;
1053
1054         return 0;
1055 }
1056
1057 /**
1058  * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
1059  * @clk_in:     I2C clock input frequency in Hz
1060  * @id:         Pointer to the I2C device structure
1061  *
1062  * The device must be idle rather than busy transferring data before setting
1063  * these device options.
1064  * The data rate is set by values in the control register.
1065  * The formula for determining the correct register values is
1066  *      Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
1067  * See the hardware data sheet for a full explanation of setting the serial
1068  * clock rate. The clock can not be faster than the input clock divide by 22.
1069  * The two most common clock rates are 100KHz and 400KHz.
1070  *
1071  * Return: 0 on success, negative error otherwise
1072  */
1073 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
1074 {
1075         unsigned int div_a, div_b;
1076         unsigned int ctrl_reg;
1077         int ret = 0;
1078         unsigned long fscl = id->i2c_clk;
1079
1080         ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
1081         if (ret)
1082                 return ret;
1083
1084         ctrl_reg = id->ctrl_reg;
1085         ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
1086         ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1087                         (div_b << CDNS_I2C_CR_DIVB_SHIFT));
1088         id->ctrl_reg = ctrl_reg;
1089         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1090 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1091         id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1092                                  CDNS_I2C_CR_DIVB_MASK);
1093 #endif
1094         return 0;
1095 }
1096
1097 /**
1098  * cdns_i2c_clk_notifier_cb - Clock rate change callback
1099  * @nb:         Pointer to notifier block
1100  * @event:      Notification reason
1101  * @data:       Pointer to notification data object
1102  *
1103  * This function is called when the cdns_i2c input clock frequency changes.
1104  * The callback checks whether a valid bus frequency can be generated after the
1105  * change. If so, the change is acknowledged, otherwise the change is aborted.
1106  * New dividers are written to the HW in the pre- or post change notification
1107  * depending on the scaling direction.
1108  *
1109  * Return:      NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
1110  *              to acknowledge the change, NOTIFY_DONE if the notification is
1111  *              considered irrelevant.
1112  */
1113 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
1114                 event, void *data)
1115 {
1116         struct clk_notifier_data *ndata = data;
1117         struct cdns_i2c *id = to_cdns_i2c(nb);
1118
1119         if (pm_runtime_suspended(id->dev))
1120                 return NOTIFY_OK;
1121
1122         switch (event) {
1123         case PRE_RATE_CHANGE:
1124         {
1125                 unsigned long input_clk = ndata->new_rate;
1126                 unsigned long fscl = id->i2c_clk;
1127                 unsigned int div_a, div_b;
1128                 int ret;
1129
1130                 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
1131                 if (ret) {
1132                         dev_warn(id->adap.dev.parent,
1133                                         "clock rate change rejected\n");
1134                         return NOTIFY_STOP;
1135                 }
1136
1137                 /* scale up */
1138                 if (ndata->new_rate > ndata->old_rate)
1139                         cdns_i2c_setclk(ndata->new_rate, id);
1140
1141                 return NOTIFY_OK;
1142         }
1143         case POST_RATE_CHANGE:
1144                 id->input_clk = ndata->new_rate;
1145                 /* scale down */
1146                 if (ndata->new_rate < ndata->old_rate)
1147                         cdns_i2c_setclk(ndata->new_rate, id);
1148                 return NOTIFY_OK;
1149         case ABORT_RATE_CHANGE:
1150                 /* scale up */
1151                 if (ndata->new_rate > ndata->old_rate)
1152                         cdns_i2c_setclk(ndata->old_rate, id);
1153                 return NOTIFY_OK;
1154         default:
1155                 return NOTIFY_DONE;
1156         }
1157 }
1158
1159 /**
1160  * cdns_i2c_runtime_suspend -  Runtime suspend method for the driver
1161  * @dev:        Address of the platform_device structure
1162  *
1163  * Put the driver into low power mode.
1164  *
1165  * Return: 0 always
1166  */
1167 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
1168 {
1169         struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1170
1171         clk_disable(xi2c->clk);
1172
1173         return 0;
1174 }
1175
1176 /**
1177  * cdns_i2c_init -  Controller initialisation
1178  * @id:         Device private data structure
1179  *
1180  * Initialise the i2c controller.
1181  *
1182  */
1183 static void cdns_i2c_init(struct cdns_i2c *id)
1184 {
1185         cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);
1186         /*
1187          * Cadence I2C controller has a bug wherein it generates
1188          * invalid read transaction after HW timeout in master receiver mode.
1189          * HW timeout is not used by this driver and the interrupt is disabled.
1190          * But the feature itself cannot be disabled. Hence maximum value
1191          * is written to this register to reduce the chances of error.
1192          */
1193         cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
1194 }
1195
1196 /**
1197  * cdns_i2c_runtime_resume - Runtime resume
1198  * @dev:        Address of the platform_device structure
1199  *
1200  * Runtime resume callback.
1201  *
1202  * Return: 0 on success and error value on error
1203  */
1204 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
1205 {
1206         struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1207         int ret;
1208
1209         ret = clk_enable(xi2c->clk);
1210         if (ret) {
1211                 dev_err(dev, "Cannot enable clock.\n");
1212                 return ret;
1213         }
1214         cdns_i2c_init(xi2c);
1215
1216         return 0;
1217 }
1218
1219 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
1220         SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
1221                            cdns_i2c_runtime_resume, NULL)
1222 };
1223
1224 static const struct cdns_platform_data r1p10_i2c_def = {
1225         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
1226 };
1227
1228 static const struct of_device_id cdns_i2c_of_match[] = {
1229         { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
1230         { .compatible = "cdns,i2c-r1p14",},
1231         { /* end of table */ }
1232 };
1233 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
1234
1235 /**
1236  * cdns_i2c_probe - Platform registration call
1237  * @pdev:       Handle to the platform device structure
1238  *
1239  * This function does all the memory allocation and registration for the i2c
1240  * device. User can modify the address mode to 10 bit address mode using the
1241  * ioctl call with option I2C_TENBIT.
1242  *
1243  * Return: 0 on success, negative error otherwise
1244  */
1245 static int cdns_i2c_probe(struct platform_device *pdev)
1246 {
1247         struct resource *r_mem;
1248         struct cdns_i2c *id;
1249         int ret;
1250         const struct of_device_id *match;
1251
1252         id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
1253         if (!id)
1254                 return -ENOMEM;
1255
1256         id->dev = &pdev->dev;
1257         platform_set_drvdata(pdev, id);
1258
1259         match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
1260         if (match && match->data) {
1261                 const struct cdns_platform_data *data = match->data;
1262                 id->quirks = data->quirks;
1263         }
1264
1265         id->rinfo.pinctrl = devm_pinctrl_get(&pdev->dev);
1266         if (IS_ERR(id->rinfo.pinctrl)) {
1267                 int err = PTR_ERR(id->rinfo.pinctrl);
1268
1269                 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1270                 if (err != -ENODEV)
1271                         return err;
1272         } else {
1273                 id->adap.bus_recovery_info = &id->rinfo;
1274         }
1275
1276         id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
1277         if (IS_ERR(id->membase))
1278                 return PTR_ERR(id->membase);
1279
1280         ret = platform_get_irq(pdev, 0);
1281         if (ret < 0)
1282                 return ret;
1283         id->irq = ret;
1284
1285         id->adap.owner = THIS_MODULE;
1286         id->adap.dev.of_node = pdev->dev.of_node;
1287         id->adap.algo = &cdns_i2c_algo;
1288         id->adap.timeout = CDNS_I2C_TIMEOUT;
1289         id->adap.retries = 3;           /* Default retry value. */
1290         id->adap.algo_data = id;
1291         id->adap.dev.parent = &pdev->dev;
1292         init_completion(&id->xfer_done);
1293         snprintf(id->adap.name, sizeof(id->adap.name),
1294                  "Cadence I2C at %08lx", (unsigned long)r_mem->start);
1295
1296         id->clk = devm_clk_get(&pdev->dev, NULL);
1297         if (IS_ERR(id->clk))
1298                 return dev_err_probe(&pdev->dev, PTR_ERR(id->clk),
1299                                      "input clock not found.\n");
1300
1301         ret = clk_prepare_enable(id->clk);
1302         if (ret)
1303                 dev_err(&pdev->dev, "Unable to enable clock.\n");
1304
1305         pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
1306         pm_runtime_use_autosuspend(id->dev);
1307         pm_runtime_set_active(id->dev);
1308         pm_runtime_enable(id->dev);
1309
1310         id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
1311         if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
1312                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1313         id->input_clk = clk_get_rate(id->clk);
1314
1315         ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1316                         &id->i2c_clk);
1317         if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1318                 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
1319
1320 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1321         /* Set initial mode to master */
1322         id->dev_mode = CDNS_I2C_MODE_MASTER;
1323         id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
1324 #endif
1325         id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS;
1326
1327         ret = cdns_i2c_setclk(id->input_clk, id);
1328         if (ret) {
1329                 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
1330                 ret = -EINVAL;
1331                 goto err_clk_dis;
1332         }
1333
1334         ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
1335                                  DRIVER_NAME, id);
1336         if (ret) {
1337                 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
1338                 goto err_clk_dis;
1339         }
1340         cdns_i2c_init(id);
1341
1342         ret = i2c_add_adapter(&id->adap);
1343         if (ret < 0)
1344                 goto err_clk_dis;
1345
1346         dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
1347                  id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
1348
1349         return 0;
1350
1351 err_clk_dis:
1352         clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1353         clk_disable_unprepare(id->clk);
1354         pm_runtime_disable(&pdev->dev);
1355         pm_runtime_set_suspended(&pdev->dev);
1356         return ret;
1357 }
1358
1359 /**
1360  * cdns_i2c_remove - Unregister the device after releasing the resources
1361  * @pdev:       Handle to the platform device structure
1362  *
1363  * This function frees all the resources allocated to the device.
1364  *
1365  * Return: 0 always
1366  */
1367 static int cdns_i2c_remove(struct platform_device *pdev)
1368 {
1369         struct cdns_i2c *id = platform_get_drvdata(pdev);
1370
1371         pm_runtime_disable(&pdev->dev);
1372         pm_runtime_set_suspended(&pdev->dev);
1373         pm_runtime_dont_use_autosuspend(&pdev->dev);
1374
1375         i2c_del_adapter(&id->adap);
1376         clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1377         clk_disable_unprepare(id->clk);
1378
1379         return 0;
1380 }
1381
1382 static struct platform_driver cdns_i2c_drv = {
1383         .driver = {
1384                 .name  = DRIVER_NAME,
1385                 .of_match_table = cdns_i2c_of_match,
1386                 .pm = &cdns_i2c_dev_pm_ops,
1387         },
1388         .probe  = cdns_i2c_probe,
1389         .remove = cdns_i2c_remove,
1390 };
1391
1392 module_platform_driver(cdns_i2c_drv);
1393
1394 MODULE_AUTHOR("Xilinx Inc.");
1395 MODULE_DESCRIPTION("Cadence I2C bus driver");
1396 MODULE_LICENSE("GPL");