drivers/clk/mediatek/clk-mt8183.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2018 MediaTek Inc.
   4 // Author: Weiyi Lu <[email protected]>
   5
   6 #include <linux/delay.h>
   7 #include <linux/mfd/syscon.h>
   8 #include <linux/of.h>
   9 #include <linux/of_address.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/slab.h>
  13
  14 #include "clk-gate.h"
  15 #include "clk-mtk.h"
  16 #include "clk-mux.h"
  17 #include "clk-pll.h"
  18
  19 #include <dt-bindings/clock/mt8183-clk.h>
  20
  21 static DEFINE_SPINLOCK(mt8183_clk_lock);
  22
  23 static const struct mtk_fixed_clk top_fixed_clks[] = {
  24         FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
  25         FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
  26         FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
  27 };
  28
  29 static const struct mtk_fixed_factor top_early_divs[] = {
  30         FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
  31 };
  32
  33 static const struct mtk_fixed_factor top_divs[] = {
  34         FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
  35         FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
  36         FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
  37         FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
  38         FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
  39         FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
  40         FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
  41         FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
  42         FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
  43         FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
  44         FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
  45         FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0),
  46         FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0),
  47         FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0),
  48         FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0),
  49         FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0),
  50         FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0),
  51         FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0),
  52         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0),
  53         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0),
  54         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0),
  55         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0),
  56         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
  57         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0),
  58         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0),
  59         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0),
  60         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
  61         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
  62         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
  63         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
  64         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
  65         FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0),
  66         FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0),
  67         FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0),
  68         FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0),
  69         FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0),
  70         FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0),
  71         FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
  72         FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
  73         FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
  74         FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
  75         FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
  76         FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
  77         FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
  78         FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
  79         FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
  80         FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
  81         FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
  82         FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
  83         FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
  84         FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
  85         FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
  86         FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
  87         FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
  88         FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
  89         FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
  90         FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
  91         FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
  92         FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
  93         FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
  94         FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
  95         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
  96         FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
  97         FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
  98         FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
  99         FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
 100         FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
 101         FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
 102         FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
 103         FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
 104         FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0),
 105         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0),
 106 };
 107
 108 static const char * const axi_parents[] = {
 109         "clk26m",
 110         "syspll_d2_d4",
 111         "syspll_d7",
 112         "osc_d4"
 113 };
 114
 115 static const char * const mm_parents[] = {
 116         "clk26m",
 117         "mmpll_d7",
 118         "syspll_d3",
 119         "univpll_d2_d2",
 120         "syspll_d2_d2",
 121         "syspll_d3_d2"
 122 };
 123
 124 static const char * const img_parents[] = {
 125         "clk26m",
 126         "mmpll_d6",
 127         "univpll_d3",
 128         "syspll_d3",
 129         "univpll_d2_d2",
 130         "syspll_d2_d2",
 131         "univpll_d3_d2",
 132         "syspll_d3_d2"
 133 };
 134
 135 static const char * const cam_parents[] = {
 136         "clk26m",
 137         "syspll_d2",
 138         "mmpll_d6",
 139         "syspll_d3",
 140         "mmpll_d7",
 141         "univpll_d3",
 142         "univpll_d2_d2",
 143         "syspll_d2_d2",
 144         "syspll_d3_d2",
 145         "univpll_d3_d2"
 146 };
 147
 148 static const char * const dsp_parents[] = {
 149         "clk26m",
 150         "mmpll_d6",
 151         "mmpll_d7",
 152         "univpll_d3",
 153         "syspll_d3",
 154         "univpll_d2_d2",
 155         "syspll_d2_d2",
 156         "univpll_d3_d2",
 157         "syspll_d3_d2"
 158 };
 159
 160 static const char * const dsp1_parents[] = {
 161         "clk26m",
 162         "mmpll_d6",
 163         "mmpll_d7",
 164         "univpll_d3",
 165         "syspll_d3",
 166         "univpll_d2_d2",
 167         "syspll_d2_d2",
 168         "univpll_d3_d2",
 169         "syspll_d3_d2"
 170 };
 171
 172 static const char * const dsp2_parents[] = {
 173         "clk26m",
 174         "mmpll_d6",
 175         "mmpll_d7",
 176         "univpll_d3",
 177         "syspll_d3",
 178         "univpll_d2_d2",
 179         "syspll_d2_d2",
 180         "univpll_d3_d2",
 181         "syspll_d3_d2"
 182 };
 183
 184 static const char * const ipu_if_parents[] = {
 185         "clk26m",
 186         "mmpll_d6",
 187         "mmpll_d7",
 188         "univpll_d3",
 189         "syspll_d3",
 190         "univpll_d2_d2",
 191         "syspll_d2_d2",
 192         "univpll_d3_d2",
 193         "syspll_d3_d2"
 194 };
 195
 196 static const char * const mfg_parents[] = {
 197         "clk26m",
 198         "mfgpll_ck",
 199         "univpll_d3",
 200         "syspll_d3"
 201 };
 202
 203 static const char * const f52m_mfg_parents[] = {
 204         "clk26m",
 205         "univpll_d3_d2",
 206         "univpll_d3_d4",
 207         "univpll_d3_d8"
 208 };
 209
 210 static const char * const camtg_parents[] = {
 211         "clk26m",
 212         "univ_192m_d8",
 213         "univpll_d3_d8",
 214         "univ_192m_d4",
 215         "univpll_d3_d16",
 216         "csw_f26m_ck_d2",
 217         "univ_192m_d16",
 218         "univ_192m_d32"
 219 };
 220
 221 static const char * const camtg2_parents[] = {
 222         "clk26m",
 223         "univ_192m_d8",
 224         "univpll_d3_d8",
 225         "univ_192m_d4",
 226         "univpll_d3_d16",
 227         "csw_f26m_ck_d2",
 228         "univ_192m_d16",
 229         "univ_192m_d32"
 230 };
 231
 232 static const char * const camtg3_parents[] = {
 233         "clk26m",
 234         "univ_192m_d8",
 235         "univpll_d3_d8",
 236         "univ_192m_d4",
 237         "univpll_d3_d16",
 238         "csw_f26m_ck_d2",
 239         "univ_192m_d16",
 240         "univ_192m_d32"
 241 };
 242
 243 static const char * const camtg4_parents[] = {
 244         "clk26m",
 245         "univ_192m_d8",
 246         "univpll_d3_d8",
 247         "univ_192m_d4",
 248         "univpll_d3_d16",
 249         "csw_f26m_ck_d2",
 250         "univ_192m_d16",
 251         "univ_192m_d32"
 252 };
 253
 254 static const char * const uart_parents[] = {
 255         "clk26m",
 256         "univpll_d3_d8"
 257 };
 258
 259 static const char * const spi_parents[] = {
 260         "clk26m",
 261         "syspll_d5_d2",
 262         "syspll_d3_d4",
 263         "msdcpll_d4"
 264 };
 265
 266 static const char * const msdc50_hclk_parents[] = {
 267         "clk26m",
 268         "syspll_d2_d2",
 269         "syspll_d3_d2"
 270 };
 271
 272 static const char * const msdc50_0_parents[] = {
 273         "clk26m",
 274         "msdcpll_ck",
 275         "msdcpll_d2",
 276         "univpll_d2_d4",
 277         "syspll_d3_d2",
 278         "univpll_d2_d2"
 279 };
 280
 281 static const char * const msdc30_1_parents[] = {
 282         "clk26m",
 283         "univpll_d3_d2",
 284         "syspll_d3_d2",
 285         "syspll_d7",
 286         "msdcpll_d2"
 287 };
 288
 289 static const char * const msdc30_2_parents[] = {
 290         "clk26m",
 291         "univpll_d3_d2",
 292         "syspll_d3_d2",
 293         "syspll_d7",
 294         "msdcpll_d2"
 295 };
 296
 297 static const char * const audio_parents[] = {
 298         "clk26m",
 299         "syspll_d5_d4",
 300         "syspll_d7_d4",
 301         "syspll_d2_d16"
 302 };
 303
 304 static const char * const aud_intbus_parents[] = {
 305         "clk26m",
 306         "syspll_d2_d4",
 307         "syspll_d7_d2"
 308 };
 309
 310 static const char * const pmicspi_parents[] = {
 311         "clk26m",
 312         "syspll_d2_d8",
 313         "osc_d8"
 314 };
 315
 316 static const char * const fpwrap_ulposc_parents[] = {
 317         "clk26m",
 318         "osc_d16",
 319         "osc_d4",
 320         "osc_d8"
 321 };
 322
 323 static const char * const atb_parents[] = {
 324         "clk26m",
 325         "syspll_d2_d2",
 326         "syspll_d5"
 327 };
 328
 329 static const char * const dpi0_parents[] = {
 330         "clk26m",
 331         "tvdpll_d2",
 332         "tvdpll_d4",
 333         "tvdpll_d8",
 334         "tvdpll_d16",
 335         "univpll_d5_d2",
 336         "univpll_d3_d4",
 337         "syspll_d3_d4",
 338         "univpll_d3_d8"
 339 };
 340
 341 static const char * const scam_parents[] = {
 342         "clk26m",
 343         "syspll_d5_d2"
 344 };
 345
 346 static const char * const disppwm_parents[] = {
 347         "clk26m",
 348         "univpll_d3_d4",
 349         "osc_d2",
 350         "osc_d4",
 351         "osc_d16"
 352 };
 353
 354 static const char * const usb_top_parents[] = {
 355         "clk26m",
 356         "univpll_d5_d4",
 357         "univpll_d3_d4",
 358         "univpll_d5_d2"
 359 };
 360
 361
 362 static const char * const ssusb_top_xhci_parents[] = {
 363         "clk26m",
 364         "univpll_d5_d4",
 365         "univpll_d3_d4",
 366         "univpll_d5_d2"
 367 };
 368
 369 static const char * const spm_parents[] = {
 370         "clk26m",
 371         "syspll_d2_d8"
 372 };
 373
 374 static const char * const i2c_parents[] = {
 375         "clk26m",
 376         "syspll_d2_d8",
 377         "univpll_d5_d2"
 378 };
 379
 380 static const char * const scp_parents[] = {
 381         "clk26m",
 382         "univpll_d2_d8",
 383         "syspll_d5",
 384         "syspll_d2_d2",
 385         "univpll_d2_d2",
 386         "syspll_d3",
 387         "univpll_d3"
 388 };
 389
 390 static const char * const seninf_parents[] = {
 391         "clk26m",
 392         "univpll_d2_d2",
 393         "univpll_d3_d2",
 394         "univpll_d2_d4"
 395 };
 396
 397 static const char * const dxcc_parents[] = {
 398         "clk26m",
 399         "syspll_d2_d2",
 400         "syspll_d2_d4",
 401         "syspll_d2_d8"
 402 };
 403
 404 static const char * const aud_engen1_parents[] = {
 405         "clk26m",
 406         "apll1_d2",
 407         "apll1_d4",
 408         "apll1_d8"
 409 };
 410
 411 static const char * const aud_engen2_parents[] = {
 412         "clk26m",
 413         "apll2_d2",
 414         "apll2_d4",
 415         "apll2_d8"
 416 };
 417
 418 static const char * const faes_ufsfde_parents[] = {
 419         "clk26m",
 420         "syspll_d2",
 421         "syspll_d2_d2",
 422         "syspll_d3",
 423         "syspll_d2_d4",
 424         "univpll_d3"
 425 };
 426
 427 static const char * const fufs_parents[] = {
 428         "clk26m",
 429         "syspll_d2_d4",
 430         "syspll_d2_d8",
 431         "syspll_d2_d16"
 432 };
 433
 434 static const char * const aud_1_parents[] = {
 435         "clk26m",
 436         "apll1_ck"
 437 };
 438
 439 static const char * const aud_2_parents[] = {
 440         "clk26m",
 441         "apll2_ck"
 442 };
 443
 444 /*
 445  * CRITICAL CLOCK:
 446  * axi_sel is the main bus clock of whole SOC.
 447  * spm_sel is the clock of the always-on co-processor.
 448  */
 449 static const struct mtk_mux top_muxes[] = {
 450         /* CLK_CFG_0 */
 451         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
 452                 axi_parents, 0x40,
 453                 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
 454         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
 455                 mm_parents, 0x40,
 456                 0x44, 0x48, 8, 3, 15, 0x004, 1),
 457         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
 458                 img_parents, 0x40,
 459                 0x44, 0x48, 16, 3, 23, 0x004, 2),
 460         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
 461                 cam_parents, 0x40,
 462                 0x44, 0x48, 24, 4, 31, 0x004, 3),
 463         /* CLK_CFG_1 */
 464         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
 465                 dsp_parents, 0x50,
 466                 0x54, 0x58, 0, 4, 7, 0x004, 4),
 467         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
 468                 dsp1_parents, 0x50,
 469                 0x54, 0x58, 8, 4, 15, 0x004, 5),
 470         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
 471                 dsp2_parents, 0x50,
 472                 0x54, 0x58, 16, 4, 23, 0x004, 6),
 473         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
 474                 ipu_if_parents, 0x50,
 475                 0x54, 0x58, 24, 4, 31, 0x004, 7),
 476         /* CLK_CFG_2 */
 477         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
 478                 mfg_parents, 0x60,
 479                 0x64, 0x68, 0, 2, 7, 0x004, 8),
 480         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
 481                 f52m_mfg_parents, 0x60,
 482                 0x64, 0x68, 8, 2, 15, 0x004, 9),
 483         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
 484                 camtg_parents, 0x60,
 485                 0x64, 0x68, 16, 3, 23, 0x004, 10),
 486         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
 487                 camtg2_parents, 0x60,
 488                 0x64, 0x68, 24, 3, 31, 0x004, 11),
 489         /* CLK_CFG_3 */
 490         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
 491                 camtg3_parents, 0x70,
 492                 0x74, 0x78, 0, 3, 7, 0x004, 12),
 493         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
 494                 camtg4_parents, 0x70,
 495                 0x74, 0x78, 8, 3, 15, 0x004, 13),
 496         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
 497                 uart_parents, 0x70,
 498                 0x74, 0x78, 16, 1, 23, 0x004, 14),
 499         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
 500                 spi_parents, 0x70,
 501                 0x74, 0x78, 24, 2, 31, 0x004, 15),
 502         /* CLK_CFG_4 */
 503         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
 504                 msdc50_hclk_parents, 0x80,
 505                 0x84, 0x88, 0, 2, 7, 0x004, 16),
 506         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
 507                 msdc50_0_parents, 0x80,
 508                 0x84, 0x88, 8, 3, 15, 0x004, 17),
 509         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
 510                 msdc30_1_parents, 0x80,
 511                 0x84, 0x88, 16, 3, 23, 0x004, 18),
 512         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
 513                 msdc30_2_parents, 0x80,
 514                 0x84, 0x88, 24, 3, 31, 0x004, 19),
 515         /* CLK_CFG_5 */
 516         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
 517                 audio_parents, 0x90,
 518                 0x94, 0x98, 0, 2, 7, 0x004, 20),
 519         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
 520                 aud_intbus_parents, 0x90,
 521                 0x94, 0x98, 8, 2, 15, 0x004, 21),
 522         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
 523                 pmicspi_parents, 0x90,
 524                 0x94, 0x98, 16, 2, 23, 0x004, 22),
 525         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
 526                 fpwrap_ulposc_parents, 0x90,
 527                 0x94, 0x98, 24, 2, 31, 0x004, 23),
 528         /* CLK_CFG_6 */
 529         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
 530                 atb_parents, 0xa0,
 531                 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
 532         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
 533                 dpi0_parents, 0xa0,
 534                 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
 535         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
 536                 scam_parents, 0xa0,
 537                 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
 538         /* CLK_CFG_7 */
 539         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
 540                 disppwm_parents, 0xb0,
 541                 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
 542         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
 543                 usb_top_parents, 0xb0,
 544                 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
 545         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
 546                 ssusb_top_xhci_parents, 0xb0,
 547                 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
 548         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
 549                 spm_parents, 0xb0,
 550                 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
 551         /* CLK_CFG_8 */
 552         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
 553                 i2c_parents, 0xc0,
 554                 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
 555         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
 556                 scp_parents, 0xc0,
 557                 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
 558         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
 559                 seninf_parents, 0xc0,
 560                 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
 561         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
 562                 dxcc_parents, 0xc0,
 563                 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
 564         /* CLK_CFG_9 */
 565         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
 566                 aud_engen1_parents, 0xd0,
 567                 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
 568         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
 569                 aud_engen2_parents, 0xd0,
 570                 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
 571         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
 572                 faes_ufsfde_parents, 0xd0,
 573                 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
 574         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
 575                 fufs_parents, 0xd0,
 576                 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
 577         /* CLK_CFG_10 */
 578         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
 579                 aud_1_parents, 0xe0,
 580                 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
 581         MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
 582                 aud_2_parents, 0xe0,
 583                 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
 584 };
 585
 586 static const char * const apll_i2s0_parents[] = {
 587         "aud_1_sel",
 588         "aud_2_sel"
 589 };
 590
 591 static const char * const apll_i2s1_parents[] = {
 592         "aud_1_sel",
 593         "aud_2_sel"
 594 };
 595
 596 static const char * const apll_i2s2_parents[] = {
 597         "aud_1_sel",
 598         "aud_2_sel"
 599 };
 600
 601 static const char * const apll_i2s3_parents[] = {
 602         "aud_1_sel",
 603         "aud_2_sel"
 604 };
 605
 606 static const char * const apll_i2s4_parents[] = {
 607         "aud_1_sel",
 608         "aud_2_sel"
 609 };
 610
 611 static const char * const apll_i2s5_parents[] = {
 612         "aud_1_sel",
 613         "aud_2_sel"
 614 };
 615
 616 static struct mtk_composite top_aud_muxes[] = {
 617         MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
 618                 0x320, 8, 1),
 619         MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
 620                 0x320, 9, 1),
 621         MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
 622                 0x320, 10, 1),
 623         MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
 624                 0x320, 11, 1),
 625         MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
 626                 0x320, 12, 1),
 627         MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
 628                 0x328, 20, 1),
 629 };
 630
 631 static const char * const mcu_mp0_parents[] = {
 632         "clk26m",
 633         "armpll_ll",
 634         "armpll_div_pll1",
 635         "armpll_div_pll2"
 636 };
 637
 638 static const char * const mcu_mp2_parents[] = {
 639         "clk26m",
 640         "armpll_l",
 641         "armpll_div_pll1",
 642         "armpll_div_pll2"
 643 };
 644
 645 static const char * const mcu_bus_parents[] = {
 646         "clk26m",
 647         "ccipll",
 648         "armpll_div_pll1",
 649         "armpll_div_pll2"
 650 };
 651
 652 static struct mtk_composite mcu_muxes[] = {
 653         /* mp0_pll_divider_cfg */
 654         MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
 655         /* mp2_pll_divider_cfg */
 656         MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
 657         /* bus_pll_divider_cfg */
 658         MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
 659 };
 660
 661 static struct mtk_composite top_aud_divs[] = {
 662         DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
 663                 0x320, 2, 0x324, 8, 0),
 664         DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel",
 665                 0x320, 3, 0x324, 8, 8),
 666         DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel",
 667                 0x320, 4, 0x324, 8, 16),
 668         DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel",
 669                 0x320, 5, 0x324, 8, 24),
 670         DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel",
 671                 0x320, 6, 0x328, 8, 0),
 672         DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
 673                 0x320, 7, 0x328, 8, 8),
 674 };
 675
 676 static const struct mtk_gate_regs top_cg_regs = {
 677         .set_ofs = 0x104,
 678         .clr_ofs = 0x104,
 679         .sta_ofs = 0x104,
 680 };
 681
 682 #define GATE_TOP(_id, _name, _parent, _shift)                   \
 683         GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift,     \
 684                 &mtk_clk_gate_ops_no_setclr_inv)
 685
 686 static const struct mtk_gate top_clks[] = {
 687         /* TOP */
 688         GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
 689         GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
 690 };
 691
 692 static const struct mtk_gate_regs infra0_cg_regs = {
 693         .set_ofs = 0x80,
 694         .clr_ofs = 0x84,
 695         .sta_ofs = 0x90,
 696 };
 697
 698 static const struct mtk_gate_regs infra1_cg_regs = {
 699         .set_ofs = 0x88,
 700         .clr_ofs = 0x8c,
 701         .sta_ofs = 0x94,
 702 };
 703
 704 static const struct mtk_gate_regs infra2_cg_regs = {
 705         .set_ofs = 0xa4,
 706         .clr_ofs = 0xa8,
 707         .sta_ofs = 0xac,
 708 };
 709
 710 static const struct mtk_gate_regs infra3_cg_regs = {
 711         .set_ofs = 0xc0,
 712         .clr_ofs = 0xc4,
 713         .sta_ofs = 0xc8,
 714 };
 715
 716 #define GATE_INFRA0(_id, _name, _parent, _shift)                \
 717         GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift,  \
 718                 &mtk_clk_gate_ops_setclr)
 719
 720 #define GATE_INFRA1(_id, _name, _parent, _shift)                \
 721         GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift,  \
 722                 &mtk_clk_gate_ops_setclr)
 723
 724 #define GATE_INFRA2(_id, _name, _parent, _shift)                \
 725         GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift,  \
 726                 &mtk_clk_gate_ops_setclr)
 727
 728 #define GATE_INFRA3(_id, _name, _parent, _shift)                \
 729         GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift,  \
 730                 &mtk_clk_gate_ops_setclr)
 731
 732 static const struct mtk_gate infra_clks[] = {
 733         /* INFRA0 */
 734         GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
 735                 "axi_sel", 0),
 736         GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
 737                 "axi_sel", 1),
 738         GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
 739                 "axi_sel", 2),
 740         GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
 741                 "axi_sel", 3),
 742         GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
 743                 "scp_sel", 4),
 744         GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
 745                 "f_f26m_ck", 5),
 746         GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
 747                 "axi_sel", 6),
 748         GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
 749                 "axi_sel", 8),
 750         GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
 751                 "axi_sel", 9),
 752         GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
 753                 "axi_sel", 10),
 754         GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
 755                 "i2c_sel", 11),
 756         GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
 757                 "i2c_sel", 12),
 758         GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
 759                 "i2c_sel", 13),
 760         GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
 761                 "i2c_sel", 14),
 762         GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
 763                 "axi_sel", 15),
 764         GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
 765                 "i2c_sel", 16),
 766         GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
 767                 "i2c_sel", 17),
 768         GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
 769                 "i2c_sel", 18),
 770         GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
 771                 "i2c_sel", 19),
 772         GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
 773                 "i2c_sel", 21),
 774         GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
 775                 "uart_sel", 22),
 776         GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
 777                 "uart_sel", 23),
 778         GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
 779                 "uart_sel", 24),
 780         GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
 781                 "uart_sel", 25),
 782         GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
 783                 "axi_sel", 27),
 784         GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
 785                 "axi_sel", 28),
 786         GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
 787                 "axi_sel", 31),
 788         /* INFRA1 */
 789         GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
 790                 "spi_sel", 1),
 791         GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
 792                 "msdc50_hclk_sel", 2),
 793         GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
 794                 "axi_sel", 4),
 795         GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
 796                 "axi_sel", 5),
 797         GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
 798                 "msdc50_0_sel", 6),
 799         GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
 800                 "f_f26m_ck", 7),
 801         GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
 802                 "axi_sel", 8),
 803         GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
 804                 "axi_sel", 9),
 805         GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
 806                 "f_f26m_ck", 10),
 807         GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
 808                 "axi_sel", 11),
 809         GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
 810                 "axi_sel", 12),
 811         GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
 812                 "axi_sel", 13),
 813         GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
 814                 "f_f26m_ck", 14),
 815         GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
 816                 "msdc30_1_sel", 16),
 817         GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
 818                 "msdc30_2_sel", 17),
 819         GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
 820                 "axi_sel", 18),
 821         GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
 822                 "axi_sel", 19),
 823         GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
 824                 "axi_sel", 20),
 825         GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
 826                 "axi_sel", 23),
 827         GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
 828                 "axi_sel", 24),
 829         GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio",
 830                 "axi_sel", 25),
 831         GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
 832                 "axi_sel", 26),
 833         GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
 834                 "dxcc_sel", 27),
 835         GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
 836                 "dxcc_sel", 28),
 837         GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
 838                 "axi_sel", 30),
 839         GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
 840                 "f_f26m_ck", 31),
 841         /* INFRA2 */
 842         GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
 843                 "f_f26m_ck", 0),
 844         GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
 845                 "usb_top_sel", 1),
 846         GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
 847                 "axi_sel", 2),
 848         GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk",
 849                 "axi_sel", 3),
 850         GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk",
 851                 "f_f26m_ck", 4),
 852         GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
 853                 "spi_sel", 6),
 854         GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
 855                 "i2c_sel", 7),
 856         GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
 857                 "f_f26m_ck", 8),
 858         GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
 859                 "spi_sel", 9),
 860         GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
 861                 "spi_sel", 10),
 862         GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
 863                 "ssusb_top_xhci_sel", 11),
 864         GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
 865                 "fufs_sel", 12),
 866         GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
 867                 "fufs_sel", 13),
 868         GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
 869                 "axi_sel", 14),
 870         GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
 871                 "axi_sel", 16),
 872         GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
 873                 "i2c_sel", 18),
 874         GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
 875                 "i2c_sel", 19),
 876         GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
 877                 "i2c_sel", 20),
 878         GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
 879                 "i2c_sel", 21),
 880         GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
 881                 "i2c_sel", 22),
 882         GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
 883                 "i2c_sel", 23),
 884         GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
 885                 "i2c_sel", 24),
 886         GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
 887                 "spi_sel", 25),
 888         GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
 889                 "spi_sel", 26),
 890         GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
 891                 "axi_sel", 27),
 892         GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
 893                 "fufs_sel", 28),
 894         GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
 895                 "faes_ufsfde_sel", 29),
 896         GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
 897                 "fufs_sel", 30),
 898         /* INFRA3 */
 899         GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
 900                 "msdc50_0_sel", 0),
 901         GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
 902                 "msdc50_0_sel", 1),
 903         GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
 904                 "msdc50_0_sel", 2),
 905         GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
 906                 "axi_sel", 5),
 907         GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
 908                 "i2c_sel", 6),
 909         GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
 910                 "msdc50_hclk_sel", 7),
 911         GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
 912                 "msdc50_hclk_sel", 8),
 913         GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
 914                 "axi_sel", 16),
 915         GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
 916                 "axi_sel", 17),
 917         GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
 918                 "axi_sel", 18),
 919         GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
 920                 "axi_sel", 19),
 921         GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
 922                 "f_f26m_ck", 20),
 923         GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
 924                 "axi_sel", 21),
 925         GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
 926                 "i2c_sel", 22),
 927         GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
 928                 "i2c_sel", 23),
 929         GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
 930                 "msdc50_0_sel", 24),
 931 };
 932
 933 static const struct mtk_gate_regs peri_cg_regs = {
 934         .set_ofs = 0x20c,
 935         .clr_ofs = 0x20c,
 936         .sta_ofs = 0x20c,
 937 };
 938
 939 #define GATE_PERI(_id, _name, _parent, _shift)                  \
 940         GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift,    \
 941                 &mtk_clk_gate_ops_no_setclr_inv)
 942
 943 static const struct mtk_gate peri_clks[] = {
 944         GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
 945 };
 946
 947 static const struct mtk_gate_regs apmixed_cg_regs = {
 948         .set_ofs = 0x20,
 949         .clr_ofs = 0x20,
 950         .sta_ofs = 0x20,
 951 };
 952
 953 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
 954         GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs,           \
 955                 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
 956
 957 #define GATE_APMIXED(_id, _name, _parent, _shift)       \
 958         GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
 959
 960 /*
 961  * CRITICAL CLOCK:
 962  * apmixed_appll26m is the toppest clock gate of all PLLs.
 963  */
 964 static const struct mtk_gate apmixed_clks[] = {
 965         /* AUDIO0 */
 966         GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m",
 967                 "f_f26m_ck", 4),
 968         GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
 969                 "f_f26m_ck", 5, CLK_IS_CRITICAL),
 970         GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
 971                 "f_f26m_ck", 6),
 972         GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m",
 973                 "f_f26m_ck", 7),
 974         GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m",
 975                 "f_f26m_ck", 8),
 976         GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m",
 977                 "f_f26m_ck", 9),
 978         GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
 979                 "f_f26m_ck", 11),
 980         GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m",
 981                 "f_f26m_ck", 13),
 982         GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
 983                 "f_f26m_ck", 14),
 984         GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
 985                 "f_f26m_ck", 16),
 986         GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
 987                 "f_f26m_ck", 17),
 988 };
 989
 990 #define MT8183_PLL_FMAX         (3800UL * MHZ)
 991 #define MT8183_PLL_FMIN         (1500UL * MHZ)
 992
 993 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,             \
 994                         _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,    \
 995                         _pd_shift, _tuner_reg,  _tuner_en_reg,          \
 996                         _tuner_en_bit, _pcw_reg, _pcw_shift,            \
 997                         _pcw_chg_reg, _div_table) {                     \
 998                 .id = _id,                                              \
 999                 .name = _name,                                          \
1000                 .reg = _reg,                                            \
1001                 .pwr_reg = _pwr_reg,                                    \
1002                 .en_mask = _en_mask,                                    \
1003                 .flags = _flags,                                        \
1004                 .rst_bar_mask = _rst_bar_mask,                          \
1005                 .fmax = MT8183_PLL_FMAX,                                \
1006                 .fmin = MT8183_PLL_FMIN,                                \
1007                 .pcwbits = _pcwbits,                                    \
1008                 .pcwibits = _pcwibits,                                  \
1009                 .pd_reg = _pd_reg,                                      \
1010                 .pd_shift = _pd_shift,                                  \
1011                 .tuner_reg = _tuner_reg,                                \
1012                 .tuner_en_reg = _tuner_en_reg,                          \
1013                 .tuner_en_bit = _tuner_en_bit,                          \
1014                 .pcw_reg = _pcw_reg,                                    \
1015                 .pcw_shift = _pcw_shift,                                \
1016                 .pcw_chg_reg = _pcw_chg_reg,                            \
1017                 .div_table = _div_table,                                \
1018         }
1019
1020 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,               \
1021                         _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,    \
1022                         _pd_shift, _tuner_reg, _tuner_en_reg,           \
1023                         _tuner_en_bit, _pcw_reg, _pcw_shift,            \
1024                         _pcw_chg_reg)                                   \
1025                 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,     \
1026                         _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,    \
1027                         _pd_shift, _tuner_reg, _tuner_en_reg,           \
1028                         _tuner_en_bit, _pcw_reg, _pcw_shift,            \
1029                         _pcw_chg_reg, NULL)
1030
1031 static const struct mtk_pll_div_table armpll_div_table[] = {
1032         { .div = 0, .freq = MT8183_PLL_FMAX },
1033         { .div = 1, .freq = 1500 * MHZ },
1034         { .div = 2, .freq = 750 * MHZ },
1035         { .div = 3, .freq = 375 * MHZ },
1036         { .div = 4, .freq = 187500000 },
1037         { } /* sentinel */
1038 };
1039
1040 static const struct mtk_pll_div_table mfgpll_div_table[] = {
1041         { .div = 0, .freq = MT8183_PLL_FMAX },
1042         { .div = 1, .freq = 1600 * MHZ },
1043         { .div = 2, .freq = 800 * MHZ },
1044         { .div = 3, .freq = 400 * MHZ },
1045         { .div = 4, .freq = 200 * MHZ },
1046         { } /* sentinel */
1047 };
1048
1049 static const struct mtk_pll_data plls[] = {
1050         PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
1051                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
1052                 0x0204, 0, 0, armpll_div_table),
1053         PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0,
1054                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
1055                 0x0214, 0, 0, armpll_div_table),
1056         PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0,
1057                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
1058                 0x0294, 0, 0),
1059         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0,
1060                 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
1061                 0x0224, 0, 0),
1062         PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0,
1063                 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
1064                 0x0234, 0, 0),
1065         PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0,
1066                 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
1067                 mfgpll_div_table),
1068         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
1069                 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
1070         PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0,
1071                 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
1072         PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
1073                 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
1074                 0x0274, 0, 0),
1075         PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0,
1076                 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
1077         PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0,
1078                 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
1079 };
1080
1081 static u16 infra_rst_ofs[] = {
1082         INFRA_RST0_SET_OFFSET,
1083         INFRA_RST1_SET_OFFSET,
1084         INFRA_RST2_SET_OFFSET,
1085         INFRA_RST3_SET_OFFSET,
1086 };
1087
1088 static const struct mtk_clk_rst_desc clk_rst_desc = {
1089         .version = MTK_RST_SET_CLR,
1090         .rst_bank_ofs = infra_rst_ofs,
1091         .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
1092 };
1093
1094 static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
1095 {
1096         struct clk_hw_onecell_data *clk_data;
1097         struct device_node *node = pdev->dev.of_node;
1098
1099         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1100
1101         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1102
1103         mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
1104                 clk_data);
1105
1106         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1107 }
1108
1109 static struct clk_hw_onecell_data *top_clk_data;
1110
1111 static void clk_mt8183_top_init_early(struct device_node *node)
1112 {
1113         int i;
1114
1115         top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1116
1117         for (i = 0; i < CLK_TOP_NR_CLK; i++)
1118                 top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
1119
1120         mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1121                         top_clk_data);
1122
1123         of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1124 }
1125
1126 CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
1127                         clk_mt8183_top_init_early);
1128
1129 /* Register mux notifier for MFG mux */
1130 static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
1131 {
1132         struct mtk_mux_nb *mfg_mux_nb;
1133         int i;
1134
1135         mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
1136         if (!mfg_mux_nb)
1137                 return -ENOMEM;
1138
1139         for (i = 0; i < ARRAY_SIZE(top_muxes); i++)
1140                 if (top_muxes[i].id == CLK_TOP_MUX_MFG)
1141                         break;
1142         if (i == ARRAY_SIZE(top_muxes))
1143                 return -EINVAL;
1144
1145         mfg_mux_nb->ops = top_muxes[i].ops;
1146         mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
1147
1148         return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
1149 }
1150
1151 static int clk_mt8183_top_probe(struct platform_device *pdev)
1152 {
1153         void __iomem *base;
1154         struct device_node *node = pdev->dev.of_node;
1155         int ret;
1156
1157         base = devm_platform_ioremap_resource(pdev, 0);
1158         if (IS_ERR(base))
1159                 return PTR_ERR(base);
1160
1161         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1162                 top_clk_data);
1163
1164         mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1165                 top_clk_data);
1166
1167         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1168
1169         mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
1170                 node, &mt8183_clk_lock, top_clk_data);
1171
1172         mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
1173                 base, &mt8183_clk_lock, top_clk_data);
1174
1175         mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1176                 base, &mt8183_clk_lock, top_clk_data);
1177
1178         mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1179                 top_clk_data);
1180
1181         ret = clk_mt8183_reg_mfg_mux_notifier(&pdev->dev,
1182                                               top_clk_data->hws[CLK_TOP_MUX_MFG]->clk);
1183         if (ret)
1184                 return ret;
1185
1186         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
1187                                       top_clk_data);
1188 }
1189
1190 static int clk_mt8183_infra_probe(struct platform_device *pdev)
1191 {
1192         struct clk_hw_onecell_data *clk_data;
1193         struct device_node *node = pdev->dev.of_node;
1194         int r;
1195
1196         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1197
1198         mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1199                 clk_data);
1200
1201         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1202         if (r) {
1203                 dev_err(&pdev->dev,
1204                         "%s(): could not register clock provider: %d\n",
1205                         __func__, r);
1206                 return r;
1207         }
1208
1209         mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
1210
1211         return r;
1212 }
1213
1214 static int clk_mt8183_peri_probe(struct platform_device *pdev)
1215 {
1216         struct clk_hw_onecell_data *clk_data;
1217         struct device_node *node = pdev->dev.of_node;
1218
1219         clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1220
1221         mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1222                                clk_data);
1223
1224         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1225 }
1226
1227 static int clk_mt8183_mcu_probe(struct platform_device *pdev)
1228 {
1229         struct clk_hw_onecell_data *clk_data;
1230         struct device_node *node = pdev->dev.of_node;
1231         void __iomem *base;
1232
1233         base = devm_platform_ioremap_resource(pdev, 0);
1234         if (IS_ERR(base))
1235                 return PTR_ERR(base);
1236
1237         clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1238
1239         mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1240                         &mt8183_clk_lock, clk_data);
1241
1242         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1243 }
1244
1245 static const struct of_device_id of_match_clk_mt8183[] = {
1246         {
1247                 .compatible = "mediatek,mt8183-apmixedsys",
1248                 .data = clk_mt8183_apmixed_probe,
1249         }, {
1250                 .compatible = "mediatek,mt8183-topckgen",
1251                 .data = clk_mt8183_top_probe,
1252         }, {
1253                 .compatible = "mediatek,mt8183-infracfg",
1254                 .data = clk_mt8183_infra_probe,
1255         }, {
1256                 .compatible = "mediatek,mt8183-pericfg",
1257                 .data = clk_mt8183_peri_probe,
1258         }, {
1259                 .compatible = "mediatek,mt8183-mcucfg",
1260                 .data = clk_mt8183_mcu_probe,
1261         }, {
1262                 /* sentinel */
1263         }
1264 };
1265
1266 static int clk_mt8183_probe(struct platform_device *pdev)
1267 {
1268         int (*clk_probe)(struct platform_device *pdev);
1269         int r;
1270
1271         clk_probe = of_device_get_match_data(&pdev->dev);
1272         if (!clk_probe)
1273                 return -EINVAL;
1274
1275         r = clk_probe(pdev);
1276         if (r)
1277                 dev_err(&pdev->dev,
1278                         "could not register clock provider: %s: %d\n",
1279                         pdev->name, r);
1280
1281         return r;
1282 }
1283
1284 static struct platform_driver clk_mt8183_drv = {
1285         .probe = clk_mt8183_probe,
1286         .driver = {
1287                 .name = "clk-mt8183",
1288                 .of_match_table = of_match_clk_mt8183,
1289         },
1290 };
1291
1292 static int __init clk_mt8183_init(void)
1293 {
1294         return platform_driver_register(&clk_mt8183_drv);
1295 }
1296
1297 arch_initcall(clk_mt8183_init);