drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _AMDGPU_RAS_H
  25 #define _AMDGPU_RAS_H
  26
  27 #include <linux/debugfs.h>
  28 #include <linux/list.h>
  29 #include <linux/kfifo.h>
  30 #include <linux/radix-tree.h>
  31 #include <linux/siphash.h>
  32 #include "ta_ras_if.h"
  33 #include "amdgpu_ras_eeprom.h"
  34 #include "amdgpu_smuio.h"
  35 #include "amdgpu_aca.h"
  36
  37 struct amdgpu_iv_entry;
  38
  39 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x)              AMDGPU_GET_REG_FIELD(x, 0, 0)
  40 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x)                   AMDGPU_GET_REG_FIELD(x, 1, 1)
  41 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x)        AMDGPU_GET_REG_FIELD(x, 2, 2)
  42 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x)        AMDGPU_GET_REG_FIELD(x, 3, 3)
  43 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x)      AMDGPU_GET_REG_FIELD(x, 4, 4)
  44 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x)      AMDGPU_GET_REG_FIELD(x, 5, 5)
  45 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x)              AMDGPU_GET_REG_FIELD(x, 6, 6)
  46 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x)             AMDGPU_GET_REG_FIELD(x, 7, 7)
  47 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x)                 AMDGPU_GET_REG_FIELD(x, 10, 8)
  48 #define AMDGPU_RAS_GPU_ERR_AID_ID(x)                    AMDGPU_GET_REG_FIELD(x, 12, 11)
  49 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x)                    AMDGPU_GET_REG_FIELD(x, 14, 13)
  50
  51 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT    100
  52 #define AMDGPU_RAS_BOOT_STEADY_STATUS           0xBA
  53 #define AMDGPU_RAS_BOOT_STATUS_MASK             0xFF
  54
  55 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS           (0x1 << 0)
  56 /* position of instance value in sub_block_index of
  57  * ta_ras_trigger_error_input, the sub block uses lower 12 bits
  58  */
  59 #define AMDGPU_RAS_INST_MASK 0xfffff000
  60 #define AMDGPU_RAS_INST_SHIFT 0xc
  61
  62 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29
  63 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000
  64
  65 /* Reserve 8 physical dram row for possible retirement.
  66  * In worst cases, it will lose 8 * 2MB memory in vram domain */
  67 #define AMDGPU_RAS_RESERVED_VRAM_SIZE   (16ULL << 20)
  68 /* The high three bits indicates socketid */
  69 #define AMDGPU_RAS_GET_FEATURES(val)  ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)
  70
  71 #define RAS_EVENT_LOG(adev, id, fmt, ...)       \
  72         amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__);
  73
  74 enum amdgpu_ras_block {
  75         AMDGPU_RAS_BLOCK__UMC = 0,
  76         AMDGPU_RAS_BLOCK__SDMA,
  77         AMDGPU_RAS_BLOCK__GFX,
  78         AMDGPU_RAS_BLOCK__MMHUB,
  79         AMDGPU_RAS_BLOCK__ATHUB,
  80         AMDGPU_RAS_BLOCK__PCIE_BIF,
  81         AMDGPU_RAS_BLOCK__HDP,
  82         AMDGPU_RAS_BLOCK__XGMI_WAFL,
  83         AMDGPU_RAS_BLOCK__DF,
  84         AMDGPU_RAS_BLOCK__SMN,
  85         AMDGPU_RAS_BLOCK__SEM,
  86         AMDGPU_RAS_BLOCK__MP0,
  87         AMDGPU_RAS_BLOCK__MP1,
  88         AMDGPU_RAS_BLOCK__FUSE,
  89         AMDGPU_RAS_BLOCK__MCA,
  90         AMDGPU_RAS_BLOCK__VCN,
  91         AMDGPU_RAS_BLOCK__JPEG,
  92         AMDGPU_RAS_BLOCK__IH,
  93         AMDGPU_RAS_BLOCK__MPIO,
  94
  95         AMDGPU_RAS_BLOCK__LAST
  96 };
  97
  98 enum amdgpu_ras_mca_block {
  99         AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
 100         AMDGPU_RAS_MCA_BLOCK__MP1,
 101         AMDGPU_RAS_MCA_BLOCK__MPIO,
 102         AMDGPU_RAS_MCA_BLOCK__IOHC,
 103
 104         AMDGPU_RAS_MCA_BLOCK__LAST
 105 };
 106
 107 #define AMDGPU_RAS_BLOCK_COUNT  AMDGPU_RAS_BLOCK__LAST
 108 #define AMDGPU_RAS_MCA_BLOCK_COUNT      AMDGPU_RAS_MCA_BLOCK__LAST
 109 #define AMDGPU_RAS_BLOCK_MASK   ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
 110
 111 enum amdgpu_ras_gfx_subblock {
 112         /* CPC */
 113         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
 114         AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
 115                 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
 116         AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
 117         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
 118         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
 119         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
 120         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
 121         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
 122         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
 123         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
 124                 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
 125         /* CPF */
 126         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
 127         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
 128                 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
 129         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
 130         AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
 131         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
 132         /* CPG */
 133         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
 134         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
 135                 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
 136         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
 137         AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
 138         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
 139         /* GDS */
 140         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
 141         AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
 142         AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
 143         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
 144         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
 145         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 146         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
 147                 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 148         /* SPI */
 149         AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
 150         /* SQ */
 151         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 152         AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 153         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
 154         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
 155         AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 156         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 157         /* SQC (3 ranges) */
 158         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 159         /* SQC range 0 */
 160         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
 161                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 162         AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 163                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
 164         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 165         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 166         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 167         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 168         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 169         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 170         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
 171                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 172         /* SQC range 1 */
 173         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 174         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 175                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 176         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 177         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 178         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 179         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 180         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 181         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 182         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 183         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 184         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
 185                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 186         /* SQC range 2 */
 187         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 188         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 189                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 190         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 191         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 192         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 193         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 194         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 195         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 196         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 197         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 198         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
 199                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 200         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
 201                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
 202         /* TA */
 203         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 204         AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
 205                 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 206         AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
 207         AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
 208         AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
 209         AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 210         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 211         /* TCA */
 212         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 213         AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
 214                 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 215         AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 216         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
 217                 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 218         /* TCC (5 sub-ranges) */
 219         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 220         /* TCC range 0 */
 221         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
 222                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 223         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
 224                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
 225         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 226         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 227         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 228         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 229         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 230         AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 231         AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 232         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
 233                 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 234         /* TCC range 1 */
 235         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 236         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
 237                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 238         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 239         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
 240                 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 241         /* TCC range 2 */
 242         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 243         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
 244                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 245         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 246         AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 247         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 248         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 249         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 250         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 251         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 252         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
 253                 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 254         /* TCC range 3 */
 255         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 256         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
 257                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 258         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 259         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
 260                 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 261         /* TCC range 4 */
 262         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 263         AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 264                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 265         AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 266         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
 267                 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 268         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
 269                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
 270         /* TCI */
 271         AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 272         /* TCP */
 273         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 274         AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
 275                 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 276         AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 277         AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 278         AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
 279         AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
 280         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 281         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 282         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
 283                 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 284         /* TD */
 285         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 286         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
 287                 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 288         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 289         AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 290         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 291         /* EA (3 sub-ranges) */
 292         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 293         /* EA range 0 */
 294         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
 295                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 296         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
 297                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
 298         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 299         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 300         AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 301         AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 302         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 303         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 304         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 305         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
 306                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 307         /* EA range 1 */
 308         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 309         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
 310                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 311         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 312         AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 313         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 314         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 315         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 316         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 317         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
 318                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 319         /* EA range 2 */
 320         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 321         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
 322                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 323         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 324         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 325         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 326         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
 327                 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 328         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
 329                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
 330         /* UTC VM L2 bank */
 331         AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 332         /* UTC VM walker */
 333         AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
 334         /* UTC ATC L2 2MB cache */
 335         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 336         /* UTC ATC L2 4KB cache */
 337         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 338         AMDGPU_RAS_BLOCK__GFX_MAX
 339 };
 340
 341 enum amdgpu_ras_error_type {
 342         AMDGPU_RAS_ERROR__NONE                                                  = 0,
 343         AMDGPU_RAS_ERROR__PARITY                                                = 1,
 344         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE                                    = 2,
 345         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE                                   = 4,
 346         AMDGPU_RAS_ERROR__POISON                                                = 8,
 347 };
 348
 349 enum amdgpu_ras_ret {
 350         AMDGPU_RAS_SUCCESS = 0,
 351         AMDGPU_RAS_FAIL,
 352         AMDGPU_RAS_UE,
 353         AMDGPU_RAS_CE,
 354         AMDGPU_RAS_PT,
 355 };
 356
 357 enum amdgpu_ras_error_query_mode {
 358         AMDGPU_RAS_INVALID_ERROR_QUERY          = 0,
 359         AMDGPU_RAS_DIRECT_ERROR_QUERY           = 1,
 360         AMDGPU_RAS_FIRMWARE_ERROR_QUERY         = 2,
 361 };
 362
 363 /* ras error status reisger fields */
 364 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT     0x0
 365 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK       0x00000001L
 366 #define ERR_STATUS_LO__MEMORY_ID__SHIFT                 0x18
 367 #define ERR_STATUS_LO__MEMORY_ID_MASK                   0xFF000000L
 368 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT       0x2
 369 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK         0x00000004L
 370 #define ERR_STATUS__ERR_CNT__SHIFT                      0x17
 371 #define ERR_STATUS__ERR_CNT_MASK                        0x03800000L
 372
 373 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
 374         ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
 375
 376 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
 377         (adev->reg_offset[hwip][ip_inst][segment] + (reg))
 378
 379 #define AMDGPU_RAS_ERR_INFO_VALID       (1 << 0)
 380 #define AMDGPU_RAS_ERR_STATUS_VALID     (1 << 1)
 381 #define AMDGPU_RAS_ERR_ADDRESS_VALID    (1 << 2)
 382
 383 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET  (0x1 << 0)
 384 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET  (0x1 << 1)
 385
 386 struct amdgpu_ras_err_status_reg_entry {
 387         uint32_t hwip;
 388         uint32_t ip_inst;
 389         uint32_t seg_lo;
 390         uint32_t reg_lo;
 391         uint32_t seg_hi;
 392         uint32_t reg_hi;
 393         uint32_t reg_inst;
 394         uint32_t flags;
 395         const char *block_name;
 396 };
 397
 398 struct amdgpu_ras_memory_id_entry {
 399         uint32_t memory_id;
 400         const char *name;
 401 };
 402
 403 struct ras_common_if {
 404         enum amdgpu_ras_block block;
 405         enum amdgpu_ras_error_type type;
 406         uint32_t sub_block_index;
 407         char name[32];
 408 };
 409
 410 #define MAX_UMC_CHANNEL_NUM 32
 411
 412 struct ecc_info_per_ch {
 413         uint16_t ce_count_lo_chip;
 414         uint16_t ce_count_hi_chip;
 415         uint64_t mca_umc_status;
 416         uint64_t mca_umc_addr;
 417         uint64_t mca_ceumc_addr;
 418 };
 419
 420 struct umc_ecc_info {
 421         struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
 422
 423         /* Determine smu ecctable whether support
 424          * record correctable error address
 425          */
 426         int record_ce_addr_supported;
 427 };
 428
 429 enum ras_event_type {
 430         RAS_EVENT_TYPE_INVALID = -1,
 431         RAS_EVENT_TYPE_ISR = 0,
 432         RAS_EVENT_TYPE_COUNT,
 433 };
 434
 435 struct ras_event_manager {
 436         atomic64_t seqnos[RAS_EVENT_TYPE_COUNT];
 437 };
 438
 439 struct ras_query_context {
 440         enum ras_event_type type;
 441         u64 event_id;
 442 };
 443
 444 typedef int (*pasid_notify)(struct amdgpu_device *adev,
 445                 uint16_t pasid, void *data);
 446
 447 struct ras_poison_msg {
 448         enum amdgpu_ras_block block;
 449         uint16_t pasid;
 450         uint32_t reset;
 451         pasid_notify pasid_fn;
 452         void *data;
 453 };
 454
 455 struct ras_err_pages {
 456         uint32_t count;
 457         uint64_t *pfn;
 458 };
 459
 460 struct ras_ecc_err {
 461         u64 hash_index;
 462         uint64_t status;
 463         uint64_t ipid;
 464         uint64_t addr;
 465         struct ras_err_pages err_pages;
 466 };
 467
 468 struct ras_ecc_log_info {
 469         struct mutex lock;
 470         siphash_key_t ecc_key;
 471         struct radix_tree_root de_page_tree;
 472         bool    de_updated;
 473 };
 474
 475 struct amdgpu_ras {
 476         /* ras infrastructure */
 477         /* for ras itself. */
 478         uint32_t features;
 479         uint32_t schema;
 480         struct list_head head;
 481         /* sysfs */
 482         struct device_attribute features_attr;
 483         struct device_attribute version_attr;
 484         struct device_attribute schema_attr;
 485         struct bin_attribute badpages_attr;
 486         struct dentry *de_ras_eeprom_table;
 487         /* block array */
 488         struct ras_manager *objs;
 489
 490         /* gpu recovery */
 491         struct work_struct recovery_work;
 492         atomic_t in_recovery;
 493         struct amdgpu_device *adev;
 494         /* error handler data */
 495         struct ras_err_handler_data *eh_data;
 496         struct mutex recovery_lock;
 497
 498         uint32_t flags;
 499         bool reboot;
 500         struct amdgpu_ras_eeprom_control eeprom_control;
 501
 502         bool error_query_ready;
 503
 504         /* bad page count threshold */
 505         uint32_t bad_page_cnt_threshold;
 506
 507         /* disable ras error count harvest in recovery */
 508         bool disable_ras_err_cnt_harvest;
 509
 510         /* is poison mode supported */
 511         bool poison_supported;
 512
 513         /* RAS count errors delayed work */
 514         struct delayed_work ras_counte_delay_work;
 515         atomic_t ras_ue_count;
 516         atomic_t ras_ce_count;
 517
 518         /* record umc error info queried from smu */
 519         struct umc_ecc_info umc_ecc;
 520
 521         /* Indicates smu whether need update bad channel info */
 522         bool update_channel_flag;
 523         /* Record status of smu mca debug mode */
 524         bool is_aca_debug_mode;
 525         bool is_rma;
 526
 527         /* Record special requirements of gpu reset caller */
 528         uint32_t  gpu_reset_flags;
 529
 530         struct task_struct *page_retirement_thread;
 531         wait_queue_head_t page_retirement_wq;
 532         struct mutex page_retirement_lock;
 533         atomic_t page_retirement_req_cnt;
 534         struct mutex page_rsv_lock;
 535         DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128);
 536         struct ras_ecc_log_info  umc_ecc_log;
 537         struct delayed_work page_retirement_dwork;
 538
 539         /* Fatal error detected flag */
 540         atomic_t fed;
 541
 542         /* RAS event manager */
 543         struct ras_event_manager __event_mgr;
 544         struct ras_event_manager *event_mgr;
 545
 546         uint64_t reserved_pages_in_bytes;
 547 };
 548
 549 struct ras_fs_data {
 550         char sysfs_name[48];
 551         char debugfs_name[32];
 552 };
 553
 554 struct ras_err_addr {
 555         struct list_head node;
 556         uint64_t err_status;
 557         uint64_t err_ipid;
 558         uint64_t err_addr;
 559 };
 560
 561 struct ras_err_info {
 562         struct amdgpu_smuio_mcm_config_info mcm_info;
 563         u64 ce_count;
 564         u64 ue_count;
 565         u64 de_count;
 566         struct list_head err_addr_list;
 567 };
 568
 569 struct ras_err_node {
 570         struct list_head node;
 571         struct ras_err_info err_info;
 572 };
 573
 574 struct ras_err_data {
 575         unsigned long ue_count;
 576         unsigned long ce_count;
 577         unsigned long de_count;
 578         unsigned long err_addr_cnt;
 579         struct eeprom_table_record *err_addr;
 580         unsigned long err_addr_len;
 581         u32 err_list_count;
 582         struct list_head err_node_list;
 583 };
 584
 585 #define for_each_ras_error(err_node, err_data) \
 586         list_for_each_entry(err_node, &(err_data)->err_node_list, node)
 587
 588 struct ras_err_handler_data {
 589         /* point to bad page records array */
 590         struct eeprom_table_record *bps;
 591         /* the count of entries */
 592         int count;
 593         /* the space can place new entries */
 594         int space_left;
 595 };
 596
 597 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
 598                 void *err_data,
 599                 struct amdgpu_iv_entry *entry);
 600
 601 struct ras_ih_data {
 602         /* interrupt bottom half */
 603         struct work_struct ih_work;
 604         int inuse;
 605         /* IP callback */
 606         ras_ih_cb cb;
 607         /* full of entries */
 608         unsigned char *ring;
 609         unsigned int ring_size;
 610         unsigned int element_size;
 611         unsigned int aligned_element_size;
 612         unsigned int rptr;
 613         unsigned int wptr;
 614 };
 615
 616 struct ras_manager {
 617         struct ras_common_if head;
 618         /* reference count */
 619         int use;
 620         /* ras block link */
 621         struct list_head node;
 622         /* the device */
 623         struct amdgpu_device *adev;
 624         /* sysfs */
 625         struct device_attribute sysfs_attr;
 626         int attr_inuse;
 627
 628         /* fs node name */
 629         struct ras_fs_data fs_data;
 630
 631         /* IH data */
 632         struct ras_ih_data ih_data;
 633
 634         struct ras_err_data err_data;
 635
 636         struct aca_handle aca_handle;
 637 };
 638
 639 struct ras_badpage {
 640         unsigned int bp;
 641         unsigned int size;
 642         unsigned int flags;
 643 };
 644
 645 /* interfaces for IP */
 646 struct ras_fs_if {
 647         struct ras_common_if head;
 648         const char* sysfs_name;
 649         char debugfs_name[32];
 650 };
 651
 652 struct ras_query_if {
 653         struct ras_common_if head;
 654         unsigned long ue_count;
 655         unsigned long ce_count;
 656         unsigned long de_count;
 657 };
 658
 659 struct ras_inject_if {
 660         struct ras_common_if head;
 661         uint64_t address;
 662         uint64_t value;
 663         uint32_t instance_mask;
 664 };
 665
 666 struct ras_cure_if {
 667         struct ras_common_if head;
 668         uint64_t address;
 669 };
 670
 671 struct ras_ih_if {
 672         struct ras_common_if head;
 673         ras_ih_cb cb;
 674 };
 675
 676 struct ras_dispatch_if {
 677         struct ras_common_if head;
 678         struct amdgpu_iv_entry *entry;
 679 };
 680
 681 struct ras_debug_if {
 682         union {
 683                 struct ras_common_if head;
 684                 struct ras_inject_if inject;
 685         };
 686         int op;
 687 };
 688
 689 struct amdgpu_ras_block_object {
 690         struct ras_common_if  ras_comm;
 691
 692         int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
 693                                 enum amdgpu_ras_block block, uint32_t sub_block_index);
 694         int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 695         void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 696         ras_ih_cb ras_cb;
 697         const struct amdgpu_ras_block_hw_ops *hw_ops;
 698 };
 699
 700 struct amdgpu_ras_block_hw_ops {
 701         int  (*ras_error_inject)(struct amdgpu_device *adev,
 702                         void *inject_if, uint32_t instance_mask);
 703         void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
 704         void (*query_ras_error_status)(struct amdgpu_device *adev);
 705         void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
 706         void (*reset_ras_error_count)(struct amdgpu_device *adev);
 707         void (*reset_ras_error_status)(struct amdgpu_device *adev);
 708         bool (*query_poison_status)(struct amdgpu_device *adev);
 709         bool (*handle_poison_consumption)(struct amdgpu_device *adev);
 710 };
 711
 712 /* work flow
 713  * vbios
 714  * 1: ras feature enable (enabled by default)
 715  * psp
 716  * 2: ras framework init (in ip_init)
 717  * IP
 718  * 3: IH add
 719  * 4: debugfs/sysfs create
 720  * 5: query/inject
 721  * 6: debugfs/sysfs remove
 722  * 7: IH remove
 723  * 8: feature disable
 724  */
 725
 726
 727 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
 728
 729 void amdgpu_ras_resume(struct amdgpu_device *adev);
 730 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 731
 732 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 733                                  unsigned long *ce_count,
 734                                  unsigned long *ue_count,
 735                                  struct ras_query_if *query_info);
 736
 737 /* error handling functions */
 738 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 739                 struct eeprom_table_record *bps, int pages);
 740
 741 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
 742                 unsigned long *new_cnt);
 743
 744 static inline enum ta_ras_block
 745 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
 746         switch (block) {
 747         case AMDGPU_RAS_BLOCK__UMC:
 748                 return TA_RAS_BLOCK__UMC;
 749         case AMDGPU_RAS_BLOCK__SDMA:
 750                 return TA_RAS_BLOCK__SDMA;
 751         case AMDGPU_RAS_BLOCK__GFX:
 752                 return TA_RAS_BLOCK__GFX;
 753         case AMDGPU_RAS_BLOCK__MMHUB:
 754                 return TA_RAS_BLOCK__MMHUB;
 755         case AMDGPU_RAS_BLOCK__ATHUB:
 756                 return TA_RAS_BLOCK__ATHUB;
 757         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 758                 return TA_RAS_BLOCK__PCIE_BIF;
 759         case AMDGPU_RAS_BLOCK__HDP:
 760                 return TA_RAS_BLOCK__HDP;
 761         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 762                 return TA_RAS_BLOCK__XGMI_WAFL;
 763         case AMDGPU_RAS_BLOCK__DF:
 764                 return TA_RAS_BLOCK__DF;
 765         case AMDGPU_RAS_BLOCK__SMN:
 766                 return TA_RAS_BLOCK__SMN;
 767         case AMDGPU_RAS_BLOCK__SEM:
 768                 return TA_RAS_BLOCK__SEM;
 769         case AMDGPU_RAS_BLOCK__MP0:
 770                 return TA_RAS_BLOCK__MP0;
 771         case AMDGPU_RAS_BLOCK__MP1:
 772                 return TA_RAS_BLOCK__MP1;
 773         case AMDGPU_RAS_BLOCK__FUSE:
 774                 return TA_RAS_BLOCK__FUSE;
 775         case AMDGPU_RAS_BLOCK__MCA:
 776                 return TA_RAS_BLOCK__MCA;
 777         case AMDGPU_RAS_BLOCK__VCN:
 778                 return TA_RAS_BLOCK__VCN;
 779         case AMDGPU_RAS_BLOCK__JPEG:
 780                 return TA_RAS_BLOCK__JPEG;
 781         default:
 782                 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
 783                 return TA_RAS_BLOCK__UMC;
 784         }
 785 }
 786
 787 static inline enum ta_ras_error_type
 788 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
 789         switch (error) {
 790         case AMDGPU_RAS_ERROR__NONE:
 791                 return TA_RAS_ERROR__NONE;
 792         case AMDGPU_RAS_ERROR__PARITY:
 793                 return TA_RAS_ERROR__PARITY;
 794         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
 795                 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
 796         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
 797                 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
 798         case AMDGPU_RAS_ERROR__POISON:
 799                 return TA_RAS_ERROR__POISON;
 800         default:
 801                 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
 802                 return TA_RAS_ERROR__NONE;
 803         }
 804 }
 805
 806 /* called in ip_init and ip_fini */
 807 int amdgpu_ras_init(struct amdgpu_device *adev);
 808 int amdgpu_ras_late_init(struct amdgpu_device *adev);
 809 int amdgpu_ras_fini(struct amdgpu_device *adev);
 810 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
 811
 812 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
 813                         struct ras_common_if *ras_block);
 814
 815 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
 816                           struct ras_common_if *ras_block);
 817
 818 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 819                 struct ras_common_if *head, bool enable);
 820
 821 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 822                 struct ras_common_if *head, bool enable);
 823
 824 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
 825                 struct ras_common_if *head);
 826
 827 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
 828                 struct ras_common_if *head);
 829
 830 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 831
 832 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 833                 struct ras_query_if *info);
 834
 835 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
 836                 enum amdgpu_ras_block block);
 837 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 838                 enum amdgpu_ras_block block);
 839
 840 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 841                 struct ras_inject_if *info);
 842
 843 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
 844                 struct ras_common_if *head);
 845
 846 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
 847                 struct ras_common_if *head);
 848
 849 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
 850                 struct ras_dispatch_if *info);
 851
 852 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 853                 struct ras_common_if *head);
 854
 855 extern atomic_t amdgpu_ras_in_intr;
 856
 857 static inline bool amdgpu_ras_intr_triggered(void)
 858 {
 859         return !!atomic_read(&amdgpu_ras_in_intr);
 860 }
 861
 862 static inline void amdgpu_ras_intr_cleared(void)
 863 {
 864         atomic_set(&amdgpu_ras_in_intr, 0);
 865 }
 866
 867 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
 868
 869 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 870
 871 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 872
 873 void amdgpu_release_ras_context(struct amdgpu_device *adev);
 874
 875 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
 876
 877 const char *get_ras_block_str(struct ras_common_if *ras_block);
 878
 879 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
 880
 881 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
 882
 883 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
 884
 885 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
 886
 887 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
 888
 889 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);
 890 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable);
 891 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev);
 892 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
 893                                      unsigned int *mode);
 894
 895 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
 896                                 struct amdgpu_ras_block_object *ras_block_obj);
 897 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
 898 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);
 899 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
 900                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
 901                                          uint32_t instance,
 902                                          uint32_t *memory_id);
 903 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
 904                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
 905                                        uint32_t instance,
 906                                        unsigned long *err_cnt);
 907 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
 908                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
 909                                            uint32_t reg_list_size,
 910                                            const struct amdgpu_ras_memory_id_entry *mem_list,
 911                                            uint32_t mem_list_size,
 912                                            uint32_t instance,
 913                                            uint32_t err_type,
 914                                            unsigned long *err_count);
 915 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
 916                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
 917                                            uint32_t reg_list_size,
 918                                            uint32_t instance);
 919
 920 int amdgpu_ras_error_data_init(struct ras_err_data *err_data);
 921 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data);
 922 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
 923                 struct amdgpu_smuio_mcm_config_info *mcm_info,
 924                 struct ras_err_addr *err_addr, u64 count);
 925 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
 926                 struct amdgpu_smuio_mcm_config_info *mcm_info,
 927                 struct ras_err_addr *err_addr, u64 count);
 928 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,
 929                 struct amdgpu_smuio_mcm_config_info *mcm_info,
 930                 struct ras_err_addr *err_addr, u64 count);
 931 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances);
 932 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
 933                                const struct aca_info *aca_info, void *data);
 934 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk);
 935
 936 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr,
 937                                   struct aca_handle *handle, char *buf, void *data);
 938
 939 void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info,
 940                         struct ras_err_addr *err_addr);
 941
 942 void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info,
 943                 struct ras_err_addr *mca_err_addr);
 944
 945 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status);
 946 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev);
 947
 948 bool amdgpu_ras_event_id_is_valid(struct amdgpu_device *adev, u64 id);
 949 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type);
 950
 951 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn);
 952
 953 int amdgpu_ras_put_poison_req(struct amdgpu_device *adev,
 954                 enum amdgpu_ras_block block, uint16_t pasid,
 955                 pasid_notify pasid_fn, void *data, uint32_t reset);
 956
 957 bool amdgpu_ras_in_recovery(struct amdgpu_device *adev);
 958
 959 __printf(3, 4)
 960 void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
 961                                 const char *fmt, ...);
 962
 963 #endif