drivers/net/ethernet/xscale/ixp4xx_eth.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Intel IXP4xx Ethernet driver for Linux
   4  *
   5  * Copyright (C) 2007 Krzysztof Halasa <[email protected]>
   6  *
   7  * Ethernet port config (0x00 is not present on IXP42X):
   8  *
   9  * logical port         0x00            0x10            0x20
  10  * NPE                  0 (NPE-A)       1 (NPE-B)       2 (NPE-C)
  11  * physical PortId      2               0               1
  12  * TX queue             23              24              25
  13  * RX-free queue        26              27              28
  14  * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
  15  *
  16  * Queue entries:
  17  * bits 0 -> 1  - NPE ID (RX and TX-done)
  18  * bits 0 -> 2  - priority (TX, per 802.1D)
  19  * bits 3 -> 4  - port ID (user-set?)
  20  * bits 5 -> 31 - physical descriptor address
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmapool.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/io.h>
  28 #include <linux/kernel.h>
  29 #include <linux/net_tstamp.h>
  30 #include <linux/of.h>
  31 #include <linux/of_mdio.h>
  32 #include <linux/phy.h>
  33 #include <linux/platform_data/eth_ixp4xx.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/ptp_classify.h>
  36 #include <linux/slab.h>
  37 #include <linux/module.h>
  38 #include <linux/soc/ixp4xx/npe.h>
  39 #include <linux/soc/ixp4xx/qmgr.h>
  40
  41 #include "ixp46x_ts.h"
  42
  43 #define DEBUG_DESC              0
  44 #define DEBUG_RX                0
  45 #define DEBUG_TX                0
  46 #define DEBUG_PKT_BYTES         0
  47 #define DEBUG_MDIO              0
  48 #define DEBUG_CLOSE             0
  49
  50 #define DRV_NAME                "ixp4xx_eth"
  51
  52 #define MAX_NPES                3
  53
  54 #define RX_DESCS                64 /* also length of all RX queues */
  55 #define TX_DESCS                16 /* also length of all TX queues */
  56 #define TXDONE_QUEUE_LEN        64 /* dwords */
  57
  58 #define POOL_ALLOC_SIZE         (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
  59 #define REGS_SIZE               0x1000
  60 #define MAX_MRU                 1536 /* 0x600 */
  61 #define RX_BUFF_SIZE            ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
  62
  63 #define NAPI_WEIGHT             16
  64 #define MDIO_INTERVAL           (3 * HZ)
  65 #define MAX_MDIO_RETRIES        100 /* microseconds, typically 30 cycles */
  66 #define MAX_CLOSE_WAIT          1000 /* microseconds, typically 2-3 cycles */
  67
  68 #define NPE_ID(port_id)         ((port_id) >> 4)
  69 #define PHYSICAL_ID(port_id)    ((NPE_ID(port_id) + 2) % 3)
  70 #define TX_QUEUE(port_id)       (NPE_ID(port_id) + 23)
  71 #define RXFREE_QUEUE(port_id)   (NPE_ID(port_id) + 26)
  72 #define TXDONE_QUEUE            31
  73
  74 #define PTP_SLAVE_MODE          1
  75 #define PTP_MASTER_MODE         2
  76 #define PORT2CHANNEL(p)         NPE_ID(p->id)
  77
  78 /* TX Control Registers */
  79 #define TX_CNTRL0_TX_EN         0x01
  80 #define TX_CNTRL0_HALFDUPLEX    0x02
  81 #define TX_CNTRL0_RETRY         0x04
  82 #define TX_CNTRL0_PAD_EN        0x08
  83 #define TX_CNTRL0_APPEND_FCS    0x10
  84 #define TX_CNTRL0_2DEFER        0x20
  85 #define TX_CNTRL0_RMII          0x40 /* reduced MII */
  86 #define TX_CNTRL1_RETRIES       0x0F /* 4 bits */
  87
  88 /* RX Control Registers */
  89 #define RX_CNTRL0_RX_EN         0x01
  90 #define RX_CNTRL0_PADSTRIP_EN   0x02
  91 #define RX_CNTRL0_SEND_FCS      0x04
  92 #define RX_CNTRL0_PAUSE_EN      0x08
  93 #define RX_CNTRL0_LOOP_EN       0x10
  94 #define RX_CNTRL0_ADDR_FLTR_EN  0x20
  95 #define RX_CNTRL0_RX_RUNT_EN    0x40
  96 #define RX_CNTRL0_BCAST_DIS     0x80
  97 #define RX_CNTRL1_DEFER_EN      0x01
  98
  99 /* Core Control Register */
 100 #define CORE_RESET              0x01
 101 #define CORE_RX_FIFO_FLUSH      0x02
 102 #define CORE_TX_FIFO_FLUSH      0x04
 103 #define CORE_SEND_JAM           0x08
 104 #define CORE_MDC_EN             0x10 /* MDIO using NPE-B ETH-0 only */
 105
 106 #define DEFAULT_TX_CNTRL0       (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY |    \
 107                                  TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
 108                                  TX_CNTRL0_2DEFER)
 109 #define DEFAULT_RX_CNTRL0       RX_CNTRL0_RX_EN
 110 #define DEFAULT_CORE_CNTRL      CORE_MDC_EN
 111
 112
 113 /* NPE message codes */
 114 #define NPE_GETSTATUS                   0x00
 115 #define NPE_EDB_SETPORTADDRESS          0x01
 116 #define NPE_EDB_GETMACADDRESSDATABASE   0x02
 117 #define NPE_EDB_SETMACADDRESSSDATABASE  0x03
 118 #define NPE_GETSTATS                    0x04
 119 #define NPE_RESETSTATS                  0x05
 120 #define NPE_SETMAXFRAMELENGTHS          0x06
 121 #define NPE_VLAN_SETRXTAGMODE           0x07
 122 #define NPE_VLAN_SETDEFAULTRXVID        0x08
 123 #define NPE_VLAN_SETPORTVLANTABLEENTRY  0x09
 124 #define NPE_VLAN_SETPORTVLANTABLERANGE  0x0A
 125 #define NPE_VLAN_SETRXQOSENTRY          0x0B
 126 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
 127 #define NPE_STP_SETBLOCKINGSTATE        0x0D
 128 #define NPE_FW_SETFIREWALLMODE          0x0E
 129 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
 130 #define NPE_PC_SETAPMACTABLE            0x11
 131 #define NPE_SETLOOPBACK_MODE            0x12
 132 #define NPE_PC_SETBSSIDTABLE            0x13
 133 #define NPE_ADDRESS_FILTER_CONFIG       0x14
 134 #define NPE_APPENDFCSCONFIG             0x15
 135 #define NPE_NOTIFY_MAC_RECOVERY_DONE    0x16
 136 #define NPE_MAC_RECOVERY_START          0x17
 137
 138
 139 #ifdef __ARMEB__
 140 typedef struct sk_buff buffer_t;
 141 #define free_buffer dev_kfree_skb
 142 #define free_buffer_irq dev_consume_skb_irq
 143 #else
 144 typedef void buffer_t;
 145 #define free_buffer kfree
 146 #define free_buffer_irq kfree
 147 #endif
 148
 149 struct eth_regs {
 150         u32 tx_control[2], __res1[2];           /* 000 */
 151         u32 rx_control[2], __res2[2];           /* 010 */
 152         u32 random_seed, __res3[3];             /* 020 */
 153         u32 partial_empty_threshold, __res4;    /* 030 */
 154         u32 partial_full_threshold, __res5;     /* 038 */
 155         u32 tx_start_bytes, __res6[3];          /* 040 */
 156         u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
 157         u32 tx_2part_deferral[2], __res8[2];    /* 060 */
 158         u32 slot_time, __res9[3];               /* 070 */
 159         u32 mdio_command[4];                    /* 080 */
 160         u32 mdio_status[4];                     /* 090 */
 161         u32 mcast_mask[6], __res10[2];          /* 0A0 */
 162         u32 mcast_addr[6], __res11[2];          /* 0C0 */
 163         u32 int_clock_threshold, __res12[3];    /* 0E0 */
 164         u32 hw_addr[6], __res13[61];            /* 0F0 */
 165         u32 core_control;                       /* 1FC */
 166 };
 167
 168 struct port {
 169         struct eth_regs __iomem *regs;
 170         struct npe *npe;
 171         struct net_device *netdev;
 172         struct napi_struct napi;
 173         struct eth_plat_info *plat;
 174         buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
 175         struct desc *desc_tab;  /* coherent */
 176         u32 desc_tab_phys;
 177         int id;                 /* logical port ID */
 178         int speed, duplex;
 179         u8 firmware[4];
 180         int hwts_tx_en;
 181         int hwts_rx_en;
 182 };
 183
 184 /* NPE message structure */
 185 struct msg {
 186 #ifdef __ARMEB__
 187         u8 cmd, eth_id, byte2, byte3;
 188         u8 byte4, byte5, byte6, byte7;
 189 #else
 190         u8 byte3, byte2, eth_id, cmd;
 191         u8 byte7, byte6, byte5, byte4;
 192 #endif
 193 };
 194
 195 /* Ethernet packet descriptor */
 196 struct desc {
 197         u32 next;               /* pointer to next buffer, unused */
 198
 199 #ifdef __ARMEB__
 200         u16 buf_len;            /* buffer length */
 201         u16 pkt_len;            /* packet length */
 202         u32 data;               /* pointer to data buffer in RAM */
 203         u8 dest_id;
 204         u8 src_id;
 205         u16 flags;
 206         u8 qos;
 207         u8 padlen;
 208         u16 vlan_tci;
 209 #else
 210         u16 pkt_len;            /* packet length */
 211         u16 buf_len;            /* buffer length */
 212         u32 data;               /* pointer to data buffer in RAM */
 213         u16 flags;
 214         u8 src_id;
 215         u8 dest_id;
 216         u16 vlan_tci;
 217         u8 padlen;
 218         u8 qos;
 219 #endif
 220
 221 #ifdef __ARMEB__
 222         u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
 223         u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
 224         u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
 225 #else
 226         u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
 227         u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
 228         u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
 229 #endif
 230 };
 231
 232
 233 #define rx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
 234                                  (n) * sizeof(struct desc))
 235 #define rx_desc_ptr(port, n)    (&(port)->desc_tab[n])
 236
 237 #define tx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
 238                                  ((n) + RX_DESCS) * sizeof(struct desc))
 239 #define tx_desc_ptr(port, n)    (&(port)->desc_tab[(n) + RX_DESCS])
 240
 241 #ifndef __ARMEB__
 242 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
 243 {
 244         int i;
 245         for (i = 0; i < cnt; i++)
 246                 dest[i] = swab32(src[i]);
 247 }
 248 #endif
 249
 250 static DEFINE_SPINLOCK(mdio_lock);
 251 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
 252 static struct mii_bus *mdio_bus;
 253 static struct device_node *mdio_bus_np;
 254 static int ports_open;
 255 static struct port *npe_port_tab[MAX_NPES];
 256 static struct dma_pool *dma_pool;
 257
 258 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 259 {
 260         u8 *data = skb->data;
 261         unsigned int offset;
 262         u16 *hi, *id;
 263         u32 lo;
 264
 265         if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4)
 266                 return 0;
 267
 268         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 269
 270         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 271                 return 0;
 272
 273         hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
 274         id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 275
 276         memcpy(&lo, &hi[1], sizeof(lo));
 277
 278         return (uid_hi == ntohs(*hi) &&
 279                 uid_lo == ntohl(lo) &&
 280                 seqid  == ntohs(*id));
 281 }
 282
 283 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
 284 {
 285         struct skb_shared_hwtstamps *shhwtstamps;
 286         struct ixp46x_ts_regs *regs;
 287         u64 ns;
 288         u32 ch, hi, lo, val;
 289         u16 uid, seq;
 290
 291         if (!port->hwts_rx_en)
 292                 return;
 293
 294         ch = PORT2CHANNEL(port);
 295
 296         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 297
 298         val = __raw_readl(&regs->channel[ch].ch_event);
 299
 300         if (!(val & RX_SNAPSHOT_LOCKED))
 301                 return;
 302
 303         lo = __raw_readl(&regs->channel[ch].src_uuid_lo);
 304         hi = __raw_readl(&regs->channel[ch].src_uuid_hi);
 305
 306         uid = hi & 0xffff;
 307         seq = (hi >> 16) & 0xffff;
 308
 309         if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
 310                 goto out;
 311
 312         lo = __raw_readl(&regs->channel[ch].rx_snap_lo);
 313         hi = __raw_readl(&regs->channel[ch].rx_snap_hi);
 314         ns = ((u64) hi) << 32;
 315         ns |= lo;
 316         ns <<= TICKS_NS_SHIFT;
 317
 318         shhwtstamps = skb_hwtstamps(skb);
 319         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 320         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 321 out:
 322         __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
 323 }
 324
 325 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
 326 {
 327         struct skb_shared_hwtstamps shhwtstamps;
 328         struct ixp46x_ts_regs *regs;
 329         struct skb_shared_info *shtx;
 330         u64 ns;
 331         u32 ch, cnt, hi, lo, val;
 332
 333         shtx = skb_shinfo(skb);
 334         if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
 335                 shtx->tx_flags |= SKBTX_IN_PROGRESS;
 336         else
 337                 return;
 338
 339         ch = PORT2CHANNEL(port);
 340
 341         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 342
 343         /*
 344          * This really stinks, but we have to poll for the Tx time stamp.
 345          * Usually, the time stamp is ready after 4 to 6 microseconds.
 346          */
 347         for (cnt = 0; cnt < 100; cnt++) {
 348                 val = __raw_readl(&regs->channel[ch].ch_event);
 349                 if (val & TX_SNAPSHOT_LOCKED)
 350                         break;
 351                 udelay(1);
 352         }
 353         if (!(val & TX_SNAPSHOT_LOCKED)) {
 354                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 355                 return;
 356         }
 357
 358         lo = __raw_readl(&regs->channel[ch].tx_snap_lo);
 359         hi = __raw_readl(&regs->channel[ch].tx_snap_hi);
 360         ns = ((u64) hi) << 32;
 361         ns |= lo;
 362         ns <<= TICKS_NS_SHIFT;
 363
 364         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 365         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 366         skb_tstamp_tx(skb, &shhwtstamps);
 367
 368         __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
 369 }
 370
 371 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 372 {
 373         struct hwtstamp_config cfg;
 374         struct ixp46x_ts_regs *regs;
 375         struct port *port = netdev_priv(netdev);
 376         int ch;
 377
 378         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 379                 return -EFAULT;
 380
 381         if (cfg.flags) /* reserved for future extensions */
 382                 return -EINVAL;
 383
 384         ch = PORT2CHANNEL(port);
 385         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 386
 387         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 388                 return -ERANGE;
 389
 390         switch (cfg.rx_filter) {
 391         case HWTSTAMP_FILTER_NONE:
 392                 port->hwts_rx_en = 0;
 393                 break;
 394         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 395                 port->hwts_rx_en = PTP_SLAVE_MODE;
 396                 __raw_writel(0, &regs->channel[ch].ch_control);
 397                 break;
 398         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 399                 port->hwts_rx_en = PTP_MASTER_MODE;
 400                 __raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);
 401                 break;
 402         default:
 403                 return -ERANGE;
 404         }
 405
 406         port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
 407
 408         /* Clear out any old time stamps. */
 409         __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
 410                      &regs->channel[ch].ch_event);
 411
 412         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 413 }
 414
 415 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 416 {
 417         struct hwtstamp_config cfg;
 418         struct port *port = netdev_priv(netdev);
 419
 420         cfg.flags = 0;
 421         cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 422
 423         switch (port->hwts_rx_en) {
 424         case 0:
 425                 cfg.rx_filter = HWTSTAMP_FILTER_NONE;
 426                 break;
 427         case PTP_SLAVE_MODE:
 428                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 429                 break;
 430         case PTP_MASTER_MODE:
 431                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 432                 break;
 433         default:
 434                 WARN_ON_ONCE(1);
 435                 return -ERANGE;
 436         }
 437
 438         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 439 }
 440
 441 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
 442                            int write, u16 cmd)
 443 {
 444         int cycles = 0;
 445
 446         if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
 447                 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
 448                 return -1;
 449         }
 450
 451         if (write) {
 452                 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
 453                 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
 454         }
 455         __raw_writel(((phy_id << 5) | location) & 0xFF,
 456                      &mdio_regs->mdio_command[2]);
 457         __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
 458                      &mdio_regs->mdio_command[3]);
 459
 460         while ((cycles < MAX_MDIO_RETRIES) &&
 461                (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
 462                 udelay(1);
 463                 cycles++;
 464         }
 465
 466         if (cycles == MAX_MDIO_RETRIES) {
 467                 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
 468                        phy_id);
 469                 return -1;
 470         }
 471
 472 #if DEBUG_MDIO
 473         printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
 474                phy_id, write ? "write" : "read", cycles);
 475 #endif
 476
 477         if (write)
 478                 return 0;
 479
 480         if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
 481 #if DEBUG_MDIO
 482                 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
 483                        phy_id);
 484 #endif
 485                 return 0xFFFF; /* don't return error */
 486         }
 487
 488         return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
 489                 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
 490 }
 491
 492 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
 493 {
 494         unsigned long flags;
 495         int ret;
 496
 497         spin_lock_irqsave(&mdio_lock, flags);
 498         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
 499         spin_unlock_irqrestore(&mdio_lock, flags);
 500 #if DEBUG_MDIO
 501         printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
 502                phy_id, location, ret);
 503 #endif
 504         return ret;
 505 }
 506
 507 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
 508                              u16 val)
 509 {
 510         unsigned long flags;
 511         int ret;
 512
 513         spin_lock_irqsave(&mdio_lock, flags);
 514         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
 515         spin_unlock_irqrestore(&mdio_lock, flags);
 516 #if DEBUG_MDIO
 517         printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
 518                bus->name, phy_id, location, val, ret);
 519 #endif
 520         return ret;
 521 }
 522
 523 static int ixp4xx_mdio_register(struct eth_regs __iomem *regs)
 524 {
 525         int err;
 526
 527         if (!(mdio_bus = mdiobus_alloc()))
 528                 return -ENOMEM;
 529
 530         mdio_regs = regs;
 531         __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
 532         mdio_bus->name = "IXP4xx MII Bus";
 533         mdio_bus->read = &ixp4xx_mdio_read;
 534         mdio_bus->write = &ixp4xx_mdio_write;
 535         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
 536
 537         err = of_mdiobus_register(mdio_bus, mdio_bus_np);
 538         if (err)
 539                 mdiobus_free(mdio_bus);
 540         return err;
 541 }
 542
 543 static void ixp4xx_mdio_remove(void)
 544 {
 545         mdiobus_unregister(mdio_bus);
 546         mdiobus_free(mdio_bus);
 547 }
 548
 549
 550 static void ixp4xx_adjust_link(struct net_device *dev)
 551 {
 552         struct port *port = netdev_priv(dev);
 553         struct phy_device *phydev = dev->phydev;
 554
 555         if (!phydev->link) {
 556                 if (port->speed) {
 557                         port->speed = 0;
 558                         printk(KERN_INFO "%s: link down\n", dev->name);
 559                 }
 560                 return;
 561         }
 562
 563         if (port->speed == phydev->speed && port->duplex == phydev->duplex)
 564                 return;
 565
 566         port->speed = phydev->speed;
 567         port->duplex = phydev->duplex;
 568
 569         if (port->duplex)
 570                 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
 571                              &port->regs->tx_control[0]);
 572         else
 573                 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
 574                              &port->regs->tx_control[0]);
 575
 576         netdev_info(dev, "%s: link up, speed %u Mb/s, %s duplex\n",
 577                     dev->name, port->speed, port->duplex ? "full" : "half");
 578 }
 579
 580
 581 static inline void debug_pkt(struct net_device *dev, const char *func,
 582                              u8 *data, int len)
 583 {
 584 #if DEBUG_PKT_BYTES
 585         int i;
 586
 587         netdev_debug(dev, "%s(%i) ", func, len);
 588         for (i = 0; i < len; i++) {
 589                 if (i >= DEBUG_PKT_BYTES)
 590                         break;
 591                 printk("%s%02X",
 592                        ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
 593                        data[i]);
 594         }
 595         printk("\n");
 596 #endif
 597 }
 598
 599
 600 static inline void debug_desc(u32 phys, struct desc *desc)
 601 {
 602 #if DEBUG_DESC
 603         printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
 604                " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
 605                phys, desc->next, desc->buf_len, desc->pkt_len,
 606                desc->data, desc->dest_id, desc->src_id, desc->flags,
 607                desc->qos, desc->padlen, desc->vlan_tci,
 608                desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
 609                desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
 610                desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
 611                desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
 612 #endif
 613 }
 614
 615 static inline int queue_get_desc(unsigned int queue, struct port *port,
 616                                  int is_tx)
 617 {
 618         u32 phys, tab_phys, n_desc;
 619         struct desc *tab;
 620
 621         if (!(phys = qmgr_get_entry(queue)))
 622                 return -1;
 623
 624         phys &= ~0x1F; /* mask out non-address bits */
 625         tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
 626         tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
 627         n_desc = (phys - tab_phys) / sizeof(struct desc);
 628         BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
 629         debug_desc(phys, &tab[n_desc]);
 630         BUG_ON(tab[n_desc].next);
 631         return n_desc;
 632 }
 633
 634 static inline void queue_put_desc(unsigned int queue, u32 phys,
 635                                   struct desc *desc)
 636 {
 637         debug_desc(phys, desc);
 638         BUG_ON(phys & 0x1F);
 639         qmgr_put_entry(queue, phys);
 640         /* Don't check for queue overflow here, we've allocated sufficient
 641            length and queues >= 32 don't support this check anyway. */
 642 }
 643
 644
 645 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
 646 {
 647 #ifdef __ARMEB__
 648         dma_unmap_single(&port->netdev->dev, desc->data,
 649                          desc->buf_len, DMA_TO_DEVICE);
 650 #else
 651         dma_unmap_single(&port->netdev->dev, desc->data & ~3,
 652                          ALIGN((desc->data & 3) + desc->buf_len, 4),
 653                          DMA_TO_DEVICE);
 654 #endif
 655 }
 656
 657
 658 static void eth_rx_irq(void *pdev)
 659 {
 660         struct net_device *dev = pdev;
 661         struct port *port = netdev_priv(dev);
 662
 663 #if DEBUG_RX
 664         printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
 665 #endif
 666         qmgr_disable_irq(port->plat->rxq);
 667         napi_schedule(&port->napi);
 668 }
 669
 670 static int eth_poll(struct napi_struct *napi, int budget)
 671 {
 672         struct port *port = container_of(napi, struct port, napi);
 673         struct net_device *dev = port->netdev;
 674         unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
 675         int received = 0;
 676
 677 #if DEBUG_RX
 678         netdev_debug(dev, "eth_poll\n");
 679 #endif
 680
 681         while (received < budget) {
 682                 struct sk_buff *skb;
 683                 struct desc *desc;
 684                 int n;
 685 #ifdef __ARMEB__
 686                 struct sk_buff *temp;
 687                 u32 phys;
 688 #endif
 689
 690                 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
 691 #if DEBUG_RX
 692                         netdev_debug(dev, "eth_poll napi_complete\n");
 693 #endif
 694                         napi_complete(napi);
 695                         qmgr_enable_irq(rxq);
 696                         if (!qmgr_stat_below_low_watermark(rxq) &&
 697                             napi_reschedule(napi)) { /* not empty again */
 698 #if DEBUG_RX
 699                                 netdev_debug(dev, "eth_poll napi_reschedule succeeded\n");
 700 #endif
 701                                 qmgr_disable_irq(rxq);
 702                                 continue;
 703                         }
 704 #if DEBUG_RX
 705                         netdev_debug(dev, "eth_poll all done\n");
 706 #endif
 707                         return received; /* all work done */
 708                 }
 709
 710                 desc = rx_desc_ptr(port, n);
 711
 712 #ifdef __ARMEB__
 713                 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
 714                         phys = dma_map_single(&dev->dev, skb->data,
 715                                               RX_BUFF_SIZE, DMA_FROM_DEVICE);
 716                         if (dma_mapping_error(&dev->dev, phys)) {
 717                                 dev_kfree_skb(skb);
 718                                 skb = NULL;
 719                         }
 720                 }
 721 #else
 722                 skb = netdev_alloc_skb(dev,
 723                                        ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
 724 #endif
 725
 726                 if (!skb) {
 727                         dev->stats.rx_dropped++;
 728                         /* put the desc back on RX-ready queue */
 729                         desc->buf_len = MAX_MRU;
 730                         desc->pkt_len = 0;
 731                         queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 732                         continue;
 733                 }
 734
 735                 /* process received frame */
 736 #ifdef __ARMEB__
 737                 temp = skb;
 738                 skb = port->rx_buff_tab[n];
 739                 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
 740                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
 741 #else
 742                 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
 743                                         RX_BUFF_SIZE, DMA_FROM_DEVICE);
 744                 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
 745                               ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
 746 #endif
 747                 skb_reserve(skb, NET_IP_ALIGN);
 748                 skb_put(skb, desc->pkt_len);
 749
 750                 debug_pkt(dev, "eth_poll", skb->data, skb->len);
 751
 752                 ixp_rx_timestamp(port, skb);
 753                 skb->protocol = eth_type_trans(skb, dev);
 754                 dev->stats.rx_packets++;
 755                 dev->stats.rx_bytes += skb->len;
 756                 netif_receive_skb(skb);
 757
 758                 /* put the new buffer on RX-free queue */
 759 #ifdef __ARMEB__
 760                 port->rx_buff_tab[n] = temp;
 761                 desc->data = phys + NET_IP_ALIGN;
 762 #endif
 763                 desc->buf_len = MAX_MRU;
 764                 desc->pkt_len = 0;
 765                 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 766                 received++;
 767         }
 768
 769 #if DEBUG_RX
 770         netdev_debug(dev, "eth_poll(): end, not all work done\n");
 771 #endif
 772         return received;                /* not all work done */
 773 }
 774
 775
 776 static void eth_txdone_irq(void *unused)
 777 {
 778         u32 phys;
 779
 780 #if DEBUG_TX
 781         printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
 782 #endif
 783         while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
 784                 u32 npe_id, n_desc;
 785                 struct port *port;
 786                 struct desc *desc;
 787                 int start;
 788
 789                 npe_id = phys & 3;
 790                 BUG_ON(npe_id >= MAX_NPES);
 791                 port = npe_port_tab[npe_id];
 792                 BUG_ON(!port);
 793                 phys &= ~0x1F; /* mask out non-address bits */
 794                 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
 795                 BUG_ON(n_desc >= TX_DESCS);
 796                 desc = tx_desc_ptr(port, n_desc);
 797                 debug_desc(phys, desc);
 798
 799                 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
 800                         port->netdev->stats.tx_packets++;
 801                         port->netdev->stats.tx_bytes += desc->pkt_len;
 802
 803                         dma_unmap_tx(port, desc);
 804 #if DEBUG_TX
 805                         printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
 806                                port->netdev->name, port->tx_buff_tab[n_desc]);
 807 #endif
 808                         free_buffer_irq(port->tx_buff_tab[n_desc]);
 809                         port->tx_buff_tab[n_desc] = NULL;
 810                 }
 811
 812                 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
 813                 queue_put_desc(port->plat->txreadyq, phys, desc);
 814                 if (start) { /* TX-ready queue was empty */
 815 #if DEBUG_TX
 816                         printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
 817                                port->netdev->name);
 818 #endif
 819                         netif_wake_queue(port->netdev);
 820                 }
 821         }
 822 }
 823
 824 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 825 {
 826         struct port *port = netdev_priv(dev);
 827         unsigned int txreadyq = port->plat->txreadyq;
 828         int len, offset, bytes, n;
 829         void *mem;
 830         u32 phys;
 831         struct desc *desc;
 832
 833 #if DEBUG_TX
 834         netdev_debug(dev, "eth_xmit\n");
 835 #endif
 836
 837         if (unlikely(skb->len > MAX_MRU)) {
 838                 dev_kfree_skb(skb);
 839                 dev->stats.tx_errors++;
 840                 return NETDEV_TX_OK;
 841         }
 842
 843         debug_pkt(dev, "eth_xmit", skb->data, skb->len);
 844
 845         len = skb->len;
 846 #ifdef __ARMEB__
 847         offset = 0; /* no need to keep alignment */
 848         bytes = len;
 849         mem = skb->data;
 850 #else
 851         offset = (int)skb->data & 3; /* keep 32-bit alignment */
 852         bytes = ALIGN(offset + len, 4);
 853         if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
 854                 dev_kfree_skb(skb);
 855                 dev->stats.tx_dropped++;
 856                 return NETDEV_TX_OK;
 857         }
 858         memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
 859 #endif
 860
 861         phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
 862         if (dma_mapping_error(&dev->dev, phys)) {
 863                 dev_kfree_skb(skb);
 864 #ifndef __ARMEB__
 865                 kfree(mem);
 866 #endif
 867                 dev->stats.tx_dropped++;
 868                 return NETDEV_TX_OK;
 869         }
 870
 871         n = queue_get_desc(txreadyq, port, 1);
 872         BUG_ON(n < 0);
 873         desc = tx_desc_ptr(port, n);
 874
 875 #ifdef __ARMEB__
 876         port->tx_buff_tab[n] = skb;
 877 #else
 878         port->tx_buff_tab[n] = mem;
 879 #endif
 880         desc->data = phys + offset;
 881         desc->buf_len = desc->pkt_len = len;
 882
 883         /* NPE firmware pads short frames with zeros internally */
 884         wmb();
 885         queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
 886
 887         if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
 888 #if DEBUG_TX
 889                 netdev_debug(dev, "eth_xmit queue full\n");
 890 #endif
 891                 netif_stop_queue(dev);
 892                 /* we could miss TX ready interrupt */
 893                 /* really empty in fact */
 894                 if (!qmgr_stat_below_low_watermark(txreadyq)) {
 895 #if DEBUG_TX
 896                         netdev_debug(dev, "eth_xmit ready again\n");
 897 #endif
 898                         netif_wake_queue(dev);
 899                 }
 900         }
 901
 902 #if DEBUG_TX
 903         netdev_debug(dev, "eth_xmit end\n");
 904 #endif
 905
 906         ixp_tx_timestamp(port, skb);
 907         skb_tx_timestamp(skb);
 908
 909 #ifndef __ARMEB__
 910         dev_kfree_skb(skb);
 911 #endif
 912         return NETDEV_TX_OK;
 913 }
 914
 915
 916 static void eth_set_mcast_list(struct net_device *dev)
 917 {
 918         struct port *port = netdev_priv(dev);
 919         struct netdev_hw_addr *ha;
 920         u8 diffs[ETH_ALEN], *addr;
 921         int i;
 922         static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
 923
 924         if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) {
 925                 for (i = 0; i < ETH_ALEN; i++) {
 926                         __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
 927                         __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
 928                 }
 929                 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
 930                         &port->regs->rx_control[0]);
 931                 return;
 932         }
 933
 934         if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
 935                 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
 936                              &port->regs->rx_control[0]);
 937                 return;
 938         }
 939
 940         eth_zero_addr(diffs);
 941
 942         addr = NULL;
 943         netdev_for_each_mc_addr(ha, dev) {
 944                 if (!addr)
 945                         addr = ha->addr; /* first MAC address */
 946                 for (i = 0; i < ETH_ALEN; i++)
 947                         diffs[i] |= addr[i] ^ ha->addr[i];
 948         }
 949
 950         for (i = 0; i < ETH_ALEN; i++) {
 951                 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
 952                 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
 953         }
 954
 955         __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
 956                      &port->regs->rx_control[0]);
 957 }
 958
 959
 960 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 961 {
 962         if (!netif_running(dev))
 963                 return -EINVAL;
 964
 965         if (cpu_is_ixp46x()) {
 966                 if (cmd == SIOCSHWTSTAMP)
 967                         return hwtstamp_set(dev, req);
 968                 if (cmd == SIOCGHWTSTAMP)
 969                         return hwtstamp_get(dev, req);
 970         }
 971
 972         return phy_mii_ioctl(dev->phydev, req, cmd);
 973 }
 974
 975 /* ethtool support */
 976
 977 static void ixp4xx_get_drvinfo(struct net_device *dev,
 978                                struct ethtool_drvinfo *info)
 979 {
 980         struct port *port = netdev_priv(dev);
 981
 982         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 983         snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
 984                  port->firmware[0], port->firmware[1],
 985                  port->firmware[2], port->firmware[3]);
 986         strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
 987 }
 988
 989 int ixp46x_phc_index = -1;
 990 EXPORT_SYMBOL_GPL(ixp46x_phc_index);
 991
 992 static int ixp4xx_get_ts_info(struct net_device *dev,
 993                               struct ethtool_ts_info *info)
 994 {
 995         if (!cpu_is_ixp46x()) {
 996                 info->so_timestamping =
 997                         SOF_TIMESTAMPING_TX_SOFTWARE |
 998                         SOF_TIMESTAMPING_RX_SOFTWARE |
 999                         SOF_TIMESTAMPING_SOFTWARE;
1000                 info->phc_index = -1;
1001                 return 0;
1002         }
1003         info->so_timestamping =
1004                 SOF_TIMESTAMPING_TX_HARDWARE |
1005                 SOF_TIMESTAMPING_RX_HARDWARE |
1006                 SOF_TIMESTAMPING_RAW_HARDWARE;
1007         info->phc_index = ixp46x_phc_index;
1008         info->tx_types =
1009                 (1 << HWTSTAMP_TX_OFF) |
1010                 (1 << HWTSTAMP_TX_ON);
1011         info->rx_filters =
1012                 (1 << HWTSTAMP_FILTER_NONE) |
1013                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1014                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1015         return 0;
1016 }
1017
1018 static const struct ethtool_ops ixp4xx_ethtool_ops = {
1019         .get_drvinfo = ixp4xx_get_drvinfo,
1020         .nway_reset = phy_ethtool_nway_reset,
1021         .get_link = ethtool_op_get_link,
1022         .get_ts_info = ixp4xx_get_ts_info,
1023         .get_link_ksettings = phy_ethtool_get_link_ksettings,
1024         .set_link_ksettings = phy_ethtool_set_link_ksettings,
1025 };
1026
1027
1028 static int request_queues(struct port *port)
1029 {
1030         int err;
1031
1032         err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1033                                  "%s:RX-free", port->netdev->name);
1034         if (err)
1035                 return err;
1036
1037         err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1038                                  "%s:RX", port->netdev->name);
1039         if (err)
1040                 goto rel_rxfree;
1041
1042         err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1043                                  "%s:TX", port->netdev->name);
1044         if (err)
1045                 goto rel_rx;
1046
1047         err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1048                                  "%s:TX-ready", port->netdev->name);
1049         if (err)
1050                 goto rel_tx;
1051
1052         /* TX-done queue handles skbs sent out by the NPEs */
1053         if (!ports_open) {
1054                 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1055                                          "%s:TX-done", DRV_NAME);
1056                 if (err)
1057                         goto rel_txready;
1058         }
1059         return 0;
1060
1061 rel_txready:
1062         qmgr_release_queue(port->plat->txreadyq);
1063 rel_tx:
1064         qmgr_release_queue(TX_QUEUE(port->id));
1065 rel_rx:
1066         qmgr_release_queue(port->plat->rxq);
1067 rel_rxfree:
1068         qmgr_release_queue(RXFREE_QUEUE(port->id));
1069         printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1070                port->netdev->name);
1071         return err;
1072 }
1073
1074 static void release_queues(struct port *port)
1075 {
1076         qmgr_release_queue(RXFREE_QUEUE(port->id));
1077         qmgr_release_queue(port->plat->rxq);
1078         qmgr_release_queue(TX_QUEUE(port->id));
1079         qmgr_release_queue(port->plat->txreadyq);
1080
1081         if (!ports_open)
1082                 qmgr_release_queue(TXDONE_QUEUE);
1083 }
1084
1085 static int init_queues(struct port *port)
1086 {
1087         int i;
1088
1089         if (!ports_open) {
1090                 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1091                                            POOL_ALLOC_SIZE, 32, 0);
1092                 if (!dma_pool)
1093                         return -ENOMEM;
1094         }
1095
1096         if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1097                                               &port->desc_tab_phys)))
1098                 return -ENOMEM;
1099         memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1100         memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1101         memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1102
1103         /* Setup RX buffers */
1104         for (i = 0; i < RX_DESCS; i++) {
1105                 struct desc *desc = rx_desc_ptr(port, i);
1106                 buffer_t *buff; /* skb or kmalloc()ated memory */
1107                 void *data;
1108 #ifdef __ARMEB__
1109                 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1110                         return -ENOMEM;
1111                 data = buff->data;
1112 #else
1113                 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1114                         return -ENOMEM;
1115                 data = buff;
1116 #endif
1117                 desc->buf_len = MAX_MRU;
1118                 desc->data = dma_map_single(&port->netdev->dev, data,
1119                                             RX_BUFF_SIZE, DMA_FROM_DEVICE);
1120                 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1121                         free_buffer(buff);
1122                         return -EIO;
1123                 }
1124                 desc->data += NET_IP_ALIGN;
1125                 port->rx_buff_tab[i] = buff;
1126         }
1127
1128         return 0;
1129 }
1130
1131 static void destroy_queues(struct port *port)
1132 {
1133         int i;
1134
1135         if (port->desc_tab) {
1136                 for (i = 0; i < RX_DESCS; i++) {
1137                         struct desc *desc = rx_desc_ptr(port, i);
1138                         buffer_t *buff = port->rx_buff_tab[i];
1139                         if (buff) {
1140                                 dma_unmap_single(&port->netdev->dev,
1141                                                  desc->data - NET_IP_ALIGN,
1142                                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
1143                                 free_buffer(buff);
1144                         }
1145                 }
1146                 for (i = 0; i < TX_DESCS; i++) {
1147                         struct desc *desc = tx_desc_ptr(port, i);
1148                         buffer_t *buff = port->tx_buff_tab[i];
1149                         if (buff) {
1150                                 dma_unmap_tx(port, desc);
1151                                 free_buffer(buff);
1152                         }
1153                 }
1154                 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1155                 port->desc_tab = NULL;
1156         }
1157
1158         if (!ports_open && dma_pool) {
1159                 dma_pool_destroy(dma_pool);
1160                 dma_pool = NULL;
1161         }
1162 }
1163
1164 static int eth_open(struct net_device *dev)
1165 {
1166         struct port *port = netdev_priv(dev);
1167         struct npe *npe = port->npe;
1168         struct msg msg;
1169         int i, err;
1170
1171         if (!npe_running(npe)) {
1172                 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1173                 if (err)
1174                         return err;
1175
1176                 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1177                         netdev_err(dev, "%s not responding\n", npe_name(npe));
1178                         return -EIO;
1179                 }
1180                 port->firmware[0] = msg.byte4;
1181                 port->firmware[1] = msg.byte5;
1182                 port->firmware[2] = msg.byte6;
1183                 port->firmware[3] = msg.byte7;
1184         }
1185
1186         memset(&msg, 0, sizeof(msg));
1187         msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1188         msg.eth_id = port->id;
1189         msg.byte5 = port->plat->rxq | 0x80;
1190         msg.byte7 = port->plat->rxq << 4;
1191         for (i = 0; i < 8; i++) {
1192                 msg.byte3 = i;
1193                 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1194                         return -EIO;
1195         }
1196
1197         msg.cmd = NPE_EDB_SETPORTADDRESS;
1198         msg.eth_id = PHYSICAL_ID(port->id);
1199         msg.byte2 = dev->dev_addr[0];
1200         msg.byte3 = dev->dev_addr[1];
1201         msg.byte4 = dev->dev_addr[2];
1202         msg.byte5 = dev->dev_addr[3];
1203         msg.byte6 = dev->dev_addr[4];
1204         msg.byte7 = dev->dev_addr[5];
1205         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1206                 return -EIO;
1207
1208         memset(&msg, 0, sizeof(msg));
1209         msg.cmd = NPE_FW_SETFIREWALLMODE;
1210         msg.eth_id = port->id;
1211         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1212                 return -EIO;
1213
1214         if ((err = request_queues(port)) != 0)
1215                 return err;
1216
1217         if ((err = init_queues(port)) != 0) {
1218                 destroy_queues(port);
1219                 release_queues(port);
1220                 return err;
1221         }
1222
1223         port->speed = 0;        /* force "link up" message */
1224         phy_start(dev->phydev);
1225
1226         for (i = 0; i < ETH_ALEN; i++)
1227                 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1228         __raw_writel(0x08, &port->regs->random_seed);
1229         __raw_writel(0x12, &port->regs->partial_empty_threshold);
1230         __raw_writel(0x30, &port->regs->partial_full_threshold);
1231         __raw_writel(0x08, &port->regs->tx_start_bytes);
1232         __raw_writel(0x15, &port->regs->tx_deferral);
1233         __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1234         __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1235         __raw_writel(0x80, &port->regs->slot_time);
1236         __raw_writel(0x01, &port->regs->int_clock_threshold);
1237
1238         /* Populate queues with buffers, no failure after this point */
1239         for (i = 0; i < TX_DESCS; i++)
1240                 queue_put_desc(port->plat->txreadyq,
1241                                tx_desc_phys(port, i), tx_desc_ptr(port, i));
1242
1243         for (i = 0; i < RX_DESCS; i++)
1244                 queue_put_desc(RXFREE_QUEUE(port->id),
1245                                rx_desc_phys(port, i), rx_desc_ptr(port, i));
1246
1247         __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1248         __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1249         __raw_writel(0, &port->regs->rx_control[1]);
1250         __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1251
1252         napi_enable(&port->napi);
1253         eth_set_mcast_list(dev);
1254         netif_start_queue(dev);
1255
1256         qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1257                      eth_rx_irq, dev);
1258         if (!ports_open) {
1259                 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1260                              eth_txdone_irq, NULL);
1261                 qmgr_enable_irq(TXDONE_QUEUE);
1262         }
1263         ports_open++;
1264         /* we may already have RX data, enables IRQ */
1265         napi_schedule(&port->napi);
1266         return 0;
1267 }
1268
1269 static int eth_close(struct net_device *dev)
1270 {
1271         struct port *port = netdev_priv(dev);
1272         struct msg msg;
1273         int buffs = RX_DESCS; /* allocated RX buffers */
1274         int i;
1275
1276         ports_open--;
1277         qmgr_disable_irq(port->plat->rxq);
1278         napi_disable(&port->napi);
1279         netif_stop_queue(dev);
1280
1281         while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1282                 buffs--;
1283
1284         memset(&msg, 0, sizeof(msg));
1285         msg.cmd = NPE_SETLOOPBACK_MODE;
1286         msg.eth_id = port->id;
1287         msg.byte3 = 1;
1288         if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1289                 netdev_crit(dev, "unable to enable loopback\n");
1290
1291         i = 0;
1292         do {                    /* drain RX buffers */
1293                 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1294                         buffs--;
1295                 if (!buffs)
1296                         break;
1297                 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1298                         /* we have to inject some packet */
1299                         struct desc *desc;
1300                         u32 phys;
1301                         int n = queue_get_desc(port->plat->txreadyq, port, 1);
1302                         BUG_ON(n < 0);
1303                         desc = tx_desc_ptr(port, n);
1304                         phys = tx_desc_phys(port, n);
1305                         desc->buf_len = desc->pkt_len = 1;
1306                         wmb();
1307                         queue_put_desc(TX_QUEUE(port->id), phys, desc);
1308                 }
1309                 udelay(1);
1310         } while (++i < MAX_CLOSE_WAIT);
1311
1312         if (buffs)
1313                 netdev_crit(dev, "unable to drain RX queue, %i buffer(s)"
1314                             " left in NPE\n", buffs);
1315 #if DEBUG_CLOSE
1316         if (!buffs)
1317                 netdev_debug(dev, "draining RX queue took %i cycles\n", i);
1318 #endif
1319
1320         buffs = TX_DESCS;
1321         while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1322                 buffs--; /* cancel TX */
1323
1324         i = 0;
1325         do {
1326                 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1327                         buffs--;
1328                 if (!buffs)
1329                         break;
1330         } while (++i < MAX_CLOSE_WAIT);
1331
1332         if (buffs)
1333                 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) "
1334                             "left in NPE\n", buffs);
1335 #if DEBUG_CLOSE
1336         if (!buffs)
1337                 netdev_debug(dev, "draining TX queues took %i cycles\n", i);
1338 #endif
1339
1340         msg.byte3 = 0;
1341         if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1342                 netdev_crit(dev, "unable to disable loopback\n");
1343
1344         phy_stop(dev->phydev);
1345
1346         if (!ports_open)
1347                 qmgr_disable_irq(TXDONE_QUEUE);
1348         destroy_queues(port);
1349         release_queues(port);
1350         return 0;
1351 }
1352
1353 static const struct net_device_ops ixp4xx_netdev_ops = {
1354         .ndo_open = eth_open,
1355         .ndo_stop = eth_close,
1356         .ndo_start_xmit = eth_xmit,
1357         .ndo_set_rx_mode = eth_set_mcast_list,
1358         .ndo_do_ioctl = eth_ioctl,
1359         .ndo_set_mac_address = eth_mac_addr,
1360         .ndo_validate_addr = eth_validate_addr,
1361 };
1362
1363 #ifdef CONFIG_OF
1364 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
1365 {
1366         struct device_node *np = dev->of_node;
1367         struct of_phandle_args queue_spec;
1368         struct of_phandle_args npe_spec;
1369         struct device_node *mdio_np;
1370         struct eth_plat_info *plat;
1371         int ret;
1372
1373         plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
1374         if (!plat)
1375                 return NULL;
1376
1377         ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,
1378                                                &npe_spec);
1379         if (ret) {
1380                 dev_err(dev, "no NPE engine specified\n");
1381                 return NULL;
1382         }
1383         /* NPE ID 0x00, 0x10, 0x20... */
1384         plat->npe = (npe_spec.args[0] << 4);
1385
1386         /* Check if this device has an MDIO bus */
1387         mdio_np = of_get_child_by_name(np, "mdio");
1388         if (mdio_np) {
1389                 plat->has_mdio = true;
1390                 mdio_bus_np = mdio_np;
1391                 /* DO NOT put the mdio_np, it will be used */
1392         }
1393
1394         /* Get the rx queue as a resource from queue manager */
1395         ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0,
1396                                                &queue_spec);
1397         if (ret) {
1398                 dev_err(dev, "no rx queue phandle\n");
1399                 return NULL;
1400         }
1401         plat->rxq = queue_spec.args[0];
1402
1403         /* Get the txready queue as resource from queue manager */
1404         ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0,
1405                                                &queue_spec);
1406         if (ret) {
1407                 dev_err(dev, "no txready queue phandle\n");
1408                 return NULL;
1409         }
1410         plat->txreadyq = queue_spec.args[0];
1411
1412         return plat;
1413 }
1414 #else
1415 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
1416 {
1417         return NULL;
1418 }
1419 #endif
1420
1421 static int ixp4xx_eth_probe(struct platform_device *pdev)
1422 {
1423         struct phy_device *phydev = NULL;
1424         struct device *dev = &pdev->dev;
1425         struct device_node *np = dev->of_node;
1426         struct eth_plat_info *plat;
1427         struct net_device *ndev;
1428         struct resource *res;
1429         struct port *port;
1430         int err;
1431
1432         if (np) {
1433                 plat = ixp4xx_of_get_platdata(dev);
1434                 if (!plat)
1435                         return -ENODEV;
1436         } else {
1437                 plat = dev_get_platdata(dev);
1438                 if (!plat)
1439                         return -ENODEV;
1440                 plat->npe = pdev->id;
1441                 switch (plat->npe) {
1442                 case IXP4XX_ETH_NPEA:
1443                         /* If the MDIO bus is not up yet, defer probe */
1444                         break;
1445                 case IXP4XX_ETH_NPEB:
1446                         /* On all except IXP43x, NPE-B is used for the MDIO bus.
1447                          * If there is no NPE-B in the feature set, bail out,
1448                          * else we have the MDIO bus here.
1449                          */
1450                         if (!cpu_is_ixp43x()) {
1451                                 if (!(ixp4xx_read_feature_bits() &
1452                                       IXP4XX_FEATURE_NPEB_ETH0))
1453                                         return -ENODEV;
1454                                 /* Else register the MDIO bus on NPE-B */
1455                                 plat->has_mdio = true;
1456                         }
1457                         break;
1458                 case IXP4XX_ETH_NPEC:
1459                         /* IXP43x lacks NPE-B and uses NPE-C for the MDIO bus
1460                          * access, if there is no NPE-C, no bus, nothing works,
1461                          * so bail out.
1462                          */
1463                         if (cpu_is_ixp43x()) {
1464                                 if (!(ixp4xx_read_feature_bits() &
1465                                       IXP4XX_FEATURE_NPEC_ETH))
1466                                         return -ENODEV;
1467                                 /* Else register the MDIO bus on NPE-B */
1468                                 plat->has_mdio = true;
1469                         }
1470                         break;
1471                 default:
1472                         return -ENODEV;
1473                 }
1474         }
1475
1476         if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port))))
1477                 return -ENOMEM;
1478
1479         SET_NETDEV_DEV(ndev, dev);
1480         port = netdev_priv(ndev);
1481         port->netdev = ndev;
1482         port->id = plat->npe;
1483
1484         /* Get the port resource and remap */
1485         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1486         if (!res)
1487                 return -ENODEV;
1488         port->regs = devm_ioremap_resource(dev, res);
1489         if (IS_ERR(port->regs))
1490                 return PTR_ERR(port->regs);
1491
1492         /* Register the MDIO bus if we have it */
1493         if (plat->has_mdio) {
1494                 err = ixp4xx_mdio_register(port->regs);
1495                 if (err) {
1496                         dev_err(dev, "failed to register MDIO bus\n");
1497                         return err;
1498                 }
1499         }
1500         /* If the instance with the MDIO bus has not yet appeared,
1501          * defer probing until it gets probed.
1502          */
1503         if (!mdio_bus)
1504                 return -EPROBE_DEFER;
1505
1506         ndev->netdev_ops = &ixp4xx_netdev_ops;
1507         ndev->ethtool_ops = &ixp4xx_ethtool_ops;
1508         ndev->tx_queue_len = 100;
1509         /* Inherit the DMA masks from the platform device */
1510         ndev->dev.dma_mask = dev->dma_mask;
1511         ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
1512
1513         netif_napi_add(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
1514
1515         if (!(port->npe = npe_request(NPE_ID(port->id))))
1516                 return -EIO;
1517
1518         port->plat = plat;
1519         npe_port_tab[NPE_ID(port->id)] = port;
1520         memcpy(ndev->dev_addr, plat->hwaddr, ETH_ALEN);
1521
1522         platform_set_drvdata(pdev, ndev);
1523
1524         __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1525                      &port->regs->core_control);
1526         udelay(50);
1527         __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1528         udelay(50);
1529
1530         if (np) {
1531                 phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link);
1532         } else {
1533                 phydev = mdiobus_get_phy(mdio_bus, plat->phy);
1534                 if (IS_ERR(phydev)) {
1535                         err = PTR_ERR(phydev);
1536                         dev_err(dev, "could not connect phydev (%d)\n", err);
1537                         goto err_free_mem;
1538                 }
1539                 err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link,
1540                                          PHY_INTERFACE_MODE_MII);
1541                 if (err)
1542                         goto err_free_mem;
1543
1544         }
1545         if (!phydev) {
1546                 err = -ENODEV;
1547                 dev_err(dev, "no phydev\n");
1548                 goto err_free_mem;
1549         }
1550
1551         phydev->irq = PHY_POLL;
1552
1553         if ((err = register_netdev(ndev)))
1554                 goto err_phy_dis;
1555
1556         netdev_info(ndev, "%s: MII PHY %i on %s\n", ndev->name, plat->phy,
1557                     npe_name(port->npe));
1558
1559         return 0;
1560
1561 err_phy_dis:
1562         phy_disconnect(phydev);
1563 err_free_mem:
1564         npe_port_tab[NPE_ID(port->id)] = NULL;
1565         npe_release(port->npe);
1566         return err;
1567 }
1568
1569 static int ixp4xx_eth_remove(struct platform_device *pdev)
1570 {
1571         struct net_device *ndev = platform_get_drvdata(pdev);
1572         struct phy_device *phydev = ndev->phydev;
1573         struct port *port = netdev_priv(ndev);
1574
1575         unregister_netdev(ndev);
1576         phy_disconnect(phydev);
1577         ixp4xx_mdio_remove();
1578         npe_port_tab[NPE_ID(port->id)] = NULL;
1579         npe_release(port->npe);
1580         return 0;
1581 }
1582
1583 static const struct of_device_id ixp4xx_eth_of_match[] = {
1584         {
1585                 .compatible = "intel,ixp4xx-ethernet",
1586         },
1587         { },
1588 };
1589
1590 static struct platform_driver ixp4xx_eth_driver = {
1591         .driver = {
1592                 .name = DRV_NAME,
1593                 .of_match_table = of_match_ptr(ixp4xx_eth_of_match),
1594         },
1595         .probe          = ixp4xx_eth_probe,
1596         .remove         = ixp4xx_eth_remove,
1597 };
1598 module_platform_driver(ixp4xx_eth_driver);
1599
1600 MODULE_AUTHOR("Krzysztof Halasa");
1601 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1602 MODULE_LICENSE("GPL v2");
1603 MODULE_ALIAS("platform:ixp4xx_eth");