drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <[email protected]>
   5  * Copyright (C) 2016 Florian Fainelli <[email protected]>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/export.h>
  22 #include <linux/gpio.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_data/b53.h>
  26 #include <linux/phy.h>
  27 #include <linux/phylink.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/if_bridge.h>
  30 #include <net/dsa.h>
  31
  32 #include "b53_regs.h"
  33 #include "b53_priv.h"
  34
  35 struct b53_mib_desc {
  36         u8 size;
  37         u8 offset;
  38         const char *name;
  39 };
  40
  41 /* BCM5365 MIB counters */
  42 static const struct b53_mib_desc b53_mibs_65[] = {
  43         { 8, 0x00, "TxOctets" },
  44         { 4, 0x08, "TxDropPkts" },
  45         { 4, 0x10, "TxBroadcastPkts" },
  46         { 4, 0x14, "TxMulticastPkts" },
  47         { 4, 0x18, "TxUnicastPkts" },
  48         { 4, 0x1c, "TxCollisions" },
  49         { 4, 0x20, "TxSingleCollision" },
  50         { 4, 0x24, "TxMultipleCollision" },
  51         { 4, 0x28, "TxDeferredTransmit" },
  52         { 4, 0x2c, "TxLateCollision" },
  53         { 4, 0x30, "TxExcessiveCollision" },
  54         { 4, 0x38, "TxPausePkts" },
  55         { 8, 0x44, "RxOctets" },
  56         { 4, 0x4c, "RxUndersizePkts" },
  57         { 4, 0x50, "RxPausePkts" },
  58         { 4, 0x54, "Pkts64Octets" },
  59         { 4, 0x58, "Pkts65to127Octets" },
  60         { 4, 0x5c, "Pkts128to255Octets" },
  61         { 4, 0x60, "Pkts256to511Octets" },
  62         { 4, 0x64, "Pkts512to1023Octets" },
  63         { 4, 0x68, "Pkts1024to1522Octets" },
  64         { 4, 0x6c, "RxOversizePkts" },
  65         { 4, 0x70, "RxJabbers" },
  66         { 4, 0x74, "RxAlignmentErrors" },
  67         { 4, 0x78, "RxFCSErrors" },
  68         { 8, 0x7c, "RxGoodOctets" },
  69         { 4, 0x84, "RxDropPkts" },
  70         { 4, 0x88, "RxUnicastPkts" },
  71         { 4, 0x8c, "RxMulticastPkts" },
  72         { 4, 0x90, "RxBroadcastPkts" },
  73         { 4, 0x94, "RxSAChanges" },
  74         { 4, 0x98, "RxFragments" },
  75 };
  76
  77 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  78
  79 /* BCM63xx MIB counters */
  80 static const struct b53_mib_desc b53_mibs_63xx[] = {
  81         { 8, 0x00, "TxOctets" },
  82         { 4, 0x08, "TxDropPkts" },
  83         { 4, 0x0c, "TxQoSPkts" },
  84         { 4, 0x10, "TxBroadcastPkts" },
  85         { 4, 0x14, "TxMulticastPkts" },
  86         { 4, 0x18, "TxUnicastPkts" },
  87         { 4, 0x1c, "TxCollisions" },
  88         { 4, 0x20, "TxSingleCollision" },
  89         { 4, 0x24, "TxMultipleCollision" },
  90         { 4, 0x28, "TxDeferredTransmit" },
  91         { 4, 0x2c, "TxLateCollision" },
  92         { 4, 0x30, "TxExcessiveCollision" },
  93         { 4, 0x38, "TxPausePkts" },
  94         { 8, 0x3c, "TxQoSOctets" },
  95         { 8, 0x44, "RxOctets" },
  96         { 4, 0x4c, "RxUndersizePkts" },
  97         { 4, 0x50, "RxPausePkts" },
  98         { 4, 0x54, "Pkts64Octets" },
  99         { 4, 0x58, "Pkts65to127Octets" },
 100         { 4, 0x5c, "Pkts128to255Octets" },
 101         { 4, 0x60, "Pkts256to511Octets" },
 102         { 4, 0x64, "Pkts512to1023Octets" },
 103         { 4, 0x68, "Pkts1024to1522Octets" },
 104         { 4, 0x6c, "RxOversizePkts" },
 105         { 4, 0x70, "RxJabbers" },
 106         { 4, 0x74, "RxAlignmentErrors" },
 107         { 4, 0x78, "RxFCSErrors" },
 108         { 8, 0x7c, "RxGoodOctets" },
 109         { 4, 0x84, "RxDropPkts" },
 110         { 4, 0x88, "RxUnicastPkts" },
 111         { 4, 0x8c, "RxMulticastPkts" },
 112         { 4, 0x90, "RxBroadcastPkts" },
 113         { 4, 0x94, "RxSAChanges" },
 114         { 4, 0x98, "RxFragments" },
 115         { 4, 0xa0, "RxSymbolErrors" },
 116         { 4, 0xa4, "RxQoSPkts" },
 117         { 8, 0xa8, "RxQoSOctets" },
 118         { 4, 0xb0, "Pkts1523to2047Octets" },
 119         { 4, 0xb4, "Pkts2048to4095Octets" },
 120         { 4, 0xb8, "Pkts4096to8191Octets" },
 121         { 4, 0xbc, "Pkts8192to9728Octets" },
 122         { 4, 0xc0, "RxDiscarded" },
 123 };
 124
 125 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 126
 127 /* MIB counters */
 128 static const struct b53_mib_desc b53_mibs[] = {
 129         { 8, 0x00, "TxOctets" },
 130         { 4, 0x08, "TxDropPkts" },
 131         { 4, 0x10, "TxBroadcastPkts" },
 132         { 4, 0x14, "TxMulticastPkts" },
 133         { 4, 0x18, "TxUnicastPkts" },
 134         { 4, 0x1c, "TxCollisions" },
 135         { 4, 0x20, "TxSingleCollision" },
 136         { 4, 0x24, "TxMultipleCollision" },
 137         { 4, 0x28, "TxDeferredTransmit" },
 138         { 4, 0x2c, "TxLateCollision" },
 139         { 4, 0x30, "TxExcessiveCollision" },
 140         { 4, 0x38, "TxPausePkts" },
 141         { 8, 0x50, "RxOctets" },
 142         { 4, 0x58, "RxUndersizePkts" },
 143         { 4, 0x5c, "RxPausePkts" },
 144         { 4, 0x60, "Pkts64Octets" },
 145         { 4, 0x64, "Pkts65to127Octets" },
 146         { 4, 0x68, "Pkts128to255Octets" },
 147         { 4, 0x6c, "Pkts256to511Octets" },
 148         { 4, 0x70, "Pkts512to1023Octets" },
 149         { 4, 0x74, "Pkts1024to1522Octets" },
 150         { 4, 0x78, "RxOversizePkts" },
 151         { 4, 0x7c, "RxJabbers" },
 152         { 4, 0x80, "RxAlignmentErrors" },
 153         { 4, 0x84, "RxFCSErrors" },
 154         { 8, 0x88, "RxGoodOctets" },
 155         { 4, 0x90, "RxDropPkts" },
 156         { 4, 0x94, "RxUnicastPkts" },
 157         { 4, 0x98, "RxMulticastPkts" },
 158         { 4, 0x9c, "RxBroadcastPkts" },
 159         { 4, 0xa0, "RxSAChanges" },
 160         { 4, 0xa4, "RxFragments" },
 161         { 4, 0xa8, "RxJumboPkts" },
 162         { 4, 0xac, "RxSymbolErrors" },
 163         { 4, 0xc0, "RxDiscarded" },
 164 };
 165
 166 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 167
 168 static const struct b53_mib_desc b53_mibs_58xx[] = {
 169         { 8, 0x00, "TxOctets" },
 170         { 4, 0x08, "TxDropPkts" },
 171         { 4, 0x0c, "TxQPKTQ0" },
 172         { 4, 0x10, "TxBroadcastPkts" },
 173         { 4, 0x14, "TxMulticastPkts" },
 174         { 4, 0x18, "TxUnicastPKts" },
 175         { 4, 0x1c, "TxCollisions" },
 176         { 4, 0x20, "TxSingleCollision" },
 177         { 4, 0x24, "TxMultipleCollision" },
 178         { 4, 0x28, "TxDeferredCollision" },
 179         { 4, 0x2c, "TxLateCollision" },
 180         { 4, 0x30, "TxExcessiveCollision" },
 181         { 4, 0x34, "TxFrameInDisc" },
 182         { 4, 0x38, "TxPausePkts" },
 183         { 4, 0x3c, "TxQPKTQ1" },
 184         { 4, 0x40, "TxQPKTQ2" },
 185         { 4, 0x44, "TxQPKTQ3" },
 186         { 4, 0x48, "TxQPKTQ4" },
 187         { 4, 0x4c, "TxQPKTQ5" },
 188         { 8, 0x50, "RxOctets" },
 189         { 4, 0x58, "RxUndersizePkts" },
 190         { 4, 0x5c, "RxPausePkts" },
 191         { 4, 0x60, "RxPkts64Octets" },
 192         { 4, 0x64, "RxPkts65to127Octets" },
 193         { 4, 0x68, "RxPkts128to255Octets" },
 194         { 4, 0x6c, "RxPkts256to511Octets" },
 195         { 4, 0x70, "RxPkts512to1023Octets" },
 196         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 197         { 4, 0x78, "RxOversizePkts" },
 198         { 4, 0x7c, "RxJabbers" },
 199         { 4, 0x80, "RxAlignmentErrors" },
 200         { 4, 0x84, "RxFCSErrors" },
 201         { 8, 0x88, "RxGoodOctets" },
 202         { 4, 0x90, "RxDropPkts" },
 203         { 4, 0x94, "RxUnicastPkts" },
 204         { 4, 0x98, "RxMulticastPkts" },
 205         { 4, 0x9c, "RxBroadcastPkts" },
 206         { 4, 0xa0, "RxSAChanges" },
 207         { 4, 0xa4, "RxFragments" },
 208         { 4, 0xa8, "RxJumboPkt" },
 209         { 4, 0xac, "RxSymblErr" },
 210         { 4, 0xb0, "InRangeErrCount" },
 211         { 4, 0xb4, "OutRangeErrCount" },
 212         { 4, 0xb8, "EEELpiEvent" },
 213         { 4, 0xbc, "EEELpiDuration" },
 214         { 4, 0xc0, "RxDiscard" },
 215         { 4, 0xc8, "TxQPKTQ6" },
 216         { 4, 0xcc, "TxQPKTQ7" },
 217         { 4, 0xd0, "TxPkts64Octets" },
 218         { 4, 0xd4, "TxPkts65to127Octets" },
 219         { 4, 0xd8, "TxPkts128to255Octets" },
 220         { 4, 0xdc, "TxPkts256to511Ocets" },
 221         { 4, 0xe0, "TxPkts512to1023Ocets" },
 222         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 223 };
 224
 225 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 226
 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 228 {
 229         unsigned int i;
 230
 231         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 232
 233         for (i = 0; i < 10; i++) {
 234                 u8 vta;
 235
 236                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 237                 if (!(vta & VTA_START_CMD))
 238                         return 0;
 239
 240                 usleep_range(100, 200);
 241         }
 242
 243         return -EIO;
 244 }
 245
 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 247                                struct b53_vlan *vlan)
 248 {
 249         if (is5325(dev)) {
 250                 u32 entry = 0;
 251
 252                 if (vlan->members) {
 253                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 254                                  VA_UNTAG_S_25) | vlan->members;
 255                         if (dev->core_rev >= 3)
 256                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 257                         else
 258                                 entry |= VA_VALID_25;
 259                 }
 260
 261                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 262                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 263                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 264         } else if (is5365(dev)) {
 265                 u16 entry = 0;
 266
 267                 if (vlan->members)
 268                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 269                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 270
 271                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 272                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 273                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 274         } else {
 275                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 276                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 277                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 278
 279                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 280         }
 281
 282         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 283                 vid, vlan->members, vlan->untag);
 284 }
 285
 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 287                                struct b53_vlan *vlan)
 288 {
 289         if (is5325(dev)) {
 290                 u32 entry = 0;
 291
 292                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 293                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 294                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 295
 296                 if (dev->core_rev >= 3)
 297                         vlan->valid = !!(entry & VA_VALID_25_R4);
 298                 else
 299                         vlan->valid = !!(entry & VA_VALID_25);
 300                 vlan->members = entry & VA_MEMBER_MASK;
 301                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 302
 303         } else if (is5365(dev)) {
 304                 u16 entry = 0;
 305
 306                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 307                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 308                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 309
 310                 vlan->valid = !!(entry & VA_VALID_65);
 311                 vlan->members = entry & VA_MEMBER_MASK;
 312                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 313         } else {
 314                 u32 entry = 0;
 315
 316                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 317                 b53_do_vlan_op(dev, VTA_CMD_READ);
 318                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 319                 vlan->members = entry & VTE_MEMBERS;
 320                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 321                 vlan->valid = true;
 322         }
 323 }
 324
 325 static void b53_set_forwarding(struct b53_device *dev, int enable)
 326 {
 327         u8 mgmt;
 328
 329         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 330
 331         if (enable)
 332                 mgmt |= SM_SW_FWD_EN;
 333         else
 334                 mgmt &= ~SM_SW_FWD_EN;
 335
 336         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 337
 338         /* Include IMP port in dumb forwarding mode
 339          */
 340         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 341         mgmt |= B53_MII_DUMB_FWDG_EN;
 342         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 343
 344         /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
 345          * frames should be flooded or not.
 346          */
 347         b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
 348         mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
 349         b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
 350 }
 351
 352 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
 353                             bool enable_filtering)
 354 {
 355         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 356
 357         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 358         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 359         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 360
 361         if (is5325(dev) || is5365(dev)) {
 362                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 363                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 364         } else if (is63xx(dev)) {
 365                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 366                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 367         } else {
 368                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 369                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 370         }
 371
 372         if (enable) {
 373                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 374                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 375                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 376                 if (enable_filtering) {
 377                         vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 378                         vc5 |= VC5_DROP_VTABLE_MISS;
 379                 } else {
 380                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 381                         vc5 &= ~VC5_DROP_VTABLE_MISS;
 382                 }
 383
 384                 if (is5325(dev))
 385                         vc0 &= ~VC0_RESERVED_1;
 386
 387                 if (is5325(dev) || is5365(dev))
 388                         vc1 |= VC1_RX_MCST_TAG_EN;
 389
 390         } else {
 391                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 392                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 393                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 394                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 395
 396                 if (is5325(dev) || is5365(dev))
 397                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 398                 else
 399                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 400
 401                 if (is5325(dev) || is5365(dev))
 402                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 403         }
 404
 405         if (!is5325(dev) && !is5365(dev))
 406                 vc5 &= ~VC5_VID_FFF_EN;
 407
 408         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 409         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 410
 411         if (is5325(dev) || is5365(dev)) {
 412                 /* enable the high 8 bit vid check on 5325 */
 413                 if (is5325(dev) && enable)
 414                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 415                                    VC3_HIGH_8BIT_EN);
 416                 else
 417                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 418
 419                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 420                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 421         } else if (is63xx(dev)) {
 422                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 423                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 424                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 425         } else {
 426                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 427                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 428                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 429         }
 430
 431         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 432
 433         dev->vlan_enabled = enable;
 434
 435         dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
 436                 port, enable, enable_filtering);
 437 }
 438
 439 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 440 {
 441         u32 port_mask = 0;
 442         u16 max_size = JMS_MIN_SIZE;
 443
 444         if (is5325(dev) || is5365(dev))
 445                 return -EINVAL;
 446
 447         if (enable) {
 448                 port_mask = dev->enabled_ports;
 449                 max_size = JMS_MAX_SIZE;
 450                 if (allow_10_100)
 451                         port_mask |= JPM_10_100_JUMBO_EN;
 452         }
 453
 454         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 455         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 456 }
 457
 458 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 459 {
 460         unsigned int i;
 461
 462         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 463                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 464
 465         for (i = 0; i < 10; i++) {
 466                 u8 fast_age_ctrl;
 467
 468                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 469                           &fast_age_ctrl);
 470
 471                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 472                         goto out;
 473
 474                 msleep(1);
 475         }
 476
 477         return -ETIMEDOUT;
 478 out:
 479         /* Only age dynamic entries (default behavior) */
 480         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 481         return 0;
 482 }
 483
 484 static int b53_fast_age_port(struct b53_device *dev, int port)
 485 {
 486         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 487
 488         return b53_flush_arl(dev, FAST_AGE_PORT);
 489 }
 490
 491 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 492 {
 493         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 494
 495         return b53_flush_arl(dev, FAST_AGE_VLAN);
 496 }
 497
 498 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 499 {
 500         struct b53_device *dev = ds->priv;
 501         unsigned int i;
 502         u16 pvlan;
 503
 504         /* Enable the IMP port to be in the same VLAN as the other ports
 505          * on a per-port basis such that we only have Port i and IMP in
 506          * the same VLAN.
 507          */
 508         b53_for_each_port(dev, i) {
 509                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 510                 pvlan |= BIT(cpu_port);
 511                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 512         }
 513 }
 514 EXPORT_SYMBOL(b53_imp_vlan_setup);
 515
 516 static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
 517                                      bool unicast)
 518 {
 519         u16 uc;
 520
 521         b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
 522         if (unicast)
 523                 uc |= BIT(port);
 524         else
 525                 uc &= ~BIT(port);
 526         b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
 527 }
 528
 529 static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
 530                                      bool multicast)
 531 {
 532         u16 mc;
 533
 534         b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
 535         if (multicast)
 536                 mc |= BIT(port);
 537         else
 538                 mc &= ~BIT(port);
 539         b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
 540
 541         b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
 542         if (multicast)
 543                 mc |= BIT(port);
 544         else
 545                 mc &= ~BIT(port);
 546         b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
 547 }
 548
 549 static void b53_port_set_learning(struct b53_device *dev, int port,
 550                                   bool learning)
 551 {
 552         u16 reg;
 553
 554         b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, &reg);
 555         if (learning)
 556                 reg &= ~BIT(port);
 557         else
 558                 reg |= BIT(port);
 559         b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
 560 }
 561
 562 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 563 {
 564         struct b53_device *dev = ds->priv;
 565         unsigned int cpu_port;
 566         int ret = 0;
 567         u16 pvlan;
 568
 569         if (!dsa_is_user_port(ds, port))
 570                 return 0;
 571
 572         cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
 573
 574         b53_port_set_ucast_flood(dev, port, true);
 575         b53_port_set_mcast_flood(dev, port, true);
 576         b53_port_set_learning(dev, port, false);
 577
 578         if (dev->ops->irq_enable)
 579                 ret = dev->ops->irq_enable(dev, port);
 580         if (ret)
 581                 return ret;
 582
 583         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 584         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 585
 586         /* Set this port, and only this one to be in the default VLAN,
 587          * if member of a bridge, restore its membership prior to
 588          * bringing down this port.
 589          */
 590         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 591         pvlan &= ~0x1ff;
 592         pvlan |= BIT(port);
 593         pvlan |= dev->ports[port].vlan_ctl_mask;
 594         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 595
 596         b53_imp_vlan_setup(ds, cpu_port);
 597
 598         /* If EEE was enabled, restore it */
 599         if (dev->ports[port].eee.eee_enabled)
 600                 b53_eee_enable_set(ds, port, true);
 601
 602         return 0;
 603 }
 604 EXPORT_SYMBOL(b53_enable_port);
 605
 606 void b53_disable_port(struct dsa_switch *ds, int port)
 607 {
 608         struct b53_device *dev = ds->priv;
 609         u8 reg;
 610
 611         /* Disable Tx/Rx for the port */
 612         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 613         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 614         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 615
 616         if (dev->ops->irq_disable)
 617                 dev->ops->irq_disable(dev, port);
 618 }
 619 EXPORT_SYMBOL(b53_disable_port);
 620
 621 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 622 {
 623         struct b53_device *dev = ds->priv;
 624         bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
 625         u8 hdr_ctl, val;
 626         u16 reg;
 627
 628         /* Resolve which bit controls the Broadcom tag */
 629         switch (port) {
 630         case 8:
 631                 val = BRCM_HDR_P8_EN;
 632                 break;
 633         case 7:
 634                 val = BRCM_HDR_P7_EN;
 635                 break;
 636         case 5:
 637                 val = BRCM_HDR_P5_EN;
 638                 break;
 639         default:
 640                 val = 0;
 641                 break;
 642         }
 643
 644         /* Enable management mode if tagging is requested */
 645         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
 646         if (tag_en)
 647                 hdr_ctl |= SM_SW_FWD_MODE;
 648         else
 649                 hdr_ctl &= ~SM_SW_FWD_MODE;
 650         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
 651
 652         /* Configure the appropriate IMP port */
 653         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
 654         if (port == 8)
 655                 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
 656         else if (port == 5)
 657                 hdr_ctl |= GC_FRM_MGMT_PORT_M;
 658         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
 659
 660         /* Enable Broadcom tags for IMP port */
 661         b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 662         if (tag_en)
 663                 hdr_ctl |= val;
 664         else
 665                 hdr_ctl &= ~val;
 666         b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 667
 668         /* Registers below are only accessible on newer devices */
 669         if (!is58xx(dev))
 670                 return;
 671
 672         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 673          * allow us to tag outgoing frames
 674          */
 675         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 676         if (tag_en)
 677                 reg &= ~BIT(port);
 678         else
 679                 reg |= BIT(port);
 680         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 681
 682         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 683          * allow delivering frames to the per-port net_devices
 684          */
 685         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 686         if (tag_en)
 687                 reg &= ~BIT(port);
 688         else
 689                 reg |= BIT(port);
 690         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 691 }
 692 EXPORT_SYMBOL(b53_brcm_hdr_setup);
 693
 694 static void b53_enable_cpu_port(struct b53_device *dev, int port)
 695 {
 696         u8 port_ctrl;
 697
 698         /* BCM5325 CPU port is at 8 */
 699         if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 700                 port = B53_CPU_PORT;
 701
 702         port_ctrl = PORT_CTRL_RX_BCST_EN |
 703                     PORT_CTRL_RX_MCST_EN |
 704                     PORT_CTRL_RX_UCST_EN;
 705         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 706
 707         b53_brcm_hdr_setup(dev->ds, port);
 708
 709         b53_port_set_ucast_flood(dev, port, true);
 710         b53_port_set_mcast_flood(dev, port, true);
 711         b53_port_set_learning(dev, port, false);
 712 }
 713
 714 static void b53_enable_mib(struct b53_device *dev)
 715 {
 716         u8 gc;
 717
 718         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 719         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 720         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 721 }
 722
 723 static u16 b53_default_pvid(struct b53_device *dev)
 724 {
 725         if (is5325(dev) || is5365(dev))
 726                 return 1;
 727         else
 728                 return 0;
 729 }
 730
 731 int b53_configure_vlan(struct dsa_switch *ds)
 732 {
 733         struct b53_device *dev = ds->priv;
 734         struct b53_vlan vl = { 0 };
 735         struct b53_vlan *v;
 736         int i, def_vid;
 737         u16 vid;
 738
 739         def_vid = b53_default_pvid(dev);
 740
 741         /* clear all vlan entries */
 742         if (is5325(dev) || is5365(dev)) {
 743                 for (i = def_vid; i < dev->num_vlans; i++)
 744                         b53_set_vlan_entry(dev, i, &vl);
 745         } else {
 746                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 747         }
 748
 749         b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);
 750
 751         b53_for_each_port(dev, i)
 752                 b53_write16(dev, B53_VLAN_PAGE,
 753                             B53_VLAN_PORT_DEF_TAG(i), def_vid);
 754
 755         /* Upon initial call we have not set-up any VLANs, but upon
 756          * system resume, we need to restore all VLAN entries.
 757          */
 758         for (vid = def_vid; vid < dev->num_vlans; vid++) {
 759                 v = &dev->vlans[vid];
 760
 761                 if (!v->members)
 762                         continue;
 763
 764                 b53_set_vlan_entry(dev, vid, v);
 765                 b53_fast_age_vlan(dev, vid);
 766         }
 767
 768         return 0;
 769 }
 770 EXPORT_SYMBOL(b53_configure_vlan);
 771
 772 static void b53_switch_reset_gpio(struct b53_device *dev)
 773 {
 774         int gpio = dev->reset_gpio;
 775
 776         if (gpio < 0)
 777                 return;
 778
 779         /* Reset sequence: RESET low(50ms)->high(20ms)
 780          */
 781         gpio_set_value(gpio, 0);
 782         mdelay(50);
 783
 784         gpio_set_value(gpio, 1);
 785         mdelay(20);
 786
 787         dev->current_page = 0xff;
 788 }
 789
 790 static int b53_switch_reset(struct b53_device *dev)
 791 {
 792         unsigned int timeout = 1000;
 793         u8 mgmt, reg;
 794
 795         b53_switch_reset_gpio(dev);
 796
 797         if (is539x(dev)) {
 798                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 799                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 800         }
 801
 802         /* This is specific to 58xx devices here, do not use is58xx() which
 803          * covers the larger Starfigther 2 family, including 7445/7278 which
 804          * still use this driver as a library and need to perform the reset
 805          * earlier.
 806          */
 807         if (dev->chip_id == BCM58XX_DEVICE_ID ||
 808             dev->chip_id == BCM583XX_DEVICE_ID) {
 809                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 810                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 811                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 812
 813                 do {
 814                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 815                         if (!(reg & SW_RST))
 816                                 break;
 817
 818                         usleep_range(1000, 2000);
 819                 } while (timeout-- > 0);
 820
 821                 if (timeout == 0) {
 822                         dev_err(dev->dev,
 823                                 "Timeout waiting for SW_RST to clear!\n");
 824                         return -ETIMEDOUT;
 825                 }
 826         }
 827
 828         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 829
 830         if (!(mgmt & SM_SW_FWD_EN)) {
 831                 mgmt &= ~SM_SW_FWD_MODE;
 832                 mgmt |= SM_SW_FWD_EN;
 833
 834                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 835                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 836
 837                 if (!(mgmt & SM_SW_FWD_EN)) {
 838                         dev_err(dev->dev, "Failed to enable switch!\n");
 839                         return -EINVAL;
 840                 }
 841         }
 842
 843         b53_enable_mib(dev);
 844
 845         return b53_flush_arl(dev, FAST_AGE_STATIC);
 846 }
 847
 848 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 849 {
 850         struct b53_device *priv = ds->priv;
 851         u16 value = 0;
 852         int ret;
 853
 854         if (priv->ops->phy_read16)
 855                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 856         else
 857                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 858                                  reg * 2, &value);
 859
 860         return ret ? ret : value;
 861 }
 862
 863 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 864 {
 865         struct b53_device *priv = ds->priv;
 866
 867         if (priv->ops->phy_write16)
 868                 return priv->ops->phy_write16(priv, addr, reg, val);
 869
 870         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 871 }
 872
 873 static int b53_reset_switch(struct b53_device *priv)
 874 {
 875         /* reset vlans */
 876         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 877         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 878
 879         priv->serdes_lane = B53_INVALID_LANE;
 880
 881         return b53_switch_reset(priv);
 882 }
 883
 884 static int b53_apply_config(struct b53_device *priv)
 885 {
 886         /* disable switching */
 887         b53_set_forwarding(priv, 0);
 888
 889         b53_configure_vlan(priv->ds);
 890
 891         /* enable switching */
 892         b53_set_forwarding(priv, 1);
 893
 894         return 0;
 895 }
 896
 897 static void b53_reset_mib(struct b53_device *priv)
 898 {
 899         u8 gc;
 900
 901         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 902
 903         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 904         msleep(1);
 905         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 906         msleep(1);
 907 }
 908
 909 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 910 {
 911         if (is5365(dev))
 912                 return b53_mibs_65;
 913         else if (is63xx(dev))
 914                 return b53_mibs_63xx;
 915         else if (is58xx(dev))
 916                 return b53_mibs_58xx;
 917         else
 918                 return b53_mibs;
 919 }
 920
 921 static unsigned int b53_get_mib_size(struct b53_device *dev)
 922 {
 923         if (is5365(dev))
 924                 return B53_MIBS_65_SIZE;
 925         else if (is63xx(dev))
 926                 return B53_MIBS_63XX_SIZE;
 927         else if (is58xx(dev))
 928                 return B53_MIBS_58XX_SIZE;
 929         else
 930                 return B53_MIBS_SIZE;
 931 }
 932
 933 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
 934 {
 935         /* These ports typically do not have built-in PHYs */
 936         switch (port) {
 937         case B53_CPU_PORT_25:
 938         case 7:
 939         case B53_CPU_PORT:
 940                 return NULL;
 941         }
 942
 943         return mdiobus_get_phy(ds->slave_mii_bus, port);
 944 }
 945
 946 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 947                      uint8_t *data)
 948 {
 949         struct b53_device *dev = ds->priv;
 950         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 951         unsigned int mib_size = b53_get_mib_size(dev);
 952         struct phy_device *phydev;
 953         unsigned int i;
 954
 955         if (stringset == ETH_SS_STATS) {
 956                 for (i = 0; i < mib_size; i++)
 957                         strlcpy(data + i * ETH_GSTRING_LEN,
 958                                 mibs[i].name, ETH_GSTRING_LEN);
 959         } else if (stringset == ETH_SS_PHY_STATS) {
 960                 phydev = b53_get_phy_device(ds, port);
 961                 if (!phydev)
 962                         return;
 963
 964                 phy_ethtool_get_strings(phydev, data);
 965         }
 966 }
 967 EXPORT_SYMBOL(b53_get_strings);
 968
 969 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 970 {
 971         struct b53_device *dev = ds->priv;
 972         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 973         unsigned int mib_size = b53_get_mib_size(dev);
 974         const struct b53_mib_desc *s;
 975         unsigned int i;
 976         u64 val = 0;
 977
 978         if (is5365(dev) && port == 5)
 979                 port = 8;
 980
 981         mutex_lock(&dev->stats_mutex);
 982
 983         for (i = 0; i < mib_size; i++) {
 984                 s = &mibs[i];
 985
 986                 if (s->size == 8) {
 987                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 988                 } else {
 989                         u32 val32;
 990
 991                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 992                                    &val32);
 993                         val = val32;
 994                 }
 995                 data[i] = (u64)val;
 996         }
 997
 998         mutex_unlock(&dev->stats_mutex);
 999 }
1000 EXPORT_SYMBOL(b53_get_ethtool_stats);
1001
1002 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1003 {
1004         struct phy_device *phydev;
1005
1006         phydev = b53_get_phy_device(ds, port);
1007         if (!phydev)
1008                 return;
1009
1010         phy_ethtool_get_stats(phydev, NULL, data);
1011 }
1012 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1013
1014 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1015 {
1016         struct b53_device *dev = ds->priv;
1017         struct phy_device *phydev;
1018
1019         if (sset == ETH_SS_STATS) {
1020                 return b53_get_mib_size(dev);
1021         } else if (sset == ETH_SS_PHY_STATS) {
1022                 phydev = b53_get_phy_device(ds, port);
1023                 if (!phydev)
1024                         return 0;
1025
1026                 return phy_ethtool_get_sset_count(phydev);
1027         }
1028
1029         return 0;
1030 }
1031 EXPORT_SYMBOL(b53_get_sset_count);
1032
1033 enum b53_devlink_resource_id {
1034         B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1035 };
1036
1037 static u64 b53_devlink_vlan_table_get(void *priv)
1038 {
1039         struct b53_device *dev = priv;
1040         struct b53_vlan *vl;
1041         unsigned int i;
1042         u64 count = 0;
1043
1044         for (i = 0; i < dev->num_vlans; i++) {
1045                 vl = &dev->vlans[i];
1046                 if (vl->members)
1047                         count++;
1048         }
1049
1050         return count;
1051 }
1052
1053 int b53_setup_devlink_resources(struct dsa_switch *ds)
1054 {
1055         struct devlink_resource_size_params size_params;
1056         struct b53_device *dev = ds->priv;
1057         int err;
1058
1059         devlink_resource_size_params_init(&size_params, dev->num_vlans,
1060                                           dev->num_vlans,
1061                                           1, DEVLINK_RESOURCE_UNIT_ENTRY);
1062
1063         err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1064                                             B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1065                                             DEVLINK_RESOURCE_ID_PARENT_TOP,
1066                                             &size_params);
1067         if (err)
1068                 goto out;
1069
1070         dsa_devlink_resource_occ_get_register(ds,
1071                                               B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1072                                               b53_devlink_vlan_table_get, dev);
1073
1074         return 0;
1075 out:
1076         dsa_devlink_resources_unregister(ds);
1077         return err;
1078 }
1079 EXPORT_SYMBOL(b53_setup_devlink_resources);
1080
1081 static int b53_setup(struct dsa_switch *ds)
1082 {
1083         struct b53_device *dev = ds->priv;
1084         unsigned int port;
1085         int ret;
1086
1087         ret = b53_reset_switch(dev);
1088         if (ret) {
1089                 dev_err(ds->dev, "failed to reset switch\n");
1090                 return ret;
1091         }
1092
1093         b53_reset_mib(dev);
1094
1095         ret = b53_apply_config(dev);
1096         if (ret) {
1097                 dev_err(ds->dev, "failed to apply configuration\n");
1098                 return ret;
1099         }
1100
1101         /* Configure IMP/CPU port, disable all other ports. Enabled
1102          * ports will be configured with .port_enable
1103          */
1104         for (port = 0; port < dev->num_ports; port++) {
1105                 if (dsa_is_cpu_port(ds, port))
1106                         b53_enable_cpu_port(dev, port);
1107                 else
1108                         b53_disable_port(ds, port);
1109         }
1110
1111         return b53_setup_devlink_resources(ds);
1112 }
1113
1114 static void b53_teardown(struct dsa_switch *ds)
1115 {
1116         dsa_devlink_resources_unregister(ds);
1117 }
1118
1119 static void b53_force_link(struct b53_device *dev, int port, int link)
1120 {
1121         u8 reg, val, off;
1122
1123         /* Override the port settings */
1124         if (port == dev->cpu_port) {
1125                 off = B53_PORT_OVERRIDE_CTRL;
1126                 val = PORT_OVERRIDE_EN;
1127         } else {
1128                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1129                 val = GMII_PO_EN;
1130         }
1131
1132         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1133         reg |= val;
1134         if (link)
1135                 reg |= PORT_OVERRIDE_LINK;
1136         else
1137                 reg &= ~PORT_OVERRIDE_LINK;
1138         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1139 }
1140
1141 static void b53_force_port_config(struct b53_device *dev, int port,
1142                                   int speed, int duplex,
1143                                   bool tx_pause, bool rx_pause)
1144 {
1145         u8 reg, val, off;
1146
1147         /* Override the port settings */
1148         if (port == dev->cpu_port) {
1149                 off = B53_PORT_OVERRIDE_CTRL;
1150                 val = PORT_OVERRIDE_EN;
1151         } else {
1152                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1153                 val = GMII_PO_EN;
1154         }
1155
1156         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1157         reg |= val;
1158         if (duplex == DUPLEX_FULL)
1159                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1160         else
1161                 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1162
1163         switch (speed) {
1164         case 2000:
1165                 reg |= PORT_OVERRIDE_SPEED_2000M;
1166                 fallthrough;
1167         case SPEED_1000:
1168                 reg |= PORT_OVERRIDE_SPEED_1000M;
1169                 break;
1170         case SPEED_100:
1171                 reg |= PORT_OVERRIDE_SPEED_100M;
1172                 break;
1173         case SPEED_10:
1174                 reg |= PORT_OVERRIDE_SPEED_10M;
1175                 break;
1176         default:
1177                 dev_err(dev->dev, "unknown speed: %d\n", speed);
1178                 return;
1179         }
1180
1181         if (rx_pause)
1182                 reg |= PORT_OVERRIDE_RX_FLOW;
1183         if (tx_pause)
1184                 reg |= PORT_OVERRIDE_TX_FLOW;
1185
1186         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1187 }
1188
1189 static void b53_adjust_link(struct dsa_switch *ds, int port,
1190                             struct phy_device *phydev)
1191 {
1192         struct b53_device *dev = ds->priv;
1193         struct ethtool_eee *p = &dev->ports[port].eee;
1194         u8 rgmii_ctrl = 0, reg = 0, off;
1195         bool tx_pause = false;
1196         bool rx_pause = false;
1197
1198         if (!phy_is_pseudo_fixed_link(phydev))
1199                 return;
1200
1201         /* Enable flow control on BCM5301x's CPU port */
1202         if (is5301x(dev) && port == dev->cpu_port)
1203                 tx_pause = rx_pause = true;
1204
1205         if (phydev->pause) {
1206                 if (phydev->asym_pause)
1207                         tx_pause = true;
1208                 rx_pause = true;
1209         }
1210
1211         b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1212                               tx_pause, rx_pause);
1213         b53_force_link(dev, port, phydev->link);
1214
1215         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1216                 if (port == 8)
1217                         off = B53_RGMII_CTRL_IMP;
1218                 else
1219                         off = B53_RGMII_CTRL_P(port);
1220
1221                 /* Configure the port RGMII clock delay by DLL disabled and
1222                  * tx_clk aligned timing (restoring to reset defaults)
1223                  */
1224                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1225                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1226                                 RGMII_CTRL_TIMING_SEL);
1227
1228                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1229                  * sure that we enable the port TX clock internal delay to
1230                  * account for this internal delay that is inserted, otherwise
1231                  * the switch won't be able to receive correctly.
1232                  *
1233                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1234                  * any delay neither on transmission nor reception, so the
1235                  * BCM53125 must also be configured accordingly to account for
1236                  * the lack of delay and introduce
1237                  *
1238                  * The BCM53125 switch has its RX clock and TX clock control
1239                  * swapped, hence the reason why we modify the TX clock path in
1240                  * the "RGMII" case
1241                  */
1242                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1243                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1244                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1245                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1246                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1247                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1248
1249                 dev_info(ds->dev, "Configured port %d for %s\n", port,
1250                          phy_modes(phydev->interface));
1251         }
1252
1253         /* configure MII port if necessary */
1254         if (is5325(dev)) {
1255                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1256                           &reg);
1257
1258                 /* reverse mii needs to be enabled */
1259                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1260                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1261                                    reg | PORT_OVERRIDE_RV_MII_25);
1262                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1263                                   &reg);
1264
1265                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1266                                 dev_err(ds->dev,
1267                                         "Failed to enable reverse MII mode\n");
1268                                 return;
1269                         }
1270                 }
1271         } else if (is5301x(dev)) {
1272                 if (port != dev->cpu_port) {
1273                         b53_force_port_config(dev, dev->cpu_port, 2000,
1274                                               DUPLEX_FULL, true, true);
1275                         b53_force_link(dev, dev->cpu_port, 1);
1276                 }
1277         }
1278
1279         /* Re-negotiate EEE if it was enabled already */
1280         p->eee_enabled = b53_eee_init(ds, port, phydev);
1281 }
1282
1283 void b53_port_event(struct dsa_switch *ds, int port)
1284 {
1285         struct b53_device *dev = ds->priv;
1286         bool link;
1287         u16 sts;
1288
1289         b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1290         link = !!(sts & BIT(port));
1291         dsa_port_phylink_mac_change(ds, port, link);
1292 }
1293 EXPORT_SYMBOL(b53_port_event);
1294
1295 void b53_phylink_validate(struct dsa_switch *ds, int port,
1296                           unsigned long *supported,
1297                           struct phylink_link_state *state)
1298 {
1299         struct b53_device *dev = ds->priv;
1300         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1301
1302         if (dev->ops->serdes_phylink_validate)
1303                 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1304
1305         /* Allow all the expected bits */
1306         phylink_set(mask, Autoneg);
1307         phylink_set_port_modes(mask);
1308         phylink_set(mask, Pause);
1309         phylink_set(mask, Asym_Pause);
1310
1311         /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1312          * support Gigabit, including Half duplex.
1313          */
1314         if (state->interface != PHY_INTERFACE_MODE_MII &&
1315             state->interface != PHY_INTERFACE_MODE_REVMII &&
1316             !phy_interface_mode_is_8023z(state->interface) &&
1317             !(is5325(dev) || is5365(dev))) {
1318                 phylink_set(mask, 1000baseT_Full);
1319                 phylink_set(mask, 1000baseT_Half);
1320         }
1321
1322         if (!phy_interface_mode_is_8023z(state->interface)) {
1323                 phylink_set(mask, 10baseT_Half);
1324                 phylink_set(mask, 10baseT_Full);
1325                 phylink_set(mask, 100baseT_Half);
1326                 phylink_set(mask, 100baseT_Full);
1327         }
1328
1329         bitmap_and(supported, supported, mask,
1330                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1331         bitmap_and(state->advertising, state->advertising, mask,
1332                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1333
1334         phylink_helper_basex_speed(state);
1335 }
1336 EXPORT_SYMBOL(b53_phylink_validate);
1337
1338 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1339                                struct phylink_link_state *state)
1340 {
1341         struct b53_device *dev = ds->priv;
1342         int ret = -EOPNOTSUPP;
1343
1344         if ((phy_interface_mode_is_8023z(state->interface) ||
1345              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1346              dev->ops->serdes_link_state)
1347                 ret = dev->ops->serdes_link_state(dev, port, state);
1348
1349         return ret;
1350 }
1351 EXPORT_SYMBOL(b53_phylink_mac_link_state);
1352
1353 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1354                             unsigned int mode,
1355                             const struct phylink_link_state *state)
1356 {
1357         struct b53_device *dev = ds->priv;
1358
1359         if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED)
1360                 return;
1361
1362         if ((phy_interface_mode_is_8023z(state->interface) ||
1363              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1364              dev->ops->serdes_config)
1365                 dev->ops->serdes_config(dev, port, mode, state);
1366 }
1367 EXPORT_SYMBOL(b53_phylink_mac_config);
1368
1369 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1370 {
1371         struct b53_device *dev = ds->priv;
1372
1373         if (dev->ops->serdes_an_restart)
1374                 dev->ops->serdes_an_restart(dev, port);
1375 }
1376 EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1377
1378 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1379                                unsigned int mode,
1380                                phy_interface_t interface)
1381 {
1382         struct b53_device *dev = ds->priv;
1383
1384         if (mode == MLO_AN_PHY)
1385                 return;
1386
1387         if (mode == MLO_AN_FIXED) {
1388                 b53_force_link(dev, port, false);
1389                 return;
1390         }
1391
1392         if (phy_interface_mode_is_8023z(interface) &&
1393             dev->ops->serdes_link_set)
1394                 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1395 }
1396 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1397
1398 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1399                              unsigned int mode,
1400                              phy_interface_t interface,
1401                              struct phy_device *phydev,
1402                              int speed, int duplex,
1403                              bool tx_pause, bool rx_pause)
1404 {
1405         struct b53_device *dev = ds->priv;
1406
1407         if (mode == MLO_AN_PHY)
1408                 return;
1409
1410         if (mode == MLO_AN_FIXED) {
1411                 b53_force_port_config(dev, port, speed, duplex,
1412                                       tx_pause, rx_pause);
1413                 b53_force_link(dev, port, true);
1414                 return;
1415         }
1416
1417         if (phy_interface_mode_is_8023z(interface) &&
1418             dev->ops->serdes_link_set)
1419                 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1420 }
1421 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1422
1423 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1424                        struct netlink_ext_ack *extack)
1425 {
1426         struct b53_device *dev = ds->priv;
1427
1428         b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);
1429
1430         return 0;
1431 }
1432 EXPORT_SYMBOL(b53_vlan_filtering);
1433
1434 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1435                             const struct switchdev_obj_port_vlan *vlan)
1436 {
1437         struct b53_device *dev = ds->priv;
1438
1439         if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
1440                 return -EOPNOTSUPP;
1441
1442         /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1443          * receiving VLAN tagged frames at all, we can still allow the port to
1444          * be configured for egress untagged.
1445          */
1446         if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1447             !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1448                 return -EINVAL;
1449
1450         if (vlan->vid >= dev->num_vlans)
1451                 return -ERANGE;
1452
1453         b53_enable_vlan(dev, port, true, ds->vlan_filtering);
1454
1455         return 0;
1456 }
1457
1458 int b53_vlan_add(struct dsa_switch *ds, int port,
1459                  const struct switchdev_obj_port_vlan *vlan,
1460                  struct netlink_ext_ack *extack)
1461 {
1462         struct b53_device *dev = ds->priv;
1463         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1464         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1465         struct b53_vlan *vl;
1466         int err;
1467
1468         err = b53_vlan_prepare(ds, port, vlan);
1469         if (err)
1470                 return err;
1471
1472         vl = &dev->vlans[vlan->vid];
1473
1474         b53_get_vlan_entry(dev, vlan->vid, vl);
1475
1476         if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1477                 untagged = true;
1478
1479         vl->members |= BIT(port);
1480         if (untagged && !dsa_is_cpu_port(ds, port))
1481                 vl->untag |= BIT(port);
1482         else
1483                 vl->untag &= ~BIT(port);
1484
1485         b53_set_vlan_entry(dev, vlan->vid, vl);
1486         b53_fast_age_vlan(dev, vlan->vid);
1487
1488         if (pvid && !dsa_is_cpu_port(ds, port)) {
1489                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1490                             vlan->vid);
1491                 b53_fast_age_vlan(dev, vlan->vid);
1492         }
1493
1494         return 0;
1495 }
1496 EXPORT_SYMBOL(b53_vlan_add);
1497
1498 int b53_vlan_del(struct dsa_switch *ds, int port,
1499                  const struct switchdev_obj_port_vlan *vlan)
1500 {
1501         struct b53_device *dev = ds->priv;
1502         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1503         struct b53_vlan *vl;
1504         u16 pvid;
1505
1506         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1507
1508         vl = &dev->vlans[vlan->vid];
1509
1510         b53_get_vlan_entry(dev, vlan->vid, vl);
1511
1512         vl->members &= ~BIT(port);
1513
1514         if (pvid == vlan->vid)
1515                 pvid = b53_default_pvid(dev);
1516
1517         if (untagged && !dsa_is_cpu_port(ds, port))
1518                 vl->untag &= ~(BIT(port));
1519
1520         b53_set_vlan_entry(dev, vlan->vid, vl);
1521         b53_fast_age_vlan(dev, vlan->vid);
1522
1523         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1524         b53_fast_age_vlan(dev, pvid);
1525
1526         return 0;
1527 }
1528 EXPORT_SYMBOL(b53_vlan_del);
1529
1530 /* Address Resolution Logic routines */
1531 static int b53_arl_op_wait(struct b53_device *dev)
1532 {
1533         unsigned int timeout = 10;
1534         u8 reg;
1535
1536         do {
1537                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1538                 if (!(reg & ARLTBL_START_DONE))
1539                         return 0;
1540
1541                 usleep_range(1000, 2000);
1542         } while (timeout--);
1543
1544         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1545
1546         return -ETIMEDOUT;
1547 }
1548
1549 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1550 {
1551         u8 reg;
1552
1553         if (op > ARLTBL_RW)
1554                 return -EINVAL;
1555
1556         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1557         reg |= ARLTBL_START_DONE;
1558         if (op)
1559                 reg |= ARLTBL_RW;
1560         else
1561                 reg &= ~ARLTBL_RW;
1562         if (dev->vlan_enabled)
1563                 reg &= ~ARLTBL_IVL_SVL_SELECT;
1564         else
1565                 reg |= ARLTBL_IVL_SVL_SELECT;
1566         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1567
1568         return b53_arl_op_wait(dev);
1569 }
1570
1571 static int b53_arl_read(struct b53_device *dev, u64 mac,
1572                         u16 vid, struct b53_arl_entry *ent, u8 *idx)
1573 {
1574         DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1575         unsigned int i;
1576         int ret;
1577
1578         ret = b53_arl_op_wait(dev);
1579         if (ret)
1580                 return ret;
1581
1582         bitmap_zero(free_bins, dev->num_arl_bins);
1583
1584         /* Read the bins */
1585         for (i = 0; i < dev->num_arl_bins; i++) {
1586                 u64 mac_vid;
1587                 u32 fwd_entry;
1588
1589                 b53_read64(dev, B53_ARLIO_PAGE,
1590                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1591                 b53_read32(dev, B53_ARLIO_PAGE,
1592                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1593                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1594
1595                 if (!(fwd_entry & ARLTBL_VALID)) {
1596                         set_bit(i, free_bins);
1597                         continue;
1598                 }
1599                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1600                         continue;
1601                 if (dev->vlan_enabled &&
1602                     ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1603                         continue;
1604                 *idx = i;
1605                 return 0;
1606         }
1607
1608         if (bitmap_weight(free_bins, dev->num_arl_bins) == 0)
1609                 return -ENOSPC;
1610
1611         *idx = find_first_bit(free_bins, dev->num_arl_bins);
1612
1613         return -ENOENT;
1614 }
1615
1616 static int b53_arl_op(struct b53_device *dev, int op, int port,
1617                       const unsigned char *addr, u16 vid, bool is_valid)
1618 {
1619         struct b53_arl_entry ent;
1620         u32 fwd_entry;
1621         u64 mac, mac_vid = 0;
1622         u8 idx = 0;
1623         int ret;
1624
1625         /* Convert the array into a 64-bit MAC */
1626         mac = ether_addr_to_u64(addr);
1627
1628         /* Perform a read for the given MAC and VID */
1629         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1630         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1631
1632         /* Issue a read operation for this MAC */
1633         ret = b53_arl_rw_op(dev, 1);
1634         if (ret)
1635                 return ret;
1636
1637         ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1638
1639         /* If this is a read, just finish now */
1640         if (op)
1641                 return ret;
1642
1643         switch (ret) {
1644         case -ETIMEDOUT:
1645                 return ret;
1646         case -ENOSPC:
1647                 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1648                         addr, vid);
1649                 return is_valid ? ret : 0;
1650         case -ENOENT:
1651                 /* We could not find a matching MAC, so reset to a new entry */
1652                 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1653                         addr, vid, idx);
1654                 fwd_entry = 0;
1655                 break;
1656         default:
1657                 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1658                         addr, vid, idx);
1659                 break;
1660         }
1661
1662         /* For multicast address, the port is a bitmask and the validity
1663          * is determined by having at least one port being still active
1664          */
1665         if (!is_multicast_ether_addr(addr)) {
1666                 ent.port = port;
1667                 ent.is_valid = is_valid;
1668         } else {
1669                 if (is_valid)
1670                         ent.port |= BIT(port);
1671                 else
1672                         ent.port &= ~BIT(port);
1673
1674                 ent.is_valid = !!(ent.port);
1675         }
1676
1677         ent.vid = vid;
1678         ent.is_static = true;
1679         ent.is_age = false;
1680         memcpy(ent.mac, addr, ETH_ALEN);
1681         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1682
1683         b53_write64(dev, B53_ARLIO_PAGE,
1684                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1685         b53_write32(dev, B53_ARLIO_PAGE,
1686                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1687
1688         return b53_arl_rw_op(dev, 0);
1689 }
1690
1691 int b53_fdb_add(struct dsa_switch *ds, int port,
1692                 const unsigned char *addr, u16 vid)
1693 {
1694         struct b53_device *priv = ds->priv;
1695
1696         /* 5325 and 5365 require some more massaging, but could
1697          * be supported eventually
1698          */
1699         if (is5325(priv) || is5365(priv))
1700                 return -EOPNOTSUPP;
1701
1702         return b53_arl_op(priv, 0, port, addr, vid, true);
1703 }
1704 EXPORT_SYMBOL(b53_fdb_add);
1705
1706 int b53_fdb_del(struct dsa_switch *ds, int port,
1707                 const unsigned char *addr, u16 vid)
1708 {
1709         struct b53_device *priv = ds->priv;
1710
1711         return b53_arl_op(priv, 0, port, addr, vid, false);
1712 }
1713 EXPORT_SYMBOL(b53_fdb_del);
1714
1715 static int b53_arl_search_wait(struct b53_device *dev)
1716 {
1717         unsigned int timeout = 1000;
1718         u8 reg;
1719
1720         do {
1721                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1722                 if (!(reg & ARL_SRCH_STDN))
1723                         return 0;
1724
1725                 if (reg & ARL_SRCH_VLID)
1726                         return 0;
1727
1728                 usleep_range(1000, 2000);
1729         } while (timeout--);
1730
1731         return -ETIMEDOUT;
1732 }
1733
1734 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1735                               struct b53_arl_entry *ent)
1736 {
1737         u64 mac_vid;
1738         u32 fwd_entry;
1739
1740         b53_read64(dev, B53_ARLIO_PAGE,
1741                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1742         b53_read32(dev, B53_ARLIO_PAGE,
1743                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1744         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1745 }
1746
1747 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1748                         dsa_fdb_dump_cb_t *cb, void *data)
1749 {
1750         if (!ent->is_valid)
1751                 return 0;
1752
1753         if (port != ent->port)
1754                 return 0;
1755
1756         return cb(ent->mac, ent->vid, ent->is_static, data);
1757 }
1758
1759 int b53_fdb_dump(struct dsa_switch *ds, int port,
1760                  dsa_fdb_dump_cb_t *cb, void *data)
1761 {
1762         struct b53_device *priv = ds->priv;
1763         struct b53_arl_entry results[2];
1764         unsigned int count = 0;
1765         int ret;
1766         u8 reg;
1767
1768         /* Start search operation */
1769         reg = ARL_SRCH_STDN;
1770         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1771
1772         do {
1773                 ret = b53_arl_search_wait(priv);
1774                 if (ret)
1775                         return ret;
1776
1777                 b53_arl_search_rd(priv, 0, &results[0]);
1778                 ret = b53_fdb_copy(port, &results[0], cb, data);
1779                 if (ret)
1780                         return ret;
1781
1782                 if (priv->num_arl_bins > 2) {
1783                         b53_arl_search_rd(priv, 1, &results[1]);
1784                         ret = b53_fdb_copy(port, &results[1], cb, data);
1785                         if (ret)
1786                                 return ret;
1787
1788                         if (!results[0].is_valid && !results[1].is_valid)
1789                                 break;
1790                 }
1791
1792         } while (count++ < b53_max_arl_entries(priv) / 2);
1793
1794         return 0;
1795 }
1796 EXPORT_SYMBOL(b53_fdb_dump);
1797
1798 int b53_mdb_add(struct dsa_switch *ds, int port,
1799                 const struct switchdev_obj_port_mdb *mdb)
1800 {
1801         struct b53_device *priv = ds->priv;
1802
1803         /* 5325 and 5365 require some more massaging, but could
1804          * be supported eventually
1805          */
1806         if (is5325(priv) || is5365(priv))
1807                 return -EOPNOTSUPP;
1808
1809         return b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1810 }
1811 EXPORT_SYMBOL(b53_mdb_add);
1812
1813 int b53_mdb_del(struct dsa_switch *ds, int port,
1814                 const struct switchdev_obj_port_mdb *mdb)
1815 {
1816         struct b53_device *priv = ds->priv;
1817         int ret;
1818
1819         ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1820         if (ret)
1821                 dev_err(ds->dev, "failed to delete MDB entry\n");
1822
1823         return ret;
1824 }
1825 EXPORT_SYMBOL(b53_mdb_del);
1826
1827 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1828 {
1829         struct b53_device *dev = ds->priv;
1830         s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1831         u16 pvlan, reg;
1832         unsigned int i;
1833
1834         /* On 7278, port 7 which connects to the ASP should only receive
1835          * traffic from matching CFP rules.
1836          */
1837         if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1838                 return -EINVAL;
1839
1840         /* Make this port leave the all VLANs join since we will have proper
1841          * VLAN entries from now on
1842          */
1843         if (is58xx(dev)) {
1844                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1845                 reg &= ~BIT(port);
1846                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1847                         reg &= ~BIT(cpu_port);
1848                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1849         }
1850
1851         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1852
1853         b53_for_each_port(dev, i) {
1854                 if (dsa_to_port(ds, i)->bridge_dev != br)
1855                         continue;
1856
1857                 /* Add this local port to the remote port VLAN control
1858                  * membership and update the remote port bitmask
1859                  */
1860                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1861                 reg |= BIT(port);
1862                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1863                 dev->ports[i].vlan_ctl_mask = reg;
1864
1865                 pvlan |= BIT(i);
1866         }
1867
1868         /* Configure the local port VLAN control membership to include
1869          * remote ports and update the local port bitmask
1870          */
1871         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1872         dev->ports[port].vlan_ctl_mask = pvlan;
1873
1874         return 0;
1875 }
1876 EXPORT_SYMBOL(b53_br_join);
1877
1878 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1879 {
1880         struct b53_device *dev = ds->priv;
1881         struct b53_vlan *vl = &dev->vlans[0];
1882         s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1883         unsigned int i;
1884         u16 pvlan, reg, pvid;
1885
1886         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1887
1888         b53_for_each_port(dev, i) {
1889                 /* Don't touch the remaining ports */
1890                 if (dsa_to_port(ds, i)->bridge_dev != br)
1891                         continue;
1892
1893                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1894                 reg &= ~BIT(port);
1895                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1896                 dev->ports[port].vlan_ctl_mask = reg;
1897
1898                 /* Prevent self removal to preserve isolation */
1899                 if (port != i)
1900                         pvlan &= ~BIT(i);
1901         }
1902
1903         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1904         dev->ports[port].vlan_ctl_mask = pvlan;
1905
1906         pvid = b53_default_pvid(dev);
1907
1908         /* Make this port join all VLANs without VLAN entries */
1909         if (is58xx(dev)) {
1910                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1911                 reg |= BIT(port);
1912                 if (!(reg & BIT(cpu_port)))
1913                         reg |= BIT(cpu_port);
1914                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1915         } else {
1916                 b53_get_vlan_entry(dev, pvid, vl);
1917                 vl->members |= BIT(port) | BIT(cpu_port);
1918                 vl->untag |= BIT(port) | BIT(cpu_port);
1919                 b53_set_vlan_entry(dev, pvid, vl);
1920         }
1921 }
1922 EXPORT_SYMBOL(b53_br_leave);
1923
1924 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1925 {
1926         struct b53_device *dev = ds->priv;
1927         u8 hw_state;
1928         u8 reg;
1929
1930         switch (state) {
1931         case BR_STATE_DISABLED:
1932                 hw_state = PORT_CTRL_DIS_STATE;
1933                 break;
1934         case BR_STATE_LISTENING:
1935                 hw_state = PORT_CTRL_LISTEN_STATE;
1936                 break;
1937         case BR_STATE_LEARNING:
1938                 hw_state = PORT_CTRL_LEARN_STATE;
1939                 break;
1940         case BR_STATE_FORWARDING:
1941                 hw_state = PORT_CTRL_FWD_STATE;
1942                 break;
1943         case BR_STATE_BLOCKING:
1944                 hw_state = PORT_CTRL_BLOCK_STATE;
1945                 break;
1946         default:
1947                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1948                 return;
1949         }
1950
1951         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1952         reg &= ~PORT_CTRL_STP_STATE_MASK;
1953         reg |= hw_state;
1954         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1955 }
1956 EXPORT_SYMBOL(b53_br_set_stp_state);
1957
1958 void b53_br_fast_age(struct dsa_switch *ds, int port)
1959 {
1960         struct b53_device *dev = ds->priv;
1961
1962         if (b53_fast_age_port(dev, port))
1963                 dev_err(ds->dev, "fast ageing failed\n");
1964 }
1965 EXPORT_SYMBOL(b53_br_fast_age);
1966
1967 int b53_br_flags_pre(struct dsa_switch *ds, int port,
1968                      struct switchdev_brport_flags flags,
1969                      struct netlink_ext_ack *extack)
1970 {
1971         if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
1972                 return -EINVAL;
1973
1974         return 0;
1975 }
1976 EXPORT_SYMBOL(b53_br_flags_pre);
1977
1978 int b53_br_flags(struct dsa_switch *ds, int port,
1979                  struct switchdev_brport_flags flags,
1980                  struct netlink_ext_ack *extack)
1981 {
1982         if (flags.mask & BR_FLOOD)
1983                 b53_port_set_ucast_flood(ds->priv, port,
1984                                          !!(flags.val & BR_FLOOD));
1985         if (flags.mask & BR_MCAST_FLOOD)
1986                 b53_port_set_mcast_flood(ds->priv, port,
1987                                          !!(flags.val & BR_MCAST_FLOOD));
1988         if (flags.mask & BR_LEARNING)
1989                 b53_port_set_learning(ds->priv, port,
1990                                       !!(flags.val & BR_LEARNING));
1991
1992         return 0;
1993 }
1994 EXPORT_SYMBOL(b53_br_flags);
1995
1996 int b53_set_mrouter(struct dsa_switch *ds, int port, bool mrouter,
1997                     struct netlink_ext_ack *extack)
1998 {
1999         b53_port_set_mcast_flood(ds->priv, port, mrouter);
2000
2001         return 0;
2002 }
2003 EXPORT_SYMBOL(b53_set_mrouter);
2004
2005 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2006 {
2007         /* Broadcom switches will accept enabling Broadcom tags on the
2008          * following ports: 5, 7 and 8, any other port is not supported
2009          */
2010         switch (port) {
2011         case B53_CPU_PORT_25:
2012         case 7:
2013         case B53_CPU_PORT:
2014                 return true;
2015         }
2016
2017         return false;
2018 }
2019
2020 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2021                                      enum dsa_tag_protocol tag_protocol)
2022 {
2023         bool ret = b53_possible_cpu_port(ds, port);
2024
2025         if (!ret) {
2026                 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2027                          port);
2028                 return ret;
2029         }
2030
2031         switch (tag_protocol) {
2032         case DSA_TAG_PROTO_BRCM:
2033         case DSA_TAG_PROTO_BRCM_PREPEND:
2034                 dev_warn(ds->dev,
2035                          "Port %d is stacked to Broadcom tag switch\n", port);
2036                 ret = false;
2037                 break;
2038         default:
2039                 ret = true;
2040                 break;
2041         }
2042
2043         return ret;
2044 }
2045
2046 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2047                                            enum dsa_tag_protocol mprot)
2048 {
2049         struct b53_device *dev = ds->priv;
2050
2051         if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2052                 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2053                 goto out;
2054         }
2055
2056         /* Older models require a different 6 byte tag */
2057         if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2058                 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2059                 goto out;
2060         }
2061
2062         /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2063          * which requires us to use the prepended Broadcom tag type
2064          */
2065         if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2066                 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2067                 goto out;
2068         }
2069
2070         dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2071 out:
2072         return dev->tag_protocol;
2073 }
2074 EXPORT_SYMBOL(b53_get_tag_protocol);
2075
2076 int b53_mirror_add(struct dsa_switch *ds, int port,
2077                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
2078 {
2079         struct b53_device *dev = ds->priv;
2080         u16 reg, loc;
2081
2082         if (ingress)
2083                 loc = B53_IG_MIR_CTL;
2084         else
2085                 loc = B53_EG_MIR_CTL;
2086
2087         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2088         reg |= BIT(port);
2089         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2090
2091         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2092         reg &= ~CAP_PORT_MASK;
2093         reg |= mirror->to_local_port;
2094         reg |= MIRROR_EN;
2095         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2096
2097         return 0;
2098 }
2099 EXPORT_SYMBOL(b53_mirror_add);
2100
2101 void b53_mirror_del(struct dsa_switch *ds, int port,
2102                     struct dsa_mall_mirror_tc_entry *mirror)
2103 {
2104         struct b53_device *dev = ds->priv;
2105         bool loc_disable = false, other_loc_disable = false;
2106         u16 reg, loc;
2107
2108         if (mirror->ingress)
2109                 loc = B53_IG_MIR_CTL;
2110         else
2111                 loc = B53_EG_MIR_CTL;
2112
2113         /* Update the desired ingress/egress register */
2114         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2115         reg &= ~BIT(port);
2116         if (!(reg & MIRROR_MASK))
2117                 loc_disable = true;
2118         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2119
2120         /* Now look at the other one to know if we can disable mirroring
2121          * entirely
2122          */
2123         if (mirror->ingress)
2124                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
2125         else
2126                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
2127         if (!(reg & MIRROR_MASK))
2128                 other_loc_disable = true;
2129
2130         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2131         /* Both no longer have ports, let's disable mirroring */
2132         if (loc_disable && other_loc_disable) {
2133                 reg &= ~MIRROR_EN;
2134                 reg &= ~mirror->to_local_port;
2135         }
2136         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2137 }
2138 EXPORT_SYMBOL(b53_mirror_del);
2139
2140 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2141 {
2142         struct b53_device *dev = ds->priv;
2143         u16 reg;
2144
2145         b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
2146         if (enable)
2147                 reg |= BIT(port);
2148         else
2149                 reg &= ~BIT(port);
2150         b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2151 }
2152 EXPORT_SYMBOL(b53_eee_enable_set);
2153
2154
2155 /* Returns 0 if EEE was not enabled, or 1 otherwise
2156  */
2157 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2158 {
2159         int ret;
2160
2161         ret = phy_init_eee(phy, 0);
2162         if (ret)
2163                 return 0;
2164
2165         b53_eee_enable_set(ds, port, true);
2166
2167         return 1;
2168 }
2169 EXPORT_SYMBOL(b53_eee_init);
2170
2171 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2172 {
2173         struct b53_device *dev = ds->priv;
2174         struct ethtool_eee *p = &dev->ports[port].eee;
2175         u16 reg;
2176
2177         if (is5325(dev) || is5365(dev))
2178                 return -EOPNOTSUPP;
2179
2180         b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
2181         e->eee_enabled = p->eee_enabled;
2182         e->eee_active = !!(reg & BIT(port));
2183
2184         return 0;
2185 }
2186 EXPORT_SYMBOL(b53_get_mac_eee);
2187
2188 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2189 {
2190         struct b53_device *dev = ds->priv;
2191         struct ethtool_eee *p = &dev->ports[port].eee;
2192
2193         if (is5325(dev) || is5365(dev))
2194                 return -EOPNOTSUPP;
2195
2196         p->eee_enabled = e->eee_enabled;
2197         b53_eee_enable_set(ds, port, e->eee_enabled);
2198
2199         return 0;
2200 }
2201 EXPORT_SYMBOL(b53_set_mac_eee);
2202
2203 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2204 {
2205         struct b53_device *dev = ds->priv;
2206         bool enable_jumbo;
2207         bool allow_10_100;
2208
2209         if (is5325(dev) || is5365(dev))
2210                 return -EOPNOTSUPP;
2211
2212         enable_jumbo = (mtu >= JMS_MIN_SIZE);
2213         allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2214
2215         return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2216 }
2217
2218 static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2219 {
2220         return JMS_MAX_SIZE;
2221 }
2222
2223 static const struct dsa_switch_ops b53_switch_ops = {
2224         .get_tag_protocol       = b53_get_tag_protocol,
2225         .setup                  = b53_setup,
2226         .teardown               = b53_teardown,
2227         .get_strings            = b53_get_strings,
2228         .get_ethtool_stats      = b53_get_ethtool_stats,
2229         .get_sset_count         = b53_get_sset_count,
2230         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
2231         .phy_read               = b53_phy_read16,
2232         .phy_write              = b53_phy_write16,
2233         .adjust_link            = b53_adjust_link,
2234         .phylink_validate       = b53_phylink_validate,
2235         .phylink_mac_link_state = b53_phylink_mac_link_state,
2236         .phylink_mac_config     = b53_phylink_mac_config,
2237         .phylink_mac_an_restart = b53_phylink_mac_an_restart,
2238         .phylink_mac_link_down  = b53_phylink_mac_link_down,
2239         .phylink_mac_link_up    = b53_phylink_mac_link_up,
2240         .port_enable            = b53_enable_port,
2241         .port_disable           = b53_disable_port,
2242         .get_mac_eee            = b53_get_mac_eee,
2243         .set_mac_eee            = b53_set_mac_eee,
2244         .port_bridge_join       = b53_br_join,
2245         .port_bridge_leave      = b53_br_leave,
2246         .port_pre_bridge_flags  = b53_br_flags_pre,
2247         .port_bridge_flags      = b53_br_flags,
2248         .port_set_mrouter       = b53_set_mrouter,
2249         .port_stp_state_set     = b53_br_set_stp_state,
2250         .port_fast_age          = b53_br_fast_age,
2251         .port_vlan_filtering    = b53_vlan_filtering,
2252         .port_vlan_add          = b53_vlan_add,
2253         .port_vlan_del          = b53_vlan_del,
2254         .port_fdb_dump          = b53_fdb_dump,
2255         .port_fdb_add           = b53_fdb_add,
2256         .port_fdb_del           = b53_fdb_del,
2257         .port_mirror_add        = b53_mirror_add,
2258         .port_mirror_del        = b53_mirror_del,
2259         .port_mdb_add           = b53_mdb_add,
2260         .port_mdb_del           = b53_mdb_del,
2261         .port_max_mtu           = b53_get_max_mtu,
2262         .port_change_mtu        = b53_change_mtu,
2263 };
2264
2265 struct b53_chip_data {
2266         u32 chip_id;
2267         const char *dev_name;
2268         u16 vlans;
2269         u16 enabled_ports;
2270         u8 cpu_port;
2271         u8 vta_regs[3];
2272         u8 arl_bins;
2273         u16 arl_buckets;
2274         u8 duplex_reg;
2275         u8 jumbo_pm_reg;
2276         u8 jumbo_size_reg;
2277 };
2278
2279 #define B53_VTA_REGS    \
2280         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2281 #define B53_VTA_REGS_9798 \
2282         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2283 #define B53_VTA_REGS_63XX \
2284         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2285
2286 static const struct b53_chip_data b53_switch_chips[] = {
2287         {
2288                 .chip_id = BCM5325_DEVICE_ID,
2289                 .dev_name = "BCM5325",
2290                 .vlans = 16,
2291                 .enabled_ports = 0x1f,
2292                 .arl_bins = 2,
2293                 .arl_buckets = 1024,
2294                 .cpu_port = B53_CPU_PORT_25,
2295                 .duplex_reg = B53_DUPLEX_STAT_FE,
2296         },
2297         {
2298                 .chip_id = BCM5365_DEVICE_ID,
2299                 .dev_name = "BCM5365",
2300                 .vlans = 256,
2301                 .enabled_ports = 0x1f,
2302                 .arl_bins = 2,
2303                 .arl_buckets = 1024,
2304                 .cpu_port = B53_CPU_PORT_25,
2305                 .duplex_reg = B53_DUPLEX_STAT_FE,
2306         },
2307         {
2308                 .chip_id = BCM5389_DEVICE_ID,
2309                 .dev_name = "BCM5389",
2310                 .vlans = 4096,
2311                 .enabled_ports = 0x1f,
2312                 .arl_bins = 4,
2313                 .arl_buckets = 1024,
2314                 .cpu_port = B53_CPU_PORT,
2315                 .vta_regs = B53_VTA_REGS,
2316                 .duplex_reg = B53_DUPLEX_STAT_GE,
2317                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2318                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2319         },
2320         {
2321                 .chip_id = BCM5395_DEVICE_ID,
2322                 .dev_name = "BCM5395",
2323                 .vlans = 4096,
2324                 .enabled_ports = 0x1f,
2325                 .arl_bins = 4,
2326                 .arl_buckets = 1024,
2327                 .cpu_port = B53_CPU_PORT,
2328                 .vta_regs = B53_VTA_REGS,
2329                 .duplex_reg = B53_DUPLEX_STAT_GE,
2330                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2331                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2332         },
2333         {
2334                 .chip_id = BCM5397_DEVICE_ID,
2335                 .dev_name = "BCM5397",
2336                 .vlans = 4096,
2337                 .enabled_ports = 0x1f,
2338                 .arl_bins = 4,
2339                 .arl_buckets = 1024,
2340                 .cpu_port = B53_CPU_PORT,
2341                 .vta_regs = B53_VTA_REGS_9798,
2342                 .duplex_reg = B53_DUPLEX_STAT_GE,
2343                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2344                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2345         },
2346         {
2347                 .chip_id = BCM5398_DEVICE_ID,
2348                 .dev_name = "BCM5398",
2349                 .vlans = 4096,
2350                 .enabled_ports = 0x7f,
2351                 .arl_bins = 4,
2352                 .arl_buckets = 1024,
2353                 .cpu_port = B53_CPU_PORT,
2354                 .vta_regs = B53_VTA_REGS_9798,
2355                 .duplex_reg = B53_DUPLEX_STAT_GE,
2356                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2357                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2358         },
2359         {
2360                 .chip_id = BCM53115_DEVICE_ID,
2361                 .dev_name = "BCM53115",
2362                 .vlans = 4096,
2363                 .enabled_ports = 0x1f,
2364                 .arl_bins = 4,
2365                 .arl_buckets = 1024,
2366                 .vta_regs = B53_VTA_REGS,
2367                 .cpu_port = B53_CPU_PORT,
2368                 .duplex_reg = B53_DUPLEX_STAT_GE,
2369                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2370                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2371         },
2372         {
2373                 .chip_id = BCM53125_DEVICE_ID,
2374                 .dev_name = "BCM53125",
2375                 .vlans = 4096,
2376                 .enabled_ports = 0xff,
2377                 .arl_bins = 4,
2378                 .arl_buckets = 1024,
2379                 .cpu_port = B53_CPU_PORT,
2380                 .vta_regs = B53_VTA_REGS,
2381                 .duplex_reg = B53_DUPLEX_STAT_GE,
2382                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2383                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2384         },
2385         {
2386                 .chip_id = BCM53128_DEVICE_ID,
2387                 .dev_name = "BCM53128",
2388                 .vlans = 4096,
2389                 .enabled_ports = 0x1ff,
2390                 .arl_bins = 4,
2391                 .arl_buckets = 1024,
2392                 .cpu_port = B53_CPU_PORT,
2393                 .vta_regs = B53_VTA_REGS,
2394                 .duplex_reg = B53_DUPLEX_STAT_GE,
2395                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2396                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2397         },
2398         {
2399                 .chip_id = BCM63XX_DEVICE_ID,
2400                 .dev_name = "BCM63xx",
2401                 .vlans = 4096,
2402                 .enabled_ports = 0, /* pdata must provide them */
2403                 .arl_bins = 4,
2404                 .arl_buckets = 1024,
2405                 .cpu_port = B53_CPU_PORT,
2406                 .vta_regs = B53_VTA_REGS_63XX,
2407                 .duplex_reg = B53_DUPLEX_STAT_63XX,
2408                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2409                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2410         },
2411         {
2412                 .chip_id = BCM53010_DEVICE_ID,
2413                 .dev_name = "BCM53010",
2414                 .vlans = 4096,
2415                 .enabled_ports = 0x1f,
2416                 .arl_bins = 4,
2417                 .arl_buckets = 1024,
2418                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2419                 .vta_regs = B53_VTA_REGS,
2420                 .duplex_reg = B53_DUPLEX_STAT_GE,
2421                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2422                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2423         },
2424         {
2425                 .chip_id = BCM53011_DEVICE_ID,
2426                 .dev_name = "BCM53011",
2427                 .vlans = 4096,
2428                 .enabled_ports = 0x1bf,
2429                 .arl_bins = 4,
2430                 .arl_buckets = 1024,
2431                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2432                 .vta_regs = B53_VTA_REGS,
2433                 .duplex_reg = B53_DUPLEX_STAT_GE,
2434                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2435                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2436         },
2437         {
2438                 .chip_id = BCM53012_DEVICE_ID,
2439                 .dev_name = "BCM53012",
2440                 .vlans = 4096,
2441                 .enabled_ports = 0x1bf,
2442                 .arl_bins = 4,
2443                 .arl_buckets = 1024,
2444                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2445                 .vta_regs = B53_VTA_REGS,
2446                 .duplex_reg = B53_DUPLEX_STAT_GE,
2447                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2448                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2449         },
2450         {
2451                 .chip_id = BCM53018_DEVICE_ID,
2452                 .dev_name = "BCM53018",
2453                 .vlans = 4096,
2454                 .enabled_ports = 0x1f,
2455                 .arl_bins = 4,
2456                 .arl_buckets = 1024,
2457                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2458                 .vta_regs = B53_VTA_REGS,
2459                 .duplex_reg = B53_DUPLEX_STAT_GE,
2460                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2461                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2462         },
2463         {
2464                 .chip_id = BCM53019_DEVICE_ID,
2465                 .dev_name = "BCM53019",
2466                 .vlans = 4096,
2467                 .enabled_ports = 0x1f,
2468                 .arl_bins = 4,
2469                 .arl_buckets = 1024,
2470                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2471                 .vta_regs = B53_VTA_REGS,
2472                 .duplex_reg = B53_DUPLEX_STAT_GE,
2473                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2474                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2475         },
2476         {
2477                 .chip_id = BCM58XX_DEVICE_ID,
2478                 .dev_name = "BCM585xx/586xx/88312",
2479                 .vlans  = 4096,
2480                 .enabled_ports = 0x1ff,
2481                 .arl_bins = 4,
2482                 .arl_buckets = 1024,
2483                 .cpu_port = B53_CPU_PORT,
2484                 .vta_regs = B53_VTA_REGS,
2485                 .duplex_reg = B53_DUPLEX_STAT_GE,
2486                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2487                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2488         },
2489         {
2490                 .chip_id = BCM583XX_DEVICE_ID,
2491                 .dev_name = "BCM583xx/11360",
2492                 .vlans = 4096,
2493                 .enabled_ports = 0x103,
2494                 .arl_bins = 4,
2495                 .arl_buckets = 1024,
2496                 .cpu_port = B53_CPU_PORT,
2497                 .vta_regs = B53_VTA_REGS,
2498                 .duplex_reg = B53_DUPLEX_STAT_GE,
2499                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2500                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2501         },
2502         /* Starfighter 2 */
2503         {
2504                 .chip_id = BCM4908_DEVICE_ID,
2505                 .dev_name = "BCM4908",
2506                 .vlans = 4096,
2507                 .enabled_ports = 0x1bf,
2508                 .arl_bins = 4,
2509                 .arl_buckets = 256,
2510                 .cpu_port = 8, /* TODO: ports 4, 5, 8 */
2511                 .vta_regs = B53_VTA_REGS,
2512                 .duplex_reg = B53_DUPLEX_STAT_GE,
2513                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2514                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2515         },
2516         {
2517                 .chip_id = BCM7445_DEVICE_ID,
2518                 .dev_name = "BCM7445",
2519                 .vlans  = 4096,
2520                 .enabled_ports = 0x1ff,
2521                 .arl_bins = 4,
2522                 .arl_buckets = 1024,
2523                 .cpu_port = B53_CPU_PORT,
2524                 .vta_regs = B53_VTA_REGS,
2525                 .duplex_reg = B53_DUPLEX_STAT_GE,
2526                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2527                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2528         },
2529         {
2530                 .chip_id = BCM7278_DEVICE_ID,
2531                 .dev_name = "BCM7278",
2532                 .vlans = 4096,
2533                 .enabled_ports = 0x1ff,
2534                 .arl_bins = 4,
2535                 .arl_buckets = 256,
2536                 .cpu_port = B53_CPU_PORT,
2537                 .vta_regs = B53_VTA_REGS,
2538                 .duplex_reg = B53_DUPLEX_STAT_GE,
2539                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2540                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2541         },
2542 };
2543
2544 static int b53_switch_init(struct b53_device *dev)
2545 {
2546         unsigned int i;
2547         int ret;
2548
2549         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2550                 const struct b53_chip_data *chip = &b53_switch_chips[i];
2551
2552                 if (chip->chip_id == dev->chip_id) {
2553                         if (!dev->enabled_ports)
2554                                 dev->enabled_ports = chip->enabled_ports;
2555                         dev->name = chip->dev_name;
2556                         dev->duplex_reg = chip->duplex_reg;
2557                         dev->vta_regs[0] = chip->vta_regs[0];
2558                         dev->vta_regs[1] = chip->vta_regs[1];
2559                         dev->vta_regs[2] = chip->vta_regs[2];
2560                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2561                         dev->cpu_port = chip->cpu_port;
2562                         dev->num_vlans = chip->vlans;
2563                         dev->num_arl_bins = chip->arl_bins;
2564                         dev->num_arl_buckets = chip->arl_buckets;
2565                         break;
2566                 }
2567         }
2568
2569         /* check which BCM5325x version we have */
2570         if (is5325(dev)) {
2571                 u8 vc4;
2572
2573                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2574
2575                 /* check reserved bits */
2576                 switch (vc4 & 3) {
2577                 case 1:
2578                         /* BCM5325E */
2579                         break;
2580                 case 3:
2581                         /* BCM5325F - do not use port 4 */
2582                         dev->enabled_ports &= ~BIT(4);
2583                         break;
2584                 default:
2585 /* On the BCM47XX SoCs this is the supported internal switch.*/
2586 #ifndef CONFIG_BCM47XX
2587                         /* BCM5325M */
2588                         return -EINVAL;
2589 #else
2590                         break;
2591 #endif
2592                 }
2593         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2594                 u64 strap_value;
2595
2596                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2597                 /* use second IMP port if GMII is enabled */
2598                 if (strap_value & SV_GMII_CTRL_115)
2599                         dev->cpu_port = 5;
2600         }
2601
2602         /* cpu port is always last */
2603         dev->num_ports = dev->cpu_port + 1;
2604         dev->enabled_ports |= BIT(dev->cpu_port);
2605
2606         /* Include non standard CPU port built-in PHYs to be probed */
2607         if (is539x(dev) || is531x5(dev)) {
2608                 for (i = 0; i < dev->num_ports; i++) {
2609                         if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2610                             !b53_possible_cpu_port(dev->ds, i))
2611                                 dev->ds->phys_mii_mask |= BIT(i);
2612                 }
2613         }
2614
2615         dev->ports = devm_kcalloc(dev->dev,
2616                                   dev->num_ports, sizeof(struct b53_port),
2617                                   GFP_KERNEL);
2618         if (!dev->ports)
2619                 return -ENOMEM;
2620
2621         dev->vlans = devm_kcalloc(dev->dev,
2622                                   dev->num_vlans, sizeof(struct b53_vlan),
2623                                   GFP_KERNEL);
2624         if (!dev->vlans)
2625                 return -ENOMEM;
2626
2627         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2628         if (dev->reset_gpio >= 0) {
2629                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2630                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
2631                 if (ret)
2632                         return ret;
2633         }
2634
2635         return 0;
2636 }
2637
2638 struct b53_device *b53_switch_alloc(struct device *base,
2639                                     const struct b53_io_ops *ops,
2640                                     void *priv)
2641 {
2642         struct dsa_switch *ds;
2643         struct b53_device *dev;
2644
2645         ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2646         if (!ds)
2647                 return NULL;
2648
2649         ds->dev = base;
2650         ds->num_ports = DSA_MAX_PORTS;
2651
2652         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2653         if (!dev)
2654                 return NULL;
2655
2656         ds->priv = dev;
2657         dev->dev = base;
2658
2659         dev->ds = ds;
2660         dev->priv = priv;
2661         dev->ops = ops;
2662         ds->ops = &b53_switch_ops;
2663         ds->untag_bridge_pvid = true;
2664         dev->vlan_enabled = true;
2665         /* Let DSA handle the case were multiple bridges span the same switch
2666          * device and different VLAN awareness settings are requested, which
2667          * would be breaking filtering semantics for any of the other bridge
2668          * devices. (not hardware supported)
2669          */
2670         ds->vlan_filtering_is_global = true;
2671
2672         mutex_init(&dev->reg_mutex);
2673         mutex_init(&dev->stats_mutex);
2674
2675         return dev;
2676 }
2677 EXPORT_SYMBOL(b53_switch_alloc);
2678
2679 int b53_switch_detect(struct b53_device *dev)
2680 {
2681         u32 id32;
2682         u16 tmp;
2683         u8 id8;
2684         int ret;
2685
2686         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2687         if (ret)
2688                 return ret;
2689
2690         switch (id8) {
2691         case 0:
2692                 /* BCM5325 and BCM5365 do not have this register so reads
2693                  * return 0. But the read operation did succeed, so assume this
2694                  * is one of them.
2695                  *
2696                  * Next check if we can write to the 5325's VTA register; for
2697                  * 5365 it is read only.
2698                  */
2699                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2700                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2701
2702                 if (tmp == 0xf)
2703                         dev->chip_id = BCM5325_DEVICE_ID;
2704                 else
2705                         dev->chip_id = BCM5365_DEVICE_ID;
2706                 break;
2707         case BCM5389_DEVICE_ID:
2708         case BCM5395_DEVICE_ID:
2709         case BCM5397_DEVICE_ID:
2710         case BCM5398_DEVICE_ID:
2711                 dev->chip_id = id8;
2712                 break;
2713         default:
2714                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2715                 if (ret)
2716                         return ret;
2717
2718                 switch (id32) {
2719                 case BCM53115_DEVICE_ID:
2720                 case BCM53125_DEVICE_ID:
2721                 case BCM53128_DEVICE_ID:
2722                 case BCM53010_DEVICE_ID:
2723                 case BCM53011_DEVICE_ID:
2724                 case BCM53012_DEVICE_ID:
2725                 case BCM53018_DEVICE_ID:
2726                 case BCM53019_DEVICE_ID:
2727                         dev->chip_id = id32;
2728                         break;
2729                 default:
2730                         dev_err(dev->dev,
2731                                 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2732                                 id8, id32);
2733                         return -ENODEV;
2734                 }
2735         }
2736
2737         if (dev->chip_id == BCM5325_DEVICE_ID)
2738                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2739                                  &dev->core_rev);
2740         else
2741                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2742                                  &dev->core_rev);
2743 }
2744 EXPORT_SYMBOL(b53_switch_detect);
2745
2746 int b53_switch_register(struct b53_device *dev)
2747 {
2748         int ret;
2749
2750         if (dev->pdata) {
2751                 dev->chip_id = dev->pdata->chip_id;
2752                 dev->enabled_ports = dev->pdata->enabled_ports;
2753         }
2754
2755         if (!dev->chip_id && b53_switch_detect(dev))
2756                 return -EINVAL;
2757
2758         ret = b53_switch_init(dev);
2759         if (ret)
2760                 return ret;
2761
2762         dev_info(dev->dev, "found switch: %s, rev %i\n",
2763                  dev->name, dev->core_rev);
2764
2765         return dsa_register_switch(dev->ds);
2766 }
2767 EXPORT_SYMBOL(b53_switch_register);
2768
2769 MODULE_AUTHOR("Jonas Gorski <[email protected]>");
2770 MODULE_DESCRIPTION("B53 switch library");
2771 MODULE_LICENSE("Dual BSD/GPL");