drivers/platform/x86/amd/pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <[email protected]>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <asm/amd_nb.h>
  14 #include <linux/acpi.h>
  15 #include <linux/bitfield.h>
  16 #include <linux/bits.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/io.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/limits.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/rtc.h>
  26 #include <linux/serio.h>
  27 #include <linux/suspend.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/uaccess.h>
  30
  31 /* SMU communication registers */
  32 #define AMD_PMC_REGISTER_MESSAGE        0x538
  33 #define AMD_PMC_REGISTER_RESPONSE       0x980
  34 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  35
  36 /* PMC Scratch Registers */
  37 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  38 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  39
  40 /* STB Registers */
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_S2IDLE_PREPARE      0xC6000001
  43 #define AMD_PMC_STB_S2IDLE_RESTORE      0xC6000002
  44 #define AMD_PMC_STB_S2IDLE_CHECK        0xC6000003
  45 #define AMD_PMC_STB_DUMMY_PC            0xC6000007
  46
  47 /* STB S2D(Spill to DRAM) has different message port offset */
  48 #define STB_SPILL_TO_DRAM               0xBE
  49 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  50 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  51 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  52
  53 /* STB Spill to DRAM Parameters */
  54 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  55 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  56
  57 /* Base address of SMU for mapping physical address to virtual address */
  58 #define AMD_PMC_MAPPING_SIZE            0x01000
  59 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  60 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  61 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  62 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  63 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  64
  65 /* SMU Response Codes */
  66 #define AMD_PMC_RESULT_OK                    0x01
  67 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  68 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  69 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  70 #define AMD_PMC_RESULT_FAILED                0xFF
  71
  72 /* FCH SSC Registers */
  73 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  74 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  75 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  76 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  77 #define FCH_SSC_MAPPING_SIZE            0x800
  78 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  79 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  80
  81 /* SMU Message Definations */
  82 #define SMU_MSG_GETSMUVERSION           0x02
  83 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  84 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  85 #define SMU_MSG_LOG_START               0x06
  86 #define SMU_MSG_LOG_RESET               0x07
  87 #define SMU_MSG_LOG_DUMP_DATA           0x08
  88 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  89 /* List of supported CPU ids */
  90 #define AMD_CPU_ID_RV                   0x15D0
  91 #define AMD_CPU_ID_RN                   0x1630
  92 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  93 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  94 #define AMD_CPU_ID_YC                   0x14B5
  95 #define AMD_CPU_ID_CB                   0x14D8
  96 #define AMD_CPU_ID_PS                   0x14E8
  97 #define AMD_CPU_ID_SP                   0x14A4
  98
  99 #define PMC_MSG_DELAY_MIN_US            50
 100 #define RESPONSE_REGISTER_LOOP_MAX      20000
 101
 102 #define SOC_SUBSYSTEM_IP_MAX    12
 103 #define DELAY_MIN_US            2000
 104 #define DELAY_MAX_US            3000
 105 #define FIFO_SIZE               4096
 106
 107 enum amd_pmc_def {
 108         MSG_TEST = 0x01,
 109         MSG_OS_HINT_PCO,
 110         MSG_OS_HINT_RN,
 111 };
 112
 113 enum s2d_arg {
 114         S2D_TELEMETRY_SIZE = 0x01,
 115         S2D_PHYS_ADDR_LOW,
 116         S2D_PHYS_ADDR_HIGH,
 117         S2D_NUM_SAMPLES,
 118 };
 119
 120 struct amd_pmc_bit_map {
 121         const char *name;
 122         u32 bit_mask;
 123 };
 124
 125 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 126         {"DISPLAY",     BIT(0)},
 127         {"CPU",         BIT(1)},
 128         {"GFX",         BIT(2)},
 129         {"VDD",         BIT(3)},
 130         {"ACP",         BIT(4)},
 131         {"VCN",         BIT(5)},
 132         {"ISP",         BIT(6)},
 133         {"NBIO",        BIT(7)},
 134         {"DF",          BIT(8)},
 135         {"USB0",        BIT(9)},
 136         {"USB1",        BIT(10)},
 137         {"LAPIC",       BIT(11)},
 138         {}
 139 };
 140
 141 struct amd_pmc_dev {
 142         void __iomem *regbase;
 143         void __iomem *smu_virt_addr;
 144         void __iomem *stb_virt_addr;
 145         void __iomem *fch_virt_addr;
 146         bool msg_port;
 147         u32 base_addr;
 148         u32 cpu_id;
 149         u32 active_ips;
 150 /* SMU version information */
 151         u8 smu_program;
 152         u8 major;
 153         u8 minor;
 154         u8 rev;
 155         struct device *dev;
 156         struct pci_dev *rdev;
 157         struct mutex lock; /* generic mutex lock */
 158         struct dentry *dbgfs_dir;
 159 };
 160
 161 static bool enable_stb;
 162 module_param(enable_stb, bool, 0644);
 163 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 164
 165 static bool disable_workarounds;
 166 module_param(disable_workarounds, bool, 0644);
 167 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
 168
 169 static struct amd_pmc_dev pmc;
 170 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 171 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 172 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 173
 174 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 175 {
 176         return ioread32(dev->regbase + reg_offset);
 177 }
 178
 179 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 180 {
 181         iowrite32(val, dev->regbase + reg_offset);
 182 }
 183
 184 struct smu_metrics {
 185         u32 table_version;
 186         u32 hint_count;
 187         u32 s0i3_last_entry_status;
 188         u32 timein_s0i2;
 189         u64 timeentering_s0i3_lastcapture;
 190         u64 timeentering_s0i3_totaltime;
 191         u64 timeto_resume_to_os_lastcapture;
 192         u64 timeto_resume_to_os_totaltime;
 193         u64 timein_s0i3_lastcapture;
 194         u64 timein_s0i3_totaltime;
 195         u64 timein_swdrips_lastcapture;
 196         u64 timein_swdrips_totaltime;
 197         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 198         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 199 } __packed;
 200
 201 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 202 {
 203         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 204         u32 size = FIFO_SIZE * sizeof(u32);
 205         u32 *buf;
 206         int rc;
 207
 208         buf = kzalloc(size, GFP_KERNEL);
 209         if (!buf)
 210                 return -ENOMEM;
 211
 212         rc = amd_pmc_read_stb(dev, buf);
 213         if (rc) {
 214                 kfree(buf);
 215                 return rc;
 216         }
 217
 218         filp->private_data = buf;
 219         return rc;
 220 }
 221
 222 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 223                                         loff_t *pos)
 224 {
 225         if (!filp->private_data)
 226                 return -EINVAL;
 227
 228         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 229                                        FIFO_SIZE * sizeof(u32));
 230 }
 231
 232 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 233 {
 234         kfree(filp->private_data);
 235         return 0;
 236 }
 237
 238 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 239         .owner = THIS_MODULE,
 240         .open = amd_pmc_stb_debugfs_open,
 241         .read = amd_pmc_stb_debugfs_read,
 242         .release = amd_pmc_stb_debugfs_release,
 243 };
 244
 245 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 246 {
 247         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 248         u32 *buf, fsize, num_samples, stb_rdptr_offset = 0;
 249         int ret;
 250
 251         /* Write dummy postcode while reading the STB buffer */
 252         ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
 253         if (ret)
 254                 dev_err(dev->dev, "error writing to STB: %d\n", ret);
 255
 256         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 257         if (!buf)
 258                 return -ENOMEM;
 259
 260         /* Spill to DRAM num_samples uses separate SMU message port */
 261         dev->msg_port = 1;
 262
 263         /* Get the num_samples to calculate the last push location */
 264         ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, STB_SPILL_TO_DRAM, 1);
 265         /* Clear msg_port for other SMU operation */
 266         dev->msg_port = 0;
 267         if (ret) {
 268                 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
 269                 kfree(buf);
 270                 return ret;
 271         }
 272
 273         /* Start capturing data from the last push location */
 274         if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
 275                 fsize  = S2D_TELEMETRY_BYTES_MAX;
 276                 stb_rdptr_offset = num_samples - fsize;
 277         } else {
 278                 fsize = num_samples;
 279                 stb_rdptr_offset = 0;
 280         }
 281
 282         memcpy_fromio(buf, dev->stb_virt_addr + stb_rdptr_offset, fsize);
 283         filp->private_data = buf;
 284
 285         return 0;
 286 }
 287
 288 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 289                                            loff_t *pos)
 290 {
 291         if (!filp->private_data)
 292                 return -EINVAL;
 293
 294         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 295                                         S2D_TELEMETRY_BYTES_MAX);
 296 }
 297
 298 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 299 {
 300         kfree(filp->private_data);
 301         return 0;
 302 }
 303
 304 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 305         .owner = THIS_MODULE,
 306         .open = amd_pmc_stb_debugfs_open_v2,
 307         .read = amd_pmc_stb_debugfs_read_v2,
 308         .release = amd_pmc_stb_debugfs_release_v2,
 309 };
 310
 311 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 312 {
 313         if (dev->cpu_id == AMD_CPU_ID_PCO) {
 314                 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
 315                 return -EINVAL;
 316         }
 317
 318         /* Get Active devices list from SMU */
 319         if (!dev->active_ips)
 320                 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 321
 322         /* Get dram address */
 323         if (!dev->smu_virt_addr) {
 324                 u32 phys_addr_low, phys_addr_hi;
 325                 u64 smu_phys_addr;
 326
 327                 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 328                 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 329                 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 330
 331                 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
 332                                                   sizeof(struct smu_metrics));
 333                 if (!dev->smu_virt_addr)
 334                         return -ENOMEM;
 335         }
 336
 337         /* Start the logging */
 338         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 339         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 340
 341         return 0;
 342 }
 343
 344 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 345 {
 346         if (!pdev->smu_virt_addr) {
 347                 int ret = amd_pmc_setup_smu_logging(pdev);
 348
 349                 if (ret)
 350                         return ret;
 351         }
 352
 353         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 354                 return -ENODEV;
 355         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 356         return 0;
 357 }
 358
 359 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 360 {
 361         struct smu_metrics table;
 362
 363         if (get_metrics_table(pdev, &table))
 364                 return;
 365
 366         if (!table.s0i3_last_entry_status)
 367                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 368         else
 369                 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
 370                          table.timein_s0i3_lastcapture);
 371 }
 372
 373 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 374 {
 375         int rc;
 376         u32 val;
 377
 378         if (dev->cpu_id == AMD_CPU_ID_PCO)
 379                 return -ENODEV;
 380
 381         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 382         if (rc)
 383                 return rc;
 384
 385         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 386         dev->major = (val >> 16) & GENMASK(7, 0);
 387         dev->minor = (val >> 8) & GENMASK(7, 0);
 388         dev->rev = (val >> 0) & GENMASK(7, 0);
 389
 390         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 391                 dev->smu_program, dev->major, dev->minor, dev->rev);
 392
 393         return 0;
 394 }
 395
 396 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
 397                                    char *buf)
 398 {
 399         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 400
 401         if (!dev->major) {
 402                 int rc = amd_pmc_get_smu_version(dev);
 403
 404                 if (rc)
 405                         return rc;
 406         }
 407         return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
 408 }
 409
 410 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
 411                                    char *buf)
 412 {
 413         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 414
 415         if (!dev->major) {
 416                 int rc = amd_pmc_get_smu_version(dev);
 417
 418                 if (rc)
 419                         return rc;
 420         }
 421         return sysfs_emit(buf, "%u\n", dev->smu_program);
 422 }
 423
 424 static DEVICE_ATTR_RO(smu_fw_version);
 425 static DEVICE_ATTR_RO(smu_program);
 426
 427 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
 428 {
 429         struct device *dev = kobj_to_dev(kobj);
 430         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 431
 432         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 433                 return 0;
 434         return 0444;
 435 }
 436
 437 static struct attribute *pmc_attrs[] = {
 438         &dev_attr_smu_fw_version.attr,
 439         &dev_attr_smu_program.attr,
 440         NULL,
 441 };
 442
 443 static struct attribute_group pmc_attr_group = {
 444         .attrs = pmc_attrs,
 445         .is_visible = pmc_attr_is_visible,
 446 };
 447
 448 static const struct attribute_group *pmc_groups[] = {
 449         &pmc_attr_group,
 450         NULL,
 451 };
 452
 453 static int smu_fw_info_show(struct seq_file *s, void *unused)
 454 {
 455         struct amd_pmc_dev *dev = s->private;
 456         struct smu_metrics table;
 457         int idx;
 458
 459         if (get_metrics_table(dev, &table))
 460                 return -EINVAL;
 461
 462         seq_puts(s, "\n=== SMU Statistics ===\n");
 463         seq_printf(s, "Table Version: %d\n", table.table_version);
 464         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 465         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 466                    "Unknown/Fail");
 467         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 468         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 469         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 470                    table.timeto_resume_to_os_lastcapture);
 471
 472         seq_puts(s, "\n=== Active time (in us) ===\n");
 473         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 474                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 475                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 476                                    table.timecondition_notmet_lastcapture[idx]);
 477         }
 478
 479         return 0;
 480 }
 481 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 482
 483 static int s0ix_stats_show(struct seq_file *s, void *unused)
 484 {
 485         struct amd_pmc_dev *dev = s->private;
 486         u64 entry_time, exit_time, residency;
 487
 488         /* Use FCH registers to get the S0ix stats */
 489         if (!dev->fch_virt_addr) {
 490                 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 491                 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 492                 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 493
 494                 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 495                 if (!dev->fch_virt_addr)
 496                         return -ENOMEM;
 497         }
 498
 499         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 500         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 501
 502         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 503         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 504
 505         /* It's in 48MHz. We need to convert it */
 506         residency = exit_time - entry_time;
 507         do_div(residency, 48);
 508
 509         seq_puts(s, "=== S0ix statistics ===\n");
 510         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 511         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 512         seq_printf(s, "Residency Time: %lld\n", residency);
 513
 514         return 0;
 515 }
 516 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 517
 518 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 519                                  struct seq_file *s)
 520 {
 521         u32 val;
 522         int rc;
 523
 524         switch (pdev->cpu_id) {
 525         case AMD_CPU_ID_CZN:
 526                 /* we haven't yet read SMU version */
 527                 if (!pdev->major) {
 528                         rc = amd_pmc_get_smu_version(pdev);
 529                         if (rc)
 530                                 return rc;
 531                 }
 532                 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
 533                         val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 534                 else
 535                         return -EINVAL;
 536                 break;
 537         case AMD_CPU_ID_YC:
 538         case AMD_CPU_ID_CB:
 539         case AMD_CPU_ID_PS:
 540                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 541                 break;
 542         default:
 543                 return -EINVAL;
 544         }
 545
 546         if (dev)
 547                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 548
 549         if (s)
 550                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 551
 552         return 0;
 553 }
 554
 555 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 556 {
 557         return amd_pmc_idlemask_read(s->private, NULL, s);
 558 }
 559 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 560
 561 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 562 {
 563         debugfs_remove_recursive(dev->dbgfs_dir);
 564 }
 565
 566 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 567 {
 568         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 569         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 570                             &smu_fw_info_fops);
 571         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 572                             &s0ix_stats_fops);
 573         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 574                             &amd_pmc_idlemask_fops);
 575         /* Enable STB only when the module_param is set */
 576         if (enable_stb) {
 577                 if (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
 578                     dev->cpu_id == AMD_CPU_ID_PS)
 579                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 580                                             &amd_pmc_stb_debugfs_fops_v2);
 581                 else
 582                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 583                                             &amd_pmc_stb_debugfs_fops);
 584         }
 585 }
 586
 587 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 588 {
 589         u32 value, message, argument, response;
 590
 591         if (dev->msg_port) {
 592                 message = AMD_S2D_REGISTER_MESSAGE;
 593                 argument = AMD_S2D_REGISTER_ARGUMENT;
 594                 response = AMD_S2D_REGISTER_RESPONSE;
 595         } else {
 596                 message = AMD_PMC_REGISTER_MESSAGE;
 597                 argument = AMD_PMC_REGISTER_ARGUMENT;
 598                 response = AMD_PMC_REGISTER_RESPONSE;
 599         }
 600
 601         value = amd_pmc_reg_read(dev, response);
 602         dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 603
 604         value = amd_pmc_reg_read(dev, argument);
 605         dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 606
 607         value = amd_pmc_reg_read(dev, message);
 608         dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
 609 }
 610
 611 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 612 {
 613         int rc;
 614         u32 val, message, argument, response;
 615
 616         mutex_lock(&dev->lock);
 617
 618         if (dev->msg_port) {
 619                 message = AMD_S2D_REGISTER_MESSAGE;
 620                 argument = AMD_S2D_REGISTER_ARGUMENT;
 621                 response = AMD_S2D_REGISTER_RESPONSE;
 622         } else {
 623                 message = AMD_PMC_REGISTER_MESSAGE;
 624                 argument = AMD_PMC_REGISTER_ARGUMENT;
 625                 response = AMD_PMC_REGISTER_RESPONSE;
 626         }
 627
 628         /* Wait until we get a valid response */
 629         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 630                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 631                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 632         if (rc) {
 633                 dev_err(dev->dev, "failed to talk to SMU\n");
 634                 goto out_unlock;
 635         }
 636
 637         /* Write zero to response register */
 638         amd_pmc_reg_write(dev, response, 0);
 639
 640         /* Write argument into response register */
 641         amd_pmc_reg_write(dev, argument, arg);
 642
 643         /* Write message ID to message ID register */
 644         amd_pmc_reg_write(dev, message, msg);
 645
 646         /* Wait until we get a valid response */
 647         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 648                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 649                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 650         if (rc) {
 651                 dev_err(dev->dev, "SMU response timed out\n");
 652                 goto out_unlock;
 653         }
 654
 655         switch (val) {
 656         case AMD_PMC_RESULT_OK:
 657                 if (ret) {
 658                         /* PMFW may take longer time to return back the data */
 659                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 660                         *data = amd_pmc_reg_read(dev, argument);
 661                 }
 662                 break;
 663         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 664                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 665                 rc = -EBUSY;
 666                 goto out_unlock;
 667         case AMD_PMC_RESULT_CMD_UNKNOWN:
 668                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 669                 rc = -EINVAL;
 670                 goto out_unlock;
 671         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 672         case AMD_PMC_RESULT_FAILED:
 673         default:
 674                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 675                 rc = -EIO;
 676                 goto out_unlock;
 677         }
 678
 679 out_unlock:
 680         mutex_unlock(&dev->lock);
 681         amd_pmc_dump_registers(dev);
 682         return rc;
 683 }
 684
 685 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 686 {
 687         switch (dev->cpu_id) {
 688         case AMD_CPU_ID_PCO:
 689                 return MSG_OS_HINT_PCO;
 690         case AMD_CPU_ID_RN:
 691         case AMD_CPU_ID_YC:
 692         case AMD_CPU_ID_CB:
 693         case AMD_CPU_ID_PS:
 694                 return MSG_OS_HINT_RN;
 695         }
 696         return -EINVAL;
 697 }
 698
 699 static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev)
 700 {
 701         struct device *d;
 702         int rc;
 703
 704         if (!pdev->major) {
 705                 rc = amd_pmc_get_smu_version(pdev);
 706                 if (rc)
 707                         return rc;
 708         }
 709
 710         if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
 711                 return 0;
 712
 713         d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
 714         if (!d)
 715                 return 0;
 716         if (device_may_wakeup(d)) {
 717                 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
 718                 disable_irq_wake(1);
 719                 device_set_wakeup_enable(d, false);
 720         }
 721         put_device(d);
 722
 723         return 0;
 724 }
 725
 726 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 727 {
 728         struct rtc_device *rtc_device;
 729         time64_t then, now, duration;
 730         struct rtc_wkalrm alarm;
 731         struct rtc_time tm;
 732         int rc;
 733
 734         /* we haven't yet read SMU version */
 735         if (!pdev->major) {
 736                 rc = amd_pmc_get_smu_version(pdev);
 737                 if (rc)
 738                         return rc;
 739         }
 740
 741         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 742                 return 0;
 743
 744         rtc_device = rtc_class_open("rtc0");
 745         if (!rtc_device)
 746                 return 0;
 747         rc = rtc_read_alarm(rtc_device, &alarm);
 748         if (rc)
 749                 return rc;
 750         if (!alarm.enabled) {
 751                 dev_dbg(pdev->dev, "alarm not enabled\n");
 752                 return 0;
 753         }
 754         rc = rtc_read_time(rtc_device, &tm);
 755         if (rc)
 756                 return rc;
 757         then = rtc_tm_to_time64(&alarm.time);
 758         now = rtc_tm_to_time64(&tm);
 759         duration = then-now;
 760
 761         /* in the past */
 762         if (then < now)
 763                 return 0;
 764
 765         /* will be stored in upper 16 bits of s0i3 hint argument,
 766          * so timer wakeup from s0i3 is limited to ~18 hours or less
 767          */
 768         if (duration <= 4 || duration > U16_MAX)
 769                 return -EINVAL;
 770
 771         *arg |= (duration << 16);
 772         rc = rtc_alarm_irq_enable(rtc_device, 0);
 773         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 774
 775         return rc;
 776 }
 777
 778 static void amd_pmc_s2idle_prepare(void)
 779 {
 780         struct amd_pmc_dev *pdev = &pmc;
 781         int rc;
 782         u8 msg;
 783         u32 arg = 1;
 784
 785         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 786         amd_pmc_setup_smu_logging(pdev);
 787
 788         /* Activate CZN specific platform bug workarounds */
 789         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 790                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 791                 if (rc) {
 792                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 793                         return;
 794                 }
 795         }
 796
 797         msg = amd_pmc_get_os_hint(pdev);
 798         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 799         if (rc) {
 800                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 801                 return;
 802         }
 803
 804         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
 805         if (rc)
 806                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 807 }
 808
 809 static void amd_pmc_s2idle_check(void)
 810 {
 811         struct amd_pmc_dev *pdev = &pmc;
 812         struct smu_metrics table;
 813         int rc;
 814
 815         /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
 816         if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
 817             table.s0i3_last_entry_status)
 818                 usleep_range(10000, 20000);
 819
 820         /* Dump the IdleMask before we add to the STB */
 821         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 822
 823         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
 824         if (rc)
 825                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 826 }
 827
 828 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
 829 {
 830         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 831                 return -ENODEV;
 832
 833         return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 834 }
 835
 836 static void amd_pmc_s2idle_restore(void)
 837 {
 838         struct amd_pmc_dev *pdev = &pmc;
 839         int rc;
 840         u8 msg;
 841
 842         msg = amd_pmc_get_os_hint(pdev);
 843         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 844         if (rc)
 845                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 846
 847         /* Let SMU know that we are looking for stats */
 848         amd_pmc_dump_data(pdev);
 849
 850         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
 851         if (rc)
 852                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 853
 854         /* Notify on failed entry */
 855         amd_pmc_validate_deepest(pdev);
 856 }
 857
 858 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 859         .prepare = amd_pmc_s2idle_prepare,
 860         .check = amd_pmc_s2idle_check,
 861         .restore = amd_pmc_s2idle_restore,
 862 };
 863
 864 static int amd_pmc_suspend_handler(struct device *dev)
 865 {
 866         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 867
 868         if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
 869                 int rc = amd_pmc_czn_wa_irq1(pdev);
 870
 871                 if (rc) {
 872                         dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
 873                         return rc;
 874                 }
 875         }
 876
 877         return 0;
 878 }
 879
 880 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL);
 881
 882 static const struct pci_device_id pmc_pci_ids[] = {
 883         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
 884         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
 885         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 886         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 887         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 888         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 889         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 890         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
 891         { }
 892 };
 893
 894 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 895 {
 896         u32 phys_addr_low, phys_addr_hi;
 897         u64 stb_phys_addr;
 898         u32 size = 0;
 899
 900         /* Spill to DRAM feature uses separate SMU message port */
 901         dev->msg_port = 1;
 902
 903         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
 904         if (size != S2D_TELEMETRY_BYTES_MAX)
 905                 return -EIO;
 906
 907         /* Get STB DRAM address */
 908         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
 909         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
 910
 911         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 912
 913         /* Clear msg_port for other SMU operation */
 914         dev->msg_port = 0;
 915
 916         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
 917         if (!dev->stb_virt_addr)
 918                 return -ENOMEM;
 919
 920         return 0;
 921 }
 922
 923 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 924 {
 925         int err;
 926
 927         err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data);
 928         if (err) {
 929                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0);
 930                 return pcibios_err_to_errno(err);
 931         }
 932
 933         return 0;
 934 }
 935
 936 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 937 {
 938         int i, err;
 939
 940         for (i = 0; i < FIFO_SIZE; i++) {
 941                 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++);
 942                 if (err) {
 943                         dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0);
 944                         return pcibios_err_to_errno(err);
 945                 }
 946         }
 947
 948         return 0;
 949 }
 950
 951 static int amd_pmc_probe(struct platform_device *pdev)
 952 {
 953         struct amd_pmc_dev *dev = &pmc;
 954         struct pci_dev *rdev;
 955         u32 base_addr_lo, base_addr_hi;
 956         u64 base_addr;
 957         int err;
 958         u32 val;
 959
 960         dev->dev = &pdev->dev;
 961
 962         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 963         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 964                 err = -ENODEV;
 965                 goto err_pci_dev_put;
 966         }
 967
 968         dev->cpu_id = rdev->device;
 969
 970         if (dev->cpu_id == AMD_CPU_ID_SP) {
 971                 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
 972                 err = -ENODEV;
 973                 goto err_pci_dev_put;
 974         }
 975
 976         dev->rdev = rdev;
 977         err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
 978         if (err) {
 979                 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
 980                 err = pcibios_err_to_errno(err);
 981                 goto err_pci_dev_put;
 982         }
 983
 984         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 985
 986         err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
 987         if (err) {
 988                 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
 989                 err = pcibios_err_to_errno(err);
 990                 goto err_pci_dev_put;
 991         }
 992
 993         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 994         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 995
 996         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 997                                     AMD_PMC_MAPPING_SIZE);
 998         if (!dev->regbase) {
 999                 err = -ENOMEM;
1000                 goto err_pci_dev_put;
1001         }
1002
1003         mutex_init(&dev->lock);
1004
1005         if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
1006                 err = amd_pmc_s2d_init(dev);
1007                 if (err)
1008                         goto err_pci_dev_put;
1009         }
1010
1011         platform_set_drvdata(pdev, dev);
1012         if (IS_ENABLED(CONFIG_SUSPEND)) {
1013                 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1014                 if (err)
1015                         dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1016         }
1017
1018         amd_pmc_dbgfs_register(dev);
1019         return 0;
1020
1021 err_pci_dev_put:
1022         pci_dev_put(rdev);
1023         return err;
1024 }
1025
1026 static void amd_pmc_remove(struct platform_device *pdev)
1027 {
1028         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1029
1030         if (IS_ENABLED(CONFIG_SUSPEND))
1031                 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1032         amd_pmc_dbgfs_unregister(dev);
1033         pci_dev_put(dev->rdev);
1034         mutex_destroy(&dev->lock);
1035 }
1036
1037 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1038         {"AMDI0005", 0},
1039         {"AMDI0006", 0},
1040         {"AMDI0007", 0},
1041         {"AMDI0008", 0},
1042         {"AMDI0009", 0},
1043         {"AMD0004", 0},
1044         {"AMD0005", 0},
1045         { }
1046 };
1047 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1048
1049 static struct platform_driver amd_pmc_driver = {
1050         .driver = {
1051                 .name = "amd_pmc",
1052                 .acpi_match_table = amd_pmc_acpi_ids,
1053                 .dev_groups = pmc_groups,
1054                 .pm = pm_sleep_ptr(&amd_pmc_pm),
1055         },
1056         .probe = amd_pmc_probe,
1057         .remove_new = amd_pmc_remove,
1058 };
1059 module_platform_driver(amd_pmc_driver);
1060
1061 MODULE_LICENSE("GPL v2");
1062 MODULE_DESCRIPTION("AMD PMC Driver");