drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include <drm/drm_vblank.h>
  27 #include <drm/drm_atomic_helper.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm_psr.h"
  32 #include "amdgpu_dm_replay.h"
  33 #include "amdgpu_dm_crtc.h"
  34 #include "amdgpu_dm_plane.h"
  35 #include "amdgpu_dm_trace.h"
  36 #include "amdgpu_dm_debugfs.h"
  37
  38 #define HPD_DETECTION_PERIOD_uS 5000000
  39 #define HPD_DETECTION_TIME_uS 1000
  40
  41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
  42 {
  43         struct drm_crtc *crtc = &acrtc->base;
  44         struct drm_device *dev = crtc->dev;
  45         unsigned long flags;
  46
  47         drm_crtc_handle_vblank(crtc);
  48
  49         spin_lock_irqsave(&dev->event_lock, flags);
  50
  51         /* Send completion event for cursor-only commits */
  52         if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
  53                 drm_crtc_send_vblank_event(crtc, acrtc->event);
  54                 drm_crtc_vblank_put(crtc);
  55                 acrtc->event = NULL;
  56         }
  57
  58         spin_unlock_irqrestore(&dev->event_lock, flags);
  59 }
  60
  61 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
  62                              struct dc_stream_state *new_stream,
  63                              struct dc_stream_state *old_stream)
  64 {
  65         return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
  66 }
  67
  68 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
  69
  70 {
  71         return acrtc->dm_irq_params.freesync_config.state ==
  72                        VRR_STATE_ACTIVE_VARIABLE ||
  73                acrtc->dm_irq_params.freesync_config.state ==
  74                        VRR_STATE_ACTIVE_FIXED;
  75 }
  76
  77 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
  78 {
  79         enum dc_irq_source irq_source;
  80         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  81         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
  82         int rc;
  83
  84         if (acrtc->otg_inst == -1)
  85                 return 0;
  86
  87         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
  88
  89         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
  90
  91         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
  92                       acrtc->crtc_id, enable ? "en" : "dis", rc);
  93         return rc;
  94 }
  95
  96 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
  97 {
  98         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
  99                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 100 }
 101
 102 /**
 103  * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features.
 104  *
 105  * @vblank_work:    is a pointer to a struct vblank_control_work object.
 106  * @vblank_enabled: indicates whether the DRM vblank counter is currently
 107  *                  enabled (true) or disabled (false).
 108  * @allow_sr_entry: represents whether entry into the self-refresh mode is
 109  *                  allowed (true) or not allowed (false).
 110  *
 111  * The DRM vblank counter enable/disable action is used as the trigger to enable
 112  * or disable various panel self-refresh features:
 113  *
 114  * Panel Replay and PSR SU
 115  * - Enable when:
 116  *      - vblank counter is disabled
 117  *      - entry is allowed: usermode demonstrates an adequate number of fast
 118  *        commits)
 119  *     - CRC capture window isn't active
 120  * - Keep enabled even when vblank counter gets enabled
 121  *
 122  * PSR1
 123  * - Enable condition same as above
 124  * - Disable when vblank counter is enabled
 125  */
 126 static void amdgpu_dm_crtc_set_panel_sr_feature(
 127         struct vblank_control_work *vblank_work,
 128         bool vblank_enabled, bool allow_sr_entry)
 129 {
 130         struct dc_link *link = vblank_work->stream->link;
 131         bool is_sr_active = (link->replay_settings.replay_allow_active ||
 132                                  link->psr_settings.psr_allow_active);
 133         bool is_crc_window_active = false;
 134
 135 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
 136         is_crc_window_active =
 137                 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
 138 #endif
 139
 140         if (link->replay_settings.replay_feature_enabled &&
 141                 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
 142                 amdgpu_dm_replay_enable(vblank_work->stream, true);
 143         } else if (vblank_enabled) {
 144                 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
 145                         amdgpu_dm_psr_disable(vblank_work->stream);
 146         } else if (link->psr_settings.psr_feature_enabled &&
 147                 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
 148
 149                 struct amdgpu_dm_connector *aconn =
 150                         (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
 151
 152                 if (!aconn->disallow_edp_enter_psr) {
 153                         struct amdgpu_display_manager *dm = vblank_work->dm;
 154
 155                         amdgpu_dm_psr_enable(vblank_work->stream);
 156                         if (dm->idle_workqueue &&
 157                             dm->dc->idle_optimizations_allowed &&
 158                             dm->idle_workqueue->enable &&
 159                             !dm->idle_workqueue->running)
 160                                 schedule_work(&dm->idle_workqueue->work);
 161                 }
 162         }
 163 }
 164
 165 bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
 166 {
 167         struct drm_connector *connector;
 168         struct drm_connector_list_iter iter;
 169         struct drm_device *dev;
 170         bool is_headless = true;
 171
 172         if (adev == NULL)
 173                 return true;
 174
 175         dev = adev->dm.ddev;
 176
 177         drm_connector_list_iter_begin(dev, &iter);
 178         drm_for_each_connector_iter(connector, &iter) {
 179
 180                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
 181                         continue;
 182
 183                 if (connector->status == connector_status_connected) {
 184                         is_headless = false;
 185                         break;
 186                 }
 187         }
 188         drm_connector_list_iter_end(&iter);
 189         return is_headless;
 190 }
 191
 192 static void amdgpu_dm_idle_worker(struct work_struct *work)
 193 {
 194         struct idle_workqueue *idle_work;
 195
 196         idle_work = container_of(work, struct idle_workqueue, work);
 197         idle_work->dm->idle_workqueue->running = true;
 198
 199         while (idle_work->enable) {
 200                 fsleep(HPD_DETECTION_PERIOD_uS);
 201                 mutex_lock(&idle_work->dm->dc_lock);
 202                 if (!idle_work->dm->dc->idle_optimizations_allowed) {
 203                         mutex_unlock(&idle_work->dm->dc_lock);
 204                         break;
 205                 }
 206                 dc_allow_idle_optimizations(idle_work->dm->dc, false);
 207
 208                 mutex_unlock(&idle_work->dm->dc_lock);
 209                 fsleep(HPD_DETECTION_TIME_uS);
 210                 mutex_lock(&idle_work->dm->dc_lock);
 211
 212                 if (!amdgpu_dm_is_headless(idle_work->dm->adev) &&
 213                     !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) {
 214                         mutex_unlock(&idle_work->dm->dc_lock);
 215                         break;
 216                 }
 217
 218                 if (idle_work->enable)
 219                         dc_allow_idle_optimizations(idle_work->dm->dc, true);
 220                 mutex_unlock(&idle_work->dm->dc_lock);
 221         }
 222         idle_work->dm->idle_workqueue->running = false;
 223 }
 224
 225 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
 226 {
 227         struct idle_workqueue *idle_work;
 228
 229         idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL);
 230         if (ZERO_OR_NULL_PTR(idle_work))
 231                 return NULL;
 232
 233         idle_work->dm = &adev->dm;
 234         idle_work->enable = false;
 235         idle_work->running = false;
 236         INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
 237
 238         return idle_work;
 239 }
 240
 241 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
 242 {
 243         struct vblank_control_work *vblank_work =
 244                 container_of(work, struct vblank_control_work, work);
 245         struct amdgpu_display_manager *dm = vblank_work->dm;
 246
 247         mutex_lock(&dm->dc_lock);
 248
 249         if (vblank_work->enable)
 250                 dm->active_vblank_irq_count++;
 251         else if (dm->active_vblank_irq_count)
 252                 dm->active_vblank_irq_count--;
 253
 254         dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
 255
 256         DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
 257
 258         /*
 259          * Control PSR based on vblank requirements from OS
 260          *
 261          * If panel supports PSR SU, there's no need to disable PSR when OS is
 262          * submitting fast atomic commits (we infer this by whether the OS
 263          * requests vblank events). Fast atomic commits will simply trigger a
 264          * full-frame-update (FFU); a specific case of selective-update (SU)
 265          * where the SU region is the full hactive*vactive region. See
 266          * fill_dc_dirty_rects().
 267          */
 268         if (vblank_work->stream && vblank_work->stream->link) {
 269                 amdgpu_dm_crtc_set_panel_sr_feature(
 270                         vblank_work, vblank_work->enable,
 271                         vblank_work->acrtc->dm_irq_params.allow_psr_entry ||
 272                         vblank_work->stream->link->replay_settings.replay_feature_enabled);
 273         }
 274
 275         mutex_unlock(&dm->dc_lock);
 276
 277         dc_stream_release(vblank_work->stream);
 278
 279         kfree(vblank_work);
 280 }
 281
 282 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
 283 {
 284         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 285         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 286         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
 287         struct amdgpu_display_manager *dm = &adev->dm;
 288         struct vblank_control_work *work;
 289         int rc = 0;
 290
 291         if (acrtc->otg_inst == -1)
 292                 goto skip;
 293
 294         if (enable) {
 295                 /* vblank irq on -> Only need vupdate irq in vrr mode */
 296                 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
 297                         rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
 298         } else {
 299                 /* vblank irq off -> vupdate irq off */
 300                 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
 301         }
 302
 303         if (rc)
 304                 return rc;
 305
 306         rc = (enable)
 307                 ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id)
 308                 : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id);
 309
 310         if (rc)
 311                 return rc;
 312
 313 skip:
 314         if (amdgpu_in_reset(adev))
 315                 return 0;
 316
 317         if (dm->vblank_control_workqueue) {
 318                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
 319                 if (!work)
 320                         return -ENOMEM;
 321
 322                 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
 323                 work->dm = dm;
 324                 work->acrtc = acrtc;
 325                 work->enable = enable;
 326
 327                 if (acrtc_state->stream) {
 328                         dc_stream_retain(acrtc_state->stream);
 329                         work->stream = acrtc_state->stream;
 330                 }
 331
 332                 queue_work(dm->vblank_control_workqueue, &work->work);
 333         }
 334
 335         return 0;
 336 }
 337
 338 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
 339 {
 340         return amdgpu_dm_crtc_set_vblank(crtc, true);
 341 }
 342
 343 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
 344 {
 345         amdgpu_dm_crtc_set_vblank(crtc, false);
 346 }
 347
 348 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
 349                                   struct drm_crtc_state *state)
 350 {
 351         struct dm_crtc_state *cur = to_dm_crtc_state(state);
 352
 353         /* TODO Destroy dc_stream objects are stream object is flattened */
 354         if (cur->stream)
 355                 dc_stream_release(cur->stream);
 356
 357
 358         __drm_atomic_helper_crtc_destroy_state(state);
 359
 360
 361         kfree(state);
 362 }
 363
 364 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
 365 {
 366         struct dm_crtc_state *state, *cur;
 367
 368         cur = to_dm_crtc_state(crtc->state);
 369
 370         if (WARN_ON(!crtc->state))
 371                 return NULL;
 372
 373         state = kzalloc(sizeof(*state), GFP_KERNEL);
 374         if (!state)
 375                 return NULL;
 376
 377         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 378
 379         if (cur->stream) {
 380                 state->stream = cur->stream;
 381                 dc_stream_retain(state->stream);
 382         }
 383
 384         state->active_planes = cur->active_planes;
 385         state->vrr_infopacket = cur->vrr_infopacket;
 386         state->abm_level = cur->abm_level;
 387         state->vrr_supported = cur->vrr_supported;
 388         state->freesync_config = cur->freesync_config;
 389         state->cm_has_degamma = cur->cm_has_degamma;
 390         state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
 391         state->regamma_tf = cur->regamma_tf;
 392         state->crc_skip_count = cur->crc_skip_count;
 393         state->mpo_requested = cur->mpo_requested;
 394         state->cursor_mode = cur->cursor_mode;
 395         /* TODO Duplicate dc_stream after objects are stream object is flattened */
 396
 397         return &state->base;
 398 }
 399
 400 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
 401 {
 402         drm_crtc_cleanup(crtc);
 403         kfree(crtc);
 404 }
 405
 406 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
 407 {
 408         struct dm_crtc_state *state;
 409
 410         if (crtc->state)
 411                 amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
 412
 413         state = kzalloc(sizeof(*state), GFP_KERNEL);
 414         if (WARN_ON(!state))
 415                 return;
 416
 417         __drm_atomic_helper_crtc_reset(crtc, &state->base);
 418 }
 419
 420 #ifdef CONFIG_DEBUG_FS
 421 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
 422 {
 423         crtc_debugfs_init(crtc);
 424
 425         return 0;
 426 }
 427 #endif
 428
 429 #ifdef AMD_PRIVATE_COLOR
 430 /**
 431  * dm_crtc_additional_color_mgmt - enable additional color properties
 432  * @crtc: DRM CRTC
 433  *
 434  * This function lets the driver enable post-blending CRTC regamma transfer
 435  * function property in addition to DRM CRTC gamma LUT. Default value means
 436  * linear transfer function, which is the default CRTC gamma LUT behaviour
 437  * without this property.
 438  */
 439 static void
 440 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
 441 {
 442         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 443
 444         if (adev->dm.dc->caps.color.mpc.ogam_ram)
 445                 drm_object_attach_property(&crtc->base,
 446                                            adev->mode_info.regamma_tf_property,
 447                                            AMDGPU_TRANSFER_FUNCTION_DEFAULT);
 448 }
 449
 450 static int
 451 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
 452                                    struct drm_crtc_state *state,
 453                                    struct drm_property *property,
 454                                    uint64_t val)
 455 {
 456         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 457         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
 458
 459         if (property == adev->mode_info.regamma_tf_property) {
 460                 if (acrtc_state->regamma_tf != val) {
 461                         acrtc_state->regamma_tf = val;
 462                         acrtc_state->base.color_mgmt_changed |= 1;
 463                 }
 464         } else {
 465                 drm_dbg_atomic(crtc->dev,
 466                                "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
 467                                crtc->base.id, crtc->name,
 468                                property->base.id, property->name);
 469                 return -EINVAL;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int
 476 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
 477                                    const struct drm_crtc_state *state,
 478                                    struct drm_property *property,
 479                                    uint64_t *val)
 480 {
 481         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 482         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
 483
 484         if (property == adev->mode_info.regamma_tf_property)
 485                 *val = acrtc_state->regamma_tf;
 486         else
 487                 return -EINVAL;
 488
 489         return 0;
 490 }
 491 #endif
 492
 493 /* Implemented only the options currently available for the driver */
 494 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 495         .reset = amdgpu_dm_crtc_reset_state,
 496         .destroy = amdgpu_dm_crtc_destroy,
 497         .set_config = drm_atomic_helper_set_config,
 498         .page_flip = drm_atomic_helper_page_flip,
 499         .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
 500         .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
 501         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
 502         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
 503         .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
 504         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
 505         .enable_vblank = amdgpu_dm_crtc_enable_vblank,
 506         .disable_vblank = amdgpu_dm_crtc_disable_vblank,
 507         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 508 #if defined(CONFIG_DEBUG_FS)
 509         .late_register = amdgpu_dm_crtc_late_register,
 510 #endif
 511 #ifdef AMD_PRIVATE_COLOR
 512         .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
 513         .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
 514 #endif
 515 };
 516
 517 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
 518 {
 519 }
 520
 521 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
 522 {
 523         struct drm_atomic_state *state = new_crtc_state->state;
 524         struct drm_plane *plane;
 525         int num_active = 0;
 526
 527         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
 528                 struct drm_plane_state *new_plane_state;
 529
 530                 /* Cursor planes are "fake". */
 531                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 532                         continue;
 533
 534                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
 535
 536                 if (!new_plane_state) {
 537                         /*
 538                          * The plane is enable on the CRTC and hasn't changed
 539                          * state. This means that it previously passed
 540                          * validation and is therefore enabled.
 541                          */
 542                         num_active += 1;
 543                         continue;
 544                 }
 545
 546                 /* We need a framebuffer to be considered enabled. */
 547                 num_active += (new_plane_state->fb != NULL);
 548         }
 549
 550         return num_active;
 551 }
 552
 553 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
 554                                                      struct drm_crtc_state *new_crtc_state)
 555 {
 556         struct dm_crtc_state *dm_new_crtc_state =
 557                 to_dm_crtc_state(new_crtc_state);
 558
 559         dm_new_crtc_state->active_planes = 0;
 560
 561         if (!dm_new_crtc_state->stream)
 562                 return;
 563
 564         dm_new_crtc_state->active_planes =
 565                 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
 566 }
 567
 568 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
 569                                       const struct drm_display_mode *mode,
 570                                       struct drm_display_mode *adjusted_mode)
 571 {
 572         return true;
 573 }
 574
 575 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
 576                                               struct drm_atomic_state *state)
 577 {
 578         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 579                                                                                 crtc);
 580         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 581         struct dc *dc = adev->dm.dc;
 582         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
 583         int ret = -EINVAL;
 584
 585         trace_amdgpu_dm_crtc_atomic_check(crtc_state);
 586
 587         amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
 588
 589         if (WARN_ON(unlikely(!dm_crtc_state->stream &&
 590                         amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
 591                 return ret;
 592         }
 593
 594         /*
 595          * We require the primary plane to be enabled whenever the CRTC is, otherwise
 596          * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
 597          * planes are disabled, which is not supported by the hardware. And there is legacy
 598          * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
 599          */
 600         if (crtc_state->enable &&
 601                 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
 602                 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
 603                 return -EINVAL;
 604         }
 605
 606         /*
 607          * Only allow async flips for fast updates that don't change the FB
 608          * pitch, the DCC state, rotation, etc.
 609          */
 610         if (crtc_state->async_flip &&
 611             dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
 612                 drm_dbg_atomic(crtc->dev,
 613                                "[CRTC:%d:%s] async flips are only supported for fast updates\n",
 614                                crtc->base.id, crtc->name);
 615                 return -EINVAL;
 616         }
 617
 618         /* In some use cases, like reset, no stream is attached */
 619         if (!dm_crtc_state->stream)
 620                 return 0;
 621
 622         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
 623                 return 0;
 624
 625         DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
 626         return ret;
 627 }
 628
 629 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
 630         .disable = amdgpu_dm_crtc_helper_disable,
 631         .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
 632         .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
 633         .get_scanout_position = amdgpu_crtc_get_scanout_position,
 634 };
 635
 636 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 637                                struct drm_plane *plane,
 638                                uint32_t crtc_index)
 639 {
 640         struct amdgpu_crtc *acrtc = NULL;
 641         struct drm_plane *cursor_plane;
 642         bool is_dcn;
 643         int res = -ENOMEM;
 644
 645         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
 646         if (!cursor_plane)
 647                 goto fail;
 648
 649         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
 650         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
 651
 652         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
 653         if (!acrtc)
 654                 goto fail;
 655
 656         res = drm_crtc_init_with_planes(
 657                         dm->ddev,
 658                         &acrtc->base,
 659                         plane,
 660                         cursor_plane,
 661                         &amdgpu_dm_crtc_funcs, NULL);
 662
 663         if (res)
 664                 goto fail;
 665
 666         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
 667
 668         /* Create (reset) the plane state */
 669         if (acrtc->base.funcs->reset)
 670                 acrtc->base.funcs->reset(&acrtc->base);
 671
 672         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
 673         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
 674
 675         acrtc->crtc_id = crtc_index;
 676         acrtc->base.enabled = false;
 677         acrtc->otg_inst = -1;
 678
 679         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
 680
 681         /* Don't enable DRM CRTC degamma property for DCE since it doesn't
 682          * support programmable degamma anywhere.
 683          */
 684         is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
 685         drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
 686                                    true, MAX_COLOR_LUT_ENTRIES);
 687
 688         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
 689
 690 #ifdef AMD_PRIVATE_COLOR
 691         dm_crtc_additional_color_mgmt(&acrtc->base);
 692 #endif
 693         return 0;
 694
 695 fail:
 696         kfree(acrtc);
 697         kfree(cursor_plane);
 698         return res;
 699 }
 700