drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29 #include "soc15_common.h"
  30 #include "vega10_enum.h"
  31
  32 #include "v9_structs.h"
  33
  34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  35
  36 #include "gc/gc_9_4_3_offset.h"
  37 #include "gc/gc_9_4_3_sh_mask.h"
  38
  39 #include "gfx_v9_4_3.h"
  40 #include "amdgpu_xcp.h"
  41 #include "amdgpu_aca.h"
  42
  43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
  44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
  45
  46 #define GFX9_MEC_HPD_SIZE 4096
  47 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  48
  49 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042
  50 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301
  51
  52 #define mmSMNAID_XCD0_MCA_SMU 0x36430400        /* SMN AID XCD0 */
  53 #define mmSMNAID_XCD1_MCA_SMU 0x38430400        /* SMN AID XCD1 */
  54 #define mmSMNXCD_XCD0_MCA_SMU 0x40430400        /* SMN XCD XCD0 */
  55
  56 struct amdgpu_gfx_ras gfx_v9_4_3_ras;
  57
  58 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
  59 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev);
  60 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);
  61 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev);
  62 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
  63                                 struct amdgpu_cu_info *cu_info);
  64
  65 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,
  66                                 uint64_t queue_mask)
  67 {
  68         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
  69         amdgpu_ring_write(kiq_ring,
  70                 PACKET3_SET_RESOURCES_VMID_MASK(0) |
  71                 /* vmid_mask:0* queue_type:0 (KIQ) */
  72                 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
  73         amdgpu_ring_write(kiq_ring,
  74                         lower_32_bits(queue_mask));     /* queue mask lo */
  75         amdgpu_ring_write(kiq_ring,
  76                         upper_32_bits(queue_mask));     /* queue mask hi */
  77         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
  78         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
  79         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
  80         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
  81 }
  82
  83 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring,
  84                                  struct amdgpu_ring *ring)
  85 {
  86         struct amdgpu_device *adev = kiq_ring->adev;
  87         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
  88         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
  89         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
  90
  91         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
  92         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
  93         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
  94                          PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
  95                          PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
  96                          PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
  97                          PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
  98                          PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
  99                          /*queue_type: normal compute queue */
 100                          PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
 101                          /* alloc format: all_on_one_pipe */
 102                          PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
 103                          PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 104                          /* num_queues: must be 1 */
 105                          PACKET3_MAP_QUEUES_NUM_QUEUES(1));
 106         amdgpu_ring_write(kiq_ring,
 107                         PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 108         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 109         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 110         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 111         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 112 }
 113
 114 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 115                                    struct amdgpu_ring *ring,
 116                                    enum amdgpu_unmap_queues_action action,
 117                                    u64 gpu_addr, u64 seq)
 118 {
 119         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 120
 121         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 122         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 123                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 124                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 125                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 126                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 127         amdgpu_ring_write(kiq_ring,
 128                         PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 129
 130         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 131                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 132                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 133                 amdgpu_ring_write(kiq_ring, seq);
 134         } else {
 135                 amdgpu_ring_write(kiq_ring, 0);
 136                 amdgpu_ring_write(kiq_ring, 0);
 137                 amdgpu_ring_write(kiq_ring, 0);
 138         }
 139 }
 140
 141 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring,
 142                                    struct amdgpu_ring *ring,
 143                                    u64 addr,
 144                                    u64 seq)
 145 {
 146         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 147
 148         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 149         amdgpu_ring_write(kiq_ring,
 150                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 151                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 152                           PACKET3_QUERY_STATUS_COMMAND(2));
 153         /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 154         amdgpu_ring_write(kiq_ring,
 155                         PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 156                         PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 157         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 158         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 159         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 160         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 161 }
 162
 163 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 164                                 uint16_t pasid, uint32_t flush_type,
 165                                 bool all_hub)
 166 {
 167         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
 168         amdgpu_ring_write(kiq_ring,
 169                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
 170                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
 171                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
 172                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
 173 }
 174
 175 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = {
 176         .kiq_set_resources = gfx_v9_4_3_kiq_set_resources,
 177         .kiq_map_queues = gfx_v9_4_3_kiq_map_queues,
 178         .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues,
 179         .kiq_query_status = gfx_v9_4_3_kiq_query_status,
 180         .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs,
 181         .set_resources_size = 8,
 182         .map_queues_size = 7,
 183         .unmap_queues_size = 6,
 184         .query_status_size = 7,
 185         .invalidate_tlbs_size = 2,
 186 };
 187
 188 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 189 {
 190         int i, num_xcc;
 191
 192         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 193         for (i = 0; i < num_xcc; i++)
 194                 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
 195 }
 196
 197 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
 198 {
 199         int i, num_xcc, dev_inst;
 200
 201         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 202         for (i = 0; i < num_xcc; i++) {
 203                 dev_inst = GET_INST(GC, i);
 204
 205                 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG,
 206                              GOLDEN_GB_ADDR_CONFIG);
 207                 /* Golden settings applied by driver for ASIC with rev_id 0 */
 208                 if (adev->rev_id == 0) {
 209                         WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1,
 210                                               REDUCE_FIFO_DEPTH_BY_2, 2);
 211                 } else {
 212                         WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2,
 213                                                 SPARE, 0x1);
 214                 }
 215         }
 216 }
 217
 218 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 219                                        bool wc, uint32_t reg, uint32_t val)
 220 {
 221         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 222         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 223                                 WRITE_DATA_DST_SEL(0) |
 224                                 (wc ? WR_CONFIRM : 0));
 225         amdgpu_ring_write(ring, reg);
 226         amdgpu_ring_write(ring, 0);
 227         amdgpu_ring_write(ring, val);
 228 }
 229
 230 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 231                                   int mem_space, int opt, uint32_t addr0,
 232                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 233                                   uint32_t inv)
 234 {
 235         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 236         amdgpu_ring_write(ring,
 237                                  /* memory (1) or register (0) */
 238                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 239                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 240                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 241                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 242
 243         if (mem_space)
 244                 BUG_ON(addr0 & 0x3); /* Dword align */
 245         amdgpu_ring_write(ring, addr0);
 246         amdgpu_ring_write(ring, addr1);
 247         amdgpu_ring_write(ring, ref);
 248         amdgpu_ring_write(ring, mask);
 249         amdgpu_ring_write(ring, inv); /* poll interval */
 250 }
 251
 252 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
 253 {
 254         uint32_t scratch_reg0_offset, xcc_offset;
 255         struct amdgpu_device *adev = ring->adev;
 256         uint32_t tmp = 0;
 257         unsigned i;
 258         int r;
 259
 260         /* Use register offset which is local to XCC in the packet */
 261         xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 262         scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);
 263         WREG32(scratch_reg0_offset, 0xCAFEDEAD);
 264         tmp = RREG32(scratch_reg0_offset);
 265
 266         r = amdgpu_ring_alloc(ring, 3);
 267         if (r)
 268                 return r;
 269
 270         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 271         amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START);
 272         amdgpu_ring_write(ring, 0xDEADBEEF);
 273         amdgpu_ring_commit(ring);
 274
 275         for (i = 0; i < adev->usec_timeout; i++) {
 276                 tmp = RREG32(scratch_reg0_offset);
 277                 if (tmp == 0xDEADBEEF)
 278                         break;
 279                 udelay(1);
 280         }
 281
 282         if (i >= adev->usec_timeout)
 283                 r = -ETIMEDOUT;
 284         return r;
 285 }
 286
 287 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 288 {
 289         struct amdgpu_device *adev = ring->adev;
 290         struct amdgpu_ib ib;
 291         struct dma_fence *f = NULL;
 292
 293         unsigned index;
 294         uint64_t gpu_addr;
 295         uint32_t tmp;
 296         long r;
 297
 298         r = amdgpu_device_wb_get(adev, &index);
 299         if (r)
 300                 return r;
 301
 302         gpu_addr = adev->wb.gpu_addr + (index * 4);
 303         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 304         memset(&ib, 0, sizeof(ib));
 305
 306         r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
 307         if (r)
 308                 goto err1;
 309
 310         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 311         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 312         ib.ptr[2] = lower_32_bits(gpu_addr);
 313         ib.ptr[3] = upper_32_bits(gpu_addr);
 314         ib.ptr[4] = 0xDEADBEEF;
 315         ib.length_dw = 5;
 316
 317         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 318         if (r)
 319                 goto err2;
 320
 321         r = dma_fence_wait_timeout(f, false, timeout);
 322         if (r == 0) {
 323                 r = -ETIMEDOUT;
 324                 goto err2;
 325         } else if (r < 0) {
 326                 goto err2;
 327         }
 328
 329         tmp = adev->wb.wb[index];
 330         if (tmp == 0xDEADBEEF)
 331                 r = 0;
 332         else
 333                 r = -EINVAL;
 334
 335 err2:
 336         amdgpu_ib_free(adev, &ib, NULL);
 337         dma_fence_put(f);
 338 err1:
 339         amdgpu_device_wb_free(adev, index);
 340         return r;
 341 }
 342
 343
 344 /* This value might differs per partition */
 345 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
 346 {
 347         uint64_t clock;
 348
 349         mutex_lock(&adev->gfx.gpu_clock_mutex);
 350         WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
 351         clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |
 352                 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
 353         mutex_unlock(&adev->gfx.gpu_clock_mutex);
 354
 355         return clock;
 356 }
 357
 358 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev)
 359 {
 360         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 361         amdgpu_ucode_release(&adev->gfx.me_fw);
 362         amdgpu_ucode_release(&adev->gfx.ce_fw);
 363         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 364         amdgpu_ucode_release(&adev->gfx.mec_fw);
 365         amdgpu_ucode_release(&adev->gfx.mec2_fw);
 366
 367         kfree(adev->gfx.rlc.register_list_format);
 368 }
 369
 370 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,
 371                                           const char *chip_name)
 372 {
 373         char fw_name[30];
 374         int err;
 375         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 376         uint16_t version_major;
 377         uint16_t version_minor;
 378
 379         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 380
 381         err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
 382         if (err)
 383                 goto out;
 384         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 385
 386         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 387         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 388         err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 389 out:
 390         if (err)
 391                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 392
 393         return err;
 394 }
 395
 396 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev)
 397 {
 398         return true;
 399 }
 400
 401 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev)
 402 {
 403         if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev))
 404                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 405 }
 406
 407 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,
 408                                           const char *chip_name)
 409 {
 410         char fw_name[30];
 411         int err;
 412
 413         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 414
 415         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
 416         if (err)
 417                 goto out;
 418         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 419         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 420
 421         adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
 422         adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
 423
 424         gfx_v9_4_3_check_if_need_gfxoff(adev);
 425
 426 out:
 427         if (err)
 428                 amdgpu_ucode_release(&adev->gfx.mec_fw);
 429         return err;
 430 }
 431
 432 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)
 433 {
 434         char ucode_prefix[15];
 435         int r;
 436
 437         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 438
 439         r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix);
 440         if (r)
 441                 return r;
 442
 443         r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix);
 444         if (r)
 445                 return r;
 446
 447         return r;
 448 }
 449
 450 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev)
 451 {
 452         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 453         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 454 }
 455
 456 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev)
 457 {
 458         int r, i, num_xcc;
 459         u32 *hpd;
 460         const __le32 *fw_data;
 461         unsigned fw_size;
 462         u32 *fw;
 463         size_t mec_hpd_size;
 464
 465         const struct gfx_firmware_header_v1_0 *mec_hdr;
 466
 467         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 468         for (i = 0; i < num_xcc; i++)
 469                 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap,
 470                         AMDGPU_MAX_COMPUTE_QUEUES);
 471
 472         /* take ownership of the relevant compute queues */
 473         amdgpu_gfx_compute_queue_acquire(adev);
 474         mec_hpd_size =
 475                 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE;
 476         if (mec_hpd_size) {
 477                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 478                                               AMDGPU_GEM_DOMAIN_VRAM |
 479                                               AMDGPU_GEM_DOMAIN_GTT,
 480                                               &adev->gfx.mec.hpd_eop_obj,
 481                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 482                                               (void **)&hpd);
 483                 if (r) {
 484                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 485                         gfx_v9_4_3_mec_fini(adev);
 486                         return r;
 487                 }
 488
 489                 if (amdgpu_emu_mode == 1) {
 490                         for (i = 0; i < mec_hpd_size / 4; i++) {
 491                                 memset((void *)(hpd + i), 0, 4);
 492                                 if (i % 50 == 0)
 493                                         msleep(1);
 494                         }
 495                 } else {
 496                         memset(hpd, 0, mec_hpd_size);
 497                 }
 498
 499                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 500                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 501         }
 502
 503         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 504
 505         fw_data = (const __le32 *)
 506                 (adev->gfx.mec_fw->data +
 507                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
 508         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
 509
 510         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
 511                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 512                                       &adev->gfx.mec.mec_fw_obj,
 513                                       &adev->gfx.mec.mec_fw_gpu_addr,
 514                                       (void **)&fw);
 515         if (r) {
 516                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
 517                 gfx_v9_4_3_mec_fini(adev);
 518                 return r;
 519         }
 520
 521         memcpy(fw, fw_data, fw_size);
 522
 523         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
 524         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 525
 526         return 0;
 527 }
 528
 529 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 530                                         u32 sh_num, u32 instance, int xcc_id)
 531 {
 532         u32 data;
 533
 534         if (instance == 0xffffffff)
 535                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
 536                                      INSTANCE_BROADCAST_WRITES, 1);
 537         else
 538                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
 539                                      INSTANCE_INDEX, instance);
 540
 541         if (se_num == 0xffffffff)
 542                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 543                                      SE_BROADCAST_WRITES, 1);
 544         else
 545                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
 546
 547         if (sh_num == 0xffffffff)
 548                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 549                                      SH_BROADCAST_WRITES, 1);
 550         else
 551                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
 552
 553         WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);
 554 }
 555
 556 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address)
 557 {
 558         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
 559                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 560                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
 561                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
 562                 (SQ_IND_INDEX__FORCE_READ_MASK));
 563         return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
 564 }
 565
 566 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 567                            uint32_t wave, uint32_t thread,
 568                            uint32_t regno, uint32_t num, uint32_t *out)
 569 {
 570         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
 571                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 572                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
 573                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 574                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
 575                 (SQ_IND_INDEX__FORCE_READ_MASK) |
 576                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 577         while (num--)
 578                 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
 579 }
 580
 581 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev,
 582                                       uint32_t xcc_id, uint32_t simd, uint32_t wave,
 583                                       uint32_t *dst, int *no_fields)
 584 {
 585         /* type 1 wave data */
 586         dst[(*no_fields)++] = 1;
 587         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
 588         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
 589         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
 590         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
 591         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
 592         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID);
 593         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
 594         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
 595         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC);
 596         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC);
 597         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS);
 598         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
 599         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0);
 600         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0);
 601         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE);
 602 }
 603
 604 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 605                                        uint32_t wave, uint32_t start,
 606                                        uint32_t size, uint32_t *dst)
 607 {
 608         wave_read_regs(adev, xcc_id, simd, wave, 0,
 609                        start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
 610 }
 611
 612 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 613                                        uint32_t wave, uint32_t thread,
 614                                        uint32_t start, uint32_t size,
 615                                        uint32_t *dst)
 616 {
 617         wave_read_regs(adev, xcc_id, simd, wave, thread,
 618                        start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 619 }
 620
 621 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
 622                                         u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
 623 {
 624         soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
 625 }
 626
 627
 628 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
 629                                                 int num_xccs_per_xcp)
 630 {
 631         int ret, i, num_xcc;
 632         u32 tmp = 0;
 633
 634         if (adev->psp.funcs) {
 635                 ret = psp_spatial_partition(&adev->psp,
 636                                             NUM_XCC(adev->gfx.xcc_mask) /
 637                                                     num_xccs_per_xcp);
 638                 if (ret)
 639                         return ret;
 640         } else {
 641                 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 642
 643                 for (i = 0; i < num_xcc; i++) {
 644                         tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
 645                                             num_xccs_per_xcp);
 646                         tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
 647                                             i % num_xccs_per_xcp);
 648                         WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,
 649                                      tmp);
 650                 }
 651                 ret = 0;
 652         }
 653
 654         adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
 655
 656         return ret;
 657 }
 658
 659 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
 660 {
 661         int xcc;
 662
 663         xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
 664         if (!xcc) {
 665                 dev_err(adev->dev, "Couldn't find xcc mapping from IH node");
 666                 return -EINVAL;
 667         }
 668
 669         return xcc - 1;
 670 }
 671
 672 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
 673         .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
 674         .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh,
 675         .read_wave_data = &gfx_v9_4_3_read_wave_data,
 676         .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
 677         .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
 678         .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
 679         .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
 680         .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst,
 681 };
 682
 683 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle,
 684                                       struct aca_bank *bank, enum aca_smu_type type,
 685                                       void *data)
 686 {
 687         struct aca_bank_info info;
 688         u64 misc0;
 689         u32 instlo;
 690         int ret;
 691
 692         ret = aca_bank_info_decode(bank, &info);
 693         if (ret)
 694                 return ret;
 695
 696         /* NOTE: overwrite info.die_id with xcd id for gfx */
 697         instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
 698         instlo &= GENMASK(31, 1);
 699         info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1;
 700
 701         misc0 = bank->regs[ACA_REG_IDX_MISC0];
 702
 703         switch (type) {
 704         case ACA_SMU_TYPE_UE:
 705                 ret = aca_error_cache_log_bank_error(handle, &info,
 706                                                      ACA_ERROR_TYPE_UE, 1ULL);
 707                 break;
 708         case ACA_SMU_TYPE_CE:
 709                 ret = aca_error_cache_log_bank_error(handle, &info,
 710                                                      ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0));
 711                 break;
 712         default:
 713                 return -EINVAL;
 714         }
 715
 716         return ret;
 717 }
 718
 719 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
 720                                          enum aca_smu_type type, void *data)
 721 {
 722         u32 instlo;
 723
 724         instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
 725         instlo &= GENMASK(31, 1);
 726         switch (instlo) {
 727         case mmSMNAID_XCD0_MCA_SMU:
 728         case mmSMNAID_XCD1_MCA_SMU:
 729         case mmSMNXCD_XCD0_MCA_SMU:
 730                 return true;
 731         default:
 732                 break;
 733         }
 734
 735         return false;
 736 }
 737
 738 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = {
 739         .aca_bank_parser = gfx_v9_4_3_aca_bank_parser,
 740         .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid,
 741 };
 742
 743 static const struct aca_info gfx_v9_4_3_aca_info = {
 744         .hwip = ACA_HWIP_TYPE_SMU,
 745         .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,
 746         .bank_ops = &gfx_v9_4_3_aca_bank_ops,
 747 };
 748
 749 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
 750 {
 751         u32 gb_addr_config;
 752
 753         adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
 754         adev->gfx.ras = &gfx_v9_4_3_ras;
 755
 756         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 757         case IP_VERSION(9, 4, 3):
 758                 adev->gfx.config.max_hw_contexts = 8;
 759                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 760                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 761                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 762                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 763                 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
 764                 break;
 765         default:
 766                 BUG();
 767                 break;
 768         }
 769
 770         adev->gfx.config.gb_addr_config = gb_addr_config;
 771
 772         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
 773                         REG_GET_FIELD(
 774                                         adev->gfx.config.gb_addr_config,
 775                                         GB_ADDR_CONFIG,
 776                                         NUM_PIPES);
 777
 778         adev->gfx.config.max_tile_pipes =
 779                 adev->gfx.config.gb_addr_config_fields.num_pipes;
 780
 781         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
 782                         REG_GET_FIELD(
 783                                         adev->gfx.config.gb_addr_config,
 784                                         GB_ADDR_CONFIG,
 785                                         NUM_BANKS);
 786         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
 787                         REG_GET_FIELD(
 788                                         adev->gfx.config.gb_addr_config,
 789                                         GB_ADDR_CONFIG,
 790                                         MAX_COMPRESSED_FRAGS);
 791         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
 792                         REG_GET_FIELD(
 793                                         adev->gfx.config.gb_addr_config,
 794                                         GB_ADDR_CONFIG,
 795                                         NUM_RB_PER_SE);
 796         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
 797                         REG_GET_FIELD(
 798                                         adev->gfx.config.gb_addr_config,
 799                                         GB_ADDR_CONFIG,
 800                                         NUM_SHADER_ENGINES);
 801         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
 802                         REG_GET_FIELD(
 803                                         adev->gfx.config.gb_addr_config,
 804                                         GB_ADDR_CONFIG,
 805                                         PIPE_INTERLEAVE_SIZE));
 806
 807         return 0;
 808 }
 809
 810 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 811                                         int xcc_id, int mec, int pipe, int queue)
 812 {
 813         unsigned irq_type;
 814         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
 815         unsigned int hw_prio;
 816         uint32_t xcc_doorbell_start;
 817
 818         ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings +
 819                                        ring_id];
 820
 821         /* mec0 is me1 */
 822         ring->xcc_id = xcc_id;
 823         ring->me = mec + 1;
 824         ring->pipe = pipe;
 825         ring->queue = queue;
 826
 827         ring->ring_obj = NULL;
 828         ring->use_doorbell = true;
 829         xcc_doorbell_start = adev->doorbell_index.mec_ring0 +
 830                              xcc_id * adev->doorbell_index.xcc_doorbell_range;
 831         ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1;
 832         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
 833                              (ring_id + xcc_id * adev->gfx.num_compute_rings) *
 834                                      GFX9_MEC_HPD_SIZE;
 835         ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
 836         sprintf(ring->name, "comp_%d.%d.%d.%d",
 837                         ring->xcc_id, ring->me, ring->pipe, ring->queue);
 838
 839         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
 840                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
 841                 + ring->pipe;
 842         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
 843                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 844         /* type-2 packets are deprecated on MEC, use type-3 instead */
 845         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 846                                 hw_prio, NULL);
 847 }
 848
 849 static int gfx_v9_4_3_sw_init(void *handle)
 850 {
 851         int i, j, k, r, ring_id, xcc_id, num_xcc;
 852         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 853
 854         adev->gfx.mec.num_mec = 2;
 855         adev->gfx.mec.num_pipe_per_mec = 4;
 856         adev->gfx.mec.num_queue_per_pipe = 8;
 857
 858         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 859
 860         /* EOP Event */
 861         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
 862         if (r)
 863                 return r;
 864
 865         /* Privileged reg */
 866         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
 867                               &adev->gfx.priv_reg_irq);
 868         if (r)
 869                 return r;
 870
 871         /* Privileged inst */
 872         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
 873                               &adev->gfx.priv_inst_irq);
 874         if (r)
 875                 return r;
 876
 877         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 878
 879         r = adev->gfx.rlc.funcs->init(adev);
 880         if (r) {
 881                 DRM_ERROR("Failed to init rlc BOs!\n");
 882                 return r;
 883         }
 884
 885         r = gfx_v9_4_3_mec_init(adev);
 886         if (r) {
 887                 DRM_ERROR("Failed to init MEC BOs!\n");
 888                 return r;
 889         }
 890
 891         /* set up the compute queues - allocate horizontally across pipes */
 892         for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
 893                 ring_id = 0;
 894                 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
 895                         for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
 896                                 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
 897                                      k++) {
 898                                         if (!amdgpu_gfx_is_mec_queue_enabled(
 899                                                         adev, xcc_id, i, k, j))
 900                                                 continue;
 901
 902                                         r = gfx_v9_4_3_compute_ring_init(adev,
 903                                                                        ring_id,
 904                                                                        xcc_id,
 905                                                                        i, k, j);
 906                                         if (r)
 907                                                 return r;
 908
 909                                         ring_id++;
 910                                 }
 911                         }
 912                 }
 913
 914                 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id);
 915                 if (r) {
 916                         DRM_ERROR("Failed to init KIQ BOs!\n");
 917                         return r;
 918                 }
 919
 920                 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
 921                 if (r)
 922                         return r;
 923
 924                 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
 925                 r = amdgpu_gfx_mqd_sw_init(adev,
 926                                 sizeof(struct v9_mqd_allocation), xcc_id);
 927                 if (r)
 928                         return r;
 929         }
 930
 931         r = gfx_v9_4_3_gpu_early_init(adev);
 932         if (r)
 933                 return r;
 934
 935         r = amdgpu_gfx_ras_sw_init(adev);
 936         if (r)
 937                 return r;
 938
 939
 940         if (!amdgpu_sriov_vf(adev))
 941                 r = amdgpu_gfx_sysfs_init(adev);
 942
 943         return r;
 944 }
 945
 946 static int gfx_v9_4_3_sw_fini(void *handle)
 947 {
 948         int i, num_xcc;
 949         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 950
 951         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 952         for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++)
 953                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 954
 955         for (i = 0; i < num_xcc; i++) {
 956                 amdgpu_gfx_mqd_sw_fini(adev, i);
 957                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring);
 958                 amdgpu_gfx_kiq_fini(adev, i);
 959         }
 960
 961         gfx_v9_4_3_mec_fini(adev);
 962         amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
 963         gfx_v9_4_3_free_microcode(adev);
 964         if (!amdgpu_sriov_vf(adev))
 965                 amdgpu_gfx_sysfs_fini(adev);
 966
 967         return 0;
 968 }
 969
 970 #define DEFAULT_SH_MEM_BASES    (0x6000)
 971 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
 972                                              int xcc_id)
 973 {
 974         int i;
 975         uint32_t sh_mem_config;
 976         uint32_t sh_mem_bases;
 977         uint32_t data;
 978
 979         /*
 980          * Configure apertures:
 981          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
 982          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
 983          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
 984          */
 985         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
 986
 987         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
 988                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 989                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
 990
 991         mutex_lock(&adev->srbm_mutex);
 992         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
 993                 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
 994                 /* CP and shaders */
 995                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);
 996                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);
 997
 998                 /* Enable trap for each kfd vmid. */
 999                 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);
1000                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1001                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);
1002         }
1003         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1004         mutex_unlock(&adev->srbm_mutex);
1005
1006         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1007            acccess. These should be enabled by FW for target VMIDs. */
1008         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1009                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
1010                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);
1011                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);
1012                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);
1013         }
1014 }
1015
1016 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id)
1017 {
1018         int vmid;
1019
1020         /*
1021          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1022          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1023          * the driver can enable them for graphics. VMID0 should maintain
1024          * access so that HWS firmware can save/restore entries.
1025          */
1026         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
1027                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);
1028                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);
1029                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);
1030                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);
1031         }
1032 }
1033
1034 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,
1035                                           int xcc_id)
1036 {
1037         u32 tmp;
1038         int i;
1039
1040         /* XXX SH_MEM regs */
1041         /* where to put LDS, scratch, GPUVM in FSA64 space */
1042         mutex_lock(&adev->srbm_mutex);
1043         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1044                 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
1045                 /* CP and shaders */
1046                 if (i == 0) {
1047                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1048                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1049                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
1050                                             !!adev->gmc.noretry);
1051                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1052                                          regSH_MEM_CONFIG, tmp);
1053                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1054                                          regSH_MEM_BASES, 0);
1055                 } else {
1056                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1057                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1058                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
1059                                             !!adev->gmc.noretry);
1060                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1061                                          regSH_MEM_CONFIG, tmp);
1062                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1063                                             (adev->gmc.private_aperture_start >>
1064                                              48));
1065                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1066                                             (adev->gmc.shared_aperture_start >>
1067                                              48));
1068                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1069                                          regSH_MEM_BASES, tmp);
1070                 }
1071         }
1072         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
1073
1074         mutex_unlock(&adev->srbm_mutex);
1075
1076         gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id);
1077         gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id);
1078 }
1079
1080 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
1081 {
1082         int i, num_xcc;
1083
1084         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1085
1086         gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
1087         adev->gfx.config.db_debug2 =
1088                 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);
1089
1090         for (i = 0; i < num_xcc; i++)
1091                 gfx_v9_4_3_xcc_constants_init(adev, i);
1092 }
1093
1094 static void
1095 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev,
1096                                            int xcc_id)
1097 {
1098         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);
1099 }
1100
1101 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id)
1102 {
1103         /*
1104          * Rlc save restore list is workable since v2_1.
1105          * And it's needed by gfxoff feature.
1106          */
1107         if (adev->gfx.rlc.is_rlc_v2_1)
1108                 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id);
1109 }
1110
1111 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id)
1112 {
1113         uint32_t data;
1114
1115         data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);
1116         data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK;
1117         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);
1118 }
1119
1120 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
1121 {
1122         uint32_t rlc_setting;
1123
1124         /* if RLC is not enabled, do nothing */
1125         rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);
1126         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
1127                 return false;
1128
1129         return true;
1130 }
1131
1132 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
1133 {
1134         uint32_t data;
1135         unsigned i;
1136
1137         data = RLC_SAFE_MODE__CMD_MASK;
1138         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
1139         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1140
1141         /* wait for RLC_SAFE_MODE */
1142         for (i = 0; i < adev->usec_timeout; i++) {
1143                 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
1144                         break;
1145                 udelay(1);
1146         }
1147 }
1148
1149 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev,
1150                                            int xcc_id)
1151 {
1152         uint32_t data;
1153
1154         data = RLC_SAFE_MODE__CMD_MASK;
1155         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1156 }
1157
1158 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
1159 {
1160         int xcc_id, num_xcc;
1161         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
1162
1163         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1164         for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
1165                 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];
1166                 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);
1167                 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);
1168                 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);
1169                 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);
1170                 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);
1171                 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);
1172                 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT);
1173         }
1174         adev->gfx.rlc.rlcg_reg_access_supported = true;
1175 }
1176
1177 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
1178 {
1179         /* init spm vmid with 0xf */
1180         if (adev->gfx.rlc.funcs->update_spm_vmid)
1181                 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
1182
1183         return 0;
1184 }
1185
1186 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev,
1187                                                int xcc_id)
1188 {
1189         u32 i, j, k;
1190         u32 mask;
1191
1192         mutex_lock(&adev->grbm_idx_mutex);
1193         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1194                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1195                         gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff,
1196                                                     xcc_id);
1197                         for (k = 0; k < adev->usec_timeout; k++) {
1198                                 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)
1199                                         break;
1200                                 udelay(1);
1201                         }
1202                         if (k == adev->usec_timeout) {
1203                                 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff,
1204                                                             0xffffffff,
1205                                                             0xffffffff, xcc_id);
1206                                 mutex_unlock(&adev->grbm_idx_mutex);
1207                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1208                                          i, j);
1209                                 return;
1210                         }
1211                 }
1212         }
1213         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
1214                                     xcc_id);
1215         mutex_unlock(&adev->grbm_idx_mutex);
1216
1217         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1218                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1219                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1220                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1221         for (k = 0; k < adev->usec_timeout; k++) {
1222                 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1223                         break;
1224                 udelay(1);
1225         }
1226 }
1227
1228 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1229                                                      bool enable, int xcc_id)
1230 {
1231         u32 tmp;
1232
1233         /* These interrupts should be enabled to drive DS clock */
1234
1235         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);
1236
1237         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1238         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1239         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1240
1241         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);
1242 }
1243
1244 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id)
1245 {
1246         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1247                               RLC_ENABLE_F32, 0);
1248         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1249         gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id);
1250 }
1251
1252 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev)
1253 {
1254         int i, num_xcc;
1255
1256         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1257         for (i = 0; i < num_xcc; i++)
1258                 gfx_v9_4_3_xcc_rlc_stop(adev, i);
1259 }
1260
1261 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id)
1262 {
1263         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1264                               SOFT_RESET_RLC, 1);
1265         udelay(50);
1266         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1267                               SOFT_RESET_RLC, 0);
1268         udelay(50);
1269 }
1270
1271 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev)
1272 {
1273         int i, num_xcc;
1274
1275         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1276         for (i = 0; i < num_xcc; i++)
1277                 gfx_v9_4_3_xcc_rlc_reset(adev, i);
1278 }
1279
1280 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id)
1281 {
1282         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1283                               RLC_ENABLE_F32, 1);
1284         udelay(50);
1285
1286         /* carrizo do enable cp interrupt after cp inited */
1287         if (!(adev->flags & AMD_IS_APU)) {
1288                 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1289                 udelay(50);
1290         }
1291 }
1292
1293 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev)
1294 {
1295 #ifdef AMDGPU_RLC_DEBUG_RETRY
1296         u32 rlc_ucode_ver;
1297 #endif
1298         int i, num_xcc;
1299
1300         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1301         for (i = 0; i < num_xcc; i++) {
1302                 gfx_v9_4_3_xcc_rlc_start(adev, i);
1303 #ifdef AMDGPU_RLC_DEBUG_RETRY
1304                 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1305                 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);
1306                 if (rlc_ucode_ver == 0x108) {
1307                         dev_info(adev->dev,
1308                                  "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1309                                  rlc_ucode_ver, adev->gfx.rlc_fw_version);
1310                         /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1311                          * default is 0x9C4 to create a 100us interval */
1312                         WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);
1313                         /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1314                          * to disable the page fault retry interrupts, default is
1315                          * 0x100 (256) */
1316                         WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);
1317                 }
1318 #endif
1319         }
1320 }
1321
1322 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev,
1323                                              int xcc_id)
1324 {
1325         const struct rlc_firmware_header_v2_0 *hdr;
1326         const __le32 *fw_data;
1327         unsigned i, fw_size;
1328
1329         if (!adev->gfx.rlc_fw)
1330                 return -EINVAL;
1331
1332         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1333         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1334
1335         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1336                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1337         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1338
1339         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,
1340                         RLCG_UCODE_LOADING_START_ADDRESS);
1341         for (i = 0; i < fw_size; i++) {
1342                 if (amdgpu_emu_mode == 1 && i % 100 == 0) {
1343                         dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i);
1344                         msleep(1);
1345                 }
1346                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
1347         }
1348         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1349
1350         return 0;
1351 }
1352
1353 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id)
1354 {
1355         int r;
1356
1357         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1358                 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
1359                 /* legacy rlc firmware loading */
1360                 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id);
1361                 if (r)
1362                         return r;
1363                 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id);
1364         }
1365
1366         amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
1367         /* disable CG */
1368         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);
1369         gfx_v9_4_3_xcc_init_pg(adev, xcc_id);
1370         amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
1371
1372         return 0;
1373 }
1374
1375 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
1376 {
1377         int r, i, num_xcc;
1378
1379         if (amdgpu_sriov_vf(adev))
1380                 return 0;
1381
1382         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1383         for (i = 0; i < num_xcc; i++) {
1384                 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
1385                 if (r)
1386                         return r;
1387         }
1388
1389         return 0;
1390 }
1391
1392 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1393                                        unsigned vmid)
1394 {
1395         u32 reg, data;
1396
1397         reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
1398         if (amdgpu_sriov_is_pp_one_vf(adev))
1399                 data = RREG32_NO_KIQ(reg);
1400         else
1401                 data = RREG32(reg);
1402
1403         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
1404         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
1405
1406         if (amdgpu_sriov_is_pp_one_vf(adev))
1407                 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1408         else
1409                 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1410 }
1411
1412 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = {
1413         {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1414         {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
1415 };
1416
1417 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev,
1418                                         uint32_t offset,
1419                                         struct soc15_reg_rlcg *entries, int arr_size)
1420 {
1421         int i, inst;
1422         uint32_t reg;
1423
1424         if (!entries)
1425                 return false;
1426
1427         for (i = 0; i < arr_size; i++) {
1428                 const struct soc15_reg_rlcg *entry;
1429
1430                 entry = &entries[i];
1431                 inst = adev->ip_map.logical_to_dev_inst ?
1432                                adev->ip_map.logical_to_dev_inst(
1433                                        adev, entry->hwip, entry->instance) :
1434                                entry->instance;
1435                 reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
1436                       entry->reg;
1437                 if (offset == reg)
1438                         return true;
1439         }
1440
1441         return false;
1442 }
1443
1444 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
1445 {
1446         return gfx_v9_4_3_check_rlcg_range(adev, offset,
1447                                         (void *)rlcg_access_gc_9_4_3,
1448                                         ARRAY_SIZE(rlcg_access_gc_9_4_3));
1449 }
1450
1451 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,
1452                                              bool enable, int xcc_id)
1453 {
1454         if (enable) {
1455                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);
1456         } else {
1457                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
1458                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1459                 adev->gfx.kiq[xcc_id].ring.sched.ready = false;
1460         }
1461         udelay(50);
1462 }
1463
1464 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev,
1465                                                     int xcc_id)
1466 {
1467         const struct gfx_firmware_header_v1_0 *mec_hdr;
1468         const __le32 *fw_data;
1469         unsigned i;
1470         u32 tmp;
1471         u32 mec_ucode_addr_offset;
1472         u32 mec_ucode_data_offset;
1473
1474         if (!adev->gfx.mec_fw)
1475                 return -EINVAL;
1476
1477         gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
1478
1479         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1480         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1481
1482         fw_data = (const __le32 *)
1483                 (adev->gfx.mec_fw->data +
1484                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1485         tmp = 0;
1486         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1487         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1488         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);
1489
1490         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,
1491                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1492         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,
1493                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1494
1495         mec_ucode_addr_offset =
1496                 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);
1497         mec_ucode_data_offset =
1498                 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);
1499
1500         /* MEC1 */
1501         WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset);
1502         for (i = 0; i < mec_hdr->jt_size; i++)
1503                 WREG32(mec_ucode_data_offset,
1504                        le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1505
1506         WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
1507         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1508
1509         return 0;
1510 }
1511
1512 /* KIQ functions */
1513 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id)
1514 {
1515         uint32_t tmp;
1516         struct amdgpu_device *adev = ring->adev;
1517
1518         /* tell RLC which is KIQ queue */
1519         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
1520         tmp &= 0xffffff00;
1521         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1522         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1523         tmp |= 0x80;
1524         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1525 }
1526
1527 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
1528 {
1529         struct amdgpu_device *adev = ring->adev;
1530
1531         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
1532                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
1533                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
1534                         mqd->cp_hqd_queue_priority =
1535                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
1536                 }
1537         }
1538 }
1539
1540 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id)
1541 {
1542         struct amdgpu_device *adev = ring->adev;
1543         struct v9_mqd *mqd = ring->mqd_ptr;
1544         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1545         uint32_t tmp;
1546
1547         mqd->header = 0xC0310800;
1548         mqd->compute_pipelinestat_enable = 0x00000001;
1549         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1550         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1551         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1552         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1553         mqd->compute_misc_reserved = 0x00000003;
1554
1555         mqd->dynamic_cu_mask_addr_lo =
1556                 lower_32_bits(ring->mqd_gpu_addr
1557                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1558         mqd->dynamic_cu_mask_addr_hi =
1559                 upper_32_bits(ring->mqd_gpu_addr
1560                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1561
1562         eop_base_addr = ring->eop_gpu_addr >> 8;
1563         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1564         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1565
1566         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1567         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);
1568         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1569                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
1570
1571         mqd->cp_hqd_eop_control = tmp;
1572
1573         /* enable doorbell? */
1574         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
1575
1576         if (ring->use_doorbell) {
1577                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1578                                     DOORBELL_OFFSET, ring->doorbell_index);
1579                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1580                                     DOORBELL_EN, 1);
1581                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1582                                     DOORBELL_SOURCE, 0);
1583                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1584                                     DOORBELL_HIT, 0);
1585         } else {
1586                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1587                                          DOORBELL_EN, 0);
1588         }
1589
1590         mqd->cp_hqd_pq_doorbell_control = tmp;
1591
1592         /* disable the queue if it's active */
1593         ring->wptr = 0;
1594         mqd->cp_hqd_dequeue_request = 0;
1595         mqd->cp_hqd_pq_rptr = 0;
1596         mqd->cp_hqd_pq_wptr_lo = 0;
1597         mqd->cp_hqd_pq_wptr_hi = 0;
1598
1599         /* set the pointer to the MQD */
1600         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1601         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1602
1603         /* set MQD vmid to 0 */
1604         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);
1605         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1606         mqd->cp_mqd_control = tmp;
1607
1608         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1609         hqd_gpu_addr = ring->gpu_addr >> 8;
1610         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1611         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1612
1613         /* set up the HQD, this is similar to CP_RB0_CNTL */
1614         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);
1615         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1616                             (order_base_2(ring->ring_size / 4) - 1));
1617         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1618                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1619 #ifdef __BIG_ENDIAN
1620         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1621 #endif
1622         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1623         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1624         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1625         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1626         mqd->cp_hqd_pq_control = tmp;
1627
1628         /* set the wb address whether it's enabled or not */
1629         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1630         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1631         mqd->cp_hqd_pq_rptr_report_addr_hi =
1632                 upper_32_bits(wb_gpu_addr) & 0xffff;
1633
1634         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1635         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1636         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1637         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1638
1639         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1640         ring->wptr = 0;
1641         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);
1642
1643         /* set the vmid for the queue */
1644         mqd->cp_hqd_vmid = 0;
1645
1646         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);
1647         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
1648         mqd->cp_hqd_persistent_state = tmp;
1649
1650         /* set MIN_IB_AVAIL_SIZE */
1651         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);
1652         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
1653         mqd->cp_hqd_ib_control = tmp;
1654
1655         /* set static priority for a queue/ring */
1656         gfx_v9_4_3_mqd_set_priority(ring, mqd);
1657         mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);
1658
1659         /* map_queues packet doesn't need activate the queue,
1660          * so only kiq need set this field.
1661          */
1662         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
1663                 mqd->cp_hqd_active = 1;
1664
1665         return 0;
1666 }
1667
1668 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring,
1669                                             int xcc_id)
1670 {
1671         struct amdgpu_device *adev = ring->adev;
1672         struct v9_mqd *mqd = ring->mqd_ptr;
1673         int j;
1674
1675         /* disable wptr polling */
1676         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
1677
1678         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,
1679                mqd->cp_hqd_eop_base_addr_lo);
1680         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,
1681                mqd->cp_hqd_eop_base_addr_hi);
1682
1683         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1684         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,
1685                mqd->cp_hqd_eop_control);
1686
1687         /* enable doorbell? */
1688         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1689                mqd->cp_hqd_pq_doorbell_control);
1690
1691         /* disable the queue if it's active */
1692         if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1693                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1694                 for (j = 0; j < adev->usec_timeout; j++) {
1695                         if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1696                                 break;
1697                         udelay(1);
1698                 }
1699                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1700                        mqd->cp_hqd_dequeue_request);
1701                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,
1702                        mqd->cp_hqd_pq_rptr);
1703                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1704                        mqd->cp_hqd_pq_wptr_lo);
1705                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1706                        mqd->cp_hqd_pq_wptr_hi);
1707         }
1708
1709         /* set the pointer to the MQD */
1710         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,
1711                mqd->cp_mqd_base_addr_lo);
1712         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,
1713                mqd->cp_mqd_base_addr_hi);
1714
1715         /* set MQD vmid to 0 */
1716         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,
1717                mqd->cp_mqd_control);
1718
1719         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1720         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,
1721                mqd->cp_hqd_pq_base_lo);
1722         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,
1723                mqd->cp_hqd_pq_base_hi);
1724
1725         /* set up the HQD, this is similar to CP_RB0_CNTL */
1726         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,
1727                mqd->cp_hqd_pq_control);
1728
1729         /* set the wb address whether it's enabled or not */
1730         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,
1731                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
1732         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1733                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
1734
1735         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1736         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,
1737                mqd->cp_hqd_pq_wptr_poll_addr_lo);
1738         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1739                mqd->cp_hqd_pq_wptr_poll_addr_hi);
1740
1741         /* enable the doorbell if requested */
1742         if (ring->use_doorbell) {
1743                 WREG32_SOC15(
1744                         GC, GET_INST(GC, xcc_id),
1745                         regCP_MEC_DOORBELL_RANGE_LOWER,
1746                         ((adev->doorbell_index.kiq +
1747                           xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1748                          2) << 2);
1749                 WREG32_SOC15(
1750                         GC, GET_INST(GC, xcc_id),
1751                         regCP_MEC_DOORBELL_RANGE_UPPER,
1752                         ((adev->doorbell_index.userqueue_end +
1753                           xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1754                          2) << 2);
1755         }
1756
1757         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1758                mqd->cp_hqd_pq_doorbell_control);
1759
1760         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1761         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1762                mqd->cp_hqd_pq_wptr_lo);
1763         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1764                mqd->cp_hqd_pq_wptr_hi);
1765
1766         /* set the vmid for the queue */
1767         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);
1768
1769         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
1770                mqd->cp_hqd_persistent_state);
1771
1772         /* activate the queue */
1773         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,
1774                mqd->cp_hqd_active);
1775
1776         if (ring->use_doorbell)
1777                 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);
1778
1779         return 0;
1780 }
1781
1782 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring,
1783                                             int xcc_id)
1784 {
1785         struct amdgpu_device *adev = ring->adev;
1786         int j;
1787
1788         /* disable the queue if it's active */
1789         if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1790
1791                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1792
1793                 for (j = 0; j < adev->usec_timeout; j++) {
1794                         if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1795                                 break;
1796                         udelay(1);
1797                 }
1798
1799                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
1800                         DRM_DEBUG("%s dequeue request failed.\n", ring->name);
1801
1802                         /* Manual disable if dequeue request times out */
1803                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);
1804                 }
1805
1806                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1807                       0);
1808         }
1809
1810         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);
1811         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);
1812         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);
1813         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
1814         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1815         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
1816         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);
1817         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);
1818
1819         return 0;
1820 }
1821
1822 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1823 {
1824         struct amdgpu_device *adev = ring->adev;
1825         struct v9_mqd *mqd = ring->mqd_ptr;
1826         struct v9_mqd *tmp_mqd;
1827
1828         gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id);
1829
1830         /* GPU could be in bad state during probe, driver trigger the reset
1831          * after load the SMU, in this case , the mqd is not be initialized.
1832          * driver need to re-init the mqd.
1833          * check mqd->cp_hqd_pq_control since this value should not be 0
1834          */
1835         tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup;
1836         if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) {
1837                 /* for GPU_RESET case , reset MQD to a clean status */
1838                 if (adev->gfx.kiq[xcc_id].mqd_backup)
1839                         memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation));
1840
1841                 /* reset ring buffer */
1842                 ring->wptr = 0;
1843                 amdgpu_ring_clear_ring(ring);
1844                 mutex_lock(&adev->srbm_mutex);
1845                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1846                 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1847                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1848                 mutex_unlock(&adev->srbm_mutex);
1849         } else {
1850                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1851                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1852                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1853                 mutex_lock(&adev->srbm_mutex);
1854                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
1855                         amdgpu_ring_clear_ring(ring);
1856                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1857                 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1858                 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1859                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1860                 mutex_unlock(&adev->srbm_mutex);
1861
1862                 if (adev->gfx.kiq[xcc_id].mqd_backup)
1863                         memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
1864         }
1865
1866         return 0;
1867 }
1868
1869 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1870 {
1871         struct amdgpu_device *adev = ring->adev;
1872         struct v9_mqd *mqd = ring->mqd_ptr;
1873         int mqd_idx = ring - &adev->gfx.compute_ring[0];
1874         struct v9_mqd *tmp_mqd;
1875
1876         /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control
1877          * is not be initialized before
1878          */
1879         tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
1880
1881         if (!tmp_mqd->cp_hqd_pq_control ||
1882             (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
1883                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1884                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1885                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1886                 mutex_lock(&adev->srbm_mutex);
1887                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1888                 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1889                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1890                 mutex_unlock(&adev->srbm_mutex);
1891
1892                 if (adev->gfx.mec.mqd_backup[mqd_idx])
1893                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
1894         } else {
1895                 /* restore MQD to a clean status */
1896                 if (adev->gfx.mec.mqd_backup[mqd_idx])
1897                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
1898                 /* reset ring buffer */
1899                 ring->wptr = 0;
1900                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
1901                 amdgpu_ring_clear_ring(ring);
1902         }
1903
1904         return 0;
1905 }
1906
1907 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id)
1908 {
1909         struct amdgpu_ring *ring;
1910         int j;
1911
1912         for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1913                 ring = &adev->gfx.compute_ring[j +  xcc_id * adev->gfx.num_compute_rings];
1914                 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1915                         mutex_lock(&adev->srbm_mutex);
1916                         soc15_grbm_select(adev, ring->me,
1917                                         ring->pipe,
1918                                         ring->queue, 0, GET_INST(GC, xcc_id));
1919                         gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id);
1920                         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1921                         mutex_unlock(&adev->srbm_mutex);
1922                 }
1923         }
1924
1925         return 0;
1926 }
1927
1928 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)
1929 {
1930         struct amdgpu_ring *ring;
1931         int r;
1932
1933         ring = &adev->gfx.kiq[xcc_id].ring;
1934
1935         r = amdgpu_bo_reserve(ring->mqd_obj, false);
1936         if (unlikely(r != 0))
1937                 return r;
1938
1939         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1940         if (unlikely(r != 0)) {
1941                 amdgpu_bo_unreserve(ring->mqd_obj);
1942                 return r;
1943         }
1944
1945         gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id);
1946         amdgpu_bo_kunmap(ring->mqd_obj);
1947         ring->mqd_ptr = NULL;
1948         amdgpu_bo_unreserve(ring->mqd_obj);
1949         return 0;
1950 }
1951
1952 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)
1953 {
1954         struct amdgpu_ring *ring = NULL;
1955         int r = 0, i;
1956
1957         gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);
1958
1959         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1960                 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
1961
1962                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1963                 if (unlikely(r != 0))
1964                         goto done;
1965                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1966                 if (!r) {
1967                         r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id);
1968                         amdgpu_bo_kunmap(ring->mqd_obj);
1969                         ring->mqd_ptr = NULL;
1970                 }
1971                 amdgpu_bo_unreserve(ring->mqd_obj);
1972                 if (r)
1973                         goto done;
1974         }
1975
1976         r = amdgpu_gfx_enable_kcq(adev, xcc_id);
1977 done:
1978         return r;
1979 }
1980
1981 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)
1982 {
1983         struct amdgpu_ring *ring;
1984         int r, j;
1985
1986         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1987
1988         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1989                 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id);
1990
1991                 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id);
1992                 if (r)
1993                         return r;
1994         }
1995
1996         r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id);
1997         if (r)
1998                 return r;
1999
2000         r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id);
2001         if (r)
2002                 return r;
2003
2004         for (j = 0; j < adev->gfx.num_compute_rings; j++) {
2005                 ring = &adev->gfx.compute_ring
2006                                 [j + xcc_id * adev->gfx.num_compute_rings];
2007                 r = amdgpu_ring_test_helper(ring);
2008                 if (r)
2009                         return r;
2010         }
2011
2012         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
2013
2014         return 0;
2015 }
2016
2017 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
2018 {
2019         int r = 0, i, num_xcc;
2020
2021         if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
2022                                             AMDGPU_XCP_FL_NONE) ==
2023             AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)
2024                 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr,
2025                                                      amdgpu_user_partt_mode);
2026
2027         if (r)
2028                 return r;
2029
2030         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2031         for (i = 0; i < num_xcc; i++) {
2032                 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
2033                 if (r)
2034                         return r;
2035         }
2036
2037         return 0;
2038 }
2039
2040 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable,
2041                                      int xcc_id)
2042 {
2043         gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id);
2044 }
2045
2046 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
2047 {
2048         if (amdgpu_gfx_disable_kcq(adev, xcc_id))
2049                 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id);
2050
2051         if (amdgpu_sriov_vf(adev)) {
2052                 /* must disable polling for SRIOV when hw finished, otherwise
2053                  * CPC engine may still keep fetching WB address which is already
2054                  * invalid after sw finished and trigger DMAR reading error in
2055                  * hypervisor side.
2056                  */
2057                 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
2058                 return;
2059         }
2060
2061         /* Use deinitialize sequence from CAIL when unbinding device
2062          * from driver, otherwise KIQ is hanging when binding back
2063          */
2064         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
2065                 mutex_lock(&adev->srbm_mutex);
2066                 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me,
2067                                   adev->gfx.kiq[xcc_id].ring.pipe,
2068                                   adev->gfx.kiq[xcc_id].ring.queue, 0,
2069                                   GET_INST(GC, xcc_id));
2070                 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring,
2071                                                  xcc_id);
2072                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
2073                 mutex_unlock(&adev->srbm_mutex);
2074         }
2075
2076         gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id);
2077         gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
2078 }
2079
2080 static int gfx_v9_4_3_hw_init(void *handle)
2081 {
2082         int r;
2083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2084
2085         if (!amdgpu_sriov_vf(adev))
2086                 gfx_v9_4_3_init_golden_registers(adev);
2087
2088         gfx_v9_4_3_constants_init(adev);
2089
2090         r = adev->gfx.rlc.funcs->resume(adev);
2091         if (r)
2092                 return r;
2093
2094         r = gfx_v9_4_3_cp_resume(adev);
2095         if (r)
2096                 return r;
2097
2098         return r;
2099 }
2100
2101 static int gfx_v9_4_3_hw_fini(void *handle)
2102 {
2103         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2104         int i, num_xcc;
2105
2106         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2107         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2108
2109         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2110         for (i = 0; i < num_xcc; i++) {
2111                 gfx_v9_4_3_xcc_fini(adev, i);
2112         }
2113
2114         return 0;
2115 }
2116
2117 static int gfx_v9_4_3_suspend(void *handle)
2118 {
2119         return gfx_v9_4_3_hw_fini(handle);
2120 }
2121
2122 static int gfx_v9_4_3_resume(void *handle)
2123 {
2124         return gfx_v9_4_3_hw_init(handle);
2125 }
2126
2127 static bool gfx_v9_4_3_is_idle(void *handle)
2128 {
2129         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2130         int i, num_xcc;
2131
2132         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2133         for (i = 0; i < num_xcc; i++) {
2134                 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),
2135                                         GRBM_STATUS, GUI_ACTIVE))
2136                         return false;
2137         }
2138         return true;
2139 }
2140
2141 static int gfx_v9_4_3_wait_for_idle(void *handle)
2142 {
2143         unsigned i;
2144         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2145
2146         for (i = 0; i < adev->usec_timeout; i++) {
2147                 if (gfx_v9_4_3_is_idle(handle))
2148                         return 0;
2149                 udelay(1);
2150         }
2151         return -ETIMEDOUT;
2152 }
2153
2154 static int gfx_v9_4_3_soft_reset(void *handle)
2155 {
2156         u32 grbm_soft_reset = 0;
2157         u32 tmp;
2158         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2159
2160         /* GRBM_STATUS */
2161         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);
2162         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2163                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2164                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2165                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2166                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2167                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2168                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2169                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2170                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2171                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2172         }
2173
2174         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2175                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2176                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2177         }
2178
2179         /* GRBM_STATUS2 */
2180         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);
2181         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2182                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2183                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2184
2185
2186         if (grbm_soft_reset) {
2187                 /* stop the rlc */
2188                 adev->gfx.rlc.funcs->stop(adev);
2189
2190                 /* Disable MEC parsing/prefetching */
2191                 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0);
2192
2193                 if (grbm_soft_reset) {
2194                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2195                         tmp |= grbm_soft_reset;
2196                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2197                         WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2198                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2199
2200                         udelay(50);
2201
2202                         tmp &= ~grbm_soft_reset;
2203                         WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2204                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2205                 }
2206
2207                 /* Wait a little for things to settle down */
2208                 udelay(50);
2209         }
2210         return 0;
2211 }
2212
2213 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring,
2214                                           uint32_t vmid,
2215                                           uint32_t gds_base, uint32_t gds_size,
2216                                           uint32_t gws_base, uint32_t gws_size,
2217                                           uint32_t oa_base, uint32_t oa_size)
2218 {
2219         struct amdgpu_device *adev = ring->adev;
2220
2221         /* GDS Base */
2222         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2223                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,
2224                                    gds_base);
2225
2226         /* GDS Size */
2227         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2228                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,
2229                                    gds_size);
2230
2231         /* GWS */
2232         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2233                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,
2234                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2235
2236         /* OA */
2237         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2238                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,
2239                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
2240 }
2241
2242 static int gfx_v9_4_3_early_init(void *handle)
2243 {
2244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2245
2246         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
2247                                           AMDGPU_MAX_COMPUTE_RINGS);
2248         gfx_v9_4_3_set_kiq_pm4_funcs(adev);
2249         gfx_v9_4_3_set_ring_funcs(adev);
2250         gfx_v9_4_3_set_irq_funcs(adev);
2251         gfx_v9_4_3_set_gds_init(adev);
2252         gfx_v9_4_3_set_rlc_funcs(adev);
2253
2254         /* init rlcg reg access ctrl */
2255         gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev);
2256
2257         return gfx_v9_4_3_init_microcode(adev);
2258 }
2259
2260 static int gfx_v9_4_3_late_init(void *handle)
2261 {
2262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2263         int r;
2264
2265         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2266         if (r)
2267                 return r;
2268
2269         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2270         if (r)
2271                 return r;
2272
2273         if (adev->gfx.ras &&
2274             adev->gfx.ras->enable_watchdog_timer)
2275                 adev->gfx.ras->enable_watchdog_timer(adev);
2276
2277         return 0;
2278 }
2279
2280 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev,
2281                                             bool enable, int xcc_id)
2282 {
2283         uint32_t def, data;
2284
2285         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
2286                 return;
2287
2288         def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2289                                   regRLC_CGTT_MGCG_OVERRIDE);
2290
2291         if (enable)
2292                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2293         else
2294                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2295
2296         if (def != data)
2297                 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2298                              regRLC_CGTT_MGCG_OVERRIDE, data);
2299
2300 }
2301
2302 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev,
2303                                                 bool enable, int xcc_id)
2304 {
2305         uint32_t def, data;
2306
2307         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
2308                 return;
2309
2310         def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2311                                   regRLC_CGTT_MGCG_OVERRIDE);
2312
2313         if (enable)
2314                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2315         else
2316                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2317
2318         if (def != data)
2319                 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2320                              regRLC_CGTT_MGCG_OVERRIDE, data);
2321 }
2322
2323 static void
2324 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2325                                                 bool enable, int xcc_id)
2326 {
2327         uint32_t data, def;
2328
2329         /* It is disabled by HW by default */
2330         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2331                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2332                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2333
2334                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2335                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2336                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2337                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2338
2339                 if (def != data)
2340                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2341
2342                 /* MGLS is a global flag to control all MGLS in GFX */
2343                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2344                         /* 2 - RLC memory Light sleep */
2345                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2346                                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2347                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2348                                 if (def != data)
2349                                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2350                         }
2351                         /* 3 - CP memory Light sleep */
2352                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2353                                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2354                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2355                                 if (def != data)
2356                                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2357                         }
2358                 }
2359         } else {
2360                 /* 1 - MGCG_OVERRIDE */
2361                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2362
2363                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2364                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2365                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2366                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2367
2368                 if (def != data)
2369                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2370
2371                 /* 2 - disable MGLS in RLC */
2372                 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2373                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2374                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2375                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2376                 }
2377
2378                 /* 3 - disable MGLS in CP */
2379                 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2380                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2381                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2382                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2383                 }
2384         }
2385
2386 }
2387
2388 static void
2389 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2390                                                 bool enable, int xcc_id)
2391 {
2392         uint32_t def, data;
2393
2394         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2395
2396                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2397                 /* unset CGCG override */
2398                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2399                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2400                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2401                 else
2402                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2403                 /* update CGCG and CGLS override bits */
2404                 if (def != data)
2405                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2406
2407                 /* CGCG Hysteresis: 400us */
2408                 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2409
2410                 data = (0x2710
2411                         << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2412                        RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2413                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2414                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2415                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2416                 if (def != data)
2417                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2418
2419                 /* set IDLE_POLL_COUNT(0x33450100)*/
2420                 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);
2421                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2422                         (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2423                 if (def != data)
2424                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);
2425         } else {
2426                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2427                 /* reset CGCG/CGLS bits */
2428                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2429                 /* disable cgcg and cgls in FSM */
2430                 if (def != data)
2431                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2432         }
2433
2434 }
2435
2436 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev,
2437                                                   bool enable, int xcc_id)
2438 {
2439         amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
2440
2441         if (enable) {
2442                 /* FGCG */
2443                 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2444                 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2445
2446                 /* CGCG/CGLS should be enabled after MGCG/MGLS
2447                  * ===  MGCG + MGLS ===
2448                  */
2449                 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2450                                                                 xcc_id);
2451                 /* ===  CGCG + CGLS === */
2452                 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2453                                                                 xcc_id);
2454         } else {
2455                 /* CGCG/CGLS should be disabled before MGCG/MGLS
2456                  * ===  CGCG + CGLS ===
2457                  */
2458                 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2459                                                                 xcc_id);
2460                 /* ===  MGCG + MGLS === */
2461                 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2462                                                                 xcc_id);
2463
2464                 /* FGCG */
2465                 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2466                 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2467         }
2468
2469         amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
2470
2471         return 0;
2472 }
2473
2474 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
2475         .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
2476         .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode,
2477         .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode,
2478         .init = gfx_v9_4_3_rlc_init,
2479         .resume = gfx_v9_4_3_rlc_resume,
2480         .stop = gfx_v9_4_3_rlc_stop,
2481         .reset = gfx_v9_4_3_rlc_reset,
2482         .start = gfx_v9_4_3_rlc_start,
2483         .update_spm_vmid = gfx_v9_4_3_update_spm_vmid,
2484         .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
2485 };
2486
2487 static int gfx_v9_4_3_set_powergating_state(void *handle,
2488                                           enum amd_powergating_state state)
2489 {
2490         return 0;
2491 }
2492
2493 static int gfx_v9_4_3_set_clockgating_state(void *handle,
2494                                           enum amd_clockgating_state state)
2495 {
2496         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2497         int i, num_xcc;
2498
2499         if (amdgpu_sriov_vf(adev))
2500                 return 0;
2501
2502         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2503         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2504         case IP_VERSION(9, 4, 3):
2505                 for (i = 0; i < num_xcc; i++)
2506                         gfx_v9_4_3_xcc_update_gfx_clock_gating(
2507                                 adev, state == AMD_CG_STATE_GATE, i);
2508                 break;
2509         default:
2510                 break;
2511         }
2512         return 0;
2513 }
2514
2515 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags)
2516 {
2517         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2518         int data;
2519
2520         if (amdgpu_sriov_vf(adev))
2521                 *flags = 0;
2522
2523         /* AMD_CG_SUPPORT_GFX_MGCG */
2524         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));
2525         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2526                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2527
2528         /* AMD_CG_SUPPORT_GFX_CGCG */
2529         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));
2530         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2531                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2532
2533         /* AMD_CG_SUPPORT_GFX_CGLS */
2534         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2535                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2536
2537         /* AMD_CG_SUPPORT_GFX_RLC_LS */
2538         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));
2539         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2540                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2541
2542         /* AMD_CG_SUPPORT_GFX_CP_LS */
2543         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));
2544         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2545                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2546 }
2547
2548 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2549 {
2550         struct amdgpu_device *adev = ring->adev;
2551         u32 ref_and_mask, reg_mem_engine;
2552         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
2553
2554         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2555                 switch (ring->me) {
2556                 case 1:
2557                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2558                         break;
2559                 case 2:
2560                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2561                         break;
2562                 default:
2563                         return;
2564                 }
2565                 reg_mem_engine = 0;
2566         } else {
2567                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2568                 reg_mem_engine = 1; /* pfp */
2569         }
2570
2571         gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2572                               adev->nbio.funcs->get_hdp_flush_req_offset(adev),
2573                               adev->nbio.funcs->get_hdp_flush_done_offset(adev),
2574                               ref_and_mask, ref_and_mask, 0x20);
2575 }
2576
2577 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring,
2578                                           struct amdgpu_job *job,
2579                                           struct amdgpu_ib *ib,
2580                                           uint32_t flags)
2581 {
2582         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2583         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2584
2585         /* Currently, there is a high possibility to get wave ID mismatch
2586          * between ME and GDS, leading to a hw deadlock, because ME generates
2587          * different wave IDs than the GDS expects. This situation happens
2588          * randomly when at least 5 compute pipes use GDS ordered append.
2589          * The wave IDs generated by ME are also wrong after suspend/resume.
2590          * Those are probably bugs somewhere else in the kernel driver.
2591          *
2592          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2593          * GDS to 0 for this ring (me/pipe).
2594          */
2595         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2596                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2597                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
2598                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2599         }
2600
2601         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2602         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2603         amdgpu_ring_write(ring,
2604 #ifdef __BIG_ENDIAN
2605                                 (2 << 0) |
2606 #endif
2607                                 lower_32_bits(ib->gpu_addr));
2608         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2609         amdgpu_ring_write(ring, control);
2610 }
2611
2612 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2613                                      u64 seq, unsigned flags)
2614 {
2615         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2616         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2617         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
2618
2619         /* RELEASE_MEM - flush caches, send int */
2620         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2621         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
2622                                                EOP_TC_NC_ACTION_EN) :
2623                                               (EOP_TCL1_ACTION_EN |
2624                                                EOP_TC_ACTION_EN |
2625                                                EOP_TC_WB_ACTION_EN |
2626                                                EOP_TC_MD_ACTION_EN)) |
2627                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2628                                  EVENT_INDEX(5)));
2629         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2630
2631         /*
2632          * the address should be Qword aligned if 64bit write, Dword
2633          * aligned if only send 32bit data low (discard data high)
2634          */
2635         if (write64bit)
2636                 BUG_ON(addr & 0x7);
2637         else
2638                 BUG_ON(addr & 0x3);
2639         amdgpu_ring_write(ring, lower_32_bits(addr));
2640         amdgpu_ring_write(ring, upper_32_bits(addr));
2641         amdgpu_ring_write(ring, lower_32_bits(seq));
2642         amdgpu_ring_write(ring, upper_32_bits(seq));
2643         amdgpu_ring_write(ring, 0);
2644 }
2645
2646 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2647 {
2648         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2649         uint32_t seq = ring->fence_drv.sync_seq;
2650         uint64_t addr = ring->fence_drv.gpu_addr;
2651
2652         gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0,
2653                               lower_32_bits(addr), upper_32_bits(addr),
2654                               seq, 0xffffffff, 4);
2655 }
2656
2657 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring,
2658                                         unsigned vmid, uint64_t pd_addr)
2659 {
2660         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2661 }
2662
2663 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring)
2664 {
2665         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2666 }
2667
2668 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring)
2669 {
2670         u64 wptr;
2671
2672         /* XXX check if swapping is necessary on BE */
2673         if (ring->use_doorbell)
2674                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2675         else
2676                 BUG();
2677         return wptr;
2678 }
2679
2680 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring)
2681 {
2682         struct amdgpu_device *adev = ring->adev;
2683
2684         /* XXX check if swapping is necessary on BE */
2685         if (ring->use_doorbell) {
2686                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2687                 WDOORBELL64(ring->doorbell_index, ring->wptr);
2688         } else {
2689                 BUG(); /* only DOORBELL method supported on gfx9 now */
2690         }
2691 }
2692
2693 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
2694                                          u64 seq, unsigned int flags)
2695 {
2696         struct amdgpu_device *adev = ring->adev;
2697
2698         /* we only allocate 32bit for each seq wb address */
2699         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
2700
2701         /* write fence seq to the "addr" */
2702         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2703         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2704                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
2705         amdgpu_ring_write(ring, lower_32_bits(addr));
2706         amdgpu_ring_write(ring, upper_32_bits(addr));
2707         amdgpu_ring_write(ring, lower_32_bits(seq));
2708
2709         if (flags & AMDGPU_FENCE_FLAG_INT) {
2710                 /* set register to trigger INT */
2711                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2712                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2713                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
2714                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
2715                 amdgpu_ring_write(ring, 0);
2716                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
2717         }
2718 }
2719
2720 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
2721                                     uint32_t reg_val_offs)
2722 {
2723         struct amdgpu_device *adev = ring->adev;
2724
2725         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
2726         amdgpu_ring_write(ring, 0 |     /* src: register*/
2727                                 (5 << 8) |      /* dst: memory */
2728                                 (1 << 20));     /* write confirm */
2729         amdgpu_ring_write(ring, reg);
2730         amdgpu_ring_write(ring, 0);
2731         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
2732                                 reg_val_offs * 4));
2733         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
2734                                 reg_val_offs * 4));
2735 }
2736
2737 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
2738                                     uint32_t val)
2739 {
2740         uint32_t cmd = 0;
2741
2742         switch (ring->funcs->type) {
2743         case AMDGPU_RING_TYPE_GFX:
2744                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
2745                 break;
2746         case AMDGPU_RING_TYPE_KIQ:
2747                 cmd = (1 << 16); /* no inc addr */
2748                 break;
2749         default:
2750                 cmd = WR_CONFIRM;
2751                 break;
2752         }
2753         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2754         amdgpu_ring_write(ring, cmd);
2755         amdgpu_ring_write(ring, reg);
2756         amdgpu_ring_write(ring, 0);
2757         amdgpu_ring_write(ring, val);
2758 }
2759
2760 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
2761                                         uint32_t val, uint32_t mask)
2762 {
2763         gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
2764 }
2765
2766 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
2767                                                   uint32_t reg0, uint32_t reg1,
2768                                                   uint32_t ref, uint32_t mask)
2769 {
2770         amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
2771                                                    ref, mask);
2772 }
2773
2774 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2775         struct amdgpu_device *adev, int me, int pipe,
2776         enum amdgpu_interrupt_state state, int xcc_id)
2777 {
2778         u32 mec_int_cntl, mec_int_cntl_reg;
2779
2780         /*
2781          * amdgpu controls only the first MEC. That's why this function only
2782          * handles the setting of interrupts for this specific MEC. All other
2783          * pipes' interrupts are set by amdkfd.
2784          */
2785
2786         if (me == 1) {
2787                 switch (pipe) {
2788                 case 0:
2789                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
2790                         break;
2791                 case 1:
2792                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
2793                         break;
2794                 case 2:
2795                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
2796                         break;
2797                 case 3:
2798                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
2799                         break;
2800                 default:
2801                         DRM_DEBUG("invalid pipe %d\n", pipe);
2802                         return;
2803                 }
2804         } else {
2805                 DRM_DEBUG("invalid me %d\n", me);
2806                 return;
2807         }
2808
2809         switch (state) {
2810         case AMDGPU_IRQ_STATE_DISABLE:
2811                 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id);
2812                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2813                                              TIME_STAMP_INT_ENABLE, 0);
2814                 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
2815                 break;
2816         case AMDGPU_IRQ_STATE_ENABLE:
2817                 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id);
2818                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2819                                              TIME_STAMP_INT_ENABLE, 1);
2820                 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
2821                 break;
2822         default:
2823                 break;
2824         }
2825 }
2826
2827 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
2828                                              struct amdgpu_irq_src *source,
2829                                              unsigned type,
2830                                              enum amdgpu_interrupt_state state)
2831 {
2832         int i, num_xcc;
2833
2834         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2835         switch (state) {
2836         case AMDGPU_IRQ_STATE_DISABLE:
2837         case AMDGPU_IRQ_STATE_ENABLE:
2838                 for (i = 0; i < num_xcc; i++)
2839                         WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2840                                 PRIV_REG_INT_ENABLE,
2841                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2842                 break;
2843         default:
2844                 break;
2845         }
2846
2847         return 0;
2848 }
2849
2850 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
2851                                               struct amdgpu_irq_src *source,
2852                                               unsigned type,
2853                                               enum amdgpu_interrupt_state state)
2854 {
2855         int i, num_xcc;
2856
2857         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2858         switch (state) {
2859         case AMDGPU_IRQ_STATE_DISABLE:
2860         case AMDGPU_IRQ_STATE_ENABLE:
2861                 for (i = 0; i < num_xcc; i++)
2862                         WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2863                                 PRIV_INSTR_INT_ENABLE,
2864                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2865                 break;
2866         default:
2867                 break;
2868         }
2869
2870         return 0;
2871 }
2872
2873 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev,
2874                                             struct amdgpu_irq_src *src,
2875                                             unsigned type,
2876                                             enum amdgpu_interrupt_state state)
2877 {
2878         int i, num_xcc;
2879
2880         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2881         for (i = 0; i < num_xcc; i++) {
2882                 switch (type) {
2883                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
2884                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2885                                 adev, 1, 0, state, i);
2886                         break;
2887                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
2888                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2889                                 adev, 1, 1, state, i);
2890                         break;
2891                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
2892                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2893                                 adev, 1, 2, state, i);
2894                         break;
2895                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
2896                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2897                                 adev, 1, 3, state, i);
2898                         break;
2899                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
2900                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2901                                 adev, 2, 0, state, i);
2902                         break;
2903                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
2904                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2905                                 adev, 2, 1, state, i);
2906                         break;
2907                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
2908                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2909                                 adev, 2, 2, state, i);
2910                         break;
2911                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
2912                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2913                                 adev, 2, 3, state, i);
2914                         break;
2915                 default:
2916                         break;
2917                 }
2918         }
2919
2920         return 0;
2921 }
2922
2923 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev,
2924                             struct amdgpu_irq_src *source,
2925                             struct amdgpu_iv_entry *entry)
2926 {
2927         int i, xcc_id;
2928         u8 me_id, pipe_id, queue_id;
2929         struct amdgpu_ring *ring;
2930
2931         DRM_DEBUG("IH: CP EOP\n");
2932         me_id = (entry->ring_id & 0x0c) >> 2;
2933         pipe_id = (entry->ring_id & 0x03) >> 0;
2934         queue_id = (entry->ring_id & 0x70) >> 4;
2935
2936         xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2937
2938         if (xcc_id == -EINVAL)
2939                 return -EINVAL;
2940
2941         switch (me_id) {
2942         case 0:
2943         case 1:
2944         case 2:
2945                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2946                         ring = &adev->gfx.compute_ring
2947                                         [i +
2948                                          xcc_id * adev->gfx.num_compute_rings];
2949                         /* Per-queue interrupt is supported for MEC starting from VI.
2950                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
2951                           */
2952
2953                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2954                                 amdgpu_fence_process(ring);
2955                 }
2956                 break;
2957         }
2958         return 0;
2959 }
2960
2961 static void gfx_v9_4_3_fault(struct amdgpu_device *adev,
2962                            struct amdgpu_iv_entry *entry)
2963 {
2964         u8 me_id, pipe_id, queue_id;
2965         struct amdgpu_ring *ring;
2966         int i, xcc_id;
2967
2968         me_id = (entry->ring_id & 0x0c) >> 2;
2969         pipe_id = (entry->ring_id & 0x03) >> 0;
2970         queue_id = (entry->ring_id & 0x70) >> 4;
2971
2972         xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2973
2974         if (xcc_id == -EINVAL)
2975                 return;
2976
2977         switch (me_id) {
2978         case 0:
2979         case 1:
2980         case 2:
2981                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2982                         ring = &adev->gfx.compute_ring
2983                                         [i +
2984                                          xcc_id * adev->gfx.num_compute_rings];
2985                         if (ring->me == me_id && ring->pipe == pipe_id &&
2986                             ring->queue == queue_id)
2987                                 drm_sched_fault(&ring->sched);
2988                 }
2989                 break;
2990         }
2991 }
2992
2993 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
2994                                  struct amdgpu_irq_src *source,
2995                                  struct amdgpu_iv_entry *entry)
2996 {
2997         DRM_ERROR("Illegal register access in command stream\n");
2998         gfx_v9_4_3_fault(adev, entry);
2999         return 0;
3000 }
3001
3002 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
3003                                   struct amdgpu_irq_src *source,
3004                                   struct amdgpu_iv_entry *entry)
3005 {
3006         DRM_ERROR("Illegal instruction in command stream\n");
3007         gfx_v9_4_3_fault(adev, entry);
3008         return 0;
3009 }
3010
3011 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring)
3012 {
3013         const unsigned int cp_coher_cntl =
3014                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
3015                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
3016                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
3017                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
3018                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
3019
3020         /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
3021         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
3022         amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
3023         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
3024         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
3025         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
3026         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
3027         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
3028 }
3029
3030 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring,
3031                                         uint32_t pipe, bool enable)
3032 {
3033         struct amdgpu_device *adev = ring->adev;
3034         uint32_t val;
3035         uint32_t wcl_cs_reg;
3036
3037         /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
3038         val = enable ? 0x1 : 0x7f;
3039
3040         switch (pipe) {
3041         case 0:
3042                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);
3043                 break;
3044         case 1:
3045                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);
3046                 break;
3047         case 2:
3048                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);
3049                 break;
3050         case 3:
3051                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);
3052                 break;
3053         default:
3054                 DRM_DEBUG("invalid pipe %d\n", pipe);
3055                 return;
3056         }
3057
3058         amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
3059
3060 }
3061 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
3062 {
3063         struct amdgpu_device *adev = ring->adev;
3064         uint32_t val;
3065         int i;
3066
3067         /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
3068          * number of gfx waves. Setting 5 bit will make sure gfx only gets
3069          * around 25% of gpu resources.
3070          */
3071         val = enable ? 0x1f : 0x07ffffff;
3072         amdgpu_ring_emit_wreg(ring,
3073                               SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),
3074                               val);
3075
3076         /* Restrict waves for normal/low priority compute queues as well
3077          * to get best QoS for high priority compute jobs.
3078          *
3079          * amdgpu controls only 1st ME(0-3 CS pipes).
3080          */
3081         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3082                 if (i != ring->pipe)
3083                         gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable);
3084
3085         }
3086 }
3087
3088 enum amdgpu_gfx_cp_ras_mem_id {
3089         AMDGPU_GFX_CP_MEM1 = 1,
3090         AMDGPU_GFX_CP_MEM2,
3091         AMDGPU_GFX_CP_MEM3,
3092         AMDGPU_GFX_CP_MEM4,
3093         AMDGPU_GFX_CP_MEM5,
3094 };
3095
3096 enum amdgpu_gfx_gcea_ras_mem_id {
3097         AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4,
3098         AMDGPU_GFX_GCEA_IORD_CMDMEM,
3099         AMDGPU_GFX_GCEA_GMIWR_CMDMEM,
3100         AMDGPU_GFX_GCEA_GMIRD_CMDMEM,
3101         AMDGPU_GFX_GCEA_DRAMWR_CMDMEM,
3102         AMDGPU_GFX_GCEA_DRAMRD_CMDMEM,
3103         AMDGPU_GFX_GCEA_MAM_DMEM0,
3104         AMDGPU_GFX_GCEA_MAM_DMEM1,
3105         AMDGPU_GFX_GCEA_MAM_DMEM2,
3106         AMDGPU_GFX_GCEA_MAM_DMEM3,
3107         AMDGPU_GFX_GCEA_MAM_AMEM0,
3108         AMDGPU_GFX_GCEA_MAM_AMEM1,
3109         AMDGPU_GFX_GCEA_MAM_AMEM2,
3110         AMDGPU_GFX_GCEA_MAM_AMEM3,
3111         AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER,
3112         AMDGPU_GFX_GCEA_WRET_TAGMEM,
3113         AMDGPU_GFX_GCEA_RRET_TAGMEM,
3114         AMDGPU_GFX_GCEA_IOWR_DATAMEM,
3115         AMDGPU_GFX_GCEA_GMIWR_DATAMEM,
3116         AMDGPU_GFX_GCEA_DRAM_DATAMEM,
3117 };
3118
3119 enum amdgpu_gfx_gc_cane_ras_mem_id {
3120         AMDGPU_GFX_GC_CANE_MEM0 = 0,
3121 };
3122
3123 enum amdgpu_gfx_gcutcl2_ras_mem_id {
3124         AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160,
3125 };
3126
3127 enum amdgpu_gfx_gds_ras_mem_id {
3128         AMDGPU_GFX_GDS_MEM0 = 0,
3129 };
3130
3131 enum amdgpu_gfx_lds_ras_mem_id {
3132         AMDGPU_GFX_LDS_BANK0 = 0,
3133         AMDGPU_GFX_LDS_BANK1,
3134         AMDGPU_GFX_LDS_BANK2,
3135         AMDGPU_GFX_LDS_BANK3,
3136         AMDGPU_GFX_LDS_BANK4,
3137         AMDGPU_GFX_LDS_BANK5,
3138         AMDGPU_GFX_LDS_BANK6,
3139         AMDGPU_GFX_LDS_BANK7,
3140         AMDGPU_GFX_LDS_BANK8,
3141         AMDGPU_GFX_LDS_BANK9,
3142         AMDGPU_GFX_LDS_BANK10,
3143         AMDGPU_GFX_LDS_BANK11,
3144         AMDGPU_GFX_LDS_BANK12,
3145         AMDGPU_GFX_LDS_BANK13,
3146         AMDGPU_GFX_LDS_BANK14,
3147         AMDGPU_GFX_LDS_BANK15,
3148         AMDGPU_GFX_LDS_BANK16,
3149         AMDGPU_GFX_LDS_BANK17,
3150         AMDGPU_GFX_LDS_BANK18,
3151         AMDGPU_GFX_LDS_BANK19,
3152         AMDGPU_GFX_LDS_BANK20,
3153         AMDGPU_GFX_LDS_BANK21,
3154         AMDGPU_GFX_LDS_BANK22,
3155         AMDGPU_GFX_LDS_BANK23,
3156         AMDGPU_GFX_LDS_BANK24,
3157         AMDGPU_GFX_LDS_BANK25,
3158         AMDGPU_GFX_LDS_BANK26,
3159         AMDGPU_GFX_LDS_BANK27,
3160         AMDGPU_GFX_LDS_BANK28,
3161         AMDGPU_GFX_LDS_BANK29,
3162         AMDGPU_GFX_LDS_BANK30,
3163         AMDGPU_GFX_LDS_BANK31,
3164         AMDGPU_GFX_LDS_SP_BUFFER_A,
3165         AMDGPU_GFX_LDS_SP_BUFFER_B,
3166 };
3167
3168 enum amdgpu_gfx_rlc_ras_mem_id {
3169         AMDGPU_GFX_RLC_GPMF32 = 1,
3170         AMDGPU_GFX_RLC_RLCVF32,
3171         AMDGPU_GFX_RLC_SCRATCH,
3172         AMDGPU_GFX_RLC_SRM_ARAM,
3173         AMDGPU_GFX_RLC_SRM_DRAM,
3174         AMDGPU_GFX_RLC_TCTAG,
3175         AMDGPU_GFX_RLC_SPM_SE,
3176         AMDGPU_GFX_RLC_SPM_GRBMT,
3177 };
3178
3179 enum amdgpu_gfx_sp_ras_mem_id {
3180         AMDGPU_GFX_SP_SIMDID0 = 0,
3181 };
3182
3183 enum amdgpu_gfx_spi_ras_mem_id {
3184         AMDGPU_GFX_SPI_MEM0 = 0,
3185         AMDGPU_GFX_SPI_MEM1,
3186         AMDGPU_GFX_SPI_MEM2,
3187         AMDGPU_GFX_SPI_MEM3,
3188 };
3189
3190 enum amdgpu_gfx_sqc_ras_mem_id {
3191         AMDGPU_GFX_SQC_INST_CACHE_A = 100,
3192         AMDGPU_GFX_SQC_INST_CACHE_B = 101,
3193         AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102,
3194         AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103,
3195         AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104,
3196         AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105,
3197         AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106,
3198         AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107,
3199         AMDGPU_GFX_SQC_DATA_CACHE_A = 200,
3200         AMDGPU_GFX_SQC_DATA_CACHE_B = 201,
3201         AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202,
3202         AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203,
3203         AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204,
3204         AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205,
3205         AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206,
3206         AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207,
3207         AMDGPU_GFX_SQC_DIRTY_BIT_A = 208,
3208         AMDGPU_GFX_SQC_DIRTY_BIT_B = 209,
3209         AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210,
3210         AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211,
3211         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212,
3212         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213,
3213         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108,
3214 };
3215
3216 enum amdgpu_gfx_sq_ras_mem_id {
3217         AMDGPU_GFX_SQ_SGPR_MEM0 = 0,
3218         AMDGPU_GFX_SQ_SGPR_MEM1,
3219         AMDGPU_GFX_SQ_SGPR_MEM2,
3220         AMDGPU_GFX_SQ_SGPR_MEM3,
3221 };
3222
3223 enum amdgpu_gfx_ta_ras_mem_id {
3224         AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1,
3225         AMDGPU_GFX_TA_FS_AFIFO_RAM_HI,
3226         AMDGPU_GFX_TA_FS_CFIFO_RAM,
3227         AMDGPU_GFX_TA_FSX_LFIFO,
3228         AMDGPU_GFX_TA_FS_DFIFO_RAM,
3229 };
3230
3231 enum amdgpu_gfx_tcc_ras_mem_id {
3232         AMDGPU_GFX_TCC_MEM1 = 1,
3233 };
3234
3235 enum amdgpu_gfx_tca_ras_mem_id {
3236         AMDGPU_GFX_TCA_MEM1 = 1,
3237 };
3238
3239 enum amdgpu_gfx_tci_ras_mem_id {
3240         AMDGPU_GFX_TCIW_MEM = 1,
3241 };
3242
3243 enum amdgpu_gfx_tcp_ras_mem_id {
3244         AMDGPU_GFX_TCP_LFIFO0 = 1,
3245         AMDGPU_GFX_TCP_SET0BANK0_RAM,
3246         AMDGPU_GFX_TCP_SET0BANK1_RAM,
3247         AMDGPU_GFX_TCP_SET0BANK2_RAM,
3248         AMDGPU_GFX_TCP_SET0BANK3_RAM,
3249         AMDGPU_GFX_TCP_SET1BANK0_RAM,
3250         AMDGPU_GFX_TCP_SET1BANK1_RAM,
3251         AMDGPU_GFX_TCP_SET1BANK2_RAM,
3252         AMDGPU_GFX_TCP_SET1BANK3_RAM,
3253         AMDGPU_GFX_TCP_SET2BANK0_RAM,
3254         AMDGPU_GFX_TCP_SET2BANK1_RAM,
3255         AMDGPU_GFX_TCP_SET2BANK2_RAM,
3256         AMDGPU_GFX_TCP_SET2BANK3_RAM,
3257         AMDGPU_GFX_TCP_SET3BANK0_RAM,
3258         AMDGPU_GFX_TCP_SET3BANK1_RAM,
3259         AMDGPU_GFX_TCP_SET3BANK2_RAM,
3260         AMDGPU_GFX_TCP_SET3BANK3_RAM,
3261         AMDGPU_GFX_TCP_VM_FIFO,
3262         AMDGPU_GFX_TCP_DB_TAGRAM0,
3263         AMDGPU_GFX_TCP_DB_TAGRAM1,
3264         AMDGPU_GFX_TCP_DB_TAGRAM2,
3265         AMDGPU_GFX_TCP_DB_TAGRAM3,
3266         AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0,
3267         AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1,
3268         AMDGPU_GFX_TCP_CMD_FIFO,
3269 };
3270
3271 enum amdgpu_gfx_td_ras_mem_id {
3272         AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1,
3273         AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM,
3274         AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM,
3275 };
3276
3277 enum amdgpu_gfx_tcx_ras_mem_id {
3278         AMDGPU_GFX_TCX_FIFOD0 = 0,
3279         AMDGPU_GFX_TCX_FIFOD1,
3280         AMDGPU_GFX_TCX_FIFOD2,
3281         AMDGPU_GFX_TCX_FIFOD3,
3282         AMDGPU_GFX_TCX_FIFOD4,
3283         AMDGPU_GFX_TCX_FIFOD5,
3284         AMDGPU_GFX_TCX_FIFOD6,
3285         AMDGPU_GFX_TCX_FIFOD7,
3286         AMDGPU_GFX_TCX_FIFOB0,
3287         AMDGPU_GFX_TCX_FIFOB1,
3288         AMDGPU_GFX_TCX_FIFOB2,
3289         AMDGPU_GFX_TCX_FIFOB3,
3290         AMDGPU_GFX_TCX_FIFOB4,
3291         AMDGPU_GFX_TCX_FIFOB5,
3292         AMDGPU_GFX_TCX_FIFOB6,
3293         AMDGPU_GFX_TCX_FIFOB7,
3294         AMDGPU_GFX_TCX_FIFOA0,
3295         AMDGPU_GFX_TCX_FIFOA1,
3296         AMDGPU_GFX_TCX_FIFOA2,
3297         AMDGPU_GFX_TCX_FIFOA3,
3298         AMDGPU_GFX_TCX_FIFOA4,
3299         AMDGPU_GFX_TCX_FIFOA5,
3300         AMDGPU_GFX_TCX_FIFOA6,
3301         AMDGPU_GFX_TCX_FIFOA7,
3302         AMDGPU_GFX_TCX_CFIFO0,
3303         AMDGPU_GFX_TCX_CFIFO1,
3304         AMDGPU_GFX_TCX_CFIFO2,
3305         AMDGPU_GFX_TCX_CFIFO3,
3306         AMDGPU_GFX_TCX_CFIFO4,
3307         AMDGPU_GFX_TCX_CFIFO5,
3308         AMDGPU_GFX_TCX_CFIFO6,
3309         AMDGPU_GFX_TCX_CFIFO7,
3310         AMDGPU_GFX_TCX_FIFO_ACKB0,
3311         AMDGPU_GFX_TCX_FIFO_ACKB1,
3312         AMDGPU_GFX_TCX_FIFO_ACKB2,
3313         AMDGPU_GFX_TCX_FIFO_ACKB3,
3314         AMDGPU_GFX_TCX_FIFO_ACKB4,
3315         AMDGPU_GFX_TCX_FIFO_ACKB5,
3316         AMDGPU_GFX_TCX_FIFO_ACKB6,
3317         AMDGPU_GFX_TCX_FIFO_ACKB7,
3318         AMDGPU_GFX_TCX_FIFO_ACKD0,
3319         AMDGPU_GFX_TCX_FIFO_ACKD1,
3320         AMDGPU_GFX_TCX_FIFO_ACKD2,
3321         AMDGPU_GFX_TCX_FIFO_ACKD3,
3322         AMDGPU_GFX_TCX_FIFO_ACKD4,
3323         AMDGPU_GFX_TCX_FIFO_ACKD5,
3324         AMDGPU_GFX_TCX_FIFO_ACKD6,
3325         AMDGPU_GFX_TCX_FIFO_ACKD7,
3326         AMDGPU_GFX_TCX_DST_FIFOA0,
3327         AMDGPU_GFX_TCX_DST_FIFOA1,
3328         AMDGPU_GFX_TCX_DST_FIFOA2,
3329         AMDGPU_GFX_TCX_DST_FIFOA3,
3330         AMDGPU_GFX_TCX_DST_FIFOA4,
3331         AMDGPU_GFX_TCX_DST_FIFOA5,
3332         AMDGPU_GFX_TCX_DST_FIFOA6,
3333         AMDGPU_GFX_TCX_DST_FIFOA7,
3334         AMDGPU_GFX_TCX_DST_FIFOB0,
3335         AMDGPU_GFX_TCX_DST_FIFOB1,
3336         AMDGPU_GFX_TCX_DST_FIFOB2,
3337         AMDGPU_GFX_TCX_DST_FIFOB3,
3338         AMDGPU_GFX_TCX_DST_FIFOB4,
3339         AMDGPU_GFX_TCX_DST_FIFOB5,
3340         AMDGPU_GFX_TCX_DST_FIFOB6,
3341         AMDGPU_GFX_TCX_DST_FIFOB7,
3342         AMDGPU_GFX_TCX_DST_FIFOD0,
3343         AMDGPU_GFX_TCX_DST_FIFOD1,
3344         AMDGPU_GFX_TCX_DST_FIFOD2,
3345         AMDGPU_GFX_TCX_DST_FIFOD3,
3346         AMDGPU_GFX_TCX_DST_FIFOD4,
3347         AMDGPU_GFX_TCX_DST_FIFOD5,
3348         AMDGPU_GFX_TCX_DST_FIFOD6,
3349         AMDGPU_GFX_TCX_DST_FIFOD7,
3350         AMDGPU_GFX_TCX_DST_FIFO_ACKB0,
3351         AMDGPU_GFX_TCX_DST_FIFO_ACKB1,
3352         AMDGPU_GFX_TCX_DST_FIFO_ACKB2,
3353         AMDGPU_GFX_TCX_DST_FIFO_ACKB3,
3354         AMDGPU_GFX_TCX_DST_FIFO_ACKB4,
3355         AMDGPU_GFX_TCX_DST_FIFO_ACKB5,
3356         AMDGPU_GFX_TCX_DST_FIFO_ACKB6,
3357         AMDGPU_GFX_TCX_DST_FIFO_ACKB7,
3358         AMDGPU_GFX_TCX_DST_FIFO_ACKD0,
3359         AMDGPU_GFX_TCX_DST_FIFO_ACKD1,
3360         AMDGPU_GFX_TCX_DST_FIFO_ACKD2,
3361         AMDGPU_GFX_TCX_DST_FIFO_ACKD3,
3362         AMDGPU_GFX_TCX_DST_FIFO_ACKD4,
3363         AMDGPU_GFX_TCX_DST_FIFO_ACKD5,
3364         AMDGPU_GFX_TCX_DST_FIFO_ACKD6,
3365         AMDGPU_GFX_TCX_DST_FIFO_ACKD7,
3366 };
3367
3368 enum amdgpu_gfx_atc_l2_ras_mem_id {
3369         AMDGPU_GFX_ATC_L2_MEM0 = 0,
3370 };
3371
3372 enum amdgpu_gfx_utcl2_ras_mem_id {
3373         AMDGPU_GFX_UTCL2_MEM0 = 0,
3374 };
3375
3376 enum amdgpu_gfx_vml2_ras_mem_id {
3377         AMDGPU_GFX_VML2_MEM0 = 0,
3378 };
3379
3380 enum amdgpu_gfx_vml2_walker_ras_mem_id {
3381         AMDGPU_GFX_VML2_WALKER_MEM0 = 0,
3382 };
3383
3384 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = {
3385         {AMDGPU_GFX_CP_MEM1, "CP_MEM1"},
3386         {AMDGPU_GFX_CP_MEM2, "CP_MEM2"},
3387         {AMDGPU_GFX_CP_MEM3, "CP_MEM3"},
3388         {AMDGPU_GFX_CP_MEM4, "CP_MEM4"},
3389         {AMDGPU_GFX_CP_MEM5, "CP_MEM5"},
3390 };
3391
3392 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = {
3393         {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"},
3394         {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"},
3395         {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"},
3396         {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"},
3397         {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"},
3398         {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"},
3399         {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"},
3400         {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"},
3401         {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"},
3402         {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"},
3403         {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"},
3404         {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"},
3405         {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"},
3406         {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"},
3407         {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"},
3408         {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"},
3409         {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"},
3410         {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"},
3411         {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"},
3412         {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"},
3413 };
3414
3415 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = {
3416         {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"},
3417 };
3418
3419 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = {
3420         {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"},
3421 };
3422
3423 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = {
3424         {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"},
3425 };
3426
3427 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = {
3428         {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"},
3429         {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"},
3430         {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"},
3431         {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"},
3432         {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"},
3433         {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"},
3434         {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"},
3435         {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"},
3436         {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"},
3437         {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"},
3438         {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"},
3439         {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"},
3440         {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"},
3441         {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"},
3442         {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"},
3443         {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"},
3444         {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"},
3445         {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"},
3446         {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"},
3447         {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"},
3448         {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"},
3449         {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"},
3450         {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"},
3451         {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"},
3452         {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"},
3453         {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"},
3454         {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"},
3455         {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"},
3456         {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"},
3457         {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"},
3458         {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"},
3459         {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"},
3460         {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"},
3461         {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"},
3462 };
3463
3464 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = {
3465         {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"},
3466         {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"},
3467         {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"},
3468         {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"},
3469         {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"},
3470         {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"},
3471         {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"},
3472         {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"},
3473 };
3474
3475 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = {
3476         {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"},
3477 };
3478
3479 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = {
3480         {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"},
3481         {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"},
3482         {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"},
3483         {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"},
3484 };
3485
3486 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = {
3487         {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"},
3488         {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"},
3489         {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"},
3490         {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"},
3491         {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"},
3492         {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"},
3493         {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"},
3494         {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"},
3495         {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"},
3496         {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"},
3497         {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"},
3498         {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"},
3499         {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"},
3500         {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"},
3501         {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"},
3502         {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"},
3503         {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"},
3504         {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"},
3505         {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"},
3506         {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"},
3507         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"},
3508         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"},
3509         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"},
3510 };
3511
3512 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = {
3513         {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"},
3514         {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"},
3515         {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"},
3516         {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"},
3517 };
3518
3519 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = {
3520         {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"},
3521         {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"},
3522         {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"},
3523         {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"},
3524         {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"},
3525 };
3526
3527 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = {
3528         {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"},
3529 };
3530
3531 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = {
3532         {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"},
3533 };
3534
3535 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = {
3536         {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"},
3537 };
3538
3539 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = {
3540         {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"},
3541         {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"},
3542         {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"},
3543         {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"},
3544         {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"},
3545         {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"},
3546         {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"},
3547         {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"},
3548         {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"},
3549         {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"},
3550         {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"},
3551         {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"},
3552         {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"},
3553         {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"},
3554         {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"},
3555         {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"},
3556         {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"},
3557         {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"},
3558         {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"},
3559         {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"},
3560         {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"},
3561         {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"},
3562         {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"},
3563         {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"},
3564         {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"},
3565 };
3566
3567 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = {
3568         {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"},
3569         {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"},
3570         {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"},
3571 };
3572
3573 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = {
3574         {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"},
3575         {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"},
3576         {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"},
3577         {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"},
3578         {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"},
3579         {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"},
3580         {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"},
3581         {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"},
3582         {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"},
3583         {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"},
3584         {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"},
3585         {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"},
3586         {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"},
3587         {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"},
3588         {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"},
3589         {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"},
3590         {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"},
3591         {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"},
3592         {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"},
3593         {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"},
3594         {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"},
3595         {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"},
3596         {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"},
3597         {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"},
3598         {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"},
3599         {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"},
3600         {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"},
3601         {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"},
3602         {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"},
3603         {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"},
3604         {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"},
3605         {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"},
3606         {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"},
3607         {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"},
3608         {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"},
3609         {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"},
3610         {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"},
3611         {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"},
3612         {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"},
3613         {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"},
3614         {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"},
3615         {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"},
3616         {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"},
3617         {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"},
3618         {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"},
3619         {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"},
3620         {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"},
3621         {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"},
3622         {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"},
3623         {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"},
3624         {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"},
3625         {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"},
3626         {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"},
3627         {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"},
3628         {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"},
3629         {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"},
3630         {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"},
3631         {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"},
3632         {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"},
3633         {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"},
3634         {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"},
3635         {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"},
3636         {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"},
3637         {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"},
3638         {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"},
3639         {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"},
3640         {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"},
3641         {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"},
3642         {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"},
3643         {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"},
3644         {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"},
3645         {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"},
3646         {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"},
3647         {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"},
3648         {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"},
3649         {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"},
3650         {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"},
3651         {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"},
3652         {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"},
3653         {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"},
3654         {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"},
3655         {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"},
3656         {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"},
3657         {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"},
3658         {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"},
3659         {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"},
3660         {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"},
3661         {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"},
3662 };
3663
3664 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = {
3665         {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"},
3666 };
3667
3668 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = {
3669         {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"},
3670 };
3671
3672 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = {
3673         {AMDGPU_GFX_VML2_MEM, "VML2_MEM"},
3674 };
3675
3676 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = {
3677         {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"},
3678 };
3679
3680 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = {
3681         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list)
3682         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list)
3683         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list)
3684         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list)
3685         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list)
3686         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list)
3687         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list)
3688         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list)
3689         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list)
3690         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list)
3691         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list)
3692         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list)
3693         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list)
3694         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list)
3695         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list)
3696         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list)
3697         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list)
3698         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list)
3699         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list)
3700         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list)
3701         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list)
3702         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list)
3703 };
3704
3705 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = {
3706         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH),
3707             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3708             AMDGPU_GFX_RLC_MEM, 1},
3709         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI),
3710             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3711             AMDGPU_GFX_CP_MEM, 1},
3712         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI),
3713             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3714             AMDGPU_GFX_CP_MEM, 1},
3715         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI),
3716             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3717             AMDGPU_GFX_CP_MEM, 1},
3718         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI),
3719             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3720             AMDGPU_GFX_GDS_MEM, 1},
3721         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI),
3722             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3723             AMDGPU_GFX_GC_CANE_MEM, 1},
3724         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI),
3725             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3726             AMDGPU_GFX_SPI_MEM, 1},
3727         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI),
3728             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3729             AMDGPU_GFX_SP_MEM, 4},
3730         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI),
3731             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3732             AMDGPU_GFX_SP_MEM, 4},
3733         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI),
3734             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3735             AMDGPU_GFX_SQ_MEM, 4},
3736         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI),
3737             5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3738             AMDGPU_GFX_SQC_MEM, 4},
3739         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI),
3740             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3741             AMDGPU_GFX_TCX_MEM, 1},
3742         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI),
3743             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3744             AMDGPU_GFX_TCC_MEM, 1},
3745         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI),
3746             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3747             AMDGPU_GFX_TA_MEM, 4},
3748         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG),
3749             27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3750             AMDGPU_GFX_TCI_MEM, 1},
3751         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG),
3752             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3753             AMDGPU_GFX_TCP_MEM, 4},
3754         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI),
3755             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3756             AMDGPU_GFX_TD_MEM, 4},
3757         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI),
3758             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3759             AMDGPU_GFX_GCEA_MEM, 1},
3760         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI),
3761             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3762             AMDGPU_GFX_LDS_MEM, 4},
3763 };
3764
3765 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = {
3766         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH),
3767             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3768             AMDGPU_GFX_RLC_MEM, 1},
3769         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI),
3770             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3771             AMDGPU_GFX_CP_MEM, 1},
3772         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI),
3773             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3774             AMDGPU_GFX_CP_MEM, 1},
3775         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI),
3776             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3777             AMDGPU_GFX_CP_MEM, 1},
3778         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI),
3779             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3780             AMDGPU_GFX_GDS_MEM, 1},
3781         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI),
3782             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3783             AMDGPU_GFX_GC_CANE_MEM, 1},
3784         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI),
3785             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3786             AMDGPU_GFX_SPI_MEM, 1},
3787         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI),
3788             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3789             AMDGPU_GFX_SP_MEM, 4},
3790         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI),
3791             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3792             AMDGPU_GFX_SP_MEM, 4},
3793         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI),
3794             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3795             AMDGPU_GFX_SQ_MEM, 4},
3796         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI),
3797             5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3798             AMDGPU_GFX_SQC_MEM, 4},
3799         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI),
3800             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3801             AMDGPU_GFX_TCX_MEM, 1},
3802         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI),
3803             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3804             AMDGPU_GFX_TCC_MEM, 1},
3805         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI),
3806             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3807             AMDGPU_GFX_TA_MEM, 4},
3808         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG),
3809             27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3810             AMDGPU_GFX_TCI_MEM, 1},
3811         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG),
3812             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3813             AMDGPU_GFX_TCP_MEM, 4},
3814         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI),
3815             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3816             AMDGPU_GFX_TD_MEM, 4},
3817         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI),
3818             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"},
3819             AMDGPU_GFX_TCA_MEM, 1},
3820         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI),
3821             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3822             AMDGPU_GFX_GCEA_MEM, 1},
3823         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI),
3824             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3825             AMDGPU_GFX_LDS_MEM, 4},
3826 };
3827
3828 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
3829                                         void *ras_error_status, int xcc_id)
3830 {
3831         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
3832         unsigned long ce_count = 0, ue_count = 0;
3833         uint32_t i, j, k;
3834
3835         /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */
3836         struct amdgpu_smuio_mcm_config_info mcm_info = {
3837                 .socket_id = adev->smuio.funcs->get_socket_id(adev),
3838                 .die_id = xcc_id & 0x01 ? 1 : 0,
3839         };
3840
3841         mutex_lock(&adev->grbm_idx_mutex);
3842
3843         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3844                 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3845                         for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3846                                 /* no need to select if instance number is 1 */
3847                                 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3848                                     gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3849                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3850
3851                                 amdgpu_ras_inst_query_ras_error_count(adev,
3852                                         &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3853                                         1,
3854                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent,
3855                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size,
3856                                         GET_INST(GC, xcc_id),
3857                                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE,
3858                                         &ce_count);
3859
3860                                 amdgpu_ras_inst_query_ras_error_count(adev,
3861                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3862                                         1,
3863                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent,
3864                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size,
3865                                         GET_INST(GC, xcc_id),
3866                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
3867                                         &ue_count);
3868                         }
3869                 }
3870         }
3871
3872         /* handle extra register entries of UE */
3873         for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) {
3874                 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) {
3875                         for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
3876                                 /* no need to select if instance number is 1 */
3877                                 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 ||
3878                                         gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1)
3879                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3880
3881                                 amdgpu_ras_inst_query_ras_error_count(adev,
3882                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3883                                         1,
3884                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent,
3885                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size,
3886                                         GET_INST(GC, xcc_id),
3887                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
3888                                         &ue_count);
3889                         }
3890                 }
3891         }
3892
3893         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3894                         xcc_id);
3895         mutex_unlock(&adev->grbm_idx_mutex);
3896
3897         /* the caller should make sure initialize value of
3898          * err_data->ue_count and err_data->ce_count
3899          */
3900         amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count);
3901         amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, ce_count);
3902 }
3903
3904 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,
3905                                         void *ras_error_status, int xcc_id)
3906 {
3907         uint32_t i, j, k;
3908
3909         mutex_lock(&adev->grbm_idx_mutex);
3910
3911         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3912                 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3913                         for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3914                                 /* no need to select if instance number is 1 */
3915                                 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3916                                     gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3917                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3918
3919                                 amdgpu_ras_inst_reset_ras_error_count(adev,
3920                                         &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3921                                         1,
3922                                         GET_INST(GC, xcc_id));
3923
3924                                 amdgpu_ras_inst_reset_ras_error_count(adev,
3925                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3926                                         1,
3927                                         GET_INST(GC, xcc_id));
3928                         }
3929                 }
3930         }
3931
3932         /* handle extra register entries of UE */
3933         for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) {
3934                 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) {
3935                         for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
3936                                 /* no need to select if instance number is 1 */
3937                                 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 ||
3938                                         gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1)
3939                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3940
3941                                 amdgpu_ras_inst_reset_ras_error_count(adev,
3942                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3943                                         1,
3944                                         GET_INST(GC, xcc_id));
3945                         }
3946                 }
3947         }
3948
3949         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3950                         xcc_id);
3951         mutex_unlock(&adev->grbm_idx_mutex);
3952 }
3953
3954 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev,
3955                                         void *ras_error_status, int xcc_id)
3956 {
3957         uint32_t i;
3958         uint32_t data;
3959
3960         if (amdgpu_sriov_vf(adev))
3961                 return;
3962
3963         data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);
3964         data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
3965                              amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0);
3966
3967         if (amdgpu_watchdog_timer.timeout_fatal_disable &&
3968             (amdgpu_watchdog_timer.period < 1 ||
3969              amdgpu_watchdog_timer.period > 0x23)) {
3970                 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
3971                 amdgpu_watchdog_timer.period = 0x23;
3972         }
3973         data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
3974                              amdgpu_watchdog_timer.period);
3975
3976         mutex_lock(&adev->grbm_idx_mutex);
3977         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3978                 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id);
3979                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data);
3980         }
3981         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3982                         xcc_id);
3983         mutex_unlock(&adev->grbm_idx_mutex);
3984 }
3985
3986 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev,
3987                                         void *ras_error_status)
3988 {
3989         amdgpu_gfx_ras_error_func(adev, ras_error_status,
3990                         gfx_v9_4_3_inst_query_ras_err_count);
3991 }
3992
3993 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev)
3994 {
3995         amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count);
3996 }
3997
3998 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev)
3999 {
4000         amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer);
4001 }
4002
4003 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
4004         .name = "gfx_v9_4_3",
4005         .early_init = gfx_v9_4_3_early_init,
4006         .late_init = gfx_v9_4_3_late_init,
4007         .sw_init = gfx_v9_4_3_sw_init,
4008         .sw_fini = gfx_v9_4_3_sw_fini,
4009         .hw_init = gfx_v9_4_3_hw_init,
4010         .hw_fini = gfx_v9_4_3_hw_fini,
4011         .suspend = gfx_v9_4_3_suspend,
4012         .resume = gfx_v9_4_3_resume,
4013         .is_idle = gfx_v9_4_3_is_idle,
4014         .wait_for_idle = gfx_v9_4_3_wait_for_idle,
4015         .soft_reset = gfx_v9_4_3_soft_reset,
4016         .set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
4017         .set_powergating_state = gfx_v9_4_3_set_powergating_state,
4018         .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
4019         .dump_ip_state = NULL,
4020         .print_ip_state = NULL,
4021 };
4022
4023 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
4024         .type = AMDGPU_RING_TYPE_COMPUTE,
4025         .align_mask = 0xff,
4026         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4027         .support_64bit_ptrs = true,
4028         .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4029         .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4030         .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4031         .emit_frame_size =
4032                 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4033                 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4034                 5 + /* hdp invalidate */
4035                 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4036                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4037                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4038                 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4039                 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */
4040                 7 + /* gfx_v9_4_3_emit_mem_sync */
4041                 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */
4042                 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */
4043         .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4044         .emit_ib = gfx_v9_4_3_ring_emit_ib_compute,
4045         .emit_fence = gfx_v9_4_3_ring_emit_fence,
4046         .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync,
4047         .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush,
4048         .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch,
4049         .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,
4050         .test_ring = gfx_v9_4_3_ring_test_ring,
4051         .test_ib = gfx_v9_4_3_ring_test_ib,
4052         .insert_nop = amdgpu_ring_insert_nop,
4053         .pad_ib = amdgpu_ring_generic_pad_ib,
4054         .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4055         .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4056         .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4057         .emit_mem_sync = gfx_v9_4_3_emit_mem_sync,
4058         .emit_wave_limit = gfx_v9_4_3_emit_wave_limit,
4059 };
4060
4061 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {
4062         .type = AMDGPU_RING_TYPE_KIQ,
4063         .align_mask = 0xff,
4064         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4065         .support_64bit_ptrs = true,
4066         .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4067         .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4068         .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4069         .emit_frame_size =
4070                 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4071                 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4072                 5 + /* hdp invalidate */
4073                 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4074                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4075                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4076                 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4077                 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */
4078         .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4079         .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq,
4080         .test_ring = gfx_v9_4_3_ring_test_ring,
4081         .insert_nop = amdgpu_ring_insert_nop,
4082         .pad_ib = amdgpu_ring_generic_pad_ib,
4083         .emit_rreg = gfx_v9_4_3_ring_emit_rreg,
4084         .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4085         .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4086         .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4087 };
4088
4089 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)
4090 {
4091         int i, j, num_xcc;
4092
4093         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
4094         for (i = 0; i < num_xcc; i++) {
4095                 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;
4096
4097                 for (j = 0; j < adev->gfx.num_compute_rings; j++)
4098                         adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs
4099                                         = &gfx_v9_4_3_ring_funcs_compute;
4100         }
4101 }
4102
4103 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = {
4104         .set = gfx_v9_4_3_set_eop_interrupt_state,
4105         .process = gfx_v9_4_3_eop_irq,
4106 };
4107
4108 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
4109         .set = gfx_v9_4_3_set_priv_reg_fault_state,
4110         .process = gfx_v9_4_3_priv_reg_irq,
4111 };
4112
4113 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
4114         .set = gfx_v9_4_3_set_priv_inst_fault_state,
4115         .process = gfx_v9_4_3_priv_inst_irq,
4116 };
4117
4118 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
4119 {
4120         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4121         adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;
4122
4123         adev->gfx.priv_reg_irq.num_types = 1;
4124         adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
4125
4126         adev->gfx.priv_inst_irq.num_types = 1;
4127         adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
4128 }
4129
4130 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)
4131 {
4132         adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;
4133 }
4134
4135
4136 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)
4137 {
4138         /* init asci gds info */
4139         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4140         case IP_VERSION(9, 4, 3):
4141                 /* 9.4.3 removed all the GDS internal memory,
4142                  * only support GWS opcode in kernel, like barrier
4143                  * semaphore.etc */
4144                 adev->gds.gds_size = 0;
4145                 break;
4146         default:
4147                 adev->gds.gds_size = 0x10000;
4148                 break;
4149         }
4150
4151         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4152         case IP_VERSION(9, 4, 3):
4153                 /* deprecated for 9.4.3, no usage at all */
4154                 adev->gds.gds_compute_max_wave_id = 0;
4155                 break;
4156         default:
4157                 /* this really depends on the chip */
4158                 adev->gds.gds_compute_max_wave_id = 0x7ff;
4159                 break;
4160         }
4161
4162         adev->gds.gws_size = 64;
4163         adev->gds.oa_size = 16;
4164 }
4165
4166 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4167                                                  u32 bitmap, int xcc_id)
4168 {
4169         u32 data;
4170
4171         if (!bitmap)
4172                 return;
4173
4174         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4175         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4176
4177         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);
4178 }
4179
4180 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id)
4181 {
4182         u32 data, mask;
4183
4184         data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);
4185         data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);
4186
4187         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4188         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4189
4190         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4191
4192         return (~data) & mask;
4193 }
4194
4195 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
4196                                  struct amdgpu_cu_info *cu_info)
4197 {
4198         int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0;
4199         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp;
4200         unsigned disable_masks[4 * 4];
4201         bool is_symmetric_cus;
4202
4203         if (!adev || !cu_info)
4204                 return -EINVAL;
4205
4206         /*
4207          * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
4208          */
4209         if (adev->gfx.config.max_shader_engines *
4210                 adev->gfx.config.max_sh_per_se > 16)
4211                 return -EINVAL;
4212
4213         amdgpu_gfx_parse_disable_cu(disable_masks,
4214                                     adev->gfx.config.max_shader_engines,
4215                                     adev->gfx.config.max_sh_per_se);
4216
4217         mutex_lock(&adev->grbm_idx_mutex);
4218         for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
4219                 is_symmetric_cus = true;
4220                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4221                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4222                                 mask = 1;
4223                                 ao_bitmap = 0;
4224                                 counter = 0;
4225                                 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id);
4226                                 gfx_v9_4_3_set_user_cu_inactive_bitmap(
4227                                         adev,
4228                                         disable_masks[i * adev->gfx.config.max_sh_per_se + j],
4229                                         xcc_id);
4230                                 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id);
4231
4232                                 cu_info->bitmap[xcc_id][i][j] = bitmap;
4233
4234                                 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
4235                                         if (bitmap & mask) {
4236                                                 if (counter < adev->gfx.config.max_cu_per_sh)
4237                                                         ao_bitmap |= mask;
4238                                                 counter++;
4239                                         }
4240                                         mask <<= 1;
4241                                 }
4242                                 active_cu_number += counter;
4243                                 if (i < 2 && j < 2)
4244                                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4245                                 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4246                         }
4247                         if (i && is_symmetric_cus && prev_counter != counter)
4248                                 is_symmetric_cus = false;
4249                         prev_counter = counter;
4250                 }
4251                 if (is_symmetric_cus) {
4252                         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);
4253                         tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1);
4254                         tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1);
4255                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);
4256                 }
4257                 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4258                                             xcc_id);
4259         }
4260         mutex_unlock(&adev->grbm_idx_mutex);
4261
4262         cu_info->number = active_cu_number;
4263         cu_info->ao_cu_mask = ao_cu_mask;
4264         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4265
4266         return 0;
4267 }
4268
4269 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = {
4270         .type = AMD_IP_BLOCK_TYPE_GFX,
4271         .major = 9,
4272         .minor = 4,
4273         .rev = 3,
4274         .funcs = &gfx_v9_4_3_ip_funcs,
4275 };
4276
4277 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask)
4278 {
4279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4280         uint32_t tmp_mask;
4281         int i, r;
4282
4283         /* TODO : Initialize golden regs */
4284         /* gfx_v9_4_3_init_golden_registers(adev); */
4285
4286         tmp_mask = inst_mask;
4287         for_each_inst(i, tmp_mask)
4288                 gfx_v9_4_3_xcc_constants_init(adev, i);
4289
4290         if (!amdgpu_sriov_vf(adev)) {
4291                 tmp_mask = inst_mask;
4292                 for_each_inst(i, tmp_mask) {
4293                         r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
4294                         if (r)
4295                                 return r;
4296                 }
4297         }
4298
4299         tmp_mask = inst_mask;
4300         for_each_inst(i, tmp_mask) {
4301                 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
4302                 if (r)
4303                         return r;
4304         }
4305
4306         return 0;
4307 }
4308
4309 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask)
4310 {
4311         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4312         int i;
4313
4314         for_each_inst(i, inst_mask)
4315                 gfx_v9_4_3_xcc_fini(adev, i);
4316
4317         return 0;
4318 }
4319
4320 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = {
4321         .suspend = &gfx_v9_4_3_xcp_suspend,
4322         .resume = &gfx_v9_4_3_xcp_resume
4323 };
4324
4325 struct amdgpu_ras_block_hw_ops  gfx_v9_4_3_ras_ops = {
4326         .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count,
4327         .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count,
4328 };
4329
4330 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
4331 {
4332         int r;
4333
4334         r = amdgpu_ras_block_late_init(adev, ras_block);
4335         if (r)
4336                 return r;
4337
4338         r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX,
4339                                 &gfx_v9_4_3_aca_info,
4340                                 NULL);
4341         if (r)
4342                 goto late_fini;
4343
4344         return 0;
4345
4346 late_fini:
4347         amdgpu_ras_block_late_fini(adev, ras_block);
4348
4349         return r;
4350 }
4351
4352 struct amdgpu_gfx_ras gfx_v9_4_3_ras = {
4353         .ras_block = {
4354                 .hw_ops = &gfx_v9_4_3_ras_ops,
4355                 .ras_late_init = &gfx_v9_4_3_ras_late_init,
4356         },
4357         .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer,
4358 };