drivers/gpu/drm/meson/meson_overlay.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 BayLibre, SAS
   4  * Author: Neil Armstrong <[email protected]>
   5  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   6  */
   7
   8 #include <linux/bitfield.h>
   9
  10 #include <drm/drm_atomic.h>
  11 #include <drm/drm_atomic_helper.h>
  12 #include <drm/drm_blend.h>
  13 #include <drm/drm_device.h>
  14 #include <drm/drm_fb_cma_helper.h>
  15 #include <drm/drm_fourcc.h>
  16 #include <drm/drm_framebuffer.h>
  17 #include <drm/drm_gem_atomic_helper.h>
  18 #include <drm/drm_gem_cma_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include "meson_overlay.h"
  22 #include "meson_registers.h"
  23 #include "meson_viu.h"
  24 #include "meson_vpp.h"
  25
  26 /* VD1_IF0_GEN_REG */
  27 #define VD_URGENT_CHROMA                BIT(28)
  28 #define VD_URGENT_LUMA                  BIT(27)
  29 #define VD_HOLD_LINES(lines)            FIELD_PREP(GENMASK(24, 19), lines)
  30 #define VD_DEMUX_MODE_RGB               BIT(16)
  31 #define VD_BYTES_PER_PIXEL(val)         FIELD_PREP(GENMASK(15, 14), val)
  32 #define VD_CHRO_RPT_LASTL_CTRL          BIT(6)
  33 #define VD_LITTLE_ENDIAN                BIT(4)
  34 #define VD_SEPARATE_EN                  BIT(1)
  35 #define VD_ENABLE                       BIT(0)
  36
  37 /* VD1_IF0_CANVAS0 */
  38 #define CANVAS_ADDR2(addr)              FIELD_PREP(GENMASK(23, 16), addr)
  39 #define CANVAS_ADDR1(addr)              FIELD_PREP(GENMASK(15, 8), addr)
  40 #define CANVAS_ADDR0(addr)              FIELD_PREP(GENMASK(7, 0), addr)
  41
  42 /* VD1_IF0_LUMA_X0 VD1_IF0_CHROMA_X0 */
  43 #define VD_X_START(value)               FIELD_PREP(GENMASK(14, 0), value)
  44 #define VD_X_END(value)                 FIELD_PREP(GENMASK(30, 16), value)
  45
  46 /* VD1_IF0_LUMA_Y0 VD1_IF0_CHROMA_Y0 */
  47 #define VD_Y_START(value)               FIELD_PREP(GENMASK(12, 0), value)
  48 #define VD_Y_END(value)                 FIELD_PREP(GENMASK(28, 16), value)
  49
  50 /* VD1_IF0_GEN_REG2 */
  51 #define VD_COLOR_MAP(value)             FIELD_PREP(GENMASK(1, 0), value)
  52
  53 /* VIU_VD1_FMT_CTRL */
  54 #define VD_HORZ_Y_C_RATIO(value)        FIELD_PREP(GENMASK(22, 21), value)
  55 #define VD_HORZ_FMT_EN                  BIT(20)
  56 #define VD_VERT_RPT_LINE0               BIT(16)
  57 #define VD_VERT_INITIAL_PHASE(value)    FIELD_PREP(GENMASK(11, 8), value)
  58 #define VD_VERT_PHASE_STEP(value)       FIELD_PREP(GENMASK(7, 1), value)
  59 #define VD_VERT_FMT_EN                  BIT(0)
  60
  61 /* VPP_POSTBLEND_VD1_H_START_END */
  62 #define VD_H_END(value)                 FIELD_PREP(GENMASK(11, 0), value)
  63 #define VD_H_START(value)               FIELD_PREP(GENMASK(27, 16), \
  64                                                    ((value) & GENMASK(13, 0)))
  65
  66 /* VPP_POSTBLEND_VD1_V_START_END */
  67 #define VD_V_END(value)                 FIELD_PREP(GENMASK(11, 0), value)
  68 #define VD_V_START(value)               FIELD_PREP(GENMASK(27, 16), value)
  69
  70 /* VPP_BLEND_VD2_V_START_END */
  71 #define VD2_V_END(value)                FIELD_PREP(GENMASK(11, 0), value)
  72 #define VD2_V_START(value)              FIELD_PREP(GENMASK(27, 16), value)
  73
  74 /* VIU_VD1_FMT_W */
  75 #define VD_V_WIDTH(value)               FIELD_PREP(GENMASK(11, 0), value)
  76 #define VD_H_WIDTH(value)               FIELD_PREP(GENMASK(27, 16), value)
  77
  78 /* VPP_HSC_REGION12_STARTP VPP_HSC_REGION34_STARTP */
  79 #define VD_REGION24_START(value)        FIELD_PREP(GENMASK(11, 0), value)
  80 #define VD_REGION13_END(value)          FIELD_PREP(GENMASK(27, 16), value)
  81
  82 /* AFBC_ENABLE */
  83 #define AFBC_DEC_ENABLE                 BIT(8)
  84 #define AFBC_FRM_START                  BIT(0)
  85
  86 /* AFBC_MODE */
  87 #define AFBC_HORZ_SKIP_UV(value)        FIELD_PREP(GENMASK(1, 0), value)
  88 #define AFBC_VERT_SKIP_UV(value)        FIELD_PREP(GENMASK(3, 2), value)
  89 #define AFBC_HORZ_SKIP_Y(value)         FIELD_PREP(GENMASK(5, 4), value)
  90 #define AFBC_VERT_SKIP_Y(value)         FIELD_PREP(GENMASK(7, 6), value)
  91 #define AFBC_COMPBITS_YUV(value)        FIELD_PREP(GENMASK(13, 8), value)
  92 #define AFBC_COMPBITS_8BIT              0
  93 #define AFBC_COMPBITS_10BIT             (2 | (2 << 2) | (2 << 4))
  94 #define AFBC_BURST_LEN(value)           FIELD_PREP(GENMASK(15, 14), value)
  95 #define AFBC_HOLD_LINE_NUM(value)       FIELD_PREP(GENMASK(22, 16), value)
  96 #define AFBC_MIF_URGENT(value)          FIELD_PREP(GENMASK(25, 24), value)
  97 #define AFBC_REV_MODE(value)            FIELD_PREP(GENMASK(27, 26), value)
  98 #define AFBC_BLK_MEM_MODE               BIT(28)
  99 #define AFBC_SCATTER_MODE               BIT(29)
 100 #define AFBC_SOFT_RESET                 BIT(31)
 101
 102 /* AFBC_SIZE_IN */
 103 #define AFBC_HSIZE_IN(value)            FIELD_PREP(GENMASK(28, 16), value)
 104 #define AFBC_VSIZE_IN(value)            FIELD_PREP(GENMASK(12, 0), value)
 105
 106 /* AFBC_DEC_DEF_COLOR */
 107 #define AFBC_DEF_COLOR_Y(value)         FIELD_PREP(GENMASK(29, 20), value)
 108 #define AFBC_DEF_COLOR_U(value)         FIELD_PREP(GENMASK(19, 10), value)
 109 #define AFBC_DEF_COLOR_V(value)         FIELD_PREP(GENMASK(9, 0), value)
 110
 111 /* AFBC_CONV_CTRL */
 112 #define AFBC_CONV_LBUF_LEN(value)       FIELD_PREP(GENMASK(11, 0), value)
 113
 114 /* AFBC_LBUF_DEPTH */
 115 #define AFBC_DEC_LBUF_DEPTH(value)      FIELD_PREP(GENMASK(27, 16), value)
 116 #define AFBC_MIF_LBUF_DEPTH(value)      FIELD_PREP(GENMASK(11, 0), value)
 117
 118 /* AFBC_OUT_XSCOPE/AFBC_SIZE_OUT */
 119 #define AFBC_HSIZE_OUT(value)           FIELD_PREP(GENMASK(28, 16), value)
 120 #define AFBC_VSIZE_OUT(value)           FIELD_PREP(GENMASK(12, 0), value)
 121 #define AFBC_OUT_HORZ_BGN(value)        FIELD_PREP(GENMASK(28, 16), value)
 122 #define AFBC_OUT_HORZ_END(value)        FIELD_PREP(GENMASK(12, 0), value)
 123
 124 /* AFBC_OUT_YSCOPE */
 125 #define AFBC_OUT_VERT_BGN(value)        FIELD_PREP(GENMASK(28, 16), value)
 126 #define AFBC_OUT_VERT_END(value)        FIELD_PREP(GENMASK(12, 0), value)
 127
 128 /* AFBC_VD_CFMT_CTRL */
 129 #define AFBC_HORZ_RPT_PIXEL0            BIT(23)
 130 #define AFBC_HORZ_Y_C_RATIO(value)      FIELD_PREP(GENMASK(22, 21), value)
 131 #define AFBC_HORZ_FMT_EN                BIT(20)
 132 #define AFBC_VERT_RPT_LINE0             BIT(16)
 133 #define AFBC_VERT_INITIAL_PHASE(value)  FIELD_PREP(GENMASK(11, 8), value)
 134 #define AFBC_VERT_PHASE_STEP(value)     FIELD_PREP(GENMASK(7, 1), value)
 135 #define AFBC_VERT_FMT_EN                BIT(0)
 136
 137 /* AFBC_VD_CFMT_W */
 138 #define AFBC_VD_V_WIDTH(value)          FIELD_PREP(GENMASK(11, 0), value)
 139 #define AFBC_VD_H_WIDTH(value)          FIELD_PREP(GENMASK(27, 16), value)
 140
 141 /* AFBC_MIF_HOR_SCOPE */
 142 #define AFBC_MIF_BLK_BGN_H(value)       FIELD_PREP(GENMASK(25, 16), value)
 143 #define AFBC_MIF_BLK_END_H(value)       FIELD_PREP(GENMASK(9, 0), value)
 144
 145 /* AFBC_MIF_VER_SCOPE */
 146 #define AFBC_MIF_BLK_BGN_V(value)       FIELD_PREP(GENMASK(27, 16), value)
 147 #define AFBC_MIF_BLK_END_V(value)       FIELD_PREP(GENMASK(11, 0), value)
 148
 149 /* AFBC_PIXEL_HOR_SCOPE */
 150 #define AFBC_DEC_PIXEL_BGN_H(value)     FIELD_PREP(GENMASK(28, 16), \
 151                                                    ((value) & GENMASK(12, 0)))
 152 #define AFBC_DEC_PIXEL_END_H(value)     FIELD_PREP(GENMASK(12, 0), value)
 153
 154 /* AFBC_PIXEL_VER_SCOPE */
 155 #define AFBC_DEC_PIXEL_BGN_V(value)     FIELD_PREP(GENMASK(28, 16), value)
 156 #define AFBC_DEC_PIXEL_END_V(value)     FIELD_PREP(GENMASK(12, 0), value)
 157
 158 /* AFBC_VD_CFMT_H */
 159 #define AFBC_VD_HEIGHT(value)           FIELD_PREP(GENMASK(12, 0), value)
 160
 161 struct meson_overlay {
 162         struct drm_plane base;
 163         struct meson_drm *priv;
 164 };
 165 #define to_meson_overlay(x) container_of(x, struct meson_overlay, base)
 166
 167 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
 168
 169 static int meson_overlay_atomic_check(struct drm_plane *plane,
 170                                       struct drm_atomic_state *state)
 171 {
 172         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 173                                                                                  plane);
 174         struct drm_crtc_state *crtc_state;
 175
 176         if (!new_plane_state->crtc)
 177                 return 0;
 178
 179         crtc_state = drm_atomic_get_crtc_state(state,
 180                                                new_plane_state->crtc);
 181         if (IS_ERR(crtc_state))
 182                 return PTR_ERR(crtc_state);
 183
 184         return drm_atomic_helper_check_plane_state(new_plane_state,
 185                                                    crtc_state,
 186                                                    FRAC_16_16(1, 5),
 187                                                    FRAC_16_16(5, 1),
 188                                                    true, true);
 189 }
 190
 191 /* Takes a fixed 16.16 number and converts it to integer. */
 192 static inline int64_t fixed16_to_int(int64_t value)
 193 {
 194         return value >> 16;
 195 }
 196
 197 static const uint8_t skip_tab[6] = {
 198         0x24, 0x04, 0x68, 0x48, 0x28, 0x08,
 199 };
 200
 201 static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase,
 202                                              int *repeat, bool interlace)
 203 {
 204         int offset_in = 0;
 205         int offset_out = 0;
 206         int repeat_skip = 0;
 207
 208         if (!interlace && ratio_y > (1 << 18))
 209                 offset_out = (1 * ratio_y) >> 10;
 210
 211         while ((offset_in + (4 << 8)) <= offset_out) {
 212                 repeat_skip++;
 213                 offset_in += 4 << 8;
 214         }
 215
 216         *phase = (offset_out - offset_in) >> 2;
 217
 218         if (*phase > 0x100)
 219                 repeat_skip++;
 220
 221         *phase = *phase & 0xff;
 222
 223         if (repeat_skip > 5)
 224                 repeat_skip = 5;
 225
 226         *repeat = skip_tab[repeat_skip];
 227 }
 228
 229 static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
 230                                               struct drm_plane *plane,
 231                                               bool interlace_mode)
 232 {
 233         struct drm_crtc_state *crtc_state = priv->crtc->state;
 234         int video_top, video_left, video_width, video_height;
 235         struct drm_plane_state *state = plane->state;
 236         unsigned int vd_start_lines, vd_end_lines;
 237         unsigned int hd_start_lines, hd_end_lines;
 238         unsigned int crtc_height, crtc_width;
 239         unsigned int vsc_startp, vsc_endp;
 240         unsigned int hsc_startp, hsc_endp;
 241         unsigned int crop_top, crop_left;
 242         int vphase, vphase_repeat_skip;
 243         unsigned int ratio_x, ratio_y;
 244         int temp_height, temp_width;
 245         unsigned int w_in, h_in;
 246         int afbc_left, afbc_right;
 247         int afbc_top_src, afbc_bottom_src;
 248         int afbc_top, afbc_bottom;
 249         int temp, start, end;
 250
 251         if (!crtc_state) {
 252                 DRM_ERROR("Invalid crtc_state\n");
 253                 return;
 254         }
 255
 256         crtc_height = crtc_state->mode.vdisplay;
 257         crtc_width = crtc_state->mode.hdisplay;
 258
 259         w_in = fixed16_to_int(state->src_w);
 260         h_in = fixed16_to_int(state->src_h);
 261         crop_top = fixed16_to_int(state->src_y);
 262         crop_left = fixed16_to_int(state->src_x);
 263
 264         video_top = state->crtc_y;
 265         video_left = state->crtc_x;
 266         video_width = state->crtc_w;
 267         video_height = state->crtc_h;
 268
 269         DRM_DEBUG("crtc_width %d crtc_height %d interlace %d\n",
 270                   crtc_width, crtc_height, interlace_mode);
 271         DRM_DEBUG("w_in %d h_in %d crop_top %d crop_left %d\n",
 272                   w_in, h_in, crop_top, crop_left);
 273         DRM_DEBUG("video top %d left %d width %d height %d\n",
 274                   video_top, video_left, video_width, video_height);
 275
 276         ratio_x = (w_in << 18) / video_width;
 277         ratio_y = (h_in << 18) / video_height;
 278
 279         if (ratio_x * video_width < (w_in << 18))
 280                 ratio_x++;
 281
 282         DRM_DEBUG("ratio x 0x%x y 0x%x\n", ratio_x, ratio_y);
 283
 284         meson_overlay_get_vertical_phase(ratio_y, &vphase, &vphase_repeat_skip,
 285                                          interlace_mode);
 286
 287         DRM_DEBUG("vphase 0x%x skip %d\n", vphase, vphase_repeat_skip);
 288
 289         /* Vertical */
 290
 291         start = video_top + video_height / 2 - ((h_in << 17) / ratio_y);
 292         end = (h_in << 18) / ratio_y + start - 1;
 293
 294         if (video_top < 0 && start < 0)
 295                 vd_start_lines = (-(start) * ratio_y) >> 18;
 296         else if (start < video_top)
 297                 vd_start_lines = ((video_top - start) * ratio_y) >> 18;
 298         else
 299                 vd_start_lines = 0;
 300
 301         if (video_top < 0)
 302                 temp_height = min_t(unsigned int,
 303                                     video_top + video_height - 1,
 304                                     crtc_height - 1);
 305         else
 306                 temp_height = min_t(unsigned int,
 307                                     video_top + video_height - 1,
 308                                     crtc_height - 1) - video_top + 1;
 309
 310         temp = vd_start_lines + (temp_height * ratio_y >> 18);
 311         vd_end_lines = (temp <= (h_in - 1)) ? temp : (h_in - 1);
 312
 313         vd_start_lines += crop_left;
 314         vd_end_lines += crop_left;
 315
 316         /*
 317          * TOFIX: Input frames are handled and scaled like progressive frames,
 318          * proper handling of interlaced field input frames need to be figured
 319          * out using the proper framebuffer flags set by userspace.
 320          */
 321         if (interlace_mode) {
 322                 start >>= 1;
 323                 end >>= 1;
 324         }
 325
 326         vsc_startp = max_t(int, start,
 327                            max_t(int, 0, video_top));
 328         vsc_endp = min_t(int, end,
 329                          min_t(int, crtc_height - 1,
 330                                video_top + video_height - 1));
 331
 332         DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n",
 333                  vsc_startp, vsc_endp, vd_start_lines, vd_end_lines);
 334
 335         afbc_top = round_down(vd_start_lines, 4);
 336         afbc_bottom = round_up(vd_end_lines + 1, 4);
 337         afbc_top_src = 0;
 338         afbc_bottom_src = round_up(h_in + 1, 4);
 339
 340         DRM_DEBUG("afbc top %d (src %d) bottom %d (src %d)\n",
 341                   afbc_top, afbc_top_src, afbc_bottom, afbc_bottom_src);
 342
 343         /* Horizontal */
 344
 345         start = video_left + video_width / 2 - ((w_in << 17) / ratio_x);
 346         end = (w_in << 18) / ratio_x + start - 1;
 347
 348         if (video_left < 0 && start < 0)
 349                 hd_start_lines = (-(start) * ratio_x) >> 18;
 350         else if (start < video_left)
 351                 hd_start_lines = ((video_left - start) * ratio_x) >> 18;
 352         else
 353                 hd_start_lines = 0;
 354
 355         if (video_left < 0)
 356                 temp_width = min_t(unsigned int,
 357                                    video_left + video_width - 1,
 358                                    crtc_width - 1);
 359         else
 360                 temp_width = min_t(unsigned int,
 361                                    video_left + video_width - 1,
 362                                    crtc_width - 1) - video_left + 1;
 363
 364         temp = hd_start_lines + (temp_width * ratio_x >> 18);
 365         hd_end_lines = (temp <= (w_in - 1)) ? temp : (w_in - 1);
 366
 367         priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
 368         hsc_startp = max_t(int, start, max_t(int, 0, video_left));
 369         hsc_endp = min_t(int, end, min_t(int, crtc_width - 1,
 370                                          video_left + video_width - 1));
 371
 372         hd_start_lines += crop_top;
 373         hd_end_lines += crop_top;
 374
 375         DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n",
 376                  hsc_startp, hsc_endp, hd_start_lines, hd_end_lines);
 377
 378         if (hd_start_lines > 0 || (hd_end_lines < w_in)) {
 379                 afbc_left = 0;
 380                 afbc_right = round_up(w_in, 32);
 381         } else {
 382                 afbc_left = round_down(hd_start_lines, 32);
 383                 afbc_right = round_up(hd_end_lines + 1, 32);
 384         }
 385
 386         DRM_DEBUG("afbc left %d right %d\n", afbc_left, afbc_right);
 387
 388         priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
 389
 390         priv->viu.vpp_vsc_ini_phase = vphase << 8;
 391         priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) |
 392                                        vphase_repeat_skip;
 393
 394         priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) |
 395                                     VD_X_END(hd_end_lines);
 396         priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) |
 397                                       VD_X_END(hd_end_lines >> 1);
 398
 399         priv->viu.viu_vd1_fmt_w =
 400                         VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) |
 401                         VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1);
 402
 403         priv->viu.vd1_afbc_vd_cfmt_w =
 404                         AFBC_VD_H_WIDTH(afbc_right - afbc_left) |
 405                         AFBC_VD_V_WIDTH(afbc_right / 2 - afbc_left / 2);
 406
 407         priv->viu.vd1_afbc_vd_cfmt_h =
 408                         AFBC_VD_HEIGHT((afbc_bottom - afbc_top) / 2);
 409
 410         priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) |
 411                                 AFBC_MIF_BLK_END_H((afbc_right / 32) - 1);
 412
 413         priv->viu.vd1_afbc_mif_ver_scope = AFBC_MIF_BLK_BGN_V(afbc_top / 4) |
 414                                 AFBC_MIF_BLK_END_H((afbc_bottom / 4) - 1);
 415
 416         priv->viu.vd1_afbc_size_out =
 417                         AFBC_HSIZE_OUT(afbc_right - afbc_left) |
 418                         AFBC_VSIZE_OUT(afbc_bottom - afbc_top);
 419
 420         priv->viu.vd1_afbc_pixel_hor_scope =
 421                         AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) |
 422                         AFBC_DEC_PIXEL_END_H(hd_end_lines - afbc_left);
 423
 424         priv->viu.vd1_afbc_pixel_ver_scope =
 425                         AFBC_DEC_PIXEL_BGN_V(vd_start_lines - afbc_top) |
 426                         AFBC_DEC_PIXEL_END_V(vd_end_lines - afbc_top);
 427
 428         priv->viu.vd1_afbc_size_in =
 429                                 AFBC_HSIZE_IN(afbc_right - afbc_left) |
 430                                 AFBC_VSIZE_IN(afbc_bottom_src - afbc_top_src);
 431
 432         priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) |
 433                                     VD_Y_END(vd_end_lines);
 434
 435         priv->viu.vd1_if0_chroma_y0 = VD_Y_START(vd_start_lines >> 1) |
 436                                       VD_Y_END(vd_end_lines >> 1);
 437
 438         priv->viu.vpp_pic_in_height = h_in;
 439
 440         priv->viu.vpp_postblend_vd1_h_start_end = VD_H_START(hsc_startp) |
 441                                                   VD_H_END(hsc_endp);
 442         priv->viu.vpp_blend_vd2_h_start_end = VD_H_START(hd_start_lines) |
 443                                               VD_H_END(hd_end_lines);
 444         priv->viu.vpp_hsc_region12_startp = VD_REGION13_END(0) |
 445                                             VD_REGION24_START(hsc_startp);
 446         priv->viu.vpp_hsc_region34_startp =
 447                                 VD_REGION13_END(hsc_startp) |
 448                                 VD_REGION24_START(hsc_endp - hsc_startp);
 449         priv->viu.vpp_hsc_region4_endp = hsc_endp - hsc_startp;
 450         priv->viu.vpp_hsc_start_phase_step = ratio_x << 6;
 451         priv->viu.vpp_hsc_region1_phase_slope = 0;
 452         priv->viu.vpp_hsc_region3_phase_slope = 0;
 453         priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16);
 454
 455         priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
 456         priv->viu.vpp_preblend_h_size = hd_end_lines - hd_start_lines + 1;
 457
 458         priv->viu.vpp_postblend_vd1_v_start_end = VD_V_START(vsc_startp) |
 459                                                   VD_V_END(vsc_endp);
 460         priv->viu.vpp_blend_vd2_v_start_end =
 461                                 VD2_V_START((vd_end_lines + 1) >> 1) |
 462                                 VD2_V_END(vd_end_lines);
 463
 464         priv->viu.vpp_vsc_region12_startp = 0;
 465         priv->viu.vpp_vsc_region34_startp =
 466                                 VD_REGION13_END(vsc_endp - vsc_startp) |
 467                                 VD_REGION24_START(vsc_endp - vsc_startp);
 468         priv->viu.vpp_vsc_region4_endp = vsc_endp - vsc_startp;
 469         priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
 470 }
 471
 472 static void meson_overlay_atomic_update(struct drm_plane *plane,
 473                                         struct drm_atomic_state *state)
 474 {
 475         struct meson_overlay *meson_overlay = to_meson_overlay(plane);
 476         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 477                                                                            plane);
 478         struct drm_framebuffer *fb = new_state->fb;
 479         struct meson_drm *priv = meson_overlay->priv;
 480         struct drm_gem_cma_object *gem;
 481         unsigned long flags;
 482         bool interlace_mode;
 483
 484         DRM_DEBUG_DRIVER("\n");
 485
 486         interlace_mode = new_state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE;
 487
 488         spin_lock_irqsave(&priv->drm->event_lock, flags);
 489
 490         if ((fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
 491                             DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
 492                 priv->viu.vd1_afbc = true;
 493
 494                 priv->viu.vd1_afbc_mode = AFBC_MIF_URGENT(3) |
 495                                           AFBC_HOLD_LINE_NUM(8) |
 496                                           AFBC_BURST_LEN(2);
 497
 498                 if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0,
 499                                                 AMLOGIC_FBC_OPTION_MEM_SAVING))
 500                         priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE;
 501
 502                 if ((fb->modifier & __fourcc_mod_amlogic_layout_mask) ==
 503                                 AMLOGIC_FBC_LAYOUT_SCATTER)
 504                         priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE;
 505
 506                 priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE;
 507
 508                 priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256);
 509
 510                 priv->viu.vd1_afbc_dec_def_color = AFBC_DEF_COLOR_Y(1023);
 511
 512                 /* 420: horizontal / 2, vertical / 4 */
 513                 priv->viu.vd1_afbc_vd_cfmt_ctrl = AFBC_HORZ_RPT_PIXEL0 |
 514                                                   AFBC_HORZ_Y_C_RATIO(1) |
 515                                                   AFBC_HORZ_FMT_EN |
 516                                                   AFBC_VERT_RPT_LINE0 |
 517                                                   AFBC_VERT_INITIAL_PHASE(12) |
 518                                                   AFBC_VERT_PHASE_STEP(8) |
 519                                                   AFBC_VERT_FMT_EN;
 520
 521                 switch (fb->format->format) {
 522                 /* AFBC Only formats */
 523                 case DRM_FORMAT_YUV420_10BIT:
 524                         priv->viu.vd1_afbc_mode |=
 525                                 AFBC_COMPBITS_YUV(AFBC_COMPBITS_10BIT);
 526                         priv->viu.vd1_afbc_dec_def_color |=
 527                                         AFBC_DEF_COLOR_U(512) |
 528                                         AFBC_DEF_COLOR_V(512);
 529                         break;
 530                 case DRM_FORMAT_YUV420_8BIT:
 531                         priv->viu.vd1_afbc_dec_def_color |=
 532                                         AFBC_DEF_COLOR_U(128) |
 533                                         AFBC_DEF_COLOR_V(128);
 534                         break;
 535                 }
 536
 537                 priv->viu.vd1_if0_gen_reg = 0;
 538                 priv->viu.vd1_if0_canvas0 = 0;
 539                 priv->viu.viu_vd1_fmt_ctrl = 0;
 540         } else {
 541                 priv->viu.vd1_afbc = false;
 542
 543                 priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA |
 544                                             VD_URGENT_LUMA |
 545                                             VD_HOLD_LINES(9) |
 546                                             VD_CHRO_RPT_LASTL_CTRL |
 547                                             VD_ENABLE;
 548         }
 549
 550         /* Setup scaler params */
 551         meson_overlay_setup_scaler_params(priv, plane, interlace_mode);
 552
 553         priv->viu.vd1_if0_repeat_loop = 0;
 554         priv->viu.vd1_if0_luma0_rpt_pat = interlace_mode ? 8 : 0;
 555         priv->viu.vd1_if0_chroma0_rpt_pat = interlace_mode ? 8 : 0;
 556         priv->viu.vd1_range_map_y = 0;
 557         priv->viu.vd1_range_map_cb = 0;
 558         priv->viu.vd1_range_map_cr = 0;
 559
 560         /* Default values for RGB888/YUV444 */
 561         priv->viu.vd1_if0_gen_reg2 = 0;
 562         priv->viu.viu_vd1_fmt_ctrl = 0;
 563
 564         /* None will match for AFBC Only formats */
 565         switch (fb->format->format) {
 566         /* TOFIX DRM_FORMAT_RGB888 should be supported */
 567         case DRM_FORMAT_YUYV:
 568                 priv->viu.vd1_if0_gen_reg |= VD_BYTES_PER_PIXEL(1);
 569                 priv->viu.vd1_if0_canvas0 =
 570                                         CANVAS_ADDR2(priv->canvas_id_vd1_0) |
 571                                         CANVAS_ADDR1(priv->canvas_id_vd1_0) |
 572                                         CANVAS_ADDR0(priv->canvas_id_vd1_0);
 573                 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
 574                                              VD_HORZ_FMT_EN |
 575                                              VD_VERT_RPT_LINE0 |
 576                                              VD_VERT_INITIAL_PHASE(12) |
 577                                              VD_VERT_PHASE_STEP(16) | /* /2 */
 578                                              VD_VERT_FMT_EN;
 579                 break;
 580         case DRM_FORMAT_NV12:
 581         case DRM_FORMAT_NV21:
 582                 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
 583                 priv->viu.vd1_if0_canvas0 =
 584                                         CANVAS_ADDR2(priv->canvas_id_vd1_1) |
 585                                         CANVAS_ADDR1(priv->canvas_id_vd1_1) |
 586                                         CANVAS_ADDR0(priv->canvas_id_vd1_0);
 587                 if (fb->format->format == DRM_FORMAT_NV12)
 588                         priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(1);
 589                 else
 590                         priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(2);
 591                 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
 592                                              VD_HORZ_FMT_EN |
 593                                              VD_VERT_RPT_LINE0 |
 594                                              VD_VERT_INITIAL_PHASE(12) |
 595                                              VD_VERT_PHASE_STEP(8) | /* /4 */
 596                                              VD_VERT_FMT_EN;
 597                 break;
 598         case DRM_FORMAT_YUV444:
 599         case DRM_FORMAT_YUV422:
 600         case DRM_FORMAT_YUV420:
 601         case DRM_FORMAT_YUV411:
 602         case DRM_FORMAT_YUV410:
 603                 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
 604                 priv->viu.vd1_if0_canvas0 =
 605                                         CANVAS_ADDR2(priv->canvas_id_vd1_2) |
 606                                         CANVAS_ADDR1(priv->canvas_id_vd1_1) |
 607                                         CANVAS_ADDR0(priv->canvas_id_vd1_0);
 608                 switch (fb->format->format) {
 609                 case DRM_FORMAT_YUV422:
 610                         priv->viu.viu_vd1_fmt_ctrl =
 611                                         VD_HORZ_Y_C_RATIO(1) | /* /2 */
 612                                         VD_HORZ_FMT_EN |
 613                                         VD_VERT_RPT_LINE0 |
 614                                         VD_VERT_INITIAL_PHASE(12) |
 615                                         VD_VERT_PHASE_STEP(16) | /* /2 */
 616                                         VD_VERT_FMT_EN;
 617                         break;
 618                 case DRM_FORMAT_YUV420:
 619                         priv->viu.viu_vd1_fmt_ctrl =
 620                                         VD_HORZ_Y_C_RATIO(1) | /* /2 */
 621                                         VD_HORZ_FMT_EN |
 622                                         VD_VERT_RPT_LINE0 |
 623                                         VD_VERT_INITIAL_PHASE(12) |
 624                                         VD_VERT_PHASE_STEP(8) | /* /4 */
 625                                         VD_VERT_FMT_EN;
 626                         break;
 627                 case DRM_FORMAT_YUV411:
 628                         priv->viu.viu_vd1_fmt_ctrl =
 629                                         VD_HORZ_Y_C_RATIO(2) | /* /4 */
 630                                         VD_HORZ_FMT_EN |
 631                                         VD_VERT_RPT_LINE0 |
 632                                         VD_VERT_INITIAL_PHASE(12) |
 633                                         VD_VERT_PHASE_STEP(16) | /* /2 */
 634                                         VD_VERT_FMT_EN;
 635                         break;
 636                 case DRM_FORMAT_YUV410:
 637                         priv->viu.viu_vd1_fmt_ctrl =
 638                                         VD_HORZ_Y_C_RATIO(2) | /* /4 */
 639                                         VD_HORZ_FMT_EN |
 640                                         VD_VERT_RPT_LINE0 |
 641                                         VD_VERT_INITIAL_PHASE(12) |
 642                                         VD_VERT_PHASE_STEP(8) | /* /4 */
 643                                         VD_VERT_FMT_EN;
 644                         break;
 645                 }
 646                 break;
 647         }
 648
 649         /* Update Canvas with buffer address */
 650         priv->viu.vd1_planes = fb->format->num_planes;
 651
 652         switch (priv->viu.vd1_planes) {
 653         case 3:
 654                 gem = drm_fb_cma_get_gem_obj(fb, 2);
 655                 priv->viu.vd1_addr2 = gem->paddr + fb->offsets[2];
 656                 priv->viu.vd1_stride2 = fb->pitches[2];
 657                 priv->viu.vd1_height2 =
 658                         drm_format_info_plane_height(fb->format,
 659                                                 fb->height, 2);
 660                 DRM_DEBUG("plane 2 addr 0x%x stride %d height %d\n",
 661                          priv->viu.vd1_addr2,
 662                          priv->viu.vd1_stride2,
 663                          priv->viu.vd1_height2);
 664                 fallthrough;
 665         case 2:
 666                 gem = drm_fb_cma_get_gem_obj(fb, 1);
 667                 priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1];
 668                 priv->viu.vd1_stride1 = fb->pitches[1];
 669                 priv->viu.vd1_height1 =
 670                         drm_format_info_plane_height(fb->format,
 671                                                 fb->height, 1);
 672                 DRM_DEBUG("plane 1 addr 0x%x stride %d height %d\n",
 673                          priv->viu.vd1_addr1,
 674                          priv->viu.vd1_stride1,
 675                          priv->viu.vd1_height1);
 676                 fallthrough;
 677         case 1:
 678                 gem = drm_fb_cma_get_gem_obj(fb, 0);
 679                 priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0];
 680                 priv->viu.vd1_stride0 = fb->pitches[0];
 681                 priv->viu.vd1_height0 =
 682                         drm_format_info_plane_height(fb->format,
 683                                                      fb->height, 0);
 684                 DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n",
 685                          priv->viu.vd1_addr0,
 686                          priv->viu.vd1_stride0,
 687                          priv->viu.vd1_height0);
 688         }
 689
 690         if (priv->viu.vd1_afbc) {
 691                 if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) {
 692                         /*
 693                          * In Scatter mode, the header contains the physical
 694                          * body content layout, thus the body content
 695                          * size isn't needed.
 696                          */
 697                         priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4;
 698                         priv->viu.vd1_afbc_body_addr = 0;
 699                 } else {
 700                         /* Default mode is 4k per superblock */
 701                         unsigned long block_size = 4096;
 702                         unsigned long body_size;
 703
 704                         /* 8bit mem saving mode is 3072bytes per superblock */
 705                         if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE)
 706                                 block_size = 3072;
 707
 708                         body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) *
 709                                     (ALIGN(priv->viu.vd1_height0, 32) / 32) *
 710                                     block_size;
 711
 712                         priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4;
 713                         /* Header is after body content */
 714                         priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 +
 715                                                         body_size) >> 4;
 716                 }
 717         }
 718
 719         priv->viu.vd1_enabled = true;
 720
 721         spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 722
 723         DRM_DEBUG_DRIVER("\n");
 724 }
 725
 726 static void meson_overlay_atomic_disable(struct drm_plane *plane,
 727                                        struct drm_atomic_state *state)
 728 {
 729         struct meson_overlay *meson_overlay = to_meson_overlay(plane);
 730         struct meson_drm *priv = meson_overlay->priv;
 731
 732         DRM_DEBUG_DRIVER("\n");
 733
 734         priv->viu.vd1_enabled = false;
 735
 736         /* Disable VD1 */
 737         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 738                 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
 739                 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
 740                 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
 741                 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0));
 742         } else
 743                 writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0,
 744                                     priv->io_base + _REG(VPP_MISC));
 745
 746 }
 747
 748 static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = {
 749         .atomic_check   = meson_overlay_atomic_check,
 750         .atomic_disable = meson_overlay_atomic_disable,
 751         .atomic_update  = meson_overlay_atomic_update,
 752 };
 753
 754 static bool meson_overlay_format_mod_supported(struct drm_plane *plane,
 755                                                u32 format, u64 modifier)
 756 {
 757         if (modifier == DRM_FORMAT_MOD_LINEAR &&
 758             format != DRM_FORMAT_YUV420_8BIT &&
 759             format != DRM_FORMAT_YUV420_10BIT)
 760                 return true;
 761
 762         if ((modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
 763                         DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
 764                 unsigned int layout = modifier &
 765                         DRM_FORMAT_MOD_AMLOGIC_FBC(
 766                                 __fourcc_mod_amlogic_layout_mask, 0);
 767                 unsigned int options =
 768                         (modifier >> __fourcc_mod_amlogic_options_shift) &
 769                         __fourcc_mod_amlogic_options_mask;
 770
 771                 if (format != DRM_FORMAT_YUV420_8BIT &&
 772                     format != DRM_FORMAT_YUV420_10BIT) {
 773                         DRM_DEBUG_KMS("%llx invalid format 0x%08x\n",
 774                                       modifier, format);
 775                         return false;
 776                 }
 777
 778                 if (layout != AMLOGIC_FBC_LAYOUT_BASIC &&
 779                     layout != AMLOGIC_FBC_LAYOUT_SCATTER) {
 780                         DRM_DEBUG_KMS("%llx invalid layout %x\n",
 781                                       modifier, layout);
 782                         return false;
 783                 }
 784
 785                 if (options &&
 786                     options != AMLOGIC_FBC_OPTION_MEM_SAVING) {
 787                         DRM_DEBUG_KMS("%llx invalid layout %x\n",
 788                                       modifier, layout);
 789                         return false;
 790                 }
 791
 792                 return true;
 793         }
 794
 795         DRM_DEBUG_KMS("invalid modifier %llx for format 0x%08x\n",
 796                       modifier, format);
 797
 798         return false;
 799 }
 800
 801 static const struct drm_plane_funcs meson_overlay_funcs = {
 802         .update_plane           = drm_atomic_helper_update_plane,
 803         .disable_plane          = drm_atomic_helper_disable_plane,
 804         .destroy                = drm_plane_cleanup,
 805         .reset                  = drm_atomic_helper_plane_reset,
 806         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 807         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 808         .format_mod_supported   = meson_overlay_format_mod_supported,
 809 };
 810
 811 static const uint32_t supported_drm_formats[] = {
 812         DRM_FORMAT_YUYV,
 813         DRM_FORMAT_NV12,
 814         DRM_FORMAT_NV21,
 815         DRM_FORMAT_YUV444,
 816         DRM_FORMAT_YUV422,
 817         DRM_FORMAT_YUV420,
 818         DRM_FORMAT_YUV411,
 819         DRM_FORMAT_YUV410,
 820         DRM_FORMAT_YUV420_8BIT, /* Amlogic FBC Only */
 821         DRM_FORMAT_YUV420_10BIT, /* Amlogic FBC Only */
 822 };
 823
 824 static const uint64_t format_modifiers[] = {
 825         DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,
 826                                    AMLOGIC_FBC_OPTION_MEM_SAVING),
 827         DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC,
 828                                    AMLOGIC_FBC_OPTION_MEM_SAVING),
 829         DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 0),
 830         DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0),
 831         DRM_FORMAT_MOD_LINEAR,
 832         DRM_FORMAT_MOD_INVALID,
 833 };
 834
 835 int meson_overlay_create(struct meson_drm *priv)
 836 {
 837         struct meson_overlay *meson_overlay;
 838         struct drm_plane *plane;
 839
 840         DRM_DEBUG_DRIVER("\n");
 841
 842         meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay),
 843                                    GFP_KERNEL);
 844         if (!meson_overlay)
 845                 return -ENOMEM;
 846
 847         meson_overlay->priv = priv;
 848         plane = &meson_overlay->base;
 849
 850         drm_universal_plane_init(priv->drm, plane, 0xFF,
 851                                  &meson_overlay_funcs,
 852                                  supported_drm_formats,
 853                                  ARRAY_SIZE(supported_drm_formats),
 854                                  format_modifiers,
 855                                  DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane");
 856
 857         drm_plane_helper_add(plane, &meson_overlay_helper_funcs);
 858
 859         /* For now, VD Overlay plane is always on the back */
 860         drm_plane_create_zpos_immutable_property(plane, 0);
 861
 862         priv->overlay_plane = plane;
 863
 864         DRM_DEBUG_DRIVER("\n");
 865
 866         return 0;
 867 }