drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <[email protected]>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/display/drm_hdmi_helper.h>
  35 #include <drm/display/drm_hdmi_state_helper.h>
  36 #include <drm/display/drm_scdc_helper.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_drv.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41 #include <drm/drm_simple_kms_helper.h>
  42 #include <linux/clk.h>
  43 #include <linux/component.h>
  44 #include <linux/gpio/consumer.h>
  45 #include <linux/i2c.h>
  46 #include <linux/of.h>
  47 #include <linux/of_address.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/rational.h>
  50 #include <linux/reset.h>
  51 #include <sound/dmaengine_pcm.h>
  52 #include <sound/hdmi-codec.h>
  53 #include <sound/pcm_drm_eld.h>
  54 #include <sound/pcm_params.h>
  55 #include <sound/soc.h>
  56 #include "media/cec.h"
  57 #include "vc4_drv.h"
  58 #include "vc4_hdmi.h"
  59 #include "vc4_hdmi_regs.h"
  60 #include "vc4_regs.h"
  61
  62 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  63 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  64 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  65 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  66 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  67 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  68
  69 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  70 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  71 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  72 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  73
  74 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  75 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  76 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  77 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  78 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  79 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  80
  81 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  82 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  83
  84 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  85 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  86 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  87 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  90
  91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  93
  94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  96
  97 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  98
  99 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
 101
 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK   VC4_MASK(7, 0)
 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE     BIT(0)
 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE   BIT(4)
 105
 106 # define VC4_HD_M_SW_RST                        BIT(2)
 107 # define VC4_HD_M_ENABLE                        BIT(0)
 108
 109 #define HSM_MIN_CLOCK_FREQ      120000000
 110 #define CEC_CLOCK_FREQ 40000
 111
 112 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 113
 114 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
 115 {
 116         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 117
 118         lockdep_assert_held(&vc4_hdmi->mutex);
 119
 120         if (!display->is_hdmi)
 121                 return false;
 122
 123         if (!display->hdmi.scdc.supported ||
 124             !display->hdmi.scdc.scrambling.supported)
 125                 return false;
 126
 127         return true;
 128 }
 129
 130 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 131                                            unsigned int bpc,
 132                                            enum hdmi_colorspace fmt)
 133 {
 134         unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
 135
 136         return clock > HDMI_14_MAX_TMDS_CLK;
 137 }
 138
 139 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 140 {
 141         struct drm_debugfs_entry *entry = m->private;
 142         struct vc4_hdmi *vc4_hdmi = entry->file.data;
 143         struct drm_device *drm = vc4_hdmi->connector.dev;
 144         struct drm_printer p = drm_seq_file_printer(m);
 145         int idx;
 146
 147         if (!drm_dev_enter(drm, &idx))
 148                 return -ENODEV;
 149
 150         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 151
 152         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 153         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 154         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 155         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 156         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 157         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 158         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 159         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 160
 161         pm_runtime_put(&vc4_hdmi->pdev->dev);
 162
 163         drm_dev_exit(idx);
 164
 165         return 0;
 166 }
 167
 168 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 169 {
 170         struct drm_device *drm = vc4_hdmi->connector.dev;
 171         unsigned long flags;
 172         int idx;
 173
 174         /*
 175          * We can be called by our bind callback, when the
 176          * connector->dev pointer might not be initialised yet.
 177          */
 178         if (drm && !drm_dev_enter(drm, &idx))
 179                 return;
 180
 181         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 182
 183         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 184         udelay(1);
 185         HDMI_WRITE(HDMI_M_CTL, 0);
 186
 187         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 188
 189         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 190                    VC4_HDMI_SW_RESET_HDMI |
 191                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 192
 193         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 194
 195         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 196
 197         if (drm)
 198                 drm_dev_exit(idx);
 199 }
 200
 201 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 202 {
 203         struct drm_device *drm = vc4_hdmi->connector.dev;
 204         unsigned long flags;
 205         int idx;
 206
 207         /*
 208          * We can be called by our bind callback, when the
 209          * connector->dev pointer might not be initialised yet.
 210          */
 211         if (drm && !drm_dev_enter(drm, &idx))
 212                 return;
 213
 214         reset_control_reset(vc4_hdmi->reset);
 215
 216         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 217
 218         HDMI_WRITE(HDMI_DVP_CTL, 0);
 219
 220         HDMI_WRITE(HDMI_CLOCK_STOP,
 221                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 222
 223         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 224
 225         if (drm)
 226                 drm_dev_exit(idx);
 227 }
 228
 229 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 230 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 231 {
 232         struct drm_device *drm = vc4_hdmi->connector.dev;
 233         unsigned long cec_rate;
 234         unsigned long flags;
 235         u16 clk_cnt;
 236         u32 value;
 237         int idx;
 238
 239         /*
 240          * This function is called by our runtime_resume implementation
 241          * and thus at bind time, when we haven't registered our
 242          * connector yet and thus don't have a pointer to the DRM
 243          * device.
 244          */
 245         if (drm && !drm_dev_enter(drm, &idx))
 246                 return;
 247
 248         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 249
 250         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 251
 252         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 253         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 254
 255         /*
 256          * Set the clock divider: the hsm_clock rate and this divider
 257          * setting will give a 40 kHz CEC clock.
 258          */
 259         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 260         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 261         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 262
 263         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 264
 265         if (drm)
 266                 drm_dev_exit(idx);
 267 }
 268 #else
 269 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 270 #endif
 271
 272 static int reset_pipe(struct drm_crtc *crtc,
 273                         struct drm_modeset_acquire_ctx *ctx)
 274 {
 275         struct drm_atomic_state *state;
 276         struct drm_crtc_state *crtc_state;
 277         int ret;
 278
 279         state = drm_atomic_state_alloc(crtc->dev);
 280         if (!state)
 281                 return -ENOMEM;
 282
 283         state->acquire_ctx = ctx;
 284
 285         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 286         if (IS_ERR(crtc_state)) {
 287                 ret = PTR_ERR(crtc_state);
 288                 goto out;
 289         }
 290
 291         crtc_state->connectors_changed = true;
 292
 293         ret = drm_atomic_commit(state);
 294 out:
 295         drm_atomic_state_put(state);
 296
 297         return ret;
 298 }
 299
 300 static int vc4_hdmi_reset_link(struct drm_connector *connector,
 301                                struct drm_modeset_acquire_ctx *ctx)
 302 {
 303         struct drm_device *drm;
 304         struct vc4_hdmi *vc4_hdmi;
 305         struct drm_connector_state *conn_state;
 306         struct drm_crtc_state *crtc_state;
 307         struct drm_crtc *crtc;
 308         bool scrambling_needed;
 309         u8 config;
 310         int ret;
 311
 312         if (!connector)
 313                 return 0;
 314
 315         drm = connector->dev;
 316         ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
 317         if (ret)
 318                 return ret;
 319
 320         conn_state = connector->state;
 321         crtc = conn_state->crtc;
 322         if (!crtc)
 323                 return 0;
 324
 325         ret = drm_modeset_lock(&crtc->mutex, ctx);
 326         if (ret)
 327                 return ret;
 328
 329         crtc_state = crtc->state;
 330         if (!crtc_state->active)
 331                 return 0;
 332
 333         vc4_hdmi = connector_to_vc4_hdmi(connector);
 334         mutex_lock(&vc4_hdmi->mutex);
 335
 336         if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
 337                 mutex_unlock(&vc4_hdmi->mutex);
 338                 return 0;
 339         }
 340
 341         scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
 342                                                            vc4_hdmi->output_bpc,
 343                                                            vc4_hdmi->output_format);
 344         if (!scrambling_needed) {
 345                 mutex_unlock(&vc4_hdmi->mutex);
 346                 return 0;
 347         }
 348
 349         if (conn_state->commit &&
 350             !try_wait_for_completion(&conn_state->commit->hw_done)) {
 351                 mutex_unlock(&vc4_hdmi->mutex);
 352                 return 0;
 353         }
 354
 355         ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
 356         if (ret < 0) {
 357                 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
 358                 mutex_unlock(&vc4_hdmi->mutex);
 359                 return 0;
 360         }
 361
 362         if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
 363                 mutex_unlock(&vc4_hdmi->mutex);
 364                 return 0;
 365         }
 366
 367         mutex_unlock(&vc4_hdmi->mutex);
 368
 369         /*
 370          * HDMI 2.0 says that one should not send scrambled data
 371          * prior to configuring the sink scrambling, and that
 372          * TMDS clock/data transmission should be suspended when
 373          * changing the TMDS clock rate in the sink. So let's
 374          * just do a full modeset here, even though some sinks
 375          * would be perfectly happy if were to just reconfigure
 376          * the SCDC settings on the fly.
 377          */
 378         return reset_pipe(crtc, ctx);
 379 }
 380
 381 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
 382                                     struct drm_modeset_acquire_ctx *ctx,
 383                                     enum drm_connector_status status)
 384 {
 385         struct drm_connector *connector = &vc4_hdmi->connector;
 386         const struct drm_edid *drm_edid;
 387         int ret;
 388
 389         /*
 390          * NOTE: This function should really be called with vc4_hdmi->mutex
 391          * held, but doing so results in reentrancy issues since
 392          * cec_s_phys_addr() might call .adap_enable, which leads to that
 393          * funtion being called with our mutex held.
 394          *
 395          * A similar situation occurs with vc4_hdmi_reset_link() that
 396          * will call into our KMS hooks if the scrambling was enabled.
 397          *
 398          * Concurrency isn't an issue at the moment since we don't share
 399          * any state with any of the other frameworks so we can ignore
 400          * the lock for now.
 401          */
 402
 403         if (status == connector_status_disconnected) {
 404                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 405                 return;
 406         }
 407
 408         drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
 409
 410         drm_edid_connector_update(connector, drm_edid);
 411         cec_s_phys_addr(vc4_hdmi->cec_adap,
 412                         connector->display_info.source_physical_address, false);
 413
 414         if (!drm_edid)
 415                 return;
 416
 417         drm_edid_free(drm_edid);
 418
 419         for (;;) {
 420                 ret = vc4_hdmi_reset_link(connector, ctx);
 421                 if (ret == -EDEADLK) {
 422                         drm_modeset_backoff(ctx);
 423                         continue;
 424                 }
 425
 426                 break;
 427         }
 428 }
 429
 430 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
 431                                          struct drm_modeset_acquire_ctx *ctx,
 432                                          bool force)
 433 {
 434         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 435         enum drm_connector_status status = connector_status_disconnected;
 436         int ret;
 437
 438         /*
 439          * NOTE: This function should really take vc4_hdmi->mutex, but
 440          * doing so results in reentrancy issues since
 441          * vc4_hdmi_handle_hotplug() can call into other functions that
 442          * would take the mutex while it's held here.
 443          *
 444          * Concurrency isn't an issue at the moment since we don't share
 445          * any state with any of the other frameworks so we can ignore
 446          * the lock for now.
 447          */
 448
 449         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 450         if (ret) {
 451                 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
 452                              ret);
 453                 return connector_status_unknown;
 454         }
 455
 456         if (vc4_hdmi->hpd_gpio) {
 457                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 458                         status = connector_status_connected;
 459         } else {
 460                 if (vc4_hdmi->variant->hp_detect &&
 461                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 462                         status = connector_status_connected;
 463         }
 464
 465         vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
 466         pm_runtime_put(&vc4_hdmi->pdev->dev);
 467
 468         return status;
 469 }
 470
 471 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 472 {
 473         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 474         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
 475         const struct drm_edid *drm_edid;
 476         int ret = 0;
 477
 478         /*
 479          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
 480          * results in reentrancy issues since cec_s_phys_addr() might call
 481          * .adap_enable, which leads to that funtion being called with our mutex
 482          * held.
 483          *
 484          * Concurrency isn't an issue at the moment since we don't share
 485          * any state with any of the other frameworks so we can ignore
 486          * the lock for now.
 487          */
 488
 489         drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
 490         drm_edid_connector_update(connector, drm_edid);
 491         cec_s_phys_addr(vc4_hdmi->cec_adap,
 492                         connector->display_info.source_physical_address, false);
 493         if (!drm_edid)
 494                 return 0;
 495
 496         ret = drm_edid_connector_add_modes(connector);
 497         drm_edid_free(drm_edid);
 498
 499         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
 500                 struct drm_device *drm = connector->dev;
 501                 const struct drm_display_mode *mode;
 502
 503                 list_for_each_entry(mode, &connector->probed_modes, head) {
 504                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) {
 505                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 506                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 507                         }
 508                 }
 509         }
 510
 511         return ret;
 512 }
 513
 514 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 515                                            struct drm_atomic_state *state)
 516 {
 517         struct drm_connector_state *old_state =
 518                 drm_atomic_get_old_connector_state(state, connector);
 519         struct drm_connector_state *new_state =
 520                 drm_atomic_get_new_connector_state(state, connector);
 521         struct drm_crtc *crtc = new_state->crtc;
 522
 523         if (!crtc)
 524                 return 0;
 525
 526         if (old_state->tv.margins.left != new_state->tv.margins.left ||
 527             old_state->tv.margins.right != new_state->tv.margins.right ||
 528             old_state->tv.margins.top != new_state->tv.margins.top ||
 529             old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
 530                 struct drm_crtc_state *crtc_state;
 531                 int ret;
 532
 533                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 534                 if (IS_ERR(crtc_state))
 535                         return PTR_ERR(crtc_state);
 536
 537                 /*
 538                  * Strictly speaking, we should be calling
 539                  * drm_atomic_helper_check_planes() after our call to
 540                  * drm_atomic_add_affected_planes(). However, the
 541                  * connector atomic_check is called as part of
 542                  * drm_atomic_helper_check_modeset() that already
 543                  * happens before a call to
 544                  * drm_atomic_helper_check_planes() in
 545                  * drm_atomic_helper_check().
 546                  */
 547                 ret = drm_atomic_add_affected_planes(state, crtc);
 548                 if (ret)
 549                         return ret;
 550         }
 551
 552         if (old_state->colorspace != new_state->colorspace) {
 553                 struct drm_crtc_state *crtc_state;
 554
 555                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 556                 if (IS_ERR(crtc_state))
 557                         return PTR_ERR(crtc_state);
 558
 559                 crtc_state->mode_changed = true;
 560         }
 561
 562         return drm_atomic_helper_connector_hdmi_check(connector, state);
 563 }
 564
 565 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 566 {
 567         drm_atomic_helper_connector_reset(connector);
 568         __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
 569         drm_atomic_helper_connector_tv_margins_reset(connector);
 570 }
 571
 572 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 573         .fill_modes = drm_helper_probe_single_connector_modes,
 574         .reset = vc4_hdmi_connector_reset,
 575         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 576         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 577 };
 578
 579 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 580         .detect_ctx = vc4_hdmi_connector_detect_ctx,
 581         .get_modes = vc4_hdmi_connector_get_modes,
 582         .atomic_check = vc4_hdmi_connector_atomic_check,
 583 };
 584
 585 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs;
 586
 587 static int vc4_hdmi_connector_init(struct drm_device *dev,
 588                                    struct vc4_hdmi *vc4_hdmi)
 589 {
 590         struct drm_connector *connector = &vc4_hdmi->connector;
 591         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 592         unsigned int max_bpc = 8;
 593         int ret;
 594
 595         if (vc4_hdmi->variant->supports_hdr)
 596                 max_bpc = 12;
 597
 598         ret = drmm_connector_hdmi_init(dev, connector,
 599                                        "Broadcom", "Videocore",
 600                                        &vc4_hdmi_connector_funcs,
 601                                        &vc4_hdmi_hdmi_connector_funcs,
 602                                        DRM_MODE_CONNECTOR_HDMIA,
 603                                        vc4_hdmi->ddc,
 604                                        BIT(HDMI_COLORSPACE_RGB) |
 605                                        BIT(HDMI_COLORSPACE_YUV422) |
 606                                        BIT(HDMI_COLORSPACE_YUV444),
 607                                        max_bpc);
 608         if (ret)
 609                 return ret;
 610
 611         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 612
 613         /*
 614          * Some of the properties below require access to state, like bpc.
 615          * Allocate some default initial connector state with our reset helper.
 616          */
 617         if (connector->funcs->reset)
 618                 connector->funcs->reset(connector);
 619
 620         /* Create and attach TV margin props to this connector. */
 621         ret = drm_mode_create_tv_margin_properties(dev);
 622         if (ret)
 623                 return ret;
 624
 625         ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
 626         if (ret)
 627                 return ret;
 628
 629         drm_connector_attach_colorspace_property(connector);
 630         drm_connector_attach_tv_margin_properties(connector);
 631
 632         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 633                              DRM_CONNECTOR_POLL_DISCONNECT);
 634
 635         connector->interlace_allowed = 1;
 636         connector->doublescan_allowed = 0;
 637         connector->stereo_allowed = 1;
 638
 639         ret = drm_connector_attach_broadcast_rgb_property(connector);
 640         if (ret)
 641                 return ret;
 642
 643         drm_connector_attach_encoder(connector, encoder);
 644
 645         return 0;
 646 }
 647
 648 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi,
 649                                 enum hdmi_infoframe_type type,
 650                                 bool poll)
 651 {
 652         struct drm_device *drm = vc4_hdmi->connector.dev;
 653         u32 packet_id = type - 0x80;
 654         unsigned long flags;
 655         int ret = 0;
 656         int idx;
 657
 658         if (!drm_dev_enter(drm, &idx))
 659                 return -ENODEV;
 660
 661         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 662         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 663                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 664         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 665
 666         if (poll) {
 667                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 668                                  BIT(packet_id)), 100);
 669         }
 670
 671         drm_dev_exit(idx);
 672         return ret;
 673 }
 674
 675 static int vc4_hdmi_write_infoframe(struct drm_connector *connector,
 676                                     enum hdmi_infoframe_type type,
 677                                     const u8 *infoframe, size_t len)
 678 {
 679         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 680         struct drm_device *drm = connector->dev;
 681         u32 packet_id = type - 0x80;
 682         const struct vc4_hdmi_register *ram_packet_start =
 683                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 684         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 685         u32 packet_reg_next = ram_packet_start->offset +
 686                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 687         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 688                                                        ram_packet_start->reg);
 689         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 690         unsigned long flags;
 691         ssize_t i;
 692         int ret;
 693         int idx;
 694
 695         if (!drm_dev_enter(drm, &idx))
 696                 return 0;
 697
 698         if (len > sizeof(buffer)) {
 699                 ret = -ENOMEM;
 700                 goto out;
 701         }
 702
 703         memcpy(buffer, infoframe, len);
 704
 705         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 706                     VC4_HDMI_RAM_PACKET_ENABLE),
 707                   "Packet RAM has to be on to store the packet.");
 708
 709         ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
 710         if (ret) {
 711                 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
 712                 goto out;
 713         }
 714
 715         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 716
 717         for (i = 0; i < len; i += 7) {
 718                 writel(buffer[i + 0] << 0 |
 719                        buffer[i + 1] << 8 |
 720                        buffer[i + 2] << 16,
 721                        base + packet_reg);
 722                 packet_reg += 4;
 723
 724                 writel(buffer[i + 3] << 0 |
 725                        buffer[i + 4] << 8 |
 726                        buffer[i + 5] << 16 |
 727                        buffer[i + 6] << 24,
 728                        base + packet_reg);
 729                 packet_reg += 4;
 730         }
 731
 732         /*
 733          * clear remainder of packet ram as it's included in the
 734          * infoframe and triggers a checksum error on hdmi analyser
 735          */
 736         for (; packet_reg < packet_reg_next; packet_reg += 4)
 737                 writel(0, base + packet_reg);
 738
 739         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 740                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 741
 742         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 743
 744         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 745                         BIT(packet_id)), 100);
 746         if (ret)
 747                 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
 748
 749 out:
 750         drm_dev_exit(idx);
 751         return ret;
 752 }
 753
 754 #define SCRAMBLING_POLLING_DELAY_MS     1000
 755
 756 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 757 {
 758         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 759         struct drm_connector *connector = &vc4_hdmi->connector;
 760         struct drm_device *drm = connector->dev;
 761         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 762         unsigned long flags;
 763         int idx;
 764
 765         lockdep_assert_held(&vc4_hdmi->mutex);
 766
 767         if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
 768                 return;
 769
 770         if (!vc4_hdmi_mode_needs_scrambling(mode,
 771                                             vc4_hdmi->output_bpc,
 772                                             vc4_hdmi->output_format))
 773                 return;
 774
 775         if (!drm_dev_enter(drm, &idx))
 776                 return;
 777
 778         drm_scdc_set_high_tmds_clock_ratio(connector, true);
 779         drm_scdc_set_scrambling(connector, true);
 780
 781         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 782         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 783                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 784         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 785
 786         drm_dev_exit(idx);
 787
 788         vc4_hdmi->scdc_enabled = true;
 789
 790         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 791                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 792 }
 793
 794 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 795 {
 796         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 797         struct drm_connector *connector = &vc4_hdmi->connector;
 798         struct drm_device *drm = connector->dev;
 799         unsigned long flags;
 800         int idx;
 801
 802         lockdep_assert_held(&vc4_hdmi->mutex);
 803
 804         if (!vc4_hdmi->scdc_enabled)
 805                 return;
 806
 807         vc4_hdmi->scdc_enabled = false;
 808
 809         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 810                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 811
 812         if (!drm_dev_enter(drm, &idx))
 813                 return;
 814
 815         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 816         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 817                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 818         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 819
 820         drm_scdc_set_scrambling(connector, false);
 821         drm_scdc_set_high_tmds_clock_ratio(connector, false);
 822
 823         drm_dev_exit(idx);
 824 }
 825
 826 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 827 {
 828         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 829                                                  struct vc4_hdmi,
 830                                                  scrambling_work);
 831         struct drm_connector *connector = &vc4_hdmi->connector;
 832
 833         if (drm_scdc_get_scrambling_status(connector))
 834                 return;
 835
 836         drm_scdc_set_high_tmds_clock_ratio(connector, true);
 837         drm_scdc_set_scrambling(connector, true);
 838
 839         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 840                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 841 }
 842
 843 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 844                                                struct drm_atomic_state *state)
 845 {
 846         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 847         struct drm_device *drm = vc4_hdmi->connector.dev;
 848         unsigned long flags;
 849         int idx;
 850
 851         mutex_lock(&vc4_hdmi->mutex);
 852
 853         vc4_hdmi->packet_ram_enabled = false;
 854
 855         if (!drm_dev_enter(drm, &idx))
 856                 goto out;
 857
 858         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 859
 860         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 861
 862         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 863
 864         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 865
 866         mdelay(1);
 867
 868         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 869         HDMI_WRITE(HDMI_VID_CTL,
 870                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 871         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 872
 873         vc4_hdmi_disable_scrambling(encoder);
 874
 875         drm_dev_exit(idx);
 876
 877 out:
 878         mutex_unlock(&vc4_hdmi->mutex);
 879 }
 880
 881 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 882                                                  struct drm_atomic_state *state)
 883 {
 884         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 885         struct drm_device *drm = vc4_hdmi->connector.dev;
 886         unsigned long flags;
 887         int ret;
 888         int idx;
 889
 890         mutex_lock(&vc4_hdmi->mutex);
 891
 892         if (!drm_dev_enter(drm, &idx))
 893                 goto out;
 894
 895         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 896         HDMI_WRITE(HDMI_VID_CTL,
 897                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 898         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 899
 900         if (vc4_hdmi->variant->phy_disable)
 901                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 902
 903         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 904         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 905
 906         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 907         if (ret < 0)
 908                 drm_err(drm, "Failed to release power domain: %d\n", ret);
 909
 910         drm_dev_exit(idx);
 911
 912 out:
 913         mutex_unlock(&vc4_hdmi->mutex);
 914 }
 915
 916 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 917                                struct drm_connector_state *state,
 918                                const struct drm_display_mode *mode)
 919 {
 920         struct drm_device *drm = vc4_hdmi->connector.dev;
 921         unsigned long flags;
 922         u32 csc_ctl;
 923         int idx;
 924
 925         if (!drm_dev_enter(drm, &idx))
 926                 return;
 927
 928         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 929
 930         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 931                                 VC4_HD_CSC_CTL_ORDER);
 932
 933         if (state->hdmi.is_limited_range) {
 934                 /* CEA VICs other than #1 requre limited range RGB
 935                  * output unless overridden by an AVI infoframe.
 936                  * Apply a colorspace conversion to squash 0-255 down
 937                  * to 16-235.  The matrix here is:
 938                  *
 939                  * [ 0      0      0.8594 16]
 940                  * [ 0      0.8594 0      16]
 941                  * [ 0.8594 0      0      16]
 942                  * [ 0      0      0       1]
 943                  */
 944                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 945                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 946                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 947                                          VC4_HD_CSC_CTL_MODE);
 948
 949                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 950                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 951                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 952                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 953                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 954                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 955         }
 956
 957         /* The RGB order applies even when CSC is disabled. */
 958         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 959
 960         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 961
 962         drm_dev_exit(idx);
 963 }
 964
 965 /*
 966  * Matrices for (internal) RGB to RGB output.
 967  *
 968  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
 969  */
 970 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
 971         {
 972                 /*
 973                  * Full range - unity
 974                  *
 975                  * [ 1      0      0      0]
 976                  * [ 0      1      0      0]
 977                  * [ 0      0      1      0]
 978                  */
 979                 { 0x2000, 0x0000, 0x0000, 0x0000 },
 980                 { 0x0000, 0x2000, 0x0000, 0x0000 },
 981                 { 0x0000, 0x0000, 0x2000, 0x0000 },
 982         },
 983         {
 984                 /*
 985                  * Limited range
 986                  *
 987                  * CEA VICs other than #1 require limited range RGB
 988                  * output unless overridden by an AVI infoframe. Apply a
 989                  * colorspace conversion to squash 0-255 down to 16-235.
 990                  * The matrix here is:
 991                  *
 992                  * [ 0.8594 0      0      16]
 993                  * [ 0      0.8594 0      16]
 994                  * [ 0      0      0.8594 16]
 995                  */
 996                 { 0x1b80, 0x0000, 0x0000, 0x0400 },
 997                 { 0x0000, 0x1b80, 0x0000, 0x0400 },
 998                 { 0x0000, 0x0000, 0x1b80, 0x0400 },
 999         },
1000 };
1001
1002 /*
1003  * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1004  *
1005  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1006  */
1007 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1008         {
1009                 /*
1010                  * Full Range
1011                  *
1012                  * [  0.299000  0.587000  0.114000  0   ]
1013                  * [ -0.168736 -0.331264  0.500000  128 ]
1014                  * [  0.500000 -0.418688 -0.081312  128 ]
1015                  */
1016                 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1017                 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1018                 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1019         },
1020         {
1021                 /* Limited Range
1022                  *
1023                  * [  0.255785  0.502160  0.097523  16  ]
1024                  * [ -0.147644 -0.289856  0.437500  128 ]
1025                  * [  0.437500 -0.366352 -0.071148  128 ]
1026                  */
1027                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1028                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1029                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1030         },
1031 };
1032
1033 /*
1034  * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1035  *
1036  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1037  */
1038 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1039         {
1040                 /*
1041                  * Full Range
1042                  *
1043                  * [  0.212600  0.715200  0.072200  0   ]
1044                  * [ -0.114572 -0.385428  0.500000  128 ]
1045                  * [  0.500000 -0.454153 -0.045847  128 ]
1046                  */
1047                 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1048                 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1049                 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1050         },
1051         {
1052                 /*
1053                  * Limited Range
1054                  *
1055                  * [  0.181906  0.611804  0.061758  16  ]
1056                  * [ -0.100268 -0.337232  0.437500  128 ]
1057                  * [  0.437500 -0.397386 -0.040114  128 ]
1058                  */
1059                 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1060                 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1061                 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1062         },
1063 };
1064
1065 /*
1066  * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1067  *
1068  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1069  */
1070 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1071         {
1072                 /*
1073                  * Full Range
1074                  *
1075                  * [  0.262700  0.678000  0.059300  0   ]
1076                  * [ -0.139630 -0.360370  0.500000  128 ]
1077                  * [  0.500000 -0.459786 -0.040214  128 ]
1078                  */
1079                 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1080                 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1081                 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1082         },
1083         {
1084                 /* Limited Range
1085                  *
1086                  * [  0.224732  0.580008  0.050729  16  ]
1087                  * [ -0.122176 -0.315324  0.437500  128 ]
1088                  * [  0.437500 -0.402312 -0.035188  128 ]
1089                  */
1090                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1091                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1092                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1093         },
1094 };
1095
1096 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1097                                     const u16 coeffs[3][4])
1098 {
1099         lockdep_assert_held(&vc4_hdmi->hw_lock);
1100
1101         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1102         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1103         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1104         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1105         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1106         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1107 }
1108
1109 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1110                                          const u16 coeffs[3][4])
1111 {
1112         lockdep_assert_held(&vc4_hdmi->hw_lock);
1113
1114         /* YUV444 needs the CSC matrices using the channels in a different order */
1115         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1116         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1117         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1118         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1119         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1120         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1121 }
1122
1123 static const u16
1124 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1125 {
1126         switch (colorspace) {
1127         case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1128         case DRM_MODE_COLORIMETRY_XVYCC_601:
1129         case DRM_MODE_COLORIMETRY_SYCC_601:
1130         case DRM_MODE_COLORIMETRY_OPYCC_601:
1131         case DRM_MODE_COLORIMETRY_BT601_YCC:
1132                 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1133
1134         default:
1135         case DRM_MODE_COLORIMETRY_NO_DATA:
1136         case DRM_MODE_COLORIMETRY_BT709_YCC:
1137         case DRM_MODE_COLORIMETRY_XVYCC_709:
1138         case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1139         case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1140                 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1141
1142         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1143         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1144         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1145         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1146         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1147                 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1148         }
1149 }
1150
1151 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1152                                struct drm_connector_state *state,
1153                                const struct drm_display_mode *mode)
1154 {
1155         struct drm_device *drm = vc4_hdmi->connector.dev;
1156         unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0;
1157         unsigned long flags;
1158         const u16 (*csc)[4];
1159         u32 if_cfg = 0;
1160         u32 if_xbar = 0x543210;
1161         u32 csc_chan_ctl = 0;
1162         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1163                                                                VC5_MT_CP_CSC_CTL_MODE);
1164         int idx;
1165
1166         if (!drm_dev_enter(drm, &idx))
1167                 return;
1168
1169         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1170
1171         switch (state->hdmi.output_format) {
1172         case HDMI_COLORSPACE_YUV444:
1173                 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1174
1175                 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1176                 break;
1177
1178         case HDMI_COLORSPACE_YUV422:
1179                 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1180
1181                 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1182                                          VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1183                         VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1184                         VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1185
1186                 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1187                                               VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1188
1189                 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1190                                         VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1191
1192                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1193                 break;
1194
1195         case HDMI_COLORSPACE_RGB:
1196                 if_xbar = 0x354021;
1197
1198                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1199                 break;
1200
1201         default:
1202                 break;
1203         }
1204
1205         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1206         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1207         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1208         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1209
1210         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1211
1212         drm_dev_exit(idx);
1213 }
1214
1215 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1216                                  struct drm_connector_state *state,
1217                                  const struct drm_display_mode *mode)
1218 {
1219         struct drm_device *drm = vc4_hdmi->connector.dev;
1220         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1221         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1222         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1223         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1224         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1225                                    VC4_HDMI_VERTA_VSP) |
1226                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1227                                    VC4_HDMI_VERTA_VFP) |
1228                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1229         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1230                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1231                                    interlaced,
1232                                    VC4_HDMI_VERTB_VBP));
1233         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1234                           VC4_SET_FIELD(mode->crtc_vtotal -
1235                                         mode->crtc_vsync_end,
1236                                         VC4_HDMI_VERTB_VBP));
1237         unsigned long flags;
1238         u32 reg;
1239         int idx;
1240
1241         if (!drm_dev_enter(drm, &idx))
1242                 return;
1243
1244         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1245
1246         HDMI_WRITE(HDMI_HORZA,
1247                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1248                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1249                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1250                                  VC4_HDMI_HORZA_HAP));
1251
1252         HDMI_WRITE(HDMI_HORZB,
1253                    VC4_SET_FIELD((mode->htotal -
1254                                   mode->hsync_end) * pixel_rep,
1255                                  VC4_HDMI_HORZB_HBP) |
1256                    VC4_SET_FIELD((mode->hsync_end -
1257                                   mode->hsync_start) * pixel_rep,
1258                                  VC4_HDMI_HORZB_HSP) |
1259                    VC4_SET_FIELD((mode->hsync_start -
1260                                   mode->hdisplay) * pixel_rep,
1261                                  VC4_HDMI_HORZB_HFP));
1262
1263         HDMI_WRITE(HDMI_VERTA0, verta);
1264         HDMI_WRITE(HDMI_VERTA1, verta);
1265
1266         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1267         HDMI_WRITE(HDMI_VERTB1, vertb);
1268
1269         reg = HDMI_READ(HDMI_MISC_CONTROL);
1270         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1271         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1272         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1273
1274         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1275
1276         drm_dev_exit(idx);
1277 }
1278
1279 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1280                                  struct drm_connector_state *state,
1281                                  const struct drm_display_mode *mode)
1282 {
1283         struct drm_device *drm = vc4_hdmi->connector.dev;
1284         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1285         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1286         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1287         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1288         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1289                                    VC5_HDMI_VERTA_VSP) |
1290                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1291                                    VC5_HDMI_VERTA_VFP) |
1292                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1293         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1294                                    VC5_HDMI_VERTB_VSPO) |
1295                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1296                                    interlaced,
1297                                    VC4_HDMI_VERTB_VBP));
1298         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1299                           VC4_SET_FIELD(mode->crtc_vtotal -
1300                                         mode->crtc_vsync_end,
1301                                         VC4_HDMI_VERTB_VBP));
1302         unsigned long flags;
1303         unsigned char gcp;
1304         u32 reg;
1305         int idx;
1306
1307         if (!drm_dev_enter(drm, &idx))
1308                 return;
1309
1310         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1311
1312         HDMI_WRITE(HDMI_HORZA,
1313                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1314                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1315                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1316                                  VC5_HDMI_HORZA_HAP) |
1317                    VC4_SET_FIELD((mode->hsync_start -
1318                                   mode->hdisplay) * pixel_rep,
1319                                  VC5_HDMI_HORZA_HFP));
1320
1321         HDMI_WRITE(HDMI_HORZB,
1322                    VC4_SET_FIELD((mode->htotal -
1323                                   mode->hsync_end) * pixel_rep,
1324                                  VC5_HDMI_HORZB_HBP) |
1325                    VC4_SET_FIELD((mode->hsync_end -
1326                                   mode->hsync_start) * pixel_rep,
1327                                  VC5_HDMI_HORZB_HSP));
1328
1329         HDMI_WRITE(HDMI_VERTA0, verta);
1330         HDMI_WRITE(HDMI_VERTA1, verta);
1331
1332         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1333         HDMI_WRITE(HDMI_VERTB1, vertb);
1334
1335         switch (state->hdmi.output_bpc) {
1336         case 12:
1337                 gcp = 6;
1338                 break;
1339         case 10:
1340                 gcp = 5;
1341                 break;
1342         case 8:
1343         default:
1344                 gcp = 0;
1345                 break;
1346         }
1347
1348         /*
1349          * YCC422 is always 36-bit and not considered deep colour so
1350          * doesn't signal in GCP.
1351          */
1352         if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) {
1353                 gcp = 0;
1354         }
1355
1356         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1357         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1358                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1359         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1360                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1361         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1362
1363         reg = HDMI_READ(HDMI_GCP_WORD_1);
1364         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1365         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1366         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1367         reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1368         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1369
1370         reg = HDMI_READ(HDMI_GCP_CONFIG);
1371         reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1372         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1373
1374         reg = HDMI_READ(HDMI_MISC_CONTROL);
1375         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1376         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1377         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1378
1379         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1380
1381         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1382
1383         drm_dev_exit(idx);
1384 }
1385
1386 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1387 {
1388         struct drm_device *drm = vc4_hdmi->connector.dev;
1389         unsigned long flags;
1390         u32 drift;
1391         int ret;
1392         int idx;
1393
1394         if (!drm_dev_enter(drm, &idx))
1395                 return;
1396
1397         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1398
1399         drift = HDMI_READ(HDMI_FIFO_CTL);
1400         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1401
1402         HDMI_WRITE(HDMI_FIFO_CTL,
1403                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1404         HDMI_WRITE(HDMI_FIFO_CTL,
1405                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1406
1407         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1408
1409         usleep_range(1000, 1100);
1410
1411         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1412
1413         HDMI_WRITE(HDMI_FIFO_CTL,
1414                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1415         HDMI_WRITE(HDMI_FIFO_CTL,
1416                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1417
1418         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1419
1420         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1421                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1422         WARN_ONCE(ret, "Timeout waiting for "
1423                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1424
1425         drm_dev_exit(idx);
1426 }
1427
1428 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1429                                                 struct drm_atomic_state *state)
1430 {
1431         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1432         struct drm_device *drm = vc4_hdmi->connector.dev;
1433         struct drm_connector *connector = &vc4_hdmi->connector;
1434         struct drm_connector_state *conn_state =
1435                 drm_atomic_get_new_connector_state(state, connector);
1436         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1437         unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate;
1438         unsigned long bvb_rate, hsm_rate;
1439         unsigned long flags;
1440         int ret;
1441         int idx;
1442
1443         mutex_lock(&vc4_hdmi->mutex);
1444
1445         if (!drm_dev_enter(drm, &idx))
1446                 goto out;
1447
1448         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1449         if (ret < 0) {
1450                 drm_err(drm, "Failed to retain power domain: %d\n", ret);
1451                 goto err_dev_exit;
1452         }
1453
1454         /*
1455          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1456          * be faster than pixel clock, infinitesimally faster, tested in
1457          * simulation. Otherwise, exact value is unimportant for HDMI
1458          * operation." This conflicts with bcm2835's vc4 documentation, which
1459          * states HSM's clock has to be at least 108% of the pixel clock.
1460          *
1461          * Real life tests reveal that vc4's firmware statement holds up, and
1462          * users are able to use pixel clocks closer to HSM's, namely for
1463          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1464          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1465          * 162MHz.
1466          *
1467          * Additionally, the AXI clock needs to be at least 25% of
1468          * pixel clock, but HSM ends up being the limiting factor.
1469          */
1470         hsm_rate = max_t(unsigned long,
1471                          HSM_MIN_CLOCK_FREQ,
1472                          div_u64(tmds_char_rate, 100) * 101);
1473         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1474         if (ret) {
1475                 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1476                 goto err_put_runtime_pm;
1477         }
1478
1479         ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1480         if (ret) {
1481                 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1482                 goto err_put_runtime_pm;
1483         }
1484
1485         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1486         if (ret) {
1487                 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1488                 goto err_put_runtime_pm;
1489         }
1490
1491
1492         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1493
1494         if (tmds_char_rate > 297000000)
1495                 bvb_rate = 300000000;
1496         else if (tmds_char_rate > 148500000)
1497                 bvb_rate = 150000000;
1498         else
1499                 bvb_rate = 75000000;
1500
1501         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1502         if (ret) {
1503                 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1504                 goto err_disable_pixel_clock;
1505         }
1506
1507         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1508         if (ret) {
1509                 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1510                 goto err_disable_pixel_clock;
1511         }
1512
1513         if (vc4_hdmi->variant->phy_init)
1514                 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state);
1515
1516         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1517
1518         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1519                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1520                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1521                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1522
1523         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1524
1525         if (vc4_hdmi->variant->set_timings)
1526                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1527
1528         drm_dev_exit(idx);
1529
1530         mutex_unlock(&vc4_hdmi->mutex);
1531
1532         return;
1533
1534 err_disable_pixel_clock:
1535         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1536 err_put_runtime_pm:
1537         pm_runtime_put(&vc4_hdmi->pdev->dev);
1538 err_dev_exit:
1539         drm_dev_exit(idx);
1540 out:
1541         mutex_unlock(&vc4_hdmi->mutex);
1542         return;
1543 }
1544
1545 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1546                                              struct drm_atomic_state *state)
1547 {
1548         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1549         struct drm_device *drm = vc4_hdmi->connector.dev;
1550         struct drm_connector *connector = &vc4_hdmi->connector;
1551         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1552         struct drm_connector_state *conn_state =
1553                 drm_atomic_get_new_connector_state(state, connector);
1554         unsigned long flags;
1555         int idx;
1556
1557         mutex_lock(&vc4_hdmi->mutex);
1558
1559         if (!drm_dev_enter(drm, &idx))
1560                 goto out;
1561
1562         if (vc4_hdmi->variant->csc_setup)
1563                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1564
1565         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1566         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1567         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1568
1569         drm_dev_exit(idx);
1570
1571 out:
1572         mutex_unlock(&vc4_hdmi->mutex);
1573 }
1574
1575 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1576                                               struct drm_atomic_state *state)
1577 {
1578         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1579         struct drm_connector *connector = &vc4_hdmi->connector;
1580         struct drm_device *drm = connector->dev;
1581         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1582         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1583         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1584         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1585         unsigned long flags;
1586         int ret;
1587         int idx;
1588
1589         mutex_lock(&vc4_hdmi->mutex);
1590
1591         if (!drm_dev_enter(drm, &idx))
1592                 goto out;
1593
1594         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1595
1596         HDMI_WRITE(HDMI_VID_CTL,
1597                    VC4_HD_VID_CTL_ENABLE |
1598                    VC4_HD_VID_CTL_CLRRGB |
1599                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1600                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1601                    VC4_HD_VID_CTL_BLANK_INSERT_EN |
1602                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1603                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1604
1605         HDMI_WRITE(HDMI_VID_CTL,
1606                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1607
1608         if (display->is_hdmi) {
1609                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1610                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1611                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1612
1613                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1614
1615                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1616                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1617                 WARN_ONCE(ret, "Timeout waiting for "
1618                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1619         } else {
1620                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1621                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1622                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1623                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1624                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1625                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1626
1627                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1628
1629                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1630                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1631                 WARN_ONCE(ret, "Timeout waiting for "
1632                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1633         }
1634
1635         if (display->is_hdmi) {
1636                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1637
1638                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1639                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1640
1641                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1642                            VC4_HDMI_RAM_PACKET_ENABLE);
1643
1644                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1645                 vc4_hdmi->packet_ram_enabled = true;
1646
1647                 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
1648         }
1649
1650         vc4_hdmi_recenter_fifo(vc4_hdmi);
1651         vc4_hdmi_enable_scrambling(encoder);
1652
1653         drm_dev_exit(idx);
1654
1655 out:
1656         mutex_unlock(&vc4_hdmi->mutex);
1657 }
1658
1659 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1660                                              struct drm_crtc_state *crtc_state,
1661                                              struct drm_connector_state *conn_state)
1662 {
1663         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1664
1665         mutex_lock(&vc4_hdmi->mutex);
1666         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1667                       &crtc_state->adjusted_mode);
1668         vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc;
1669         vc4_hdmi->output_format = conn_state->hdmi.output_format;
1670         mutex_unlock(&vc4_hdmi->mutex);
1671 }
1672
1673 static enum drm_mode_status
1674 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector,
1675                                const struct drm_display_mode *mode,
1676                                unsigned long long clock)
1677 {
1678         const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1679         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1680
1681         if (clock > vc4_hdmi->variant->max_pixel_clock)
1682                 return MODE_CLOCK_HIGH;
1683
1684         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1685                 return MODE_CLOCK_HIGH;
1686
1687         /* 4096x2160@60 is not reliable without overclocking core */
1688         if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1689             mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1690             drm_mode_vrefresh(mode) >= 50)
1691                 return MODE_CLOCK_HIGH;
1692
1693         return MODE_OK;
1694 }
1695
1696 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = {
1697         .tmds_char_rate_valid   = vc4_hdmi_connector_clock_valid,
1698         .write_infoframe        = vc4_hdmi_write_infoframe,
1699 };
1700
1701 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1702 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1703
1704 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1705                                          struct drm_crtc_state *crtc_state,
1706                                          struct drm_connector_state *conn_state)
1707 {
1708         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1709         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1710         unsigned long long tmds_char_rate = mode->clock * 1000;
1711         unsigned long long tmds_bit_rate;
1712
1713         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1714                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1715                         /* Only try to fixup DBLCLK modes to get 480i and 576i
1716                          * working.
1717                          * A generic solution for all modes with odd horizontal
1718                          * timing values seems impossible based on trying to
1719                          * solve it for 1366x768 monitors.
1720                          */
1721                         if ((mode->hsync_start - mode->hdisplay) & 1)
1722                                 mode->hsync_start--;
1723                         if ((mode->hsync_end - mode->hsync_start) & 1)
1724                                 mode->hsync_end--;
1725                 }
1726
1727                 /* Now check whether we still have odd values remaining */
1728                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1729                     (mode->hsync_end % 2) || (mode->htotal % 2))
1730                         return -EINVAL;
1731         }
1732
1733         /*
1734          * The 1440p@60 pixel rate is in the same range than the first
1735          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1736          * bandwidth). Slightly lower the frequency to bring it out of
1737          * the WiFi range.
1738          */
1739         tmds_bit_rate = tmds_char_rate * 10;
1740         if (vc4_hdmi->disable_wifi_frequencies &&
1741             (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1742              tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1743                 mode->clock = 238560;
1744                 tmds_char_rate = mode->clock * 1000;
1745         }
1746
1747         return 0;
1748 }
1749
1750 static enum drm_mode_status
1751 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1752                             const struct drm_display_mode *mode)
1753 {
1754         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1755         unsigned long long rate;
1756
1757         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1758             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1759             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1760              (mode->hsync_end % 2) || (mode->htotal % 2)))
1761                 return MODE_H_ILLEGAL;
1762
1763         rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
1764         return vc4_hdmi_connector_clock_valid(&vc4_hdmi->connector, mode, rate);
1765 }
1766
1767 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1768         .atomic_check = vc4_hdmi_encoder_atomic_check,
1769         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1770         .mode_valid = vc4_hdmi_encoder_mode_valid,
1771 };
1772
1773 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1774 {
1775         struct drm_device *drm = encoder->dev;
1776         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1777         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1778
1779         drm_debugfs_add_file(drm, variant->debugfs_name,
1780                              vc4_hdmi_debugfs_regs, vc4_hdmi);
1781
1782         return 0;
1783 }
1784
1785 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1786         .late_register = vc4_hdmi_late_register,
1787 };
1788
1789 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1790 {
1791         int i;
1792         u32 channel_map = 0;
1793
1794         for (i = 0; i < 8; i++) {
1795                 if (channel_mask & BIT(i))
1796                         channel_map |= i << (3 * i);
1797         }
1798         return channel_map;
1799 }
1800
1801 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1802 {
1803         int i;
1804         u32 channel_map = 0;
1805
1806         for (i = 0; i < 8; i++) {
1807                 if (channel_mask & BIT(i))
1808                         channel_map |= i << (4 * i);
1809         }
1810         return channel_map;
1811 }
1812
1813 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1814 {
1815         struct drm_device *drm = vc4_hdmi->connector.dev;
1816         unsigned long flags;
1817         u32 hotplug;
1818         int idx;
1819
1820         if (!drm_dev_enter(drm, &idx))
1821                 return false;
1822
1823         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1824         hotplug = HDMI_READ(HDMI_HOTPLUG);
1825         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1826
1827         drm_dev_exit(idx);
1828
1829         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1830 }
1831
1832 /* HDMI audio codec callbacks */
1833 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1834                                          unsigned int samplerate)
1835 {
1836         struct drm_device *drm = vc4_hdmi->connector.dev;
1837         u32 hsm_clock;
1838         unsigned long flags;
1839         unsigned long n, m;
1840         int idx;
1841
1842         if (!drm_dev_enter(drm, &idx))
1843                 return;
1844
1845         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1846         rational_best_approximation(hsm_clock, samplerate,
1847                                     VC4_HD_MAI_SMP_N_MASK >>
1848                                     VC4_HD_MAI_SMP_N_SHIFT,
1849                                     (VC4_HD_MAI_SMP_M_MASK >>
1850                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1851                                     &n, &m);
1852
1853         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1854         HDMI_WRITE(HDMI_MAI_SMP,
1855                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1856                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1857         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1858
1859         drm_dev_exit(idx);
1860 }
1861
1862 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1863 {
1864         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1865         u32 n, cts;
1866         u64 tmp;
1867
1868         lockdep_assert_held(&vc4_hdmi->mutex);
1869         lockdep_assert_held(&vc4_hdmi->hw_lock);
1870
1871         n = 128 * samplerate / 1000;
1872         tmp = (u64)(mode->clock * 1000) * n;
1873         do_div(tmp, 128 * samplerate);
1874         cts = tmp;
1875
1876         HDMI_WRITE(HDMI_CRP_CFG,
1877                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1878                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1879
1880         /*
1881          * We could get slightly more accurate clocks in some cases by
1882          * providing a CTS_1 value.  The two CTS values are alternated
1883          * between based on the period fields
1884          */
1885         HDMI_WRITE(HDMI_CTS_0, cts);
1886         HDMI_WRITE(HDMI_CTS_1, cts);
1887 }
1888
1889 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1890 {
1891         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1892
1893         return snd_soc_card_get_drvdata(card);
1894 }
1895
1896 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1897 {
1898         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1899
1900         lockdep_assert_held(&vc4_hdmi->mutex);
1901
1902         /*
1903          * If the encoder is currently in DVI mode, treat the codec DAI
1904          * as missing.
1905          */
1906         if (!display->is_hdmi)
1907                 return false;
1908
1909         return true;
1910 }
1911
1912 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1913 {
1914         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1915         struct drm_device *drm = vc4_hdmi->connector.dev;
1916         unsigned long flags;
1917         int ret = 0;
1918         int idx;
1919
1920         mutex_lock(&vc4_hdmi->mutex);
1921
1922         if (!drm_dev_enter(drm, &idx)) {
1923                 ret = -ENODEV;
1924                 goto out;
1925         }
1926
1927         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1928                 ret = -ENOTSUPP;
1929                 goto out_dev_exit;
1930         }
1931
1932         vc4_hdmi->audio.streaming = true;
1933
1934         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1935         HDMI_WRITE(HDMI_MAI_CTL,
1936                    VC4_HD_MAI_CTL_RESET |
1937                    VC4_HD_MAI_CTL_FLUSH |
1938                    VC4_HD_MAI_CTL_DLATE |
1939                    VC4_HD_MAI_CTL_ERRORE |
1940                    VC4_HD_MAI_CTL_ERRORF);
1941         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1942
1943         if (vc4_hdmi->variant->phy_rng_enable)
1944                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1945
1946 out_dev_exit:
1947         drm_dev_exit(idx);
1948 out:
1949         mutex_unlock(&vc4_hdmi->mutex);
1950
1951         return ret;
1952 }
1953
1954 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1955 {
1956         struct device *dev = &vc4_hdmi->pdev->dev;
1957         unsigned long flags;
1958         int ret;
1959
1960         lockdep_assert_held(&vc4_hdmi->mutex);
1961
1962         vc4_hdmi->audio.streaming = false;
1963         ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false);
1964         if (ret)
1965                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1966
1967         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1968
1969         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1970         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1971         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1972
1973         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1974 }
1975
1976 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1977 {
1978         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1979         struct drm_device *drm = vc4_hdmi->connector.dev;
1980         unsigned long flags;
1981         int idx;
1982
1983         mutex_lock(&vc4_hdmi->mutex);
1984
1985         if (!drm_dev_enter(drm, &idx))
1986                 goto out;
1987
1988         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1989
1990         HDMI_WRITE(HDMI_MAI_CTL,
1991                    VC4_HD_MAI_CTL_DLATE |
1992                    VC4_HD_MAI_CTL_ERRORE |
1993                    VC4_HD_MAI_CTL_ERRORF);
1994
1995         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1996
1997         if (vc4_hdmi->variant->phy_rng_disable)
1998                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1999
2000         vc4_hdmi->audio.streaming = false;
2001         vc4_hdmi_audio_reset(vc4_hdmi);
2002
2003         drm_dev_exit(idx);
2004
2005 out:
2006         mutex_unlock(&vc4_hdmi->mutex);
2007 }
2008
2009 static int sample_rate_to_mai_fmt(int samplerate)
2010 {
2011         switch (samplerate) {
2012         case 8000:
2013                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2014         case 11025:
2015                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2016         case 12000:
2017                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2018         case 16000:
2019                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2020         case 22050:
2021                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2022         case 24000:
2023                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2024         case 32000:
2025                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2026         case 44100:
2027                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2028         case 48000:
2029                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2030         case 64000:
2031                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2032         case 88200:
2033                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2034         case 96000:
2035                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2036         case 128000:
2037                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2038         case 176400:
2039                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2040         case 192000:
2041                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2042         default:
2043                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2044         }
2045 }
2046
2047 /* HDMI audio codec callbacks */
2048 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2049                                   struct hdmi_codec_daifmt *daifmt,
2050                                   struct hdmi_codec_params *params)
2051 {
2052         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2053         struct drm_device *drm = vc4_hdmi->connector.dev;
2054         struct drm_connector *connector = &vc4_hdmi->connector;
2055         struct vc4_dev *vc4 = to_vc4_dev(drm);
2056         unsigned int sample_rate = params->sample_rate;
2057         unsigned int channels = params->channels;
2058         unsigned long flags;
2059         u32 audio_packet_config, channel_mask;
2060         u32 channel_map;
2061         u32 mai_audio_format;
2062         u32 mai_sample_rate;
2063         int ret = 0;
2064         int idx;
2065
2066         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2067                 sample_rate, params->sample_width, channels);
2068
2069         mutex_lock(&vc4_hdmi->mutex);
2070
2071         if (!drm_dev_enter(drm, &idx)) {
2072                 ret = -ENODEV;
2073                 goto out;
2074         }
2075
2076         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2077                 ret = -EINVAL;
2078                 goto out_dev_exit;
2079         }
2080
2081         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2082
2083         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2084         HDMI_WRITE(HDMI_MAI_CTL,
2085                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2086                    VC4_HD_MAI_CTL_WHOLSMP |
2087                    VC4_HD_MAI_CTL_CHALIGN |
2088                    VC4_HD_MAI_CTL_ENABLE);
2089
2090         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2091         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2092             params->channels == 8)
2093                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2094         else
2095                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2096         HDMI_WRITE(HDMI_MAI_FMT,
2097                    VC4_SET_FIELD(mai_sample_rate,
2098                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2099                    VC4_SET_FIELD(mai_audio_format,
2100                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2101
2102         /* The B frame identifier should match the value used by alsa-lib (8) */
2103         audio_packet_config =
2104                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2105                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2106                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2107
2108         channel_mask = GENMASK(channels - 1, 0);
2109         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2110                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2111
2112         /* Set the MAI threshold */
2113         if (vc4->gen >= VC4_GEN_5)
2114                 HDMI_WRITE(HDMI_MAI_THR,
2115                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
2116                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
2117                            VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
2118                            VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
2119         else
2120                 HDMI_WRITE(HDMI_MAI_THR,
2121                            VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
2122                            VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
2123                            VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
2124                            VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
2125
2126         HDMI_WRITE(HDMI_MAI_CONFIG,
2127                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2128                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2129                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2130
2131         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2132         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2133         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2134
2135         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2136
2137         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2138
2139         ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
2140                                                                       &params->cea);
2141         if (ret)
2142                 goto out_dev_exit;
2143
2144 out_dev_exit:
2145         drm_dev_exit(idx);
2146 out:
2147         mutex_unlock(&vc4_hdmi->mutex);
2148
2149         return ret;
2150 }
2151
2152 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2153         .name = "vc4-hdmi-cpu-dai-component",
2154         .legacy_dai_naming = 1,
2155 };
2156
2157 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2158 {
2159         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2160
2161         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2162
2163         return 0;
2164 }
2165
2166 static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2167         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2168 };
2169
2170 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2171         .name = "vc4-hdmi-cpu-dai",
2172         .ops = &vc4_snd_dai_ops,
2173         .playback = {
2174                 .stream_name = "Playback",
2175                 .channels_min = 1,
2176                 .channels_max = 8,
2177                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2178                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2179                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2180                          SNDRV_PCM_RATE_192000,
2181                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2182         },
2183 };
2184
2185 static const struct snd_dmaengine_pcm_config pcm_conf = {
2186         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2187         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2188 };
2189
2190 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2191                                   uint8_t *buf, size_t len)
2192 {
2193         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2194         struct drm_connector *connector = &vc4_hdmi->connector;
2195
2196         mutex_lock(&vc4_hdmi->mutex);
2197         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2198         mutex_unlock(&vc4_hdmi->mutex);
2199
2200         return 0;
2201 }
2202
2203 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2204         .get_eld = vc4_hdmi_audio_get_eld,
2205         .prepare = vc4_hdmi_audio_prepare,
2206         .audio_shutdown = vc4_hdmi_audio_shutdown,
2207         .audio_startup = vc4_hdmi_audio_startup,
2208 };
2209
2210 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2211         .ops = &vc4_hdmi_codec_ops,
2212         .max_i2s_channels = 8,
2213         .i2s = 1,
2214 };
2215
2216 static void vc4_hdmi_audio_codec_release(void *ptr)
2217 {
2218         struct vc4_hdmi *vc4_hdmi = ptr;
2219
2220         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2221         vc4_hdmi->audio.codec_pdev = NULL;
2222 }
2223
2224 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2225 {
2226         const struct vc4_hdmi_register *mai_data =
2227                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2228         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2229         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2230         struct device *dev = &vc4_hdmi->pdev->dev;
2231         struct platform_device *codec_pdev;
2232         const __be32 *addr;
2233         int index, len;
2234         int ret;
2235
2236         /*
2237          * ASoC makes it a bit hard to retrieve a pointer to the
2238          * vc4_hdmi structure. Registering the card will overwrite our
2239          * device drvdata with a pointer to the snd_soc_card structure,
2240          * which can then be used to retrieve whatever drvdata we want
2241          * to associate.
2242          *
2243          * However, that doesn't fly in the case where we wouldn't
2244          * register an ASoC card (because of an old DT that is missing
2245          * the dmas properties for example), then the card isn't
2246          * registered and the device drvdata wouldn't be set.
2247          *
2248          * We can deal with both cases by making sure a snd_soc_card
2249          * pointer and a vc4_hdmi structure are pointing to the same
2250          * memory address, so we can treat them indistinctly without any
2251          * issue.
2252          */
2253         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2254         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2255
2256         if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2257                 dev_warn(dev,
2258                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2259                 return 0;
2260         }
2261
2262         if (mai_data->reg != VC4_HD) {
2263                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2264                 return -EINVAL;
2265         }
2266
2267         /*
2268          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2269          * the bus address specified in the DT, because the physical address
2270          * (the one returned by platform_get_resource()) is not appropriate
2271          * for DMA transfers.
2272          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2273          */
2274         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2275         /* Before BCM2711, we don't have a named register range */
2276         if (index < 0)
2277                 index = 1;
2278
2279         addr = of_get_address(dev->of_node, index, NULL, NULL);
2280         if (!addr)
2281                 return -EINVAL;
2282
2283         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2284         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2285         vc4_hdmi->audio.dma_data.maxburst = 2;
2286
2287         /*
2288          * NOTE: Strictly speaking, we should probably use a DRM-managed
2289          * registration there to avoid removing all the audio components
2290          * by the time the driver doesn't have any user anymore.
2291          *
2292          * However, the ASoC core uses a number of devm_kzalloc calls
2293          * when registering, even when using non-device-managed
2294          * functions (such as in snd_soc_register_component()).
2295          *
2296          * If we call snd_soc_unregister_component() in a DRM-managed
2297          * action, the device-managed actions have already been executed
2298          * and thus we would access memory that has been freed.
2299          *
2300          * Using device-managed hooks here probably leaves us open to a
2301          * bunch of issues if userspace still has a handle on the ALSA
2302          * device when the device is removed. However, this is mitigated
2303          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2304          * path to prevent the access to the device resources if it
2305          * isn't there anymore.
2306          *
2307          * Then, the vc4_hdmi structure is DRM-managed and thus only
2308          * freed whenever the last user has closed the DRM device file.
2309          * It should thus outlive ALSA in most situations.
2310          */
2311         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2312         if (ret) {
2313                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2314                 return ret;
2315         }
2316
2317         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2318                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2319         if (ret) {
2320                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2321                 return ret;
2322         }
2323
2324         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2325                                                    PLATFORM_DEVID_AUTO,
2326                                                    &vc4_hdmi_codec_pdata,
2327                                                    sizeof(vc4_hdmi_codec_pdata));
2328         if (IS_ERR(codec_pdev)) {
2329                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2330                 return PTR_ERR(codec_pdev);
2331         }
2332         vc4_hdmi->audio.codec_pdev = codec_pdev;
2333
2334         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2335         if (ret)
2336                 return ret;
2337
2338         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2339         dai_link->codecs        = &vc4_hdmi->audio.codec;
2340         dai_link->platforms     = &vc4_hdmi->audio.platform;
2341
2342         dai_link->num_cpus      = 1;
2343         dai_link->num_codecs    = 1;
2344         dai_link->num_platforms = 1;
2345
2346         dai_link->name = "MAI";
2347         dai_link->stream_name = "MAI PCM";
2348         dai_link->codecs->dai_name = "i2s-hifi";
2349         dai_link->cpus->dai_name = dev_name(dev);
2350         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2351         dai_link->platforms->name = dev_name(dev);
2352
2353         card->dai_link = dai_link;
2354         card->num_links = 1;
2355         card->name = vc4_hdmi->variant->card_name;
2356         card->driver_name = "vc4-hdmi";
2357         card->dev = dev;
2358         card->owner = THIS_MODULE;
2359
2360         /*
2361          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2362          * stores a pointer to the snd card object in dev->driver_data. This
2363          * means we cannot use it for something else. The hdmi back-pointer is
2364          * now stored in card->drvdata and should be retrieved with
2365          * snd_soc_card_get_drvdata() if needed.
2366          */
2367         snd_soc_card_set_drvdata(card, vc4_hdmi);
2368         ret = devm_snd_soc_register_card(dev, card);
2369         if (ret)
2370                 dev_err_probe(dev, ret, "Could not register sound card\n");
2371
2372         return ret;
2373
2374 }
2375
2376 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2377 {
2378         struct vc4_hdmi *vc4_hdmi = priv;
2379         struct drm_connector *connector = &vc4_hdmi->connector;
2380         struct drm_device *dev = connector->dev;
2381
2382         if (dev && dev->registered)
2383                 drm_connector_helper_hpd_irq_event(connector);
2384
2385         return IRQ_HANDLED;
2386 }
2387
2388 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2389 {
2390         struct drm_connector *connector = &vc4_hdmi->connector;
2391         struct platform_device *pdev = vc4_hdmi->pdev;
2392         int ret;
2393
2394         if (vc4_hdmi->variant->external_irq_controller) {
2395                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2396                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2397
2398                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2399                                                 NULL,
2400                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2401                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2402                 if (ret)
2403                         return ret;
2404
2405                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2406                                                 NULL,
2407                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2408                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2409                 if (ret)
2410                         return ret;
2411
2412                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2413         }
2414
2415         return 0;
2416 }
2417
2418 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2419 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2420 {
2421         struct vc4_hdmi *vc4_hdmi = priv;
2422
2423         if (vc4_hdmi->cec_rx_msg.len)
2424                 cec_received_msg(vc4_hdmi->cec_adap,
2425                                  &vc4_hdmi->cec_rx_msg);
2426
2427         return IRQ_HANDLED;
2428 }
2429
2430 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2431 {
2432         struct vc4_hdmi *vc4_hdmi = priv;
2433
2434         if (vc4_hdmi->cec_tx_ok) {
2435                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2436                                   0, 0, 0, 0);
2437         } else {
2438                 /*
2439                  * This CEC implementation makes 1 retry, so if we
2440                  * get a NACK, then that means it made 2 attempts.
2441                  */
2442                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2443                                   0, 2, 0, 0);
2444         }
2445         return IRQ_HANDLED;
2446 }
2447
2448 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2449 {
2450         struct vc4_hdmi *vc4_hdmi = priv;
2451         irqreturn_t ret;
2452
2453         if (vc4_hdmi->cec_irq_was_rx)
2454                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2455         else
2456                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2457
2458         return ret;
2459 }
2460
2461 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2462 {
2463         struct drm_device *dev = vc4_hdmi->connector.dev;
2464         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2465         unsigned int i;
2466
2467         lockdep_assert_held(&vc4_hdmi->hw_lock);
2468
2469         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2470                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2471
2472         if (msg->len > 16) {
2473                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2474                 return;
2475         }
2476
2477         for (i = 0; i < msg->len; i += 4) {
2478                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2479
2480                 msg->msg[i] = val & 0xff;
2481                 msg->msg[i + 1] = (val >> 8) & 0xff;
2482                 msg->msg[i + 2] = (val >> 16) & 0xff;
2483                 msg->msg[i + 3] = (val >> 24) & 0xff;
2484         }
2485 }
2486
2487 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2488 {
2489         u32 cntrl1;
2490
2491         /*
2492          * We don't need to protect the register access using
2493          * drm_dev_enter() there because the interrupt handler lifetime
2494          * is tied to the device itself, and not to the DRM device.
2495          *
2496          * So when the device will be gone, one of the first thing we
2497          * will be doing will be to unregister the interrupt handler,
2498          * and then unregister the DRM device. drm_dev_enter() would
2499          * thus always succeed if we are here.
2500          */
2501
2502         lockdep_assert_held(&vc4_hdmi->hw_lock);
2503
2504         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2505         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2506         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2507         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2508
2509         return IRQ_WAKE_THREAD;
2510 }
2511
2512 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2513 {
2514         struct vc4_hdmi *vc4_hdmi = priv;
2515         irqreturn_t ret;
2516
2517         spin_lock(&vc4_hdmi->hw_lock);
2518         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2519         spin_unlock(&vc4_hdmi->hw_lock);
2520
2521         return ret;
2522 }
2523
2524 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2525 {
2526         u32 cntrl1;
2527
2528         lockdep_assert_held(&vc4_hdmi->hw_lock);
2529
2530         /*
2531          * We don't need to protect the register access using
2532          * drm_dev_enter() there because the interrupt handler lifetime
2533          * is tied to the device itself, and not to the DRM device.
2534          *
2535          * So when the device will be gone, one of the first thing we
2536          * will be doing will be to unregister the interrupt handler,
2537          * and then unregister the DRM device. drm_dev_enter() would
2538          * thus always succeed if we are here.
2539          */
2540
2541         vc4_hdmi->cec_rx_msg.len = 0;
2542         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2543         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2544         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2545         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2546         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2547
2548         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2549
2550         return IRQ_WAKE_THREAD;
2551 }
2552
2553 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2554 {
2555         struct vc4_hdmi *vc4_hdmi = priv;
2556         irqreturn_t ret;
2557
2558         spin_lock(&vc4_hdmi->hw_lock);
2559         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2560         spin_unlock(&vc4_hdmi->hw_lock);
2561
2562         return ret;
2563 }
2564
2565 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2566 {
2567         struct vc4_hdmi *vc4_hdmi = priv;
2568         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2569         irqreturn_t ret;
2570         u32 cntrl5;
2571
2572         /*
2573          * We don't need to protect the register access using
2574          * drm_dev_enter() there because the interrupt handler lifetime
2575          * is tied to the device itself, and not to the DRM device.
2576          *
2577          * So when the device will be gone, one of the first thing we
2578          * will be doing will be to unregister the interrupt handler,
2579          * and then unregister the DRM device. drm_dev_enter() would
2580          * thus always succeed if we are here.
2581          */
2582
2583         if (!(stat & VC4_HDMI_CPU_CEC))
2584                 return IRQ_NONE;
2585
2586         spin_lock(&vc4_hdmi->hw_lock);
2587         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2588         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2589         if (vc4_hdmi->cec_irq_was_rx)
2590                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2591         else
2592                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2593
2594         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2595         spin_unlock(&vc4_hdmi->hw_lock);
2596
2597         return ret;
2598 }
2599
2600 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2601 {
2602         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2603         struct drm_device *drm = vc4_hdmi->connector.dev;
2604         /* clock period in microseconds */
2605         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2606         unsigned long flags;
2607         u32 val;
2608         int ret;
2609         int idx;
2610
2611         if (!drm_dev_enter(drm, &idx))
2612                 /*
2613                  * We can't return an error code, because the CEC
2614                  * framework will emit WARN_ON messages at unbind
2615                  * otherwise.
2616                  */
2617                 return 0;
2618
2619         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2620         if (ret) {
2621                 drm_dev_exit(idx);
2622                 return ret;
2623         }
2624
2625         mutex_lock(&vc4_hdmi->mutex);
2626
2627         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2628
2629         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2630         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2631                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2632                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2633         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2634                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2635
2636         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2637                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2638         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2639         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2640                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2641                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2642                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2643                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2644                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2645         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2646                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2647                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2648                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2649                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2650         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2651                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2652                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2653                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2654                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2655
2656         if (!vc4_hdmi->variant->external_irq_controller)
2657                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2658
2659         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2660
2661         mutex_unlock(&vc4_hdmi->mutex);
2662         drm_dev_exit(idx);
2663
2664         return 0;
2665 }
2666
2667 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2668 {
2669         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2670         struct drm_device *drm = vc4_hdmi->connector.dev;
2671         unsigned long flags;
2672         int idx;
2673
2674         if (!drm_dev_enter(drm, &idx))
2675                 /*
2676                  * We can't return an error code, because the CEC
2677                  * framework will emit WARN_ON messages at unbind
2678                  * otherwise.
2679                  */
2680                 return 0;
2681
2682         mutex_lock(&vc4_hdmi->mutex);
2683
2684         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2685
2686         if (!vc4_hdmi->variant->external_irq_controller)
2687                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2688
2689         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2690                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2691
2692         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2693
2694         mutex_unlock(&vc4_hdmi->mutex);
2695
2696         pm_runtime_put(&vc4_hdmi->pdev->dev);
2697
2698         drm_dev_exit(idx);
2699
2700         return 0;
2701 }
2702
2703 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2704 {
2705         if (enable)
2706                 return vc4_hdmi_cec_enable(adap);
2707         else
2708                 return vc4_hdmi_cec_disable(adap);
2709 }
2710
2711 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2712 {
2713         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2714         struct drm_device *drm = vc4_hdmi->connector.dev;
2715         unsigned long flags;
2716         int idx;
2717
2718         if (!drm_dev_enter(drm, &idx))
2719                 /*
2720                  * We can't return an error code, because the CEC
2721                  * framework will emit WARN_ON messages at unbind
2722                  * otherwise.
2723                  */
2724                 return 0;
2725
2726         mutex_lock(&vc4_hdmi->mutex);
2727         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2728         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2729                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2730                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2731         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2732         mutex_unlock(&vc4_hdmi->mutex);
2733
2734         drm_dev_exit(idx);
2735
2736         return 0;
2737 }
2738
2739 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2740                                       u32 signal_free_time, struct cec_msg *msg)
2741 {
2742         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2743         struct drm_device *dev = vc4_hdmi->connector.dev;
2744         unsigned long flags;
2745         u32 val;
2746         unsigned int i;
2747         int idx;
2748
2749         if (!drm_dev_enter(dev, &idx))
2750                 return -ENODEV;
2751
2752         if (msg->len > 16) {
2753                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2754                 drm_dev_exit(idx);
2755                 return -ENOMEM;
2756         }
2757
2758         mutex_lock(&vc4_hdmi->mutex);
2759
2760         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2761
2762         for (i = 0; i < msg->len; i += 4)
2763                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2764                            (msg->msg[i]) |
2765                            (msg->msg[i + 1] << 8) |
2766                            (msg->msg[i + 2] << 16) |
2767                            (msg->msg[i + 3] << 24));
2768
2769         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2770         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2771         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2772         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2773         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2774         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2775
2776         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2777
2778         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2779         mutex_unlock(&vc4_hdmi->mutex);
2780         drm_dev_exit(idx);
2781
2782         return 0;
2783 }
2784
2785 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2786         .adap_enable = vc4_hdmi_cec_adap_enable,
2787         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2788         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2789 };
2790
2791 static void vc4_hdmi_cec_release(void *ptr)
2792 {
2793         struct vc4_hdmi *vc4_hdmi = ptr;
2794
2795         cec_unregister_adapter(vc4_hdmi->cec_adap);
2796         vc4_hdmi->cec_adap = NULL;
2797 }
2798
2799 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2800 {
2801         struct cec_connector_info conn_info;
2802         struct platform_device *pdev = vc4_hdmi->pdev;
2803         struct device *dev = &pdev->dev;
2804         int ret;
2805
2806         if (!of_property_present(dev->of_node, "interrupts")) {
2807                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2808                 return 0;
2809         }
2810
2811         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2812                                                   vc4_hdmi,
2813                                                   vc4_hdmi->variant->card_name,
2814                                                   CEC_CAP_DEFAULTS |
2815                                                   CEC_CAP_CONNECTOR_INFO, 1);
2816         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2817         if (ret < 0)
2818                 return ret;
2819
2820         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2821         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2822
2823         if (vc4_hdmi->variant->external_irq_controller) {
2824                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2825                                                 vc4_cec_irq_handler_rx_bare,
2826                                                 vc4_cec_irq_handler_rx_thread, 0,
2827                                                 "vc4 hdmi cec rx", vc4_hdmi);
2828                 if (ret)
2829                         goto err_delete_cec_adap;
2830
2831                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2832                                                 vc4_cec_irq_handler_tx_bare,
2833                                                 vc4_cec_irq_handler_tx_thread, 0,
2834                                                 "vc4 hdmi cec tx", vc4_hdmi);
2835                 if (ret)
2836                         goto err_delete_cec_adap;
2837         } else {
2838                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2839                                                 vc4_cec_irq_handler,
2840                                                 vc4_cec_irq_handler_thread, 0,
2841                                                 "vc4 hdmi cec", vc4_hdmi);
2842                 if (ret)
2843                         goto err_delete_cec_adap;
2844         }
2845
2846         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2847         if (ret < 0)
2848                 goto err_delete_cec_adap;
2849
2850         /*
2851          * NOTE: Strictly speaking, we should probably use a DRM-managed
2852          * registration there to avoid removing the CEC adapter by the
2853          * time the DRM driver doesn't have any user anymore.
2854          *
2855          * However, the CEC framework already cleans up the CEC adapter
2856          * only when the last user has closed its file descriptor, so we
2857          * don't need to handle it in DRM.
2858          *
2859          * By the time the device-managed hook is executed, we will give
2860          * up our reference to the CEC adapter and therefore don't
2861          * really care when it's actually freed.
2862          *
2863          * There's still a problematic sequence: if we unregister our
2864          * CEC adapter, but the userspace keeps a handle on the CEC
2865          * adapter but not the DRM device for some reason. In such a
2866          * case, our vc4_hdmi structure will be freed, but the
2867          * cec_adapter structure will have a dangling pointer to what
2868          * used to be our HDMI controller. If we get a CEC call at that
2869          * moment, we could end up with a use-after-free. Fortunately,
2870          * the CEC framework already handles this too, by calling
2871          * cec_is_registered() in cec_ioctl() and cec_poll().
2872          */
2873         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2874         if (ret)
2875                 return ret;
2876
2877         return 0;
2878
2879 err_delete_cec_adap:
2880         cec_delete_adapter(vc4_hdmi->cec_adap);
2881
2882         return ret;
2883 }
2884 #else
2885 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2886 {
2887         return 0;
2888 }
2889 #endif
2890
2891 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2892 {
2893         struct debugfs_reg32 *regs = ptr;
2894
2895         kfree(regs);
2896 }
2897
2898 static int vc4_hdmi_build_regset(struct drm_device *drm,
2899                                  struct vc4_hdmi *vc4_hdmi,
2900                                  struct debugfs_regset32 *regset,
2901                                  enum vc4_hdmi_regs reg)
2902 {
2903         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2904         struct debugfs_reg32 *regs, *new_regs;
2905         unsigned int count = 0;
2906         unsigned int i;
2907         int ret;
2908
2909         regs = kcalloc(variant->num_registers, sizeof(*regs),
2910                        GFP_KERNEL);
2911         if (!regs)
2912                 return -ENOMEM;
2913
2914         for (i = 0; i < variant->num_registers; i++) {
2915                 const struct vc4_hdmi_register *field = &variant->registers[i];
2916
2917                 if (field->reg != reg)
2918                         continue;
2919
2920                 regs[count].name = field->name;
2921                 regs[count].offset = field->offset;
2922                 count++;
2923         }
2924
2925         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2926         if (!new_regs)
2927                 return -ENOMEM;
2928
2929         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2930         regset->regs = new_regs;
2931         regset->nregs = count;
2932
2933         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
2934         if (ret)
2935                 return ret;
2936
2937         return 0;
2938 }
2939
2940 static int vc4_hdmi_init_resources(struct drm_device *drm,
2941                                    struct vc4_hdmi *vc4_hdmi)
2942 {
2943         struct platform_device *pdev = vc4_hdmi->pdev;
2944         struct device *dev = &pdev->dev;
2945         int ret;
2946
2947         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2948         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2949                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2950
2951         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2952         if (IS_ERR(vc4_hdmi->hd_regs))
2953                 return PTR_ERR(vc4_hdmi->hd_regs);
2954
2955         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2956         if (ret)
2957                 return ret;
2958
2959         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2960         if (ret)
2961                 return ret;
2962
2963         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2964         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2965                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2966                 if (ret != -EPROBE_DEFER)
2967                         drm_err(drm, "Failed to get pixel clock\n");
2968                 return ret;
2969         }
2970
2971         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2972         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2973                 drm_err(drm, "Failed to get HDMI state machine clock\n");
2974                 return PTR_ERR(vc4_hdmi->hsm_clock);
2975         }
2976         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2977         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2978
2979         return 0;
2980 }
2981
2982 static int vc5_hdmi_init_resources(struct drm_device *drm,
2983                                    struct vc4_hdmi *vc4_hdmi)
2984 {
2985         struct platform_device *pdev = vc4_hdmi->pdev;
2986         struct device *dev = &pdev->dev;
2987         struct resource *res;
2988         int ret;
2989
2990         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2991         if (!res)
2992                 return -ENODEV;
2993
2994         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2995                                                resource_size(res));
2996         if (!vc4_hdmi->hdmicore_regs)
2997                 return -ENOMEM;
2998
2999         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3000         if (!res)
3001                 return -ENODEV;
3002
3003         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3004         if (!vc4_hdmi->hd_regs)
3005                 return -ENOMEM;
3006
3007         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3008         if (!res)
3009                 return -ENODEV;
3010
3011         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3012         if (!vc4_hdmi->cec_regs)
3013                 return -ENOMEM;
3014
3015         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3016         if (!res)
3017                 return -ENODEV;
3018
3019         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3020         if (!vc4_hdmi->csc_regs)
3021                 return -ENOMEM;
3022
3023         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3024         if (!res)
3025                 return -ENODEV;
3026
3027         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3028         if (!vc4_hdmi->dvp_regs)
3029                 return -ENOMEM;
3030
3031         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3032         if (!res)
3033                 return -ENODEV;
3034
3035         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3036         if (!vc4_hdmi->phy_regs)
3037                 return -ENOMEM;
3038
3039         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3040         if (!res)
3041                 return -ENODEV;
3042
3043         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3044         if (!vc4_hdmi->ram_regs)
3045                 return -ENOMEM;
3046
3047         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3048         if (!res)
3049                 return -ENODEV;
3050
3051         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3052         if (!vc4_hdmi->rm_regs)
3053                 return -ENOMEM;
3054
3055         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3056         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3057                 drm_err(drm, "Failed to get HDMI state machine clock\n");
3058                 return PTR_ERR(vc4_hdmi->hsm_clock);
3059         }
3060
3061         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3062         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3063                 drm_err(drm, "Failed to get pixel bvb clock\n");
3064                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3065         }
3066
3067         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3068         if (IS_ERR(vc4_hdmi->audio_clock)) {
3069                 drm_err(drm, "Failed to get audio clock\n");
3070                 return PTR_ERR(vc4_hdmi->audio_clock);
3071         }
3072
3073         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3074         if (IS_ERR(vc4_hdmi->cec_clock)) {
3075                 drm_err(drm, "Failed to get CEC clock\n");
3076                 return PTR_ERR(vc4_hdmi->cec_clock);
3077         }
3078
3079         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3080         if (IS_ERR(vc4_hdmi->reset)) {
3081                 drm_err(drm, "Failed to get HDMI reset line\n");
3082                 return PTR_ERR(vc4_hdmi->reset);
3083         }
3084
3085         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3086         if (ret)
3087                 return ret;
3088
3089         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3090         if (ret)
3091                 return ret;
3092
3093         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3094         if (ret)
3095                 return ret;
3096
3097         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3098         if (ret)
3099                 return ret;
3100
3101         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3102         if (ret)
3103                 return ret;
3104
3105         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3106         if (ret)
3107                 return ret;
3108
3109         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3110         if (ret)
3111                 return ret;
3112
3113         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3114         if (ret)
3115                 return ret;
3116
3117         return 0;
3118 }
3119
3120 static int vc4_hdmi_runtime_suspend(struct device *dev)
3121 {
3122         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3123
3124         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3125
3126         return 0;
3127 }
3128
3129 static int vc4_hdmi_runtime_resume(struct device *dev)
3130 {
3131         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3132         unsigned long __maybe_unused flags;
3133         u32 __maybe_unused value;
3134         unsigned long rate;
3135         int ret;
3136
3137         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3138         if (ret)
3139                 return ret;
3140
3141         /*
3142          * Whenever the RaspberryPi boots without an HDMI monitor
3143          * plugged in, the firmware won't have initialized the HSM clock
3144          * rate and it will be reported as 0.
3145          *
3146          * If we try to access a register of the controller in such a
3147          * case, it will lead to a silent CPU stall. Let's make sure we
3148          * prevent such a case.
3149          */
3150         rate = clk_get_rate(vc4_hdmi->hsm_clock);
3151         if (!rate) {
3152                 ret = -EINVAL;
3153                 goto err_disable_clk;
3154         }
3155
3156         if (vc4_hdmi->variant->reset)
3157                 vc4_hdmi->variant->reset(vc4_hdmi);
3158
3159 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3160         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3161         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3162         /* Set the logical address to Unregistered */
3163         value |= VC4_HDMI_CEC_ADDR_MASK;
3164         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3165         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3166
3167         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3168
3169         if (!vc4_hdmi->variant->external_irq_controller) {
3170                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3171                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3172                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3173         }
3174 #endif
3175
3176         return 0;
3177
3178 err_disable_clk:
3179         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3180         return ret;
3181 }
3182
3183 static void vc4_hdmi_put_ddc_device(void *ptr)
3184 {
3185         struct vc4_hdmi *vc4_hdmi = ptr;
3186
3187         put_device(&vc4_hdmi->ddc->dev);
3188 }
3189
3190 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3191 {
3192         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3193         struct platform_device *pdev = to_platform_device(dev);
3194         struct drm_device *drm = dev_get_drvdata(master);
3195         struct vc4_hdmi *vc4_hdmi;
3196         struct drm_encoder *encoder;
3197         struct device_node *ddc_node;
3198         int ret;
3199
3200         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3201         if (!vc4_hdmi)
3202                 return -ENOMEM;
3203
3204         ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3205         if (ret)
3206                 return ret;
3207
3208         spin_lock_init(&vc4_hdmi->hw_lock);
3209         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3210
3211         dev_set_drvdata(dev, vc4_hdmi);
3212         encoder = &vc4_hdmi->encoder.base;
3213         vc4_hdmi->encoder.type = variant->encoder_type;
3214         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3215         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3216         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3217         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3218         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3219         vc4_hdmi->pdev = pdev;
3220         vc4_hdmi->variant = variant;
3221
3222         /*
3223          * Since we don't know the state of the controller and its
3224          * display (if any), let's assume it's always enabled.
3225          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3226          * sure it's disabled, and avoid any inconsistency.
3227          */
3228         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3229                 vc4_hdmi->scdc_enabled = true;
3230
3231         ret = variant->init_resources(drm, vc4_hdmi);
3232         if (ret)
3233                 return ret;
3234
3235         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3236         if (!ddc_node) {
3237                 drm_err(drm, "Failed to find ddc node in device tree\n");
3238                 return -ENODEV;
3239         }
3240
3241         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3242         of_node_put(ddc_node);
3243         if (!vc4_hdmi->ddc) {
3244                 drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3245                 return -EPROBE_DEFER;
3246         }
3247
3248         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3249         if (ret)
3250                 return ret;
3251
3252         /* Only use the GPIO HPD pin if present in the DT, otherwise
3253          * we'll use the HDMI core's register.
3254          */
3255         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3256         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3257                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3258         }
3259
3260         vc4_hdmi->disable_wifi_frequencies =
3261                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3262
3263         ret = devm_pm_runtime_enable(dev);
3264         if (ret)
3265                 return ret;
3266
3267         /*
3268          *  We need to have the device powered up at this point to call
3269          *  our reset hook and for the CEC init.
3270          */
3271         ret = pm_runtime_resume_and_get(dev);
3272         if (ret)
3273                 return ret;
3274
3275         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3276              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3277             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3278                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3279                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3280                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3281         }
3282
3283         ret = drmm_encoder_init(drm, encoder,
3284                                 &vc4_hdmi_encoder_funcs,
3285                                 DRM_MODE_ENCODER_TMDS,
3286                                 NULL);
3287         if (ret)
3288                 goto err_put_runtime_pm;
3289
3290         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3291
3292         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3293         if (ret)
3294                 goto err_put_runtime_pm;
3295
3296         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3297         if (ret)
3298                 goto err_put_runtime_pm;
3299
3300         ret = vc4_hdmi_cec_init(vc4_hdmi);
3301         if (ret)
3302                 goto err_put_runtime_pm;
3303
3304         ret = vc4_hdmi_audio_init(vc4_hdmi);
3305         if (ret)
3306                 goto err_put_runtime_pm;
3307
3308         pm_runtime_put_sync(dev);
3309
3310         return 0;
3311
3312 err_put_runtime_pm:
3313         pm_runtime_put_sync(dev);
3314
3315         return ret;
3316 }
3317
3318 static const struct component_ops vc4_hdmi_ops = {
3319         .bind   = vc4_hdmi_bind,
3320 };
3321
3322 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3323 {
3324         return component_add(&pdev->dev, &vc4_hdmi_ops);
3325 }
3326
3327 static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3328 {
3329         component_del(&pdev->dev, &vc4_hdmi_ops);
3330 }
3331
3332 static const struct vc4_hdmi_variant bcm2835_variant = {
3333         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3334         .debugfs_name           = "hdmi_regs",
3335         .card_name              = "vc4-hdmi",
3336         .max_pixel_clock        = 162000000,
3337         .registers              = vc4_hdmi_fields,
3338         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3339
3340         .init_resources         = vc4_hdmi_init_resources,
3341         .csc_setup              = vc4_hdmi_csc_setup,
3342         .reset                  = vc4_hdmi_reset,
3343         .set_timings            = vc4_hdmi_set_timings,
3344         .phy_init               = vc4_hdmi_phy_init,
3345         .phy_disable            = vc4_hdmi_phy_disable,
3346         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3347         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3348         .channel_map            = vc4_hdmi_channel_map,
3349         .supports_hdr           = false,
3350 };
3351
3352 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3353         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3354         .debugfs_name           = "hdmi0_regs",
3355         .card_name              = "vc4-hdmi-0",
3356         .max_pixel_clock        = 600000000,
3357         .registers              = vc5_hdmi_hdmi0_fields,
3358         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3359         .phy_lane_mapping       = {
3360                 PHY_LANE_0,
3361                 PHY_LANE_1,
3362                 PHY_LANE_2,
3363                 PHY_LANE_CK,
3364         },
3365         .unsupported_odd_h_timings      = true,
3366         .external_irq_controller        = true,
3367
3368         .init_resources         = vc5_hdmi_init_resources,
3369         .csc_setup              = vc5_hdmi_csc_setup,
3370         .reset                  = vc5_hdmi_reset,
3371         .set_timings            = vc5_hdmi_set_timings,
3372         .phy_init               = vc5_hdmi_phy_init,
3373         .phy_disable            = vc5_hdmi_phy_disable,
3374         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3375         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3376         .channel_map            = vc5_hdmi_channel_map,
3377         .supports_hdr           = true,
3378         .hp_detect              = vc5_hdmi_hp_detect,
3379 };
3380
3381 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3382         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3383         .debugfs_name           = "hdmi1_regs",
3384         .card_name              = "vc4-hdmi-1",
3385         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3386         .registers              = vc5_hdmi_hdmi1_fields,
3387         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3388         .phy_lane_mapping       = {
3389                 PHY_LANE_1,
3390                 PHY_LANE_0,
3391                 PHY_LANE_CK,
3392                 PHY_LANE_2,
3393         },
3394         .unsupported_odd_h_timings      = true,
3395         .external_irq_controller        = true,
3396
3397         .init_resources         = vc5_hdmi_init_resources,
3398         .csc_setup              = vc5_hdmi_csc_setup,
3399         .reset                  = vc5_hdmi_reset,
3400         .set_timings            = vc5_hdmi_set_timings,
3401         .phy_init               = vc5_hdmi_phy_init,
3402         .phy_disable            = vc5_hdmi_phy_disable,
3403         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3404         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3405         .channel_map            = vc5_hdmi_channel_map,
3406         .supports_hdr           = true,
3407         .hp_detect              = vc5_hdmi_hp_detect,
3408 };
3409
3410 static const struct of_device_id vc4_hdmi_dt_match[] = {
3411         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3412         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3413         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3414         {}
3415 };
3416
3417 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3418         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3419                            vc4_hdmi_runtime_resume,
3420                            NULL)
3421 };
3422
3423 struct platform_driver vc4_hdmi_driver = {
3424         .probe = vc4_hdmi_dev_probe,
3425         .remove = vc4_hdmi_dev_remove,
3426         .driver = {
3427                 .name = "vc4_hdmi",
3428                 .of_match_table = vc4_hdmi_dt_match,
3429                 .pm = &vc4_hdmi_pm_ops,
3430         },
3431 };