drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30
  31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
  32 {
  33         DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
  34         DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
  35         DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
  36         DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
  37         DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
  38         DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
  39         DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
  40         DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
  41         DRM_DEBUG("ucode_array_offset_bytes: %u\n",
  42                   le32_to_cpu(hdr->ucode_array_offset_bytes));
  43         DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
  44 }
  45
  46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
  47 {
  48         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  49         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  50
  51         DRM_DEBUG("MC\n");
  52         amdgpu_ucode_print_common_hdr(hdr);
  53
  54         if (version_major == 1) {
  55                 const struct mc_firmware_header_v1_0 *mc_hdr =
  56                         container_of(hdr, struct mc_firmware_header_v1_0, header);
  57
  58                 DRM_DEBUG("io_debug_size_bytes: %u\n",
  59                           le32_to_cpu(mc_hdr->io_debug_size_bytes));
  60                 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
  61                           le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
  62         } else {
  63                 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
  64         }
  65 }
  66
  67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
  68 {
  69         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  70         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  71         const struct smc_firmware_header_v1_0 *v1_0_hdr;
  72         const struct smc_firmware_header_v2_0 *v2_0_hdr;
  73         const struct smc_firmware_header_v2_1 *v2_1_hdr;
  74
  75         DRM_DEBUG("SMC\n");
  76         amdgpu_ucode_print_common_hdr(hdr);
  77
  78         if (version_major == 1) {
  79                 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
  80                 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
  81         } else if (version_major == 2) {
  82                 switch (version_minor) {
  83                 case 0:
  84                         v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
  85                         DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
  86                         DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
  87                         break;
  88                 case 1:
  89                         v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
  90                         DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
  91                         DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
  92                         break;
  93                 default:
  94                         break;
  95                 }
  96
  97         } else {
  98                 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
  99         }
 100 }
 101
 102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
 103 {
 104         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 105         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 106
 107         DRM_DEBUG("GFX\n");
 108         amdgpu_ucode_print_common_hdr(hdr);
 109
 110         if (version_major == 1) {
 111                 const struct gfx_firmware_header_v1_0 *gfx_hdr =
 112                         container_of(hdr, struct gfx_firmware_header_v1_0, header);
 113
 114                 DRM_DEBUG("ucode_feature_version: %u\n",
 115                           le32_to_cpu(gfx_hdr->ucode_feature_version));
 116                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
 117                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
 118         } else if (version_major == 2) {
 119                 const struct gfx_firmware_header_v2_0 *gfx_hdr =
 120                         container_of(hdr, struct gfx_firmware_header_v2_0, header);
 121
 122                 DRM_DEBUG("ucode_feature_version: %u\n",
 123                           le32_to_cpu(gfx_hdr->ucode_feature_version));
 124         } else {
 125                 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
 126         }
 127 }
 128
 129 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
 130 {
 131         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 132         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 133
 134         DRM_DEBUG("RLC\n");
 135         amdgpu_ucode_print_common_hdr(hdr);
 136
 137         if (version_major == 1) {
 138                 const struct rlc_firmware_header_v1_0 *rlc_hdr =
 139                         container_of(hdr, struct rlc_firmware_header_v1_0, header);
 140
 141                 DRM_DEBUG("ucode_feature_version: %u\n",
 142                           le32_to_cpu(rlc_hdr->ucode_feature_version));
 143                 DRM_DEBUG("save_and_restore_offset: %u\n",
 144                           le32_to_cpu(rlc_hdr->save_and_restore_offset));
 145                 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
 146                           le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
 147                 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
 148                           le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
 149                 DRM_DEBUG("master_pkt_description_offset: %u\n",
 150                           le32_to_cpu(rlc_hdr->master_pkt_description_offset));
 151         } else if (version_major == 2) {
 152                 const struct rlc_firmware_header_v2_0 *rlc_hdr =
 153                         container_of(hdr, struct rlc_firmware_header_v2_0, header);
 154
 155                 DRM_DEBUG("ucode_feature_version: %u\n",
 156                           le32_to_cpu(rlc_hdr->ucode_feature_version));
 157                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
 158                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
 159                 DRM_DEBUG("save_and_restore_offset: %u\n",
 160                           le32_to_cpu(rlc_hdr->save_and_restore_offset));
 161                 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
 162                           le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
 163                 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
 164                           le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
 165                 DRM_DEBUG("reg_restore_list_size: %u\n",
 166                           le32_to_cpu(rlc_hdr->reg_restore_list_size));
 167                 DRM_DEBUG("reg_list_format_start: %u\n",
 168                           le32_to_cpu(rlc_hdr->reg_list_format_start));
 169                 DRM_DEBUG("reg_list_format_separate_start: %u\n",
 170                           le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
 171                 DRM_DEBUG("starting_offsets_start: %u\n",
 172                           le32_to_cpu(rlc_hdr->starting_offsets_start));
 173                 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
 174                           le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
 175                 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
 176                           le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 177                 DRM_DEBUG("reg_list_size_bytes: %u\n",
 178                           le32_to_cpu(rlc_hdr->reg_list_size_bytes));
 179                 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
 180                           le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 181                 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
 182                           le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
 183                 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
 184                           le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
 185                 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
 186                           le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
 187                 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
 188                           le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
 189                 if (version_minor == 1) {
 190                         const struct rlc_firmware_header_v2_1 *v2_1 =
 191                                 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
 192                         DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
 193                                   le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
 194                         DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
 195                                   le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
 196                         DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
 197                                   le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
 198                         DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
 199                                   le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
 200                         DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
 201                                   le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
 202                         DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
 203                                   le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
 204                         DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
 205                                   le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
 206                         DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
 207                                   le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
 208                         DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
 209                                   le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
 210                         DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
 211                                   le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
 212                         DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
 213                                   le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
 214                         DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
 215                                   le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
 216                         DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
 217                                   le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
 218                 }
 219         } else {
 220                 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
 221         }
 222 }
 223
 224 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
 225 {
 226         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 227         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 228
 229         DRM_DEBUG("SDMA\n");
 230         amdgpu_ucode_print_common_hdr(hdr);
 231
 232         if (version_major == 1) {
 233                 const struct sdma_firmware_header_v1_0 *sdma_hdr =
 234                         container_of(hdr, struct sdma_firmware_header_v1_0, header);
 235
 236                 DRM_DEBUG("ucode_feature_version: %u\n",
 237                           le32_to_cpu(sdma_hdr->ucode_feature_version));
 238                 DRM_DEBUG("ucode_change_version: %u\n",
 239                           le32_to_cpu(sdma_hdr->ucode_change_version));
 240                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
 241                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
 242                 if (version_minor >= 1) {
 243                         const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
 244                                 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
 245                         DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
 246                 }
 247         } else {
 248                 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
 249                           version_major, version_minor);
 250         }
 251 }
 252
 253 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
 254 {
 255         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 256         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 257         uint32_t fw_index;
 258         const struct psp_fw_bin_desc *desc;
 259
 260         DRM_DEBUG("PSP\n");
 261         amdgpu_ucode_print_common_hdr(hdr);
 262
 263         if (version_major == 1) {
 264                 const struct psp_firmware_header_v1_0 *psp_hdr =
 265                         container_of(hdr, struct psp_firmware_header_v1_0, header);
 266
 267                 DRM_DEBUG("ucode_feature_version: %u\n",
 268                           le32_to_cpu(psp_hdr->sos.fw_version));
 269                 DRM_DEBUG("sos_offset_bytes: %u\n",
 270                           le32_to_cpu(psp_hdr->sos.offset_bytes));
 271                 DRM_DEBUG("sos_size_bytes: %u\n",
 272                           le32_to_cpu(psp_hdr->sos.size_bytes));
 273                 if (version_minor == 1) {
 274                         const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
 275                                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
 276                         DRM_DEBUG("toc_header_version: %u\n",
 277                                   le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
 278                         DRM_DEBUG("toc_offset_bytes: %u\n",
 279                                   le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
 280                         DRM_DEBUG("toc_size_bytes: %u\n",
 281                                   le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
 282                         DRM_DEBUG("kdb_header_version: %u\n",
 283                                   le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
 284                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 285                                   le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
 286                         DRM_DEBUG("kdb_size_bytes: %u\n",
 287                                   le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
 288                 }
 289                 if (version_minor == 2) {
 290                         const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
 291                                 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
 292                         DRM_DEBUG("kdb_header_version: %u\n",
 293                                   le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
 294                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 295                                   le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
 296                         DRM_DEBUG("kdb_size_bytes: %u\n",
 297                                   le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
 298                 }
 299                 if (version_minor == 3) {
 300                         const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
 301                                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
 302                         const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
 303                                 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
 304                         DRM_DEBUG("toc_header_version: %u\n",
 305                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
 306                         DRM_DEBUG("toc_offset_bytes: %u\n",
 307                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
 308                         DRM_DEBUG("toc_size_bytes: %u\n",
 309                                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
 310                         DRM_DEBUG("kdb_header_version: %u\n",
 311                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
 312                         DRM_DEBUG("kdb_offset_bytes: %u\n",
 313                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
 314                         DRM_DEBUG("kdb_size_bytes: %u\n",
 315                                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
 316                         DRM_DEBUG("spl_header_version: %u\n",
 317                                   le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
 318                         DRM_DEBUG("spl_offset_bytes: %u\n",
 319                                   le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
 320                         DRM_DEBUG("spl_size_bytes: %u\n",
 321                                   le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
 322                 }
 323         } else if (version_major == 2) {
 324                 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 =
 325                          container_of(hdr, struct psp_firmware_header_v2_0, header);
 326                 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) {
 327                         desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]);
 328                         switch (desc->fw_type) {
 329                         case PSP_FW_TYPE_PSP_SOS:
 330                                 DRM_DEBUG("psp_sos_version: %u\n",
 331                                           le32_to_cpu(desc->fw_version));
 332                                 DRM_DEBUG("psp_sos_size_bytes: %u\n",
 333                                           le32_to_cpu(desc->size_bytes));
 334                                 break;
 335                         case PSP_FW_TYPE_PSP_SYS_DRV:
 336                                 DRM_DEBUG("psp_sys_drv_version: %u\n",
 337                                           le32_to_cpu(desc->fw_version));
 338                                 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",
 339                                           le32_to_cpu(desc->size_bytes));
 340                                 break;
 341                         case PSP_FW_TYPE_PSP_KDB:
 342                                 DRM_DEBUG("psp_kdb_version: %u\n",
 343                                           le32_to_cpu(desc->fw_version));
 344                                 DRM_DEBUG("psp_kdb_size_bytes: %u\n",
 345                                           le32_to_cpu(desc->size_bytes));
 346                                 break;
 347                         case PSP_FW_TYPE_PSP_TOC:
 348                                 DRM_DEBUG("psp_toc_version: %u\n",
 349                                           le32_to_cpu(desc->fw_version));
 350                                 DRM_DEBUG("psp_toc_size_bytes: %u\n",
 351                                           le32_to_cpu(desc->size_bytes));
 352                                 break;
 353                         case PSP_FW_TYPE_PSP_SPL:
 354                                 DRM_DEBUG("psp_spl_version: %u\n",
 355                                           le32_to_cpu(desc->fw_version));
 356                                 DRM_DEBUG("psp_spl_size_bytes: %u\n",
 357                                           le32_to_cpu(desc->size_bytes));
 358                                 break;
 359                         case PSP_FW_TYPE_PSP_RL:
 360                                 DRM_DEBUG("psp_rl_version: %u\n",
 361                                           le32_to_cpu(desc->fw_version));
 362                                 DRM_DEBUG("psp_rl_size_bytes: %u\n",
 363                                           le32_to_cpu(desc->size_bytes));
 364                                 break;
 365                         case PSP_FW_TYPE_PSP_SOC_DRV:
 366                                 DRM_DEBUG("psp_soc_drv_version: %u\n",
 367                                           le32_to_cpu(desc->fw_version));
 368                                 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",
 369                                           le32_to_cpu(desc->size_bytes));
 370                                 break;
 371                         case PSP_FW_TYPE_PSP_INTF_DRV:
 372                                 DRM_DEBUG("psp_intf_drv_version: %u\n",
 373                                           le32_to_cpu(desc->fw_version));
 374                                 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",
 375                                           le32_to_cpu(desc->size_bytes));
 376                                 break;
 377                         case PSP_FW_TYPE_PSP_DBG_DRV:
 378                                 DRM_DEBUG("psp_dbg_drv_version: %u\n",
 379                                           le32_to_cpu(desc->fw_version));
 380                                 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
 381                                           le32_to_cpu(desc->size_bytes));
 382                                 break;
 383                         default:
 384                                 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);
 385                                 break;
 386                         }
 387                 }
 388         } else {
 389                 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
 390                           version_major, version_minor);
 391         }
 392 }
 393
 394 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
 395 {
 396         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 397         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 398
 399         DRM_DEBUG("GPU_INFO\n");
 400         amdgpu_ucode_print_common_hdr(hdr);
 401
 402         if (version_major == 1) {
 403                 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
 404                         container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
 405
 406                 DRM_DEBUG("version_major: %u\n",
 407                           le16_to_cpu(gpu_info_hdr->version_major));
 408                 DRM_DEBUG("version_minor: %u\n",
 409                           le16_to_cpu(gpu_info_hdr->version_minor));
 410         } else {
 411                 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
 412         }
 413 }
 414
 415 int amdgpu_ucode_validate(const struct firmware *fw)
 416 {
 417         const struct common_firmware_header *hdr =
 418                 (const struct common_firmware_header *)fw->data;
 419
 420         if (fw->size == le32_to_cpu(hdr->size_bytes))
 421                 return 0;
 422
 423         return -EINVAL;
 424 }
 425
 426 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 427                                 uint16_t hdr_major, uint16_t hdr_minor)
 428 {
 429         if ((hdr->common.header_version_major == hdr_major) &&
 430                 (hdr->common.header_version_minor == hdr_minor))
 431                 return false;
 432         return true;
 433 }
 434
 435 enum amdgpu_firmware_load_type
 436 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 437 {
 438         switch (adev->asic_type) {
 439 #ifdef CONFIG_DRM_AMDGPU_SI
 440         case CHIP_TAHITI:
 441         case CHIP_PITCAIRN:
 442         case CHIP_VERDE:
 443         case CHIP_OLAND:
 444         case CHIP_HAINAN:
 445                 return AMDGPU_FW_LOAD_DIRECT;
 446 #endif
 447 #ifdef CONFIG_DRM_AMDGPU_CIK
 448         case CHIP_BONAIRE:
 449         case CHIP_KAVERI:
 450         case CHIP_KABINI:
 451         case CHIP_HAWAII:
 452         case CHIP_MULLINS:
 453                 return AMDGPU_FW_LOAD_DIRECT;
 454 #endif
 455         case CHIP_TOPAZ:
 456         case CHIP_TONGA:
 457         case CHIP_FIJI:
 458         case CHIP_CARRIZO:
 459         case CHIP_STONEY:
 460         case CHIP_POLARIS10:
 461         case CHIP_POLARIS11:
 462         case CHIP_POLARIS12:
 463         case CHIP_VEGAM:
 464                 return AMDGPU_FW_LOAD_SMU;
 465         case CHIP_VEGA10:
 466         case CHIP_RAVEN:
 467         case CHIP_VEGA12:
 468         case CHIP_VEGA20:
 469         case CHIP_ARCTURUS:
 470         case CHIP_RENOIR:
 471         case CHIP_NAVI10:
 472         case CHIP_NAVI14:
 473         case CHIP_NAVI12:
 474         case CHIP_SIENNA_CICHLID:
 475         case CHIP_NAVY_FLOUNDER:
 476         case CHIP_VANGOGH:
 477         case CHIP_DIMGREY_CAVEFISH:
 478         case CHIP_ALDEBARAN:
 479         case CHIP_BEIGE_GOBY:
 480         case CHIP_YELLOW_CARP:
 481                 if (!load_type)
 482                         return AMDGPU_FW_LOAD_DIRECT;
 483                 else
 484                         return AMDGPU_FW_LOAD_PSP;
 485         case CHIP_CYAN_SKILLFISH:
 486                 if (!(load_type &&
 487                       adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
 488                         return AMDGPU_FW_LOAD_DIRECT;
 489                 else
 490                         return AMDGPU_FW_LOAD_PSP;
 491         default:
 492                 if (!load_type)
 493                         return AMDGPU_FW_LOAD_DIRECT;
 494                 else
 495                         return AMDGPU_FW_LOAD_PSP;
 496         }
 497 }
 498
 499 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
 500 {
 501         switch (ucode_id) {
 502         case AMDGPU_UCODE_ID_SDMA0:
 503                 return "SDMA0";
 504         case AMDGPU_UCODE_ID_SDMA1:
 505                 return "SDMA1";
 506         case AMDGPU_UCODE_ID_SDMA2:
 507                 return "SDMA2";
 508         case AMDGPU_UCODE_ID_SDMA3:
 509                 return "SDMA3";
 510         case AMDGPU_UCODE_ID_SDMA4:
 511                 return "SDMA4";
 512         case AMDGPU_UCODE_ID_SDMA5:
 513                 return "SDMA5";
 514         case AMDGPU_UCODE_ID_SDMA6:
 515                 return "SDMA6";
 516         case AMDGPU_UCODE_ID_SDMA7:
 517                 return "SDMA7";
 518         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
 519                 return "SDMA_CTX";
 520         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
 521                 return "SDMA_CTL";
 522         case AMDGPU_UCODE_ID_CP_CE:
 523                 return "CP_CE";
 524         case AMDGPU_UCODE_ID_CP_PFP:
 525                 return "CP_PFP";
 526         case AMDGPU_UCODE_ID_CP_ME:
 527                 return "CP_ME";
 528         case AMDGPU_UCODE_ID_CP_MEC1:
 529                 return "CP_MEC1";
 530         case AMDGPU_UCODE_ID_CP_MEC1_JT:
 531                 return "CP_MEC1_JT";
 532         case AMDGPU_UCODE_ID_CP_MEC2:
 533                 return "CP_MEC2";
 534         case AMDGPU_UCODE_ID_CP_MEC2_JT:
 535                 return "CP_MEC2_JT";
 536         case AMDGPU_UCODE_ID_CP_MES:
 537                 return "CP_MES";
 538         case AMDGPU_UCODE_ID_CP_MES_DATA:
 539                 return "CP_MES_DATA";
 540         case AMDGPU_UCODE_ID_CP_MES1:
 541                 return "CP_MES_KIQ";
 542         case AMDGPU_UCODE_ID_CP_MES1_DATA:
 543                 return "CP_MES_KIQ_DATA";
 544         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 545                 return "RLC_RESTORE_LIST_CNTL";
 546         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 547                 return "RLC_RESTORE_LIST_GPM_MEM";
 548         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 549                 return "RLC_RESTORE_LIST_SRM_MEM";
 550         case AMDGPU_UCODE_ID_RLC_IRAM:
 551                 return "RLC_IRAM";
 552         case AMDGPU_UCODE_ID_RLC_DRAM:
 553                 return "RLC_DRAM";
 554         case AMDGPU_UCODE_ID_RLC_G:
 555                 return "RLC_G";
 556         case AMDGPU_UCODE_ID_RLC_P:
 557                 return "RLC_P";
 558         case AMDGPU_UCODE_ID_RLC_V:
 559                 return "RLC_V";
 560         case AMDGPU_UCODE_ID_IMU_I:
 561                 return "IMU_I";
 562         case AMDGPU_UCODE_ID_IMU_D:
 563                 return "IMU_D";
 564         case AMDGPU_UCODE_ID_STORAGE:
 565                 return "STORAGE";
 566         case AMDGPU_UCODE_ID_SMC:
 567                 return "SMC";
 568         case AMDGPU_UCODE_ID_PPTABLE:
 569                 return "PPTABLE";
 570         case AMDGPU_UCODE_ID_UVD:
 571                 return "UVD";
 572         case AMDGPU_UCODE_ID_UVD1:
 573                 return "UVD1";
 574         case AMDGPU_UCODE_ID_VCE:
 575                 return "VCE";
 576         case AMDGPU_UCODE_ID_VCN:
 577                 return "VCN";
 578         case AMDGPU_UCODE_ID_VCN1:
 579                 return "VCN1";
 580         case AMDGPU_UCODE_ID_DMCU_ERAM:
 581                 return "DMCU_ERAM";
 582         case AMDGPU_UCODE_ID_DMCU_INTV:
 583                 return "DMCU_INTV";
 584         case AMDGPU_UCODE_ID_VCN0_RAM:
 585                 return "VCN0_RAM";
 586         case AMDGPU_UCODE_ID_VCN1_RAM:
 587                 return "VCN1_RAM";
 588         case AMDGPU_UCODE_ID_DMCUB:
 589                 return "DMCUB";
 590         default:
 591                 return "UNKNOWN UCODE";
 592         }
 593 }
 594
 595 #define FW_VERSION_ATTR(name, mode, field)                              \
 596 static ssize_t show_##name(struct device *dev,                          \
 597                           struct device_attribute *attr,                \
 598                           char *buf)                                    \
 599 {                                                                       \
 600         struct drm_device *ddev = dev_get_drvdata(dev);                 \
 601         struct amdgpu_device *adev = drm_to_adev(ddev);                 \
 602                                                                         \
 603         return sysfs_emit(buf, "0x%08x\n", adev->field);        \
 604 }                                                                       \
 605 static DEVICE_ATTR(name, mode, show_##name, NULL)
 606
 607 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
 608 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
 609 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
 610 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
 611 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
 612 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
 613 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
 614 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
 615 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
 616 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
 617 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
 618 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
 619 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
 620 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
 621 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
 622 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);
 623 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
 624 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
 625 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
 626 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
 627 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
 628
 629 static struct attribute *fw_attrs[] = {
 630         &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
 631         &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
 632         &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
 633         &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
 634         &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
 635         &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
 636         &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
 637         &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
 638         &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
 639         &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
 640         &dev_attr_dmcu_fw_version.attr, NULL
 641 };
 642
 643 static const struct attribute_group fw_attr_group = {
 644         .name = "fw_version",
 645         .attrs = fw_attrs
 646 };
 647
 648 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
 649 {
 650         return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
 651 }
 652
 653 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
 654 {
 655         sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
 656 }
 657
 658 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
 659                                        struct amdgpu_firmware_info *ucode,
 660                                        uint64_t mc_addr, void *kptr)
 661 {
 662         const struct common_firmware_header *header = NULL;
 663         const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
 664         const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
 665         const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
 666         const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
 667         const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
 668         const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
 669         u8 *ucode_addr;
 670
 671         if (NULL == ucode->fw)
 672                 return 0;
 673
 674         ucode->mc_addr = mc_addr;
 675         ucode->kaddr = kptr;
 676
 677         if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
 678                 return 0;
 679
 680         header = (const struct common_firmware_header *)ucode->fw->data;
 681         cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 682         dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
 683         dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
 684         mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
 685         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
 686         imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
 687
 688         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 689                 switch (ucode->ucode_id) {
 690                 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
 691                         ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_jt_offset + sdma_hdr->ctx_jt_size);
 692                         ucode_addr = (u8 *)ucode->fw->data +
 693                                 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);
 694                         break;
 695                 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
 696                         ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_jt_offset + sdma_hdr->ctl_jt_size);
 697                         ucode_addr = (u8 *)ucode->fw->data +
 698                                 le32_to_cpu(sdma_hdr->ctl_ucode_offset);
 699                         break;
 700                 case AMDGPU_UCODE_ID_CP_MEC1:
 701                 case AMDGPU_UCODE_ID_CP_MEC2:
 702                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
 703                                 le32_to_cpu(cp_hdr->jt_size) * 4;
 704                         ucode_addr = (u8 *)ucode->fw->data +
 705                                 le32_to_cpu(header->ucode_array_offset_bytes);
 706                         break;
 707                 case AMDGPU_UCODE_ID_CP_MEC1_JT:
 708                 case AMDGPU_UCODE_ID_CP_MEC2_JT:
 709                         ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
 710                         ucode_addr = (u8 *)ucode->fw->data +
 711                                 le32_to_cpu(header->ucode_array_offset_bytes) +
 712                                 le32_to_cpu(cp_hdr->jt_offset) * 4;
 713                         break;
 714                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 715                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
 716                         ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
 717                         break;
 718                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 719                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
 720                         ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
 721                         break;
 722                 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 723                         ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
 724                         ucode_addr = adev->gfx.rlc.save_restore_list_srm;
 725                         break;
 726                 case AMDGPU_UCODE_ID_RLC_IRAM:
 727                         ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
 728                         ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
 729                         break;
 730                 case AMDGPU_UCODE_ID_RLC_DRAM:
 731                         ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
 732                         ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
 733                         break;
 734                 case AMDGPU_UCODE_ID_RLC_P:
 735                         ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
 736                         ucode_addr = adev->gfx.rlc.rlcp_ucode;
 737                         break;
 738                 case AMDGPU_UCODE_ID_RLC_V:
 739                         ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
 740                         ucode_addr = adev->gfx.rlc.rlcv_ucode;
 741                         break;
 742                 case AMDGPU_UCODE_ID_CP_MES:
 743                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 744                         ucode_addr = (u8 *)ucode->fw->data +
 745                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
 746                         break;
 747                 case AMDGPU_UCODE_ID_CP_MES_DATA:
 748                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 749                         ucode_addr = (u8 *)ucode->fw->data +
 750                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
 751                         break;
 752                 case AMDGPU_UCODE_ID_CP_MES1:
 753                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 754                         ucode_addr = (u8 *)ucode->fw->data +
 755                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
 756                         break;
 757                 case AMDGPU_UCODE_ID_CP_MES1_DATA:
 758                         ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 759                         ucode_addr = (u8 *)ucode->fw->data +
 760                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
 761                         break;
 762                 case AMDGPU_UCODE_ID_DMCU_ERAM:
 763                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
 764                                 le32_to_cpu(dmcu_hdr->intv_size_bytes);
 765                         ucode_addr = (u8 *)ucode->fw->data +
 766                                 le32_to_cpu(header->ucode_array_offset_bytes);
 767                         break;
 768                 case AMDGPU_UCODE_ID_DMCU_INTV:
 769                         ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
 770                         ucode_addr = (u8 *)ucode->fw->data +
 771                                 le32_to_cpu(header->ucode_array_offset_bytes) +
 772                                 le32_to_cpu(dmcu_hdr->intv_offset_bytes);
 773                         break;
 774                 case AMDGPU_UCODE_ID_DMCUB:
 775                         ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
 776                         ucode_addr = (u8 *)ucode->fw->data +
 777                                 le32_to_cpu(header->ucode_array_offset_bytes);
 778                         break;
 779                 case AMDGPU_UCODE_ID_PPTABLE:
 780                         ucode->ucode_size = ucode->fw->size;
 781                         ucode_addr = (u8 *)ucode->fw->data;
 782                         break;
 783                 case AMDGPU_UCODE_ID_IMU_I:
 784                         ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
 785                         ucode_addr = (u8 *)ucode->fw->data +
 786                                 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
 787                         break;
 788                 case AMDGPU_UCODE_ID_IMU_D:
 789                         ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
 790                         ucode_addr = (u8 *)ucode->fw->data +
 791                                 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
 792                                 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
 793                         break;
 794                 default:
 795                         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
 796                         ucode_addr = (u8 *)ucode->fw->data +
 797                                 le32_to_cpu(header->ucode_array_offset_bytes);
 798                         break;
 799                 }
 800         } else {
 801                 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
 802                 ucode_addr = (u8 *)ucode->fw->data +
 803                         le32_to_cpu(header->ucode_array_offset_bytes);
 804         }
 805
 806         memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
 807
 808         return 0;
 809 }
 810
 811 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
 812                                 uint64_t mc_addr, void *kptr)
 813 {
 814         const struct gfx_firmware_header_v1_0 *header = NULL;
 815         const struct common_firmware_header *comm_hdr = NULL;
 816         uint8_t *src_addr = NULL;
 817         uint8_t *dst_addr = NULL;
 818
 819         if (NULL == ucode->fw)
 820                 return 0;
 821
 822         comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
 823         header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 824         dst_addr = ucode->kaddr +
 825                            ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
 826                            PAGE_SIZE);
 827         src_addr = (uint8_t *)ucode->fw->data +
 828                            le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
 829                            (le32_to_cpu(header->jt_offset) * 4);
 830         memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
 831
 832         return 0;
 833 }
 834
 835 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
 836 {
 837         if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
 838                 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
 839                         amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 840                         &adev->firmware.fw_buf,
 841                         &adev->firmware.fw_buf_mc,
 842                         &adev->firmware.fw_buf_ptr);
 843                 if (!adev->firmware.fw_buf) {
 844                         dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
 845                         return -ENOMEM;
 846                 } else if (amdgpu_sriov_vf(adev)) {
 847                         memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
 848                 }
 849         }
 850         return 0;
 851 }
 852
 853 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
 854 {
 855         amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
 856                 &adev->firmware.fw_buf_mc,
 857                 &adev->firmware.fw_buf_ptr);
 858 }
 859
 860 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 861 {
 862         uint64_t fw_offset = 0;
 863         int i;
 864         struct amdgpu_firmware_info *ucode = NULL;
 865
 866  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
 867         if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
 868                 return 0;
 869         /*
 870          * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
 871          * ucode info here
 872          */
 873         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 874                 if (amdgpu_sriov_vf(adev))
 875                         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
 876                 else
 877                         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
 878         } else {
 879                 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
 880         }
 881
 882         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 883                 ucode = &adev->firmware.ucode[i];
 884                 if (ucode->fw) {
 885                         amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
 886                                                     adev->firmware.fw_buf_ptr + fw_offset);
 887                         if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
 888                             adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 889                                 const struct gfx_firmware_header_v1_0 *cp_hdr;
 890                                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 891                                 amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
 892                                                     adev->firmware.fw_buf_ptr + fw_offset);
 893                                 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
 894                         }
 895                         fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
 896                 }
 897         }
 898         return 0;
 899 }
 900
 901 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
 902 {
 903         int maj, min, rev;
 904         char *ip_name;
 905         uint32_t version = adev->ip_versions[block_type][0];
 906
 907         switch (block_type) {
 908         case GC_HWIP:
 909                 ip_name = "gc";
 910                 break;
 911         case SDMA0_HWIP:
 912                 ip_name = "sdma";
 913                 break;
 914         case MP0_HWIP:
 915                 ip_name = "psp";
 916                 break;
 917         case MP1_HWIP:
 918                 ip_name = "smu";
 919                 break;
 920         case UVD_HWIP:
 921                 ip_name = "vcn";
 922                 break;
 923         default:
 924                 BUG();
 925         }
 926
 927         maj = IP_VERSION_MAJ(version);
 928         min = IP_VERSION_MIN(version);
 929         rev = IP_VERSION_REV(version);
 930
 931         snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev);
 932 }