2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
46 #include "drm_crtc_internal.h"
48 static int oui(u8 first, u8 second, u8 third)
50 return (first << 16) | (second << 8) | third;
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
91 #define MICROSOFT_IEEE_OUI 0xca125c
93 struct detailed_mode_closure {
94 struct drm_connector *connector;
95 const struct drm_edid *drm_edid;
106 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
113 static const struct edid_quirk {
116 } edid_quirk_list[] = {
118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
137 /* Belinea 10 15 55 */
138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
141 /* Envision Peripherals, Inc. EN-7100e */
142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
143 /* Envision EN2028 */
144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
146 /* Funai Electronics PM36B */
147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
148 EDID_QUIRK_DETAILED_IN_CM),
150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
153 /* LG Philips LCD LP154W01-A5 */
154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
157 /* Samsung SyncMaster 205BW. Note: irony */
158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
159 /* Samsung SyncMaster 22[5-6]BW */
160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
166 /* ViewSonic VA2026w */
167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
169 /* Medion MD 30217 PG */
170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
181 /* Valve Index Headset */
182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
200 /* HTC Vive and Vive Pro VR Headsets */
201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
210 /* Windows Mixed Reality Headsets */
211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
218 /* Sony PlayStation VR Headset */
219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
221 /* Sensics VR Headsets */
222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
224 /* OSVR HDK and HDK2 VR Headsets */
225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
229 * Autogenerated from the DMT spec.
230 * This table is copied from xfree86/modes/xf86EdidModes.c.
232 static const struct drm_display_mode drm_dmt_modes[] = {
233 /* 0x01 - 640x350@85Hz */
234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
235 736, 832, 0, 350, 382, 385, 445, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x02 - 640x400@85Hz */
238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
239 736, 832, 0, 400, 401, 404, 445, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x03 - 720x400@85Hz */
242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
243 828, 936, 0, 400, 401, 404, 446, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x04 - 640x480@60Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
247 752, 800, 0, 480, 490, 492, 525, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x05 - 640x480@72Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
251 704, 832, 0, 480, 489, 492, 520, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x06 - 640x480@75Hz */
254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
255 720, 840, 0, 480, 481, 484, 500, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
257 /* 0x07 - 640x480@85Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
259 752, 832, 0, 480, 481, 484, 509, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x08 - 800x600@56Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
263 896, 1024, 0, 600, 601, 603, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x09 - 800x600@60Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
267 968, 1056, 0, 600, 601, 605, 628, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0a - 800x600@72Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
271 976, 1040, 0, 600, 637, 643, 666, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0b - 800x600@75Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
275 896, 1056, 0, 600, 601, 604, 625, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0c - 800x600@85Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
279 896, 1048, 0, 600, 601, 604, 631, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0d - 800x600@120Hz RB */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
283 880, 960, 0, 600, 603, 607, 636, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
285 /* 0x0e - 848x480@60Hz */
286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
287 976, 1088, 0, 480, 486, 494, 517, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x0f - 1024x768@43Hz, interlace */
290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
291 1208, 1264, 0, 768, 768, 776, 817, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
293 DRM_MODE_FLAG_INTERLACE) },
294 /* 0x10 - 1024x768@60Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
296 1184, 1344, 0, 768, 771, 777, 806, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
298 /* 0x11 - 1024x768@70Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
300 1184, 1328, 0, 768, 771, 777, 806, 0,
301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x12 - 1024x768@75Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
304 1136, 1312, 0, 768, 769, 772, 800, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x13 - 1024x768@85Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
308 1168, 1376, 0, 768, 769, 772, 808, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x14 - 1024x768@120Hz RB */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
312 1104, 1184, 0, 768, 771, 775, 813, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x15 - 1152x864@75Hz */
315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
316 1344, 1600, 0, 864, 865, 868, 900, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x55 - 1280x720@60Hz */
319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
320 1430, 1650, 0, 720, 725, 730, 750, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x16 - 1280x768@60Hz RB */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
324 1360, 1440, 0, 768, 771, 778, 790, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x17 - 1280x768@60Hz */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
328 1472, 1664, 0, 768, 771, 778, 798, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x18 - 1280x768@75Hz */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
332 1488, 1696, 0, 768, 771, 778, 805, 0,
333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x19 - 1280x768@85Hz */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
336 1496, 1712, 0, 768, 771, 778, 809, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x1a - 1280x768@120Hz RB */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
340 1360, 1440, 0, 768, 771, 778, 813, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
342 /* 0x1b - 1280x800@60Hz RB */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
344 1360, 1440, 0, 800, 803, 809, 823, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
346 /* 0x1c - 1280x800@60Hz */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
348 1480, 1680, 0, 800, 803, 809, 831, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1d - 1280x800@75Hz */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
352 1488, 1696, 0, 800, 803, 809, 838, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x1e - 1280x800@85Hz */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
356 1496, 1712, 0, 800, 803, 809, 843, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x1f - 1280x800@120Hz RB */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
360 1360, 1440, 0, 800, 803, 809, 847, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362 /* 0x20 - 1280x960@60Hz */
363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
364 1488, 1800, 0, 960, 961, 964, 1000, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x21 - 1280x960@85Hz */
367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
368 1504, 1728, 0, 960, 961, 964, 1011, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x22 - 1280x960@120Hz RB */
371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
372 1360, 1440, 0, 960, 963, 967, 1017, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x23 - 1280x1024@60Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x24 - 1280x1024@75Hz */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x25 - 1280x1024@85Hz */
383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x26 - 1280x1024@120Hz RB */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x27 - 1360x768@60Hz */
391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
392 1536, 1792, 0, 768, 771, 777, 795, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x28 - 1360x768@120Hz RB */
395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
396 1440, 1520, 0, 768, 771, 776, 813, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x51 - 1366x768@60Hz */
399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
400 1579, 1792, 0, 768, 771, 774, 798, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x56 - 1366x768@60Hz */
403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
404 1436, 1500, 0, 768, 769, 772, 800, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x29 - 1400x1050@60Hz RB */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
410 /* 0x2a - 1400x1050@60Hz */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x2b - 1400x1050@75Hz */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x2c - 1400x1050@85Hz */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x2d - 1400x1050@120Hz RB */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
426 /* 0x2e - 1440x900@60Hz RB */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
428 1520, 1600, 0, 900, 903, 909, 926, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
430 /* 0x2f - 1440x900@60Hz */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
432 1672, 1904, 0, 900, 903, 909, 934, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x30 - 1440x900@75Hz */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
436 1688, 1936, 0, 900, 903, 909, 942, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x31 - 1440x900@85Hz */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
440 1696, 1952, 0, 900, 903, 909, 948, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x32 - 1440x900@120Hz RB */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
444 1520, 1600, 0, 900, 903, 909, 953, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
446 /* 0x53 - 1600x900@60Hz */
447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
448 1704, 1800, 0, 900, 901, 904, 1000, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x33 - 1600x1200@60Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x34 - 1600x1200@65Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x35 - 1600x1200@70Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x36 - 1600x1200@75Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x37 - 1600x1200@85Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x38 - 1600x1200@120Hz RB */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
474 /* 0x39 - 1680x1050@60Hz RB */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
478 /* 0x3a - 1680x1050@60Hz */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x3b - 1680x1050@75Hz */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x3c - 1680x1050@85Hz */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3d - 1680x1050@120Hz RB */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
494 /* 0x3e - 1792x1344@60Hz */
495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x3f - 1792x1344@75Hz */
499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x40 - 1792x1344@120Hz RB */
503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x41 - 1856x1392@60Hz */
507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x42 - 1856x1392@75Hz */
511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x43 - 1856x1392@120Hz RB */
515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x52 - 1920x1080@60Hz */
519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
522 /* 0x44 - 1920x1200@60Hz RB */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
526 /* 0x45 - 1920x1200@60Hz */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x46 - 1920x1200@75Hz */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x47 - 1920x1200@85Hz */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x48 - 1920x1200@120Hz RB */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x49 - 1920x1440@60Hz */
543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x4a - 1920x1440@75Hz */
547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4b - 1920x1440@120Hz RB */
551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x54 - 2048x1152@60Hz */
555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4c - 2560x1600@60Hz RB */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
562 /* 0x4d - 2560x1600@60Hz */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x4e - 2560x1600@75Hz */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
570 /* 0x4f - 2560x1600@85Hz */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
574 /* 0x50 - 2560x1600@120Hz RB */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
578 /* 0x57 - 4096x2160@60Hz RB */
579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
589 * These more or less come from the DMT spec. The 720x400 modes are
590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
595 * The DMT modes have been fact-checked; the rest are mild guesses.
597 static const struct drm_display_mode edid_est_modes[] = {
598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
599 968, 1056, 0, 600, 601, 605, 628, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
602 896, 1024, 0, 600, 601, 603, 625, 0,
603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
605 720, 840, 0, 480, 481, 484, 500, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
608 704, 832, 0, 480, 489, 492, 520, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
611 768, 864, 0, 480, 483, 486, 525, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
614 752, 800, 0, 480, 490, 492, 525, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
617 846, 900, 0, 400, 421, 423, 449, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
620 846, 900, 0, 400, 412, 414, 449, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
626 1136, 1312, 0, 768, 769, 772, 800, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
629 1184, 1328, 0, 768, 771, 777, 806, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
632 1184, 1344, 0, 768, 771, 777, 806, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
635 1208, 1264, 0, 768, 768, 776, 817, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
638 928, 1152, 0, 624, 625, 628, 667, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
641 896, 1056, 0, 600, 601, 604, 625, 0,
642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
644 976, 1040, 0, 600, 637, 643, 666, 0,
645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
647 1344, 1600, 0, 864, 865, 868, 900, 0,
648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
658 static const struct minimode est3_modes[] = {
666 { 1024, 768, 85, 0 },
667 { 1152, 864, 75, 0 },
669 { 1280, 768, 60, 1 },
670 { 1280, 768, 60, 0 },
671 { 1280, 768, 75, 0 },
672 { 1280, 768, 85, 0 },
673 { 1280, 960, 60, 0 },
674 { 1280, 960, 85, 0 },
675 { 1280, 1024, 60, 0 },
676 { 1280, 1024, 85, 0 },
678 { 1360, 768, 60, 0 },
679 { 1440, 900, 60, 1 },
680 { 1440, 900, 60, 0 },
681 { 1440, 900, 75, 0 },
682 { 1440, 900, 85, 0 },
683 { 1400, 1050, 60, 1 },
684 { 1400, 1050, 60, 0 },
685 { 1400, 1050, 75, 0 },
687 { 1400, 1050, 85, 0 },
688 { 1680, 1050, 60, 1 },
689 { 1680, 1050, 60, 0 },
690 { 1680, 1050, 75, 0 },
691 { 1680, 1050, 85, 0 },
692 { 1600, 1200, 60, 0 },
693 { 1600, 1200, 65, 0 },
694 { 1600, 1200, 70, 0 },
696 { 1600, 1200, 75, 0 },
697 { 1600, 1200, 85, 0 },
698 { 1792, 1344, 60, 0 },
699 { 1792, 1344, 75, 0 },
700 { 1856, 1392, 60, 0 },
701 { 1856, 1392, 75, 0 },
702 { 1920, 1200, 60, 1 },
703 { 1920, 1200, 60, 0 },
705 { 1920, 1200, 75, 0 },
706 { 1920, 1200, 85, 0 },
707 { 1920, 1440, 60, 0 },
708 { 1920, 1440, 75, 0 },
711 static const struct minimode extra_modes[] = {
712 { 1024, 576, 60, 0 },
713 { 1366, 768, 60, 0 },
714 { 1600, 900, 60, 0 },
715 { 1680, 945, 60, 0 },
716 { 1920, 1080, 60, 0 },
717 { 2048, 1152, 60, 0 },
718 { 2048, 1536, 60, 0 },
722 * From CEA/CTA-861 spec.
724 * Do not access directly, instead always use cea_mode_for_vic().
726 static const struct drm_display_mode edid_cea_modes_1[] = {
727 /* 1 - 640x480@60Hz 4:3 */
728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
729 752, 800, 0, 480, 490, 492, 525, 0,
730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
732 /* 2 - 720x480@60Hz 4:3 */
733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
734 798, 858, 0, 480, 489, 495, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
737 /* 3 - 720x480@60Hz 16:9 */
738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
742 /* 4 - 1280x720@60Hz 16:9 */
743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
744 1430, 1650, 0, 720, 725, 730, 750, 0,
745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 5 - 1920x1080i@60Hz 16:9 */
748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
751 DRM_MODE_FLAG_INTERLACE),
752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 6 - 720(1440)x480i@60Hz 4:3 */
754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 480, 488, 494, 525, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
759 /* 7 - 720(1440)x480i@60Hz 16:9 */
760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 480, 488, 494, 525, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 8 - 720(1440)x240@60Hz 4:3 */
766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 240, 244, 247, 262, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_DBLCLK),
770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 9 - 720(1440)x240@60Hz 16:9 */
772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
773 801, 858, 0, 240, 244, 247, 262, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_DBLCLK),
776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 10 - 2880x480i@60Hz 4:3 */
778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 480, 488, 494, 525, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_INTERLACE),
782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
783 /* 11 - 2880x480i@60Hz 16:9 */
784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
785 3204, 3432, 0, 480, 488, 494, 525, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
787 DRM_MODE_FLAG_INTERLACE),
788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
789 /* 12 - 2880x240@60Hz 4:3 */
790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
791 3204, 3432, 0, 240, 244, 247, 262, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 13 - 2880x240@60Hz 16:9 */
795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799 /* 14 - 1440x480@60Hz 4:3 */
800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
801 1596, 1716, 0, 480, 489, 495, 525, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
804 /* 15 - 1440x480@60Hz 16:9 */
805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
809 /* 16 - 1920x1080@60Hz 16:9 */
810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 17 - 720x576@50Hz 4:3 */
815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
816 796, 864, 0, 576, 581, 586, 625, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
819 /* 18 - 720x576@50Hz 16:9 */
820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
824 /* 19 - 1280x720@50Hz 16:9 */
825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
826 1760, 1980, 0, 720, 725, 730, 750, 0,
827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 20 - 1920x1080i@50Hz 16:9 */
830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
833 DRM_MODE_FLAG_INTERLACE),
834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 21 - 720(1440)x576i@50Hz 4:3 */
836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
841 /* 22 - 720(1440)x576i@50Hz 16:9 */
842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 576, 580, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 23 - 720(1440)x288@50Hz 4:3 */
848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 288, 290, 293, 312, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_DBLCLK),
852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 24 - 720(1440)x288@50Hz 16:9 */
854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
855 795, 864, 0, 288, 290, 293, 312, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_DBLCLK),
858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 25 - 2880x576i@50Hz 4:3 */
860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 576, 580, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
863 DRM_MODE_FLAG_INTERLACE),
864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
865 /* 26 - 2880x576i@50Hz 16:9 */
866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
867 3180, 3456, 0, 576, 580, 586, 625, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
869 DRM_MODE_FLAG_INTERLACE),
870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 27 - 2880x288@50Hz 4:3 */
872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
873 3180, 3456, 0, 288, 290, 293, 312, 0,
874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 28 - 2880x288@50Hz 16:9 */
877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
881 /* 29 - 1440x576@50Hz 4:3 */
882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
883 1592, 1728, 0, 576, 581, 586, 625, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
886 /* 30 - 1440x576@50Hz 16:9 */
887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
891 /* 31 - 1920x1080@50Hz 16:9 */
892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 32 - 1920x1080@24Hz 16:9 */
897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 33 - 1920x1080@25Hz 16:9 */
902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
906 /* 34 - 1920x1080@30Hz 16:9 */
907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
911 /* 35 - 2880x480@60Hz 4:3 */
912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
913 3192, 3432, 0, 480, 489, 495, 525, 0,
914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
916 /* 36 - 2880x480@60Hz 16:9 */
917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
921 /* 37 - 2880x576@50Hz 4:3 */
922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
923 3184, 3456, 0, 576, 581, 586, 625, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
926 /* 38 - 2880x576@50Hz 16:9 */
927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 39 - 1920x1080i@50Hz 16:9 */
932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
935 DRM_MODE_FLAG_INTERLACE),
936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
937 /* 40 - 1920x1080i@100Hz 16:9 */
938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
941 DRM_MODE_FLAG_INTERLACE),
942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 41 - 1280x720@100Hz 16:9 */
944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
945 1760, 1980, 0, 720, 725, 730, 750, 0,
946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 42 - 720x576@100Hz 4:3 */
949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
950 796, 864, 0, 576, 581, 586, 625, 0,
951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
953 /* 43 - 720x576@100Hz 16:9 */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 44 - 720(1440)x576i@100Hz 4:3 */
959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
964 /* 45 - 720(1440)x576i@100Hz 16:9 */
965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
966 795, 864, 0, 576, 580, 586, 625, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 46 - 1920x1080i@120Hz 16:9 */
971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
974 DRM_MODE_FLAG_INTERLACE),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
976 /* 47 - 1280x720@120Hz 16:9 */
977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
978 1430, 1650, 0, 720, 725, 730, 750, 0,
979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 48 - 720x480@120Hz 4:3 */
982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
983 798, 858, 0, 480, 489, 495, 525, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
986 /* 49 - 720x480@120Hz 16:9 */
987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
991 /* 50 - 720(1440)x480i@120Hz 4:3 */
992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
993 801, 858, 0, 480, 488, 494, 525, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
997 /* 51 - 720(1440)x480i@120Hz 16:9 */
998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
999 801, 858, 0, 480, 488, 494, 525, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 /* 52 - 720x576@200Hz 4:3 */
1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1005 796, 864, 0, 576, 581, 586, 625, 0,
1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1008 /* 53 - 720x576@200Hz 16:9 */
1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1013 /* 54 - 720(1440)x576i@200Hz 4:3 */
1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1015 795, 864, 0, 576, 580, 586, 625, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1019 /* 55 - 720(1440)x576i@200Hz 16:9 */
1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1021 795, 864, 0, 576, 580, 586, 625, 0,
1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025 /* 56 - 720x480@240Hz 4:3 */
1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1027 798, 858, 0, 480, 489, 495, 525, 0,
1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1030 /* 57 - 720x480@240Hz 16:9 */
1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035 /* 58 - 720(1440)x480i@240Hz 4:3 */
1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1037 801, 858, 0, 480, 488, 494, 525, 0,
1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1041 /* 59 - 720(1440)x480i@240Hz 16:9 */
1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1043 801, 858, 0, 480, 488, 494, 525, 0,
1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1047 /* 60 - 1280x720@24Hz 16:9 */
1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1049 3080, 3300, 0, 720, 725, 730, 750, 0,
1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1052 /* 61 - 1280x720@25Hz 16:9 */
1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1054 3740, 3960, 0, 720, 725, 730, 750, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1057 /* 62 - 1280x720@30Hz 16:9 */
1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1059 3080, 3300, 0, 720, 725, 730, 750, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1062 /* 63 - 1920x1080@120Hz 16:9 */
1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1067 /* 64 - 1920x1080@100Hz 16:9 */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1072 /* 65 - 1280x720@24Hz 64:27 */
1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1074 3080, 3300, 0, 720, 725, 730, 750, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077 /* 66 - 1280x720@25Hz 64:27 */
1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1079 3740, 3960, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 67 - 1280x720@30Hz 64:27 */
1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1084 3080, 3300, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 68 - 1280x720@50Hz 64:27 */
1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1089 1760, 1980, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 69 - 1280x720@60Hz 64:27 */
1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1094 1430, 1650, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 70 - 1280x720@100Hz 64:27 */
1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1099 1760, 1980, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 71 - 1280x720@120Hz 64:27 */
1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1104 1430, 1650, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 72 - 1920x1080@24Hz 64:27 */
1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 73 - 1920x1080@25Hz 64:27 */
1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 74 - 1920x1080@30Hz 64:27 */
1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 75 - 1920x1080@50Hz 64:27 */
1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 76 - 1920x1080@60Hz 64:27 */
1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 77 - 1920x1080@100Hz 64:27 */
1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 78 - 1920x1080@120Hz 64:27 */
1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 79 - 1680x720@24Hz 64:27 */
1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1144 3080, 3300, 0, 720, 725, 730, 750, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 80 - 1680x720@25Hz 64:27 */
1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1149 2948, 3168, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 81 - 1680x720@30Hz 64:27 */
1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1154 2420, 2640, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 82 - 1680x720@50Hz 64:27 */
1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1159 1980, 2200, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162 /* 83 - 1680x720@60Hz 64:27 */
1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1167 /* 84 - 1680x720@100Hz 64:27 */
1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1169 1780, 2000, 0, 720, 725, 730, 825, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1172 /* 85 - 1680x720@120Hz 64:27 */
1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1177 /* 86 - 2560x1080@24Hz 64:27 */
1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1182 /* 87 - 2560x1080@25Hz 64:27 */
1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1187 /* 88 - 2560x1080@30Hz 64:27 */
1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1192 /* 89 - 2560x1080@50Hz 64:27 */
1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1197 /* 90 - 2560x1080@60Hz 64:27 */
1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1202 /* 91 - 2560x1080@100Hz 64:27 */
1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1207 /* 92 - 2560x1080@120Hz 64:27 */
1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1212 /* 93 - 3840x2160@24Hz 16:9 */
1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1217 /* 94 - 3840x2160@25Hz 16:9 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1222 /* 95 - 3840x2160@30Hz 16:9 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1227 /* 96 - 3840x2160@50Hz 16:9 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1232 /* 97 - 3840x2160@60Hz 16:9 */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1237 /* 98 - 4096x2160@24Hz 256:135 */
1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1242 /* 99 - 4096x2160@25Hz 256:135 */
1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1247 /* 100 - 4096x2160@30Hz 256:135 */
1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1252 /* 101 - 4096x2160@50Hz 256:135 */
1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1257 /* 102 - 4096x2160@60Hz 256:135 */
1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1262 /* 103 - 3840x2160@24Hz 64:27 */
1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1267 /* 104 - 3840x2160@25Hz 64:27 */
1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1272 /* 105 - 3840x2160@30Hz 64:27 */
1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1277 /* 106 - 3840x2160@50Hz 64:27 */
1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1282 /* 107 - 3840x2160@60Hz 64:27 */
1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1287 /* 108 - 1280x720@48Hz 16:9 */
1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1289 2280, 2500, 0, 720, 725, 730, 750, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1292 /* 109 - 1280x720@48Hz 64:27 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1297 /* 110 - 1680x720@48Hz 64:27 */
1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1299 2530, 2750, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1302 /* 111 - 1920x1080@48Hz 16:9 */
1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1307 /* 112 - 1920x1080@48Hz 64:27 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1312 /* 113 - 2560x1080@48Hz 64:27 */
1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1317 /* 114 - 3840x2160@48Hz 16:9 */
1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1322 /* 115 - 4096x2160@48Hz 256:135 */
1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1327 /* 116 - 3840x2160@48Hz 64:27 */
1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1332 /* 117 - 3840x2160@100Hz 16:9 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1337 /* 118 - 3840x2160@120Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1342 /* 119 - 3840x2160@100Hz 64:27 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1347 /* 120 - 3840x2160@120Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1352 /* 121 - 5120x2160@24Hz 64:27 */
1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1357 /* 122 - 5120x2160@25Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1362 /* 123 - 5120x2160@30Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1367 /* 124 - 5120x2160@48Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1372 /* 125 - 5120x2160@50Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1377 /* 126 - 5120x2160@60Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1382 /* 127 - 5120x2160@100Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 * From CEA/CTA-861 spec.
1392 * Do not access directly, instead always use cea_mode_for_vic().
1394 static const struct drm_display_mode edid_cea_modes_193[] = {
1395 /* 193 - 5120x2160@120Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1400 /* 194 - 7680x4320@24Hz 16:9 */
1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1405 /* 195 - 7680x4320@25Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1410 /* 196 - 7680x4320@30Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1415 /* 197 - 7680x4320@48Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1420 /* 198 - 7680x4320@50Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1425 /* 199 - 7680x4320@60Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1430 /* 200 - 7680x4320@100Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1435 /* 201 - 7680x4320@120Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1440 /* 202 - 7680x4320@24Hz 64:27 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1445 /* 203 - 7680x4320@25Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1450 /* 204 - 7680x4320@30Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1455 /* 205 - 7680x4320@48Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1460 /* 206 - 7680x4320@50Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1465 /* 207 - 7680x4320@60Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1470 /* 208 - 7680x4320@100Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1475 /* 209 - 7680x4320@120Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1480 /* 210 - 10240x4320@24Hz 64:27 */
1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1485 /* 211 - 10240x4320@25Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1490 /* 212 - 10240x4320@30Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1495 /* 213 - 10240x4320@48Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1500 /* 214 - 10240x4320@50Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1505 /* 215 - 10240x4320@60Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1510 /* 216 - 10240x4320@100Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1515 /* 217 - 10240x4320@120Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1520 /* 218 - 4096x2160@100Hz 256:135 */
1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1525 /* 219 - 4096x2160@120Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1533 * HDMI 1.4 4k modes. Index using the VIC.
1535 static const struct drm_display_mode edid_4k_modes[] = {
1536 /* 0 - dummy, VICs start at 1 */
1538 /* 1 - 3840x2160@30Hz */
1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1540 3840, 4016, 4104, 4400, 0,
1541 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1544 /* 2 - 3840x2160@25Hz */
1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1546 3840, 4896, 4984, 5280, 0,
1547 2160, 2168, 2178, 2250, 0,
1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1550 /* 3 - 3840x2160@24Hz */
1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1552 3840, 5116, 5204, 5500, 0,
1553 2160, 2168, 2178, 2250, 0,
1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1556 /* 4 - 4096x2160@24Hz (SMPTE) */
1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1558 4096, 5116, 5204, 5500, 0,
1559 2160, 2168, 2178, 2250, 0,
1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1564 /*** DDC fetch and block validation ***/
1567 * The opaque EDID type, internal to drm_edid.c.
1570 /* Size allocated for edid */
1572 const struct edid *edid;
1575 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1577 static int edid_hfeeodb_block_count(const struct edid *edid)
1579 int eeodb = edid_hfeeodb_extension_block_count(edid);
1581 return eeodb ? eeodb + 1 : 0;
1584 static int edid_extension_block_count(const struct edid *edid)
1586 return edid->extensions;
1589 static int edid_block_count(const struct edid *edid)
1591 return edid_extension_block_count(edid) + 1;
1594 static int edid_size_by_blocks(int num_blocks)
1596 return num_blocks * EDID_LENGTH;
1599 static int edid_size(const struct edid *edid)
1601 return edid_size_by_blocks(edid_block_count(edid));
1604 static const void *edid_block_data(const struct edid *edid, int index)
1606 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1608 return edid + index;
1611 static const void *edid_extension_block_data(const struct edid *edid, int index)
1613 return edid_block_data(edid, index + 1);
1616 /* EDID block count indicated in EDID, may exceed allocated size */
1617 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1621 /* Starting point */
1622 num_blocks = edid_block_count(drm_edid->edid);
1624 /* HF-EEODB override */
1625 if (drm_edid->size >= edid_size_by_blocks(2)) {
1629 * Note: HF-EEODB may specify a smaller extension count than the
1630 * regular one. Unlike in buffer allocation, here we can use it.
1632 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1640 /* EDID block count, limited by allocated size */
1641 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1643 /* Limit by allocated size */
1644 return min(__drm_edid_block_count(drm_edid),
1645 (int)drm_edid->size / EDID_LENGTH);
1648 /* EDID extension block count, limited by allocated size */
1649 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1651 return drm_edid_block_count(drm_edid) - 1;
1654 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1656 return edid_block_data(drm_edid->edid, index);
1659 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1662 return edid_extension_block_data(drm_edid->edid, index);
1666 * Initializer helper for legacy interfaces, where we have no choice but to
1667 * trust edid size. Not for general purpose use.
1669 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1670 const struct edid *edid)
1675 memset(drm_edid, 0, sizeof(*drm_edid));
1677 drm_edid->edid = edid;
1678 drm_edid->size = edid_size(edid);
1684 * EDID base and extension block iterator.
1686 * struct drm_edid_iter iter;
1689 * drm_edid_iter_begin(drm_edid, &iter);
1690 * drm_edid_iter_for_each(block, &iter) {
1691 * // do stuff with block
1693 * drm_edid_iter_end(&iter);
1695 struct drm_edid_iter {
1696 const struct drm_edid *drm_edid;
1698 /* Current block index. */
1702 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1703 struct drm_edid_iter *iter)
1705 memset(iter, 0, sizeof(*iter));
1707 iter->drm_edid = drm_edid;
1710 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1712 const void *block = NULL;
1714 if (!iter->drm_edid)
1717 if (iter->index < drm_edid_block_count(iter->drm_edid))
1718 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1723 #define drm_edid_iter_for_each(__block, __iter) \
1724 while (((__block) = __drm_edid_iter_next(__iter)))
1726 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1728 memset(iter, 0, sizeof(*iter));
1731 static const u8 edid_header[] = {
1732 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1735 static void edid_header_fix(void *edid)
1737 memcpy(edid, edid_header, sizeof(edid_header));
1741 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1742 * @_edid: pointer to raw base EDID block
1744 * Sanity check the header of the base EDID block.
1746 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1748 int drm_edid_header_is_valid(const void *_edid)
1750 const struct edid *edid = _edid;
1753 for (i = 0; i < sizeof(edid_header); i++) {
1754 if (edid->header[i] == edid_header[i])
1760 EXPORT_SYMBOL(drm_edid_header_is_valid);
1762 static int edid_fixup __read_mostly = 6;
1763 module_param_named(edid_fixup, edid_fixup, int, 0400);
1764 MODULE_PARM_DESC(edid_fixup,
1765 "Minimum number of valid EDID header bytes (0-8, default 6)");
1767 static int edid_block_compute_checksum(const void *_block)
1769 const u8 *block = _block;
1771 u8 csum = 0, crc = 0;
1773 for (i = 0; i < EDID_LENGTH - 1; i++)
1781 static int edid_block_get_checksum(const void *_block)
1783 const struct edid *block = _block;
1785 return block->checksum;
1788 static int edid_block_tag(const void *_block)
1790 const u8 *block = _block;
1795 static bool edid_block_is_zero(const void *edid)
1797 return !memchr_inv(edid, 0, EDID_LENGTH);
1801 * drm_edid_are_equal - compare two edid blobs.
1802 * @edid1: pointer to first blob
1803 * @edid2: pointer to second blob
1804 * This helper can be used during probing to determine if
1807 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1809 int edid1_len, edid2_len;
1810 bool edid1_present = edid1 != NULL;
1811 bool edid2_present = edid2 != NULL;
1813 if (edid1_present != edid2_present)
1817 edid1_len = edid_size(edid1);
1818 edid2_len = edid_size(edid2);
1820 if (edid1_len != edid2_len)
1823 if (memcmp(edid1, edid2, edid1_len))
1829 EXPORT_SYMBOL(drm_edid_are_equal);
1831 enum edid_block_status {
1833 EDID_BLOCK_READ_FAIL,
1836 EDID_BLOCK_HEADER_CORRUPT,
1837 EDID_BLOCK_HEADER_REPAIR,
1838 EDID_BLOCK_HEADER_FIXED,
1839 EDID_BLOCK_CHECKSUM,
1843 static enum edid_block_status edid_block_check(const void *_block,
1846 const struct edid *block = _block;
1849 return EDID_BLOCK_NULL;
1851 if (is_base_block) {
1852 int score = drm_edid_header_is_valid(block);
1854 if (score < clamp(edid_fixup, 0, 8)) {
1855 if (edid_block_is_zero(block))
1856 return EDID_BLOCK_ZERO;
1858 return EDID_BLOCK_HEADER_CORRUPT;
1862 return EDID_BLOCK_HEADER_REPAIR;
1865 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1866 if (edid_block_is_zero(block))
1867 return EDID_BLOCK_ZERO;
1869 return EDID_BLOCK_CHECKSUM;
1872 if (is_base_block) {
1873 if (block->version != 1)
1874 return EDID_BLOCK_VERSION;
1877 return EDID_BLOCK_OK;
1880 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1882 return status == EDID_BLOCK_OK ||
1883 status == EDID_BLOCK_HEADER_FIXED ||
1884 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1887 static bool edid_block_valid(const void *block, bool base)
1889 return edid_block_status_valid(edid_block_check(block, base),
1890 edid_block_tag(block));
1893 static void edid_block_status_print(enum edid_block_status status,
1894 const struct edid *block,
1900 case EDID_BLOCK_READ_FAIL:
1901 pr_debug("EDID block %d read failed\n", block_num);
1903 case EDID_BLOCK_NULL:
1904 pr_debug("EDID block %d pointer is NULL\n", block_num);
1906 case EDID_BLOCK_ZERO:
1907 pr_notice("EDID block %d is all zeroes\n", block_num);
1909 case EDID_BLOCK_HEADER_CORRUPT:
1910 pr_notice("EDID has corrupt header\n");
1912 case EDID_BLOCK_HEADER_REPAIR:
1913 pr_debug("EDID corrupt header needs repair\n");
1915 case EDID_BLOCK_HEADER_FIXED:
1916 pr_debug("EDID corrupt header fixed\n");
1918 case EDID_BLOCK_CHECKSUM:
1919 if (edid_block_status_valid(status, edid_block_tag(block))) {
1920 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1921 block_num, edid_block_tag(block),
1922 edid_block_compute_checksum(block));
1924 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1925 block_num, edid_block_tag(block),
1926 edid_block_compute_checksum(block));
1929 case EDID_BLOCK_VERSION:
1930 pr_notice("EDID has major version %d, instead of 1\n",
1934 WARN(1, "EDID block %d unknown edid block status code %d\n",
1940 static void edid_block_dump(const char *level, const void *block, int block_num)
1942 enum edid_block_status status;
1945 status = edid_block_check(block, block_num == 0);
1946 if (status == EDID_BLOCK_ZERO)
1947 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1948 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1949 sprintf(prefix, "\t[%02x] BAD ", block_num);
1951 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1953 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1954 block, EDID_LENGTH, false);
1958 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1959 * @_block: pointer to raw EDID block
1960 * @block_num: type of block to validate (0 for base, extension otherwise)
1961 * @print_bad_edid: if true, dump bad EDID blocks to the console
1962 * @edid_corrupt: if true, the header or checksum is invalid
1964 * Validate a base or extension EDID block and optionally dump bad blocks to
1967 * Return: True if the block is valid, false otherwise.
1969 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1972 struct edid *block = (struct edid *)_block;
1973 enum edid_block_status status;
1974 bool is_base_block = block_num == 0;
1977 if (WARN_ON(!block))
1980 status = edid_block_check(block, is_base_block);
1981 if (status == EDID_BLOCK_HEADER_REPAIR) {
1982 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1983 edid_header_fix(block);
1985 /* Retry with fixed header, update status if that worked. */
1986 status = edid_block_check(block, is_base_block);
1987 if (status == EDID_BLOCK_OK)
1988 status = EDID_BLOCK_HEADER_FIXED;
1993 * Unknown major version isn't corrupt but we can't use it. Only
1994 * the base block can reset edid_corrupt to false.
1996 if (is_base_block &&
1997 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1998 *edid_corrupt = false;
1999 else if (status != EDID_BLOCK_OK)
2000 *edid_corrupt = true;
2003 edid_block_status_print(status, block, block_num);
2005 /* Determine whether we can use this block with this status. */
2006 valid = edid_block_status_valid(status, edid_block_tag(block));
2008 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2009 pr_notice("Raw EDID:\n");
2010 edid_block_dump(KERN_NOTICE, block, block_num);
2015 EXPORT_SYMBOL(drm_edid_block_valid);
2018 * drm_edid_is_valid - sanity check EDID data
2021 * Sanity-check an entire EDID record (including extensions)
2023 * Return: True if the EDID data is valid, false otherwise.
2025 bool drm_edid_is_valid(struct edid *edid)
2032 for (i = 0; i < edid_block_count(edid); i++) {
2033 void *block = (void *)edid_block_data(edid, i);
2035 if (!drm_edid_block_valid(block, i, true, NULL))
2041 EXPORT_SYMBOL(drm_edid_is_valid);
2044 * drm_edid_valid - sanity check EDID data
2045 * @drm_edid: EDID data
2047 * Sanity check an EDID. Cross check block count against allocated size and
2048 * checksum the blocks.
2050 * Return: True if the EDID data is valid, false otherwise.
2052 bool drm_edid_valid(const struct drm_edid *drm_edid)
2059 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2062 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2063 const void *block = drm_edid_block_data(drm_edid, i);
2065 if (!edid_block_valid(block, i == 0))
2071 EXPORT_SYMBOL(drm_edid_valid);
2073 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2077 int i, valid_blocks = 0;
2080 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2081 * back to regular extension count here. We don't want to start
2082 * modifying the HF-EEODB extension too.
2084 for (i = 0; i < edid_block_count(edid); i++) {
2085 const void *src_block = edid_block_data(edid, i);
2087 if (edid_block_valid(src_block, i == 0)) {
2088 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2090 memmove(dst_block, src_block, EDID_LENGTH);
2095 /* We already trusted the base block to be valid here... */
2096 if (WARN_ON(!valid_blocks)) {
2101 edid->extensions = valid_blocks - 1;
2102 edid->checksum = edid_block_compute_checksum(edid);
2104 *alloc_size = edid_size_by_blocks(valid_blocks);
2106 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2113 #define DDC_SEGMENT_ADDR 0x30
2115 * drm_do_probe_ddc_edid() - get EDID information via I2C
2116 * @data: I2C device adapter
2117 * @buf: EDID data buffer to be filled
2118 * @block: 128 byte EDID block to start fetching from
2119 * @len: EDID data buffer length to fetch
2121 * Try to fetch EDID information by calling I2C driver functions.
2123 * Return: 0 on success or -1 on failure.
2126 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2128 struct i2c_adapter *adapter = data;
2129 unsigned char start = block * EDID_LENGTH;
2130 unsigned char segment = block >> 1;
2131 unsigned char xfers = segment ? 3 : 2;
2132 int ret, retries = 5;
2135 * The core I2C driver will automatically retry the transfer if the
2136 * adapter reports EAGAIN. However, we find that bit-banging transfers
2137 * are susceptible to errors under a heavily loaded machine and
2138 * generate spurious NAKs and timeouts. Retrying the transfer
2139 * of the individual block a few times seems to overcome this.
2142 struct i2c_msg msgs[] = {
2144 .addr = DDC_SEGMENT_ADDR,
2162 * Avoid sending the segment addr to not upset non-compliant
2165 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2167 if (ret == -ENXIO) {
2168 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2172 } while (ret != xfers && --retries);
2174 return ret == xfers ? 0 : -1;
2177 static void connector_bad_edid(struct drm_connector *connector,
2178 const struct edid *edid, int num_blocks)
2184 * 0x7e in the EDID is the number of extension blocks. The EDID
2185 * is 1 (base block) + num_ext_blocks big. That means we can think
2186 * of 0x7e in the EDID of the _index_ of the last block in the
2187 * combined chunk of memory.
2189 last_block = edid->extensions;
2191 /* Calculate real checksum for the last edid extension block data */
2192 if (last_block < num_blocks)
2193 connector->real_edid_checksum =
2194 edid_block_compute_checksum(edid + last_block);
2196 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2199 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2200 connector->base.id, connector->name);
2201 for (i = 0; i < num_blocks; i++)
2202 edid_block_dump(KERN_DEBUG, edid + i, i);
2205 /* Get override or firmware EDID */
2206 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2208 const struct drm_edid *override = NULL;
2210 mutex_lock(&connector->edid_override_mutex);
2212 if (connector->edid_override)
2213 override = drm_edid_dup(connector->edid_override);
2215 mutex_unlock(&connector->edid_override_mutex);
2218 override = drm_edid_load_firmware(connector);
2220 return IS_ERR(override) ? NULL : override;
2223 /* For debugfs edid_override implementation */
2224 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2226 const struct drm_edid *drm_edid;
2228 mutex_lock(&connector->edid_override_mutex);
2230 drm_edid = connector->edid_override;
2232 seq_write(m, drm_edid->edid, drm_edid->size);
2234 mutex_unlock(&connector->edid_override_mutex);
2239 /* For debugfs edid_override implementation */
2240 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2243 const struct drm_edid *drm_edid;
2245 drm_edid = drm_edid_alloc(edid, size);
2246 if (!drm_edid_valid(drm_edid)) {
2247 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2248 connector->base.id, connector->name);
2249 drm_edid_free(drm_edid);
2253 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2254 connector->base.id, connector->name);
2256 mutex_lock(&connector->edid_override_mutex);
2258 drm_edid_free(connector->edid_override);
2259 connector->edid_override = drm_edid;
2261 mutex_unlock(&connector->edid_override_mutex);
2266 /* For debugfs edid_override implementation */
2267 int drm_edid_override_reset(struct drm_connector *connector)
2269 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2270 connector->base.id, connector->name);
2272 mutex_lock(&connector->edid_override_mutex);
2274 drm_edid_free(connector->edid_override);
2275 connector->edid_override = NULL;
2277 mutex_unlock(&connector->edid_override_mutex);
2283 * drm_edid_override_connector_update - add modes from override/firmware EDID
2284 * @connector: connector we're probing
2286 * Add modes from the override/firmware EDID, if available. Only to be used from
2287 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2288 * failed during drm_get_edid() and caused the override/firmware EDID to be
2291 * Return: The number of modes added or 0 if we couldn't find any.
2293 int drm_edid_override_connector_update(struct drm_connector *connector)
2295 const struct drm_edid *override;
2298 override = drm_edid_override_get(connector);
2300 num_modes = drm_edid_connector_update(connector, override);
2302 drm_edid_free(override);
2304 drm_dbg_kms(connector->dev,
2305 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2306 connector->base.id, connector->name, num_modes);
2311 EXPORT_SYMBOL(drm_edid_override_connector_update);
2313 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2315 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2316 read_block_fn read_block,
2319 enum edid_block_status status;
2320 bool is_base_block = block_num == 0;
2323 for (try = 0; try < 4; try++) {
2324 if (read_block(context, block, block_num, EDID_LENGTH))
2325 return EDID_BLOCK_READ_FAIL;
2327 status = edid_block_check(block, is_base_block);
2328 if (status == EDID_BLOCK_HEADER_REPAIR) {
2329 edid_header_fix(block);
2331 /* Retry with fixed header, update status if that worked. */
2332 status = edid_block_check(block, is_base_block);
2333 if (status == EDID_BLOCK_OK)
2334 status = EDID_BLOCK_HEADER_FIXED;
2337 if (edid_block_status_valid(status, edid_block_tag(block)))
2340 /* Fail early for unrepairable base block all zeros. */
2341 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2348 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2349 read_block_fn read_block, void *context,
2352 enum edid_block_status status;
2353 int i, num_blocks, invalid_blocks = 0;
2354 const struct drm_edid *override;
2355 struct edid *edid, *new;
2356 size_t alloc_size = EDID_LENGTH;
2358 override = drm_edid_override_get(connector);
2360 alloc_size = override->size;
2361 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2362 drm_edid_free(override);
2368 edid = kmalloc(alloc_size, GFP_KERNEL);
2372 status = edid_block_read(edid, 0, read_block, context);
2374 edid_block_status_print(status, edid, 0);
2376 if (status == EDID_BLOCK_READ_FAIL)
2379 /* FIXME: Clarify what a corrupt EDID actually means. */
2380 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2381 connector->edid_corrupt = false;
2383 connector->edid_corrupt = true;
2385 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2386 if (status == EDID_BLOCK_ZERO)
2387 connector->null_edid_counter++;
2389 connector_bad_edid(connector, edid, 1);
2393 if (!edid_extension_block_count(edid))
2396 alloc_size = edid_size(edid);
2397 new = krealloc(edid, alloc_size, GFP_KERNEL);
2402 num_blocks = edid_block_count(edid);
2403 for (i = 1; i < num_blocks; i++) {
2404 void *block = (void *)edid_block_data(edid, i);
2406 status = edid_block_read(block, i, read_block, context);
2408 edid_block_status_print(status, block, i);
2410 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2411 if (status == EDID_BLOCK_READ_FAIL)
2414 } else if (i == 1) {
2416 * If the first EDID extension is a CTA extension, and
2417 * the first Data Block is HF-EEODB, override the
2418 * extension block count.
2420 * Note: HF-EEODB could specify a smaller extension
2421 * count too, but we can't risk allocating a smaller
2424 int eeodb = edid_hfeeodb_block_count(edid);
2426 if (eeodb > num_blocks) {
2428 alloc_size = edid_size_by_blocks(num_blocks);
2429 new = krealloc(edid, alloc_size, GFP_KERNEL);
2437 if (invalid_blocks) {
2438 connector_bad_edid(connector, edid, num_blocks);
2440 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2455 * drm_do_get_edid - get EDID data using a custom EDID block read function
2456 * @connector: connector we're probing
2457 * @read_block: EDID block read function
2458 * @context: private data passed to the block read function
2460 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2461 * exposes a different interface to read EDID blocks this function can be used
2462 * to get EDID data using a custom block read function.
2464 * As in the general case the DDC bus is accessible by the kernel at the I2C
2465 * level, drivers must make all reasonable efforts to expose it as an I2C
2466 * adapter and use drm_get_edid() instead of abusing this function.
2468 * The EDID may be overridden using debugfs override_edid or firmware EDID
2469 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2470 * order. Having either of them bypasses actual EDID reads.
2472 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2474 struct edid *drm_do_get_edid(struct drm_connector *connector,
2475 read_block_fn read_block,
2478 return _drm_do_get_edid(connector, read_block, context, NULL);
2480 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2483 * drm_edid_raw - Get a pointer to the raw EDID data.
2484 * @drm_edid: drm_edid container
2486 * Get a pointer to the raw EDID data.
2488 * This is for transition only. Avoid using this like the plague.
2490 * Return: Pointer to raw EDID data.
2492 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2494 if (!drm_edid || !drm_edid->size)
2498 * Do not return pointers where relying on EDID extension count would
2499 * lead to buffer overflow.
2501 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2504 return drm_edid->edid;
2506 EXPORT_SYMBOL(drm_edid_raw);
2508 /* Allocate struct drm_edid container *without* duplicating the edid data */
2509 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2511 struct drm_edid *drm_edid;
2513 if (!edid || !size || size < EDID_LENGTH)
2516 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2518 drm_edid->edid = edid;
2519 drm_edid->size = size;
2526 * drm_edid_alloc - Allocate a new drm_edid container
2527 * @edid: Pointer to raw EDID data
2528 * @size: Size of memory allocated for EDID
2530 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2531 * the actual size that has been allocated for the data. There is no validation
2532 * of the raw EDID data against the size, but at least the EDID base block must
2533 * fit in the buffer.
2535 * The returned pointer must be freed using drm_edid_free().
2537 * Return: drm_edid container, or NULL on errors
2539 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2541 const struct drm_edid *drm_edid;
2543 if (!edid || !size || size < EDID_LENGTH)
2546 edid = kmemdup(edid, size, GFP_KERNEL);
2550 drm_edid = _drm_edid_alloc(edid, size);
2556 EXPORT_SYMBOL(drm_edid_alloc);
2559 * drm_edid_dup - Duplicate a drm_edid container
2560 * @drm_edid: EDID to duplicate
2562 * The returned pointer must be freed using drm_edid_free().
2564 * Returns: drm_edid container copy, or NULL on errors
2566 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2571 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2573 EXPORT_SYMBOL(drm_edid_dup);
2576 * drm_edid_free - Free the drm_edid container
2577 * @drm_edid: EDID to free
2579 void drm_edid_free(const struct drm_edid *drm_edid)
2584 kfree(drm_edid->edid);
2587 EXPORT_SYMBOL(drm_edid_free);
2590 * drm_probe_ddc() - probe DDC presence
2591 * @adapter: I2C adapter to probe
2593 * Return: True on success, false on failure.
2596 drm_probe_ddc(struct i2c_adapter *adapter)
2600 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2602 EXPORT_SYMBOL(drm_probe_ddc);
2605 * drm_get_edid - get EDID data, if available
2606 * @connector: connector we're probing
2607 * @adapter: I2C adapter to use for DDC
2609 * Poke the given I2C channel to grab EDID data if possible. If found,
2610 * attach it to the connector.
2612 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2614 struct edid *drm_get_edid(struct drm_connector *connector,
2615 struct i2c_adapter *adapter)
2619 if (connector->force == DRM_FORCE_OFF)
2622 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2625 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2626 drm_connector_update_edid_property(connector, edid);
2629 EXPORT_SYMBOL(drm_get_edid);
2632 * drm_edid_read_custom - Read EDID data using given EDID block read function
2633 * @connector: Connector to use
2634 * @read_block: EDID block read function
2635 * @context: Private data passed to the block read function
2637 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2638 * exposes a different interface to read EDID blocks this function can be used
2639 * to get EDID data using a custom block read function.
2641 * As in the general case the DDC bus is accessible by the kernel at the I2C
2642 * level, drivers must make all reasonable efforts to expose it as an I2C
2643 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2646 * The EDID may be overridden using debugfs override_edid or firmware EDID
2647 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2648 * order. Having either of them bypasses actual EDID reads.
2650 * The returned pointer must be freed using drm_edid_free().
2652 * Return: Pointer to EDID, or NULL if probe/read failed.
2654 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2655 read_block_fn read_block,
2658 const struct drm_edid *drm_edid;
2662 edid = _drm_do_get_edid(connector, read_block, context, &size);
2666 /* Sanity check for now */
2667 drm_WARN_ON(connector->dev, !size);
2669 drm_edid = _drm_edid_alloc(edid, size);
2675 EXPORT_SYMBOL(drm_edid_read_custom);
2678 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2679 * @connector: Connector to use
2680 * @adapter: I2C adapter to use for DDC
2682 * Read EDID using the given I2C adapter.
2684 * The EDID may be overridden using debugfs override_edid or firmware EDID
2685 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2686 * order. Having either of them bypasses actual EDID reads.
2688 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2689 * using drm_edid_read() instead of this function.
2691 * The returned pointer must be freed using drm_edid_free().
2693 * Return: Pointer to EDID, or NULL if probe/read failed.
2695 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2696 struct i2c_adapter *adapter)
2698 const struct drm_edid *drm_edid;
2700 if (connector->force == DRM_FORCE_OFF)
2703 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2706 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2708 /* Note: Do *not* call connector updates here. */
2712 EXPORT_SYMBOL(drm_edid_read_ddc);
2715 * drm_edid_read - Read EDID data using connector's I2C adapter
2716 * @connector: Connector to use
2718 * Read EDID using the connector's I2C adapter.
2720 * The EDID may be overridden using debugfs override_edid or firmware EDID
2721 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2722 * order. Having either of them bypasses actual EDID reads.
2724 * The returned pointer must be freed using drm_edid_free().
2726 * Return: Pointer to EDID, or NULL if probe/read failed.
2728 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2730 if (drm_WARN_ON(connector->dev, !connector->ddc))
2733 return drm_edid_read_ddc(connector, connector->ddc);
2735 EXPORT_SYMBOL(drm_edid_read);
2737 static u32 edid_extract_panel_id(const struct edid *edid)
2740 * We represent the ID as a 32-bit number so it can easily be compared
2743 * NOTE that we deal with endianness differently for the top half
2744 * of this ID than for the bottom half. The bottom half (the product
2745 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2746 * that's how everyone seems to interpret it. The top half (the mfg_id)
2747 * gets stored as big endian because that makes
2748 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2749 * to write (it's easier to extract the ASCII). It doesn't really
2750 * matter, though, as long as the number here is unique.
2752 return (u32)edid->mfg_id[0] << 24 |
2753 (u32)edid->mfg_id[1] << 16 |
2754 (u32)EDID_PRODUCT_ID(edid);
2758 * drm_edid_get_panel_id - Get a panel's ID through DDC
2759 * @adapter: I2C adapter to use for DDC
2761 * This function reads the first block of the EDID of a panel and (assuming
2762 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2763 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2764 * supposed to be different for each different modem of panel.
2766 * This function is intended to be used during early probing on devices where
2767 * more than one panel might be present. Because of its intended use it must
2768 * assume that the EDID of the panel is correct, at least as far as the ID
2769 * is concerned (in other words, we don't process any overrides here).
2771 * NOTE: it's expected that this function and drm_do_get_edid() will both
2772 * be read the EDID, but there is no caching between them. Since we're only
2773 * reading the first block, hopefully this extra overhead won't be too big.
2775 * Return: A 32-bit ID that should be different for each make/model of panel.
2776 * See the functions drm_edid_encode_panel_id() and
2777 * drm_edid_decode_panel_id() for some details on the structure of this
2781 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2783 enum edid_block_status status;
2788 * There are no manufacturer IDs of 0, so if there is a problem reading
2789 * the EDID then we'll just return 0.
2792 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2796 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2798 edid_block_status_print(status, base_block, 0);
2800 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2801 panel_id = edid_extract_panel_id(base_block);
2807 EXPORT_SYMBOL(drm_edid_get_panel_id);
2810 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2811 * @connector: connector we're probing
2812 * @adapter: I2C adapter to use for DDC
2814 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2815 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2816 * switch DDC to the GPU which is retrieving EDID.
2818 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2820 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2821 struct i2c_adapter *adapter)
2823 struct drm_device *dev = connector->dev;
2824 struct pci_dev *pdev = to_pci_dev(dev->dev);
2827 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2830 vga_switcheroo_lock_ddc(pdev);
2831 edid = drm_get_edid(connector, adapter);
2832 vga_switcheroo_unlock_ddc(pdev);
2836 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2839 * drm_edid_duplicate - duplicate an EDID and the extensions
2840 * @edid: EDID to duplicate
2842 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2844 struct edid *drm_edid_duplicate(const struct edid *edid)
2846 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2848 EXPORT_SYMBOL(drm_edid_duplicate);
2850 /*** EDID parsing ***/
2853 * edid_get_quirks - return quirk flags for a given EDID
2854 * @drm_edid: EDID to process
2856 * This tells subsequent routines what fixes they need to apply.
2858 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2860 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2861 const struct edid_quirk *quirk;
2864 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2865 quirk = &edid_quirk_list[i];
2866 if (quirk->panel_id == panel_id)
2867 return quirk->quirks;
2873 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2874 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2877 * Walk the mode list for connector, clearing the preferred status on existing
2878 * modes and setting it anew for the right mode ala quirks.
2880 static void edid_fixup_preferred(struct drm_connector *connector,
2883 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2884 int target_refresh = 0;
2885 int cur_vrefresh, preferred_vrefresh;
2887 if (list_empty(&connector->probed_modes))
2890 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2891 target_refresh = 60;
2892 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2893 target_refresh = 75;
2895 preferred_mode = list_first_entry(&connector->probed_modes,
2896 struct drm_display_mode, head);
2898 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2899 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2901 if (cur_mode == preferred_mode)
2904 /* Largest mode is preferred */
2905 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2906 preferred_mode = cur_mode;
2908 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2909 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2910 /* At a given size, try to get closest to target refresh */
2911 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2912 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2913 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2914 preferred_mode = cur_mode;
2918 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2922 mode_is_rb(const struct drm_display_mode *mode)
2924 return (mode->htotal - mode->hdisplay == 160) &&
2925 (mode->hsync_end - mode->hdisplay == 80) &&
2926 (mode->hsync_end - mode->hsync_start == 32) &&
2927 (mode->vsync_start - mode->vdisplay == 3);
2931 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2932 * @dev: Device to duplicate against
2933 * @hsize: Mode width
2934 * @vsize: Mode height
2935 * @fresh: Mode refresh rate
2936 * @rb: Mode reduced-blanking-ness
2938 * Walk the DMT mode list looking for a match for the given parameters.
2940 * Return: A newly allocated copy of the mode, or NULL if not found.
2942 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2943 int hsize, int vsize, int fresh,
2948 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2949 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2951 if (hsize != ptr->hdisplay)
2953 if (vsize != ptr->vdisplay)
2955 if (fresh != drm_mode_vrefresh(ptr))
2957 if (rb != mode_is_rb(ptr))
2960 return drm_mode_duplicate(dev, ptr);
2965 EXPORT_SYMBOL(drm_mode_find_dmt);
2967 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2969 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2970 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2971 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2973 return descriptor->pixel_clock == 0 &&
2974 descriptor->data.other_data.pad1 == 0 &&
2975 descriptor->data.other_data.type == type;
2978 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2980 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2982 return descriptor->pixel_clock != 0;
2985 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2988 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2992 const u8 *det_base = ext + d;
2994 if (d < 4 || d > 127)
2998 for (i = 0; i < n; i++)
2999 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3003 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3005 unsigned int i, n = min((int)ext[0x02], 6);
3006 const u8 *det_base = ext + 5;
3009 return; /* unknown version */
3011 for (i = 0; i < n; i++)
3012 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3015 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3016 detailed_cb *cb, void *closure)
3018 struct drm_edid_iter edid_iter;
3025 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3026 cb(&drm_edid->edid->detailed_timings[i], closure);
3028 drm_edid_iter_begin(drm_edid, &edid_iter);
3029 drm_edid_iter_for_each(ext, &edid_iter) {
3032 cea_for_each_detailed_block(ext, cb, closure);
3035 vtb_for_each_detailed_block(ext, cb, closure);
3041 drm_edid_iter_end(&edid_iter);
3045 is_rb(const struct detailed_timing *descriptor, void *data)
3049 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3052 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3053 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3055 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3056 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3060 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3062 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3064 if (drm_edid->edid->revision >= 4) {
3067 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3071 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
3075 find_gtf2(const struct detailed_timing *descriptor, void *data)
3077 const struct detailed_timing **res = data;
3079 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3082 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3084 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3088 /* Secondary GTF curve kicks in above some break frequency */
3090 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3092 const struct detailed_timing *descriptor = NULL;
3094 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3096 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3098 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3102 drm_gtf2_2c(const struct drm_edid *drm_edid)
3104 const struct detailed_timing *descriptor = NULL;
3106 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3108 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3110 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3114 drm_gtf2_m(const struct drm_edid *drm_edid)
3116 const struct detailed_timing *descriptor = NULL;
3118 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3120 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3122 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3126 drm_gtf2_k(const struct drm_edid *drm_edid)
3128 const struct detailed_timing *descriptor = NULL;
3130 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3132 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3134 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3138 drm_gtf2_2j(const struct drm_edid *drm_edid)
3140 const struct detailed_timing *descriptor = NULL;
3142 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3144 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3146 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3150 get_timing_level(const struct detailed_timing *descriptor, void *data)
3154 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3157 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3159 switch (descriptor->data.other_data.data.range.flags) {
3160 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3163 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3166 case DRM_EDID_CVT_SUPPORT_FLAG:
3174 /* Get standard timing level (CVT/GTF/DMT). */
3175 static int standard_timing_level(const struct drm_edid *drm_edid)
3177 const struct edid *edid = drm_edid->edid;
3179 if (edid->revision >= 4) {
3181 * If the range descriptor doesn't
3182 * indicate otherwise default to CVT
3184 int ret = LEVEL_CVT;
3186 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3189 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3191 } else if (edid->revision >= 2) {
3199 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3200 * monitors fill with ascii space (0x20) instead.
3203 bad_std_timing(u8 a, u8 b)
3205 return (a == 0x00 && b == 0x00) ||
3206 (a == 0x01 && b == 0x01) ||
3207 (a == 0x20 && b == 0x20);
3210 static int drm_mode_hsync(const struct drm_display_mode *mode)
3212 if (mode->htotal <= 0)
3215 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3218 static struct drm_display_mode *
3219 drm_gtf2_mode(struct drm_device *dev,
3220 const struct drm_edid *drm_edid,
3221 int hsize, int vsize, int vrefresh_rate)
3223 struct drm_display_mode *mode;
3226 * This is potentially wrong if there's ever a monitor with
3227 * more than one ranges section, each claiming a different
3228 * secondary GTF curve. Please don't do that.
3230 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3234 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3235 drm_mode_destroy(dev, mode);
3236 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3237 vrefresh_rate, 0, 0,
3238 drm_gtf2_m(drm_edid),
3239 drm_gtf2_2c(drm_edid),
3240 drm_gtf2_k(drm_edid),
3241 drm_gtf2_2j(drm_edid));
3248 * Take the standard timing params (in this case width, aspect, and refresh)
3249 * and convert them into a real mode using CVT/GTF/DMT.
3251 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3252 const struct drm_edid *drm_edid,
3253 const struct std_timing *t)
3255 struct drm_device *dev = connector->dev;
3256 struct drm_display_mode *m, *mode = NULL;
3259 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3260 >> EDID_TIMING_ASPECT_SHIFT;
3261 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3262 >> EDID_TIMING_VFREQ_SHIFT;
3263 int timing_level = standard_timing_level(drm_edid);
3265 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3268 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3269 hsize = t->hsize * 8 + 248;
3270 /* vrefresh_rate = vfreq + 60 */
3271 vrefresh_rate = vfreq + 60;
3272 /* the vdisplay is calculated based on the aspect ratio */
3273 if (aspect_ratio == 0) {
3274 if (drm_edid->edid->revision < 3)
3277 vsize = (hsize * 10) / 16;
3278 } else if (aspect_ratio == 1)
3279 vsize = (hsize * 3) / 4;
3280 else if (aspect_ratio == 2)
3281 vsize = (hsize * 4) / 5;
3283 vsize = (hsize * 9) / 16;
3285 /* HDTV hack, part 1 */
3286 if (vrefresh_rate == 60 &&
3287 ((hsize == 1360 && vsize == 765) ||
3288 (hsize == 1368 && vsize == 769))) {
3294 * If this connector already has a mode for this size and refresh
3295 * rate (because it came from detailed or CVT info), use that
3296 * instead. This way we don't have to guess at interlace or
3299 list_for_each_entry(m, &connector->probed_modes, head)
3300 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3301 drm_mode_vrefresh(m) == vrefresh_rate)
3304 /* HDTV hack, part 2 */
3305 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3306 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3310 mode->hdisplay = 1366;
3311 mode->hsync_start = mode->hsync_start - 1;
3312 mode->hsync_end = mode->hsync_end - 1;
3316 /* check whether it can be found in default mode table */
3317 if (drm_monitor_supports_rb(drm_edid)) {
3318 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3323 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3327 /* okay, generate it */
3328 switch (timing_level) {
3332 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3335 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3338 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3346 * EDID is delightfully ambiguous about how interlaced modes are to be
3347 * encoded. Our internal representation is of frame height, but some
3348 * HDTV detailed timings are encoded as field height.
3350 * The format list here is from CEA, in frame size. Technically we
3351 * should be checking refresh rate too. Whatever.
3354 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3355 const struct detailed_pixel_timing *pt)
3358 static const struct {
3360 } cea_interlaced[] = {
3370 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3373 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3374 if ((mode->hdisplay == cea_interlaced[i].w) &&
3375 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3376 mode->vdisplay *= 2;
3377 mode->vsync_start *= 2;
3378 mode->vsync_end *= 2;
3384 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3388 * Create a new mode from an EDID detailed timing section. An EDID detailed
3389 * timing block contains enough info for us to create and return a new struct
3392 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3393 const struct drm_edid *drm_edid,
3394 const struct detailed_timing *timing,
3397 struct drm_device *dev = connector->dev;
3398 struct drm_display_mode *mode;
3399 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3400 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3401 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3402 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3403 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3404 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3405 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3406 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3407 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3409 /* ignore tiny modes */
3410 if (hactive < 64 || vactive < 64)
3413 if (pt->misc & DRM_EDID_PT_STEREO) {
3414 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3415 connector->base.id, connector->name);
3418 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3419 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3420 connector->base.id, connector->name);
3423 /* it is incorrect if hsync/vsync width is zero */
3424 if (!hsync_pulse_width || !vsync_pulse_width) {
3425 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3426 connector->base.id, connector->name);
3430 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3431 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3438 mode = drm_mode_create(dev);
3442 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3443 mode->clock = 1088 * 10;
3445 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3447 mode->hdisplay = hactive;
3448 mode->hsync_start = mode->hdisplay + hsync_offset;
3449 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3450 mode->htotal = mode->hdisplay + hblank;
3452 mode->vdisplay = vactive;
3453 mode->vsync_start = mode->vdisplay + vsync_offset;
3454 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3455 mode->vtotal = mode->vdisplay + vblank;
3457 /* Some EDIDs have bogus h/vtotal values */
3458 if (mode->hsync_end > mode->htotal)
3459 mode->htotal = mode->hsync_end + 1;
3460 if (mode->vsync_end > mode->vtotal)
3461 mode->vtotal = mode->vsync_end + 1;
3463 drm_mode_do_interlace_quirk(mode, pt);
3465 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3466 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3468 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3469 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3470 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3471 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3475 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3476 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3478 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3479 mode->width_mm *= 10;
3480 mode->height_mm *= 10;
3483 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3484 mode->width_mm = drm_edid->edid->width_cm * 10;
3485 mode->height_mm = drm_edid->edid->height_cm * 10;
3488 mode->type = DRM_MODE_TYPE_DRIVER;
3489 drm_mode_set_name(mode);
3495 mode_in_hsync_range(const struct drm_display_mode *mode,
3496 const struct edid *edid, const u8 *t)
3498 int hsync, hmin, hmax;
3501 if (edid->revision >= 4)
3502 hmin += ((t[4] & 0x04) ? 255 : 0);
3504 if (edid->revision >= 4)
3505 hmax += ((t[4] & 0x08) ? 255 : 0);
3506 hsync = drm_mode_hsync(mode);
3508 return (hsync <= hmax && hsync >= hmin);
3512 mode_in_vsync_range(const struct drm_display_mode *mode,
3513 const struct edid *edid, const u8 *t)
3515 int vsync, vmin, vmax;
3518 if (edid->revision >= 4)
3519 vmin += ((t[4] & 0x01) ? 255 : 0);
3521 if (edid->revision >= 4)
3522 vmax += ((t[4] & 0x02) ? 255 : 0);
3523 vsync = drm_mode_vrefresh(mode);
3525 return (vsync <= vmax && vsync >= vmin);
3529 range_pixel_clock(const struct edid *edid, const u8 *t)
3532 if (t[9] == 0 || t[9] == 255)
3535 /* 1.4 with CVT support gives us real precision, yay */
3536 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3537 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3539 /* 1.3 is pathetic, so fuzz up a bit */
3540 return t[9] * 10000 + 5001;
3543 static bool mode_in_range(const struct drm_display_mode *mode,
3544 const struct drm_edid *drm_edid,
3545 const struct detailed_timing *timing)
3547 const struct edid *edid = drm_edid->edid;
3549 const u8 *t = (const u8 *)timing;
3551 if (!mode_in_hsync_range(mode, edid, t))
3554 if (!mode_in_vsync_range(mode, edid, t))
3557 if ((max_clock = range_pixel_clock(edid, t)))
3558 if (mode->clock > max_clock)
3561 /* 1.4 max horizontal check */
3562 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3563 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3566 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3572 static bool valid_inferred_mode(const struct drm_connector *connector,
3573 const struct drm_display_mode *mode)
3575 const struct drm_display_mode *m;
3578 list_for_each_entry(m, &connector->probed_modes, head) {
3579 if (mode->hdisplay == m->hdisplay &&
3580 mode->vdisplay == m->vdisplay &&
3581 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3582 return false; /* duplicated */
3583 if (mode->hdisplay <= m->hdisplay &&
3584 mode->vdisplay <= m->vdisplay)
3590 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3591 const struct drm_edid *drm_edid,
3592 const struct detailed_timing *timing)
3595 struct drm_display_mode *newmode;
3596 struct drm_device *dev = connector->dev;
3598 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3599 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3600 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3601 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3603 drm_mode_probed_add(connector, newmode);
3612 /* fix up 1366x768 mode from 1368x768;
3613 * GFT/CVT can't express 1366 width which isn't dividable by 8
3615 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3617 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3618 mode->hdisplay = 1366;
3619 mode->hsync_start--;
3621 drm_mode_set_name(mode);
3625 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3626 const struct drm_edid *drm_edid,
3627 const struct detailed_timing *timing)
3630 struct drm_display_mode *newmode;
3631 struct drm_device *dev = connector->dev;
3633 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3634 const struct minimode *m = &extra_modes[i];
3636 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3640 drm_mode_fixup_1366x768(newmode);
3641 if (!mode_in_range(newmode, drm_edid, timing) ||
3642 !valid_inferred_mode(connector, newmode)) {
3643 drm_mode_destroy(dev, newmode);
3647 drm_mode_probed_add(connector, newmode);
3654 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3655 const struct drm_edid *drm_edid,
3656 const struct detailed_timing *timing)
3659 struct drm_display_mode *newmode;
3660 struct drm_device *dev = connector->dev;
3662 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3663 const struct minimode *m = &extra_modes[i];
3665 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3669 drm_mode_fixup_1366x768(newmode);
3670 if (!mode_in_range(newmode, drm_edid, timing) ||
3671 !valid_inferred_mode(connector, newmode)) {
3672 drm_mode_destroy(dev, newmode);
3676 drm_mode_probed_add(connector, newmode);
3683 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3684 const struct drm_edid *drm_edid,
3685 const struct detailed_timing *timing)
3688 struct drm_display_mode *newmode;
3689 struct drm_device *dev = connector->dev;
3690 bool rb = drm_monitor_supports_rb(drm_edid);
3692 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3693 const struct minimode *m = &extra_modes[i];
3695 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3699 drm_mode_fixup_1366x768(newmode);
3700 if (!mode_in_range(newmode, drm_edid, timing) ||
3701 !valid_inferred_mode(connector, newmode)) {
3702 drm_mode_destroy(dev, newmode);
3706 drm_mode_probed_add(connector, newmode);
3714 do_inferred_modes(const struct detailed_timing *timing, void *c)
3716 struct detailed_mode_closure *closure = c;
3717 const struct detailed_non_pixel *data = &timing->data.other_data;
3718 const struct detailed_data_monitor_range *range = &data->data.range;
3720 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3723 closure->modes += drm_dmt_modes_for_range(closure->connector,
3727 if (closure->drm_edid->edid->revision < 2)
3728 return; /* GTF not defined yet */
3730 switch (range->flags) {
3731 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3732 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3736 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3737 closure->modes += drm_gtf_modes_for_range(closure->connector,
3741 case DRM_EDID_CVT_SUPPORT_FLAG:
3742 if (closure->drm_edid->edid->revision < 4)
3745 closure->modes += drm_cvt_modes_for_range(closure->connector,
3749 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3755 static int add_inferred_modes(struct drm_connector *connector,
3756 const struct drm_edid *drm_edid)
3758 struct detailed_mode_closure closure = {
3759 .connector = connector,
3760 .drm_edid = drm_edid,
3763 if (drm_edid->edid->revision >= 1)
3764 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3766 return closure.modes;
3770 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3772 int i, j, m, modes = 0;
3773 struct drm_display_mode *mode;
3774 const u8 *est = ((const u8 *)timing) + 6;
3776 for (i = 0; i < 6; i++) {
3777 for (j = 7; j >= 0; j--) {
3778 m = (i * 8) + (7 - j);
3779 if (m >= ARRAY_SIZE(est3_modes))
3781 if (est[i] & (1 << j)) {
3782 mode = drm_mode_find_dmt(connector->dev,
3788 drm_mode_probed_add(connector, mode);
3799 do_established_modes(const struct detailed_timing *timing, void *c)
3801 struct detailed_mode_closure *closure = c;
3803 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3806 closure->modes += drm_est3_modes(closure->connector, timing);
3810 * Get established modes from EDID and add them. Each EDID block contains a
3811 * bitmap of the supported "established modes" list (defined above). Tease them
3812 * out and add them to the global modes list.
3814 static int add_established_modes(struct drm_connector *connector,
3815 const struct drm_edid *drm_edid)
3817 struct drm_device *dev = connector->dev;
3818 const struct edid *edid = drm_edid->edid;
3819 unsigned long est_bits = edid->established_timings.t1 |
3820 (edid->established_timings.t2 << 8) |
3821 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3823 struct detailed_mode_closure closure = {
3824 .connector = connector,
3825 .drm_edid = drm_edid,
3828 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3829 if (est_bits & (1<<i)) {
3830 struct drm_display_mode *newmode;
3832 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3834 drm_mode_probed_add(connector, newmode);
3840 if (edid->revision >= 1)
3841 drm_for_each_detailed_block(drm_edid, do_established_modes,
3844 return modes + closure.modes;
3848 do_standard_modes(const struct detailed_timing *timing, void *c)
3850 struct detailed_mode_closure *closure = c;
3851 const struct detailed_non_pixel *data = &timing->data.other_data;
3852 struct drm_connector *connector = closure->connector;
3855 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3858 for (i = 0; i < 6; i++) {
3859 const struct std_timing *std = &data->data.timings[i];
3860 struct drm_display_mode *newmode;
3862 newmode = drm_mode_std(connector, closure->drm_edid, std);
3864 drm_mode_probed_add(connector, newmode);
3871 * Get standard modes from EDID and add them. Standard modes can be calculated
3872 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3873 * add them to the list.
3875 static int add_standard_modes(struct drm_connector *connector,
3876 const struct drm_edid *drm_edid)
3879 struct detailed_mode_closure closure = {
3880 .connector = connector,
3881 .drm_edid = drm_edid,
3884 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3885 struct drm_display_mode *newmode;
3887 newmode = drm_mode_std(connector, drm_edid,
3888 &drm_edid->edid->standard_timings[i]);
3890 drm_mode_probed_add(connector, newmode);
3895 if (drm_edid->edid->revision >= 1)
3896 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3899 /* XXX should also look for standard codes in VTB blocks */
3901 return modes + closure.modes;
3904 static int drm_cvt_modes(struct drm_connector *connector,
3905 const struct detailed_timing *timing)
3907 int i, j, modes = 0;
3908 struct drm_display_mode *newmode;
3909 struct drm_device *dev = connector->dev;
3910 const struct cvt_timing *cvt;
3911 const int rates[] = { 60, 85, 75, 60, 50 };
3912 const u8 empty[3] = { 0, 0, 0 };
3914 for (i = 0; i < 4; i++) {
3917 cvt = &(timing->data.other_data.data.cvt[i]);
3919 if (!memcmp(cvt->code, empty, 3))
3922 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3923 switch (cvt->code[1] & 0x0c) {
3924 /* default - because compiler doesn't see that we've enumerated all cases */
3927 width = height * 4 / 3;
3930 width = height * 16 / 9;
3933 width = height * 16 / 10;
3936 width = height * 15 / 9;
3940 for (j = 1; j < 5; j++) {
3941 if (cvt->code[2] & (1 << j)) {
3942 newmode = drm_cvt_mode(dev, width, height,
3946 drm_mode_probed_add(connector, newmode);
3957 do_cvt_mode(const struct detailed_timing *timing, void *c)
3959 struct detailed_mode_closure *closure = c;
3961 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3964 closure->modes += drm_cvt_modes(closure->connector, timing);
3968 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
3970 struct detailed_mode_closure closure = {
3971 .connector = connector,
3972 .drm_edid = drm_edid,
3975 if (drm_edid->edid->revision >= 3)
3976 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
3978 /* XXX should also look for CVT codes in VTB blocks */
3980 return closure.modes;
3983 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
3984 struct drm_display_mode *mode);
3987 do_detailed_mode(const struct detailed_timing *timing, void *c)
3989 struct detailed_mode_closure *closure = c;
3990 struct drm_display_mode *newmode;
3992 if (!is_detailed_timing_descriptor(timing))
3995 newmode = drm_mode_detailed(closure->connector,
3996 closure->drm_edid, timing,
4001 if (closure->preferred)
4002 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4005 * Detailed modes are limited to 10kHz pixel clock resolution,
4006 * so fix up anything that looks like CEA/HDMI mode, but the clock
4007 * is just slightly off.
4009 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4011 drm_mode_probed_add(closure->connector, newmode);
4013 closure->preferred = false;
4017 * add_detailed_modes - Add modes from detailed timings
4018 * @connector: attached connector
4019 * @drm_edid: EDID block to scan
4020 * @quirks: quirks to apply
4022 static int add_detailed_modes(struct drm_connector *connector,
4023 const struct drm_edid *drm_edid, u32 quirks)
4025 struct detailed_mode_closure closure = {
4026 .connector = connector,
4027 .drm_edid = drm_edid,
4031 if (drm_edid->edid->revision >= 4)
4032 closure.preferred = true; /* first detailed timing is always preferred */
4035 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4037 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4039 return closure.modes;
4042 /* CTA-861-H Table 60 - CTA Tag Codes */
4043 #define CTA_DB_AUDIO 1
4044 #define CTA_DB_VIDEO 2
4045 #define CTA_DB_VENDOR 3
4046 #define CTA_DB_SPEAKER 4
4047 #define CTA_DB_EXTENDED_TAG 7
4049 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4050 #define CTA_EXT_DB_VIDEO_CAP 0
4051 #define CTA_EXT_DB_VENDOR 1
4052 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4053 #define CTA_EXT_DB_420_VIDEO_DATA 14
4054 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4055 #define CTA_EXT_DB_HF_EEODB 0x78
4056 #define CTA_EXT_DB_HF_SCDB 0x79
4058 #define EDID_BASIC_AUDIO (1 << 6)
4059 #define EDID_CEA_YCRCB444 (1 << 5)
4060 #define EDID_CEA_YCRCB422 (1 << 4)
4061 #define EDID_CEA_VCDB_QS (1 << 6)
4064 * Search EDID for CEA extension block.
4066 * FIXME: Prefer not returning pointers to raw EDID data.
4068 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4069 int ext_id, int *ext_index)
4071 const u8 *edid_ext = NULL;
4074 /* No EDID or EDID extensions */
4075 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4078 /* Find CEA extension */
4079 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4080 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4081 if (edid_block_tag(edid_ext) == ext_id)
4085 if (i >= drm_edid_extension_block_count(drm_edid))
4093 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4094 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4096 const struct displayid_block *block;
4097 struct displayid_iter iter;
4101 /* Look for a top level CEA extension block */
4102 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4105 /* CEA blocks can also be found embedded in a DisplayID block */
4106 displayid_iter_edid_begin(drm_edid, &iter);
4107 displayid_iter_for_each(block, &iter) {
4108 if (block->tag == DATA_BLOCK_CTA) {
4113 displayid_iter_end(&iter);
4118 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4120 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4121 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4123 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4124 return &edid_cea_modes_1[vic - 1];
4125 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4126 return &edid_cea_modes_193[vic - 193];
4130 static u8 cea_num_vics(void)
4132 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4135 static u8 cea_next_vic(u8 vic)
4137 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4143 * Calculate the alternate clock for the CEA mode
4144 * (60Hz vs. 59.94Hz etc.)
4147 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4149 unsigned int clock = cea_mode->clock;
4151 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4155 * edid_cea_modes contains the 59.94Hz
4156 * variant for 240 and 480 line modes,
4157 * and the 60Hz variant otherwise.
4159 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4160 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4162 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4168 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4171 * For certain VICs the spec allows the vertical
4172 * front porch to vary by one or two lines.
4174 * cea_modes[] stores the variant with the shortest
4175 * vertical front porch. We can adjust the mode to
4176 * get the other variants by simply increasing the
4177 * vertical front porch length.
4179 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4180 cea_mode_for_vic(9)->vtotal != 262 ||
4181 cea_mode_for_vic(12)->vtotal != 262 ||
4182 cea_mode_for_vic(13)->vtotal != 262 ||
4183 cea_mode_for_vic(23)->vtotal != 312 ||
4184 cea_mode_for_vic(24)->vtotal != 312 ||
4185 cea_mode_for_vic(27)->vtotal != 312 ||
4186 cea_mode_for_vic(28)->vtotal != 312);
4188 if (((vic == 8 || vic == 9 ||
4189 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4190 ((vic == 23 || vic == 24 ||
4191 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4192 mode->vsync_start++;
4202 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4203 unsigned int clock_tolerance)
4205 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4208 if (!to_match->clock)
4211 if (to_match->picture_aspect_ratio)
4212 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4214 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4215 struct drm_display_mode cea_mode;
4216 unsigned int clock1, clock2;
4218 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4220 /* Check both 60Hz and 59.94Hz */
4221 clock1 = cea_mode.clock;
4222 clock2 = cea_mode_alternate_clock(&cea_mode);
4224 if (abs(to_match->clock - clock1) > clock_tolerance &&
4225 abs(to_match->clock - clock2) > clock_tolerance)
4229 if (drm_mode_match(to_match, &cea_mode, match_flags))
4231 } while (cea_mode_alternate_timings(vic, &cea_mode));
4238 * drm_match_cea_mode - look for a CEA mode matching given mode
4239 * @to_match: display mode
4241 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4244 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4246 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4249 if (!to_match->clock)
4252 if (to_match->picture_aspect_ratio)
4253 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4255 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4256 struct drm_display_mode cea_mode;
4257 unsigned int clock1, clock2;
4259 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4261 /* Check both 60Hz and 59.94Hz */
4262 clock1 = cea_mode.clock;
4263 clock2 = cea_mode_alternate_clock(&cea_mode);
4265 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4266 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4270 if (drm_mode_match(to_match, &cea_mode, match_flags))
4272 } while (cea_mode_alternate_timings(vic, &cea_mode));
4277 EXPORT_SYMBOL(drm_match_cea_mode);
4279 static bool drm_valid_cea_vic(u8 vic)
4281 return cea_mode_for_vic(vic) != NULL;
4284 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4286 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4289 return mode->picture_aspect_ratio;
4291 return HDMI_PICTURE_ASPECT_NONE;
4294 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4296 return edid_4k_modes[video_code].picture_aspect_ratio;
4300 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4304 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4306 return cea_mode_alternate_clock(hdmi_mode);
4309 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4310 unsigned int clock_tolerance)
4312 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4315 if (!to_match->clock)
4318 if (to_match->picture_aspect_ratio)
4319 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4321 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4322 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4323 unsigned int clock1, clock2;
4325 /* Make sure to also match alternate clocks */
4326 clock1 = hdmi_mode->clock;
4327 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4329 if (abs(to_match->clock - clock1) > clock_tolerance &&
4330 abs(to_match->clock - clock2) > clock_tolerance)
4333 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4341 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4342 * @to_match: display mode
4344 * An HDMI mode is one defined in the HDMI vendor specific block.
4346 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4348 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4350 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4353 if (!to_match->clock)
4356 if (to_match->picture_aspect_ratio)
4357 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4359 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4360 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4361 unsigned int clock1, clock2;
4363 /* Make sure to also match alternate clocks */
4364 clock1 = hdmi_mode->clock;
4365 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4367 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4368 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4369 drm_mode_match(to_match, hdmi_mode, match_flags))
4375 static bool drm_valid_hdmi_vic(u8 vic)
4377 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4380 static int add_alternate_cea_modes(struct drm_connector *connector,
4381 const struct drm_edid *drm_edid)
4383 struct drm_device *dev = connector->dev;
4384 struct drm_display_mode *mode, *tmp;
4388 /* Don't add CTA modes if the CTA extension block is missing */
4389 if (!drm_edid_has_cta_extension(drm_edid))
4393 * Go through all probed modes and create a new mode
4394 * with the alternate clock for certain CEA modes.
4396 list_for_each_entry(mode, &connector->probed_modes, head) {
4397 const struct drm_display_mode *cea_mode = NULL;
4398 struct drm_display_mode *newmode;
4399 u8 vic = drm_match_cea_mode(mode);
4400 unsigned int clock1, clock2;
4402 if (drm_valid_cea_vic(vic)) {
4403 cea_mode = cea_mode_for_vic(vic);
4404 clock2 = cea_mode_alternate_clock(cea_mode);
4406 vic = drm_match_hdmi_mode(mode);
4407 if (drm_valid_hdmi_vic(vic)) {
4408 cea_mode = &edid_4k_modes[vic];
4409 clock2 = hdmi_mode_alternate_clock(cea_mode);
4416 clock1 = cea_mode->clock;
4418 if (clock1 == clock2)
4421 if (mode->clock != clock1 && mode->clock != clock2)
4424 newmode = drm_mode_duplicate(dev, cea_mode);
4428 /* Carry over the stereo flags */
4429 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4432 * The current mode could be either variant. Make
4433 * sure to pick the "other" clock for the new mode.
4435 if (mode->clock != clock1)
4436 newmode->clock = clock1;
4438 newmode->clock = clock2;
4440 list_add_tail(&newmode->head, &list);
4443 list_for_each_entry_safe(mode, tmp, &list, head) {
4444 list_del(&mode->head);
4445 drm_mode_probed_add(connector, mode);
4452 static u8 svd_to_vic(u8 svd)
4454 /* 0-6 bit vic, 7th bit native mode indicator */
4455 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4461 static struct drm_display_mode *
4462 drm_display_mode_from_vic_index(struct drm_connector *connector,
4463 const u8 *video_db, u8 video_len,
4466 struct drm_device *dev = connector->dev;
4467 struct drm_display_mode *newmode;
4470 if (video_db == NULL || video_index >= video_len)
4473 /* CEA modes are numbered 1..127 */
4474 vic = svd_to_vic(video_db[video_index]);
4475 if (!drm_valid_cea_vic(vic))
4478 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4486 * do_y420vdb_modes - Parse YCBCR 420 only modes
4487 * @connector: connector corresponding to the HDMI sink
4488 * @svds: start of the data block of CEA YCBCR 420 VDB
4489 * @len: length of the CEA YCBCR 420 VDB
4491 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4492 * which contains modes which can be supported in YCBCR 420
4493 * output format only.
4495 static int do_y420vdb_modes(struct drm_connector *connector,
4496 const u8 *svds, u8 svds_len)
4499 struct drm_device *dev = connector->dev;
4500 struct drm_display_info *info = &connector->display_info;
4501 struct drm_hdmi_info *hdmi = &info->hdmi;
4503 for (i = 0; i < svds_len; i++) {
4504 u8 vic = svd_to_vic(svds[i]);
4505 struct drm_display_mode *newmode;
4507 if (!drm_valid_cea_vic(vic))
4510 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4513 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4514 drm_mode_probed_add(connector, newmode);
4519 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4524 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4525 * @connector: connector corresponding to the HDMI sink
4526 * @vic: CEA vic for the video mode to be added in the map
4528 * Makes an entry for a videomode in the YCBCR 420 bitmap
4531 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4533 u8 vic = svd_to_vic(svd);
4534 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4536 if (!drm_valid_cea_vic(vic))
4539 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4543 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4545 * @video_code: CEA VIC of the mode
4547 * Creates a new mode matching the specified CEA VIC.
4549 * Returns: A new drm_display_mode on success or NULL on failure
4551 struct drm_display_mode *
4552 drm_display_mode_from_cea_vic(struct drm_device *dev,
4555 const struct drm_display_mode *cea_mode;
4556 struct drm_display_mode *newmode;
4558 cea_mode = cea_mode_for_vic(video_code);
4562 newmode = drm_mode_duplicate(dev, cea_mode);
4568 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4571 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4574 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4576 for (i = 0; i < len; i++) {
4577 struct drm_display_mode *mode;
4579 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4582 * YCBCR420 capability block contains a bitmap which
4583 * gives the index of CEA modes from CEA VDB, which
4584 * can support YCBCR 420 sampling output also (apart
4585 * from RGB/YCBCR444 etc).
4586 * For example, if the bit 0 in bitmap is set,
4587 * first mode in VDB can support YCBCR420 output too.
4588 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4590 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4591 drm_add_cmdb_modes(connector, db[i]);
4593 drm_mode_probed_add(connector, mode);
4601 struct stereo_mandatory_mode {
4602 int width, height, vrefresh;
4606 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4607 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4608 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4610 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4612 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4613 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4614 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4615 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4616 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4620 stereo_match_mandatory(const struct drm_display_mode *mode,
4621 const struct stereo_mandatory_mode *stereo_mode)
4623 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4625 return mode->hdisplay == stereo_mode->width &&
4626 mode->vdisplay == stereo_mode->height &&
4627 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4628 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4631 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4633 struct drm_device *dev = connector->dev;
4634 const struct drm_display_mode *mode;
4635 struct list_head stereo_modes;
4638 INIT_LIST_HEAD(&stereo_modes);
4640 list_for_each_entry(mode, &connector->probed_modes, head) {
4641 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4642 const struct stereo_mandatory_mode *mandatory;
4643 struct drm_display_mode *new_mode;
4645 if (!stereo_match_mandatory(mode,
4646 &stereo_mandatory_modes[i]))
4649 mandatory = &stereo_mandatory_modes[i];
4650 new_mode = drm_mode_duplicate(dev, mode);
4654 new_mode->flags |= mandatory->flags;
4655 list_add_tail(&new_mode->head, &stereo_modes);
4660 list_splice_tail(&stereo_modes, &connector->probed_modes);
4665 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4667 struct drm_device *dev = connector->dev;
4668 struct drm_display_mode *newmode;
4670 if (!drm_valid_hdmi_vic(vic)) {
4671 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4672 connector->base.id, connector->name, vic);
4676 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4680 drm_mode_probed_add(connector, newmode);
4685 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4686 const u8 *video_db, u8 video_len, u8 video_index)
4688 struct drm_display_mode *newmode;
4691 if (structure & (1 << 0)) {
4692 newmode = drm_display_mode_from_vic_index(connector, video_db,
4696 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4697 drm_mode_probed_add(connector, newmode);
4701 if (structure & (1 << 6)) {
4702 newmode = drm_display_mode_from_vic_index(connector, video_db,
4706 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4707 drm_mode_probed_add(connector, newmode);
4711 if (structure & (1 << 8)) {
4712 newmode = drm_display_mode_from_vic_index(connector, video_db,
4716 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4717 drm_mode_probed_add(connector, newmode);
4726 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4727 * @connector: connector corresponding to the HDMI sink
4728 * @db: start of the CEA vendor specific block
4729 * @len: length of the CEA block payload, ie. one can access up to db[len]
4731 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4732 * also adds the stereo 3d modes when applicable.
4735 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4736 const u8 *video_db, u8 video_len)
4738 struct drm_display_info *info = &connector->display_info;
4739 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4740 u8 vic_len, hdmi_3d_len = 0;
4747 /* no HDMI_Video_Present */
4748 if (!(db[8] & (1 << 5)))
4751 /* Latency_Fields_Present */
4752 if (db[8] & (1 << 7))
4755 /* I_Latency_Fields_Present */
4756 if (db[8] & (1 << 6))
4759 /* the declared length is not long enough for the 2 first bytes
4760 * of additional video format capabilities */
4761 if (len < (8 + offset + 2))
4766 if (db[8 + offset] & (1 << 7)) {
4767 modes += add_hdmi_mandatory_stereo_modes(connector);
4769 /* 3D_Multi_present */
4770 multi_present = (db[8 + offset] & 0x60) >> 5;
4774 vic_len = db[8 + offset] >> 5;
4775 hdmi_3d_len = db[8 + offset] & 0x1f;
4777 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4780 vic = db[9 + offset + i];
4781 modes += add_hdmi_mode(connector, vic);
4783 offset += 1 + vic_len;
4785 if (multi_present == 1)
4787 else if (multi_present == 2)
4792 if (len < (8 + offset + hdmi_3d_len - 1))
4795 if (hdmi_3d_len < multi_len)
4798 if (multi_present == 1 || multi_present == 2) {
4799 /* 3D_Structure_ALL */
4800 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4802 /* check if 3D_MASK is present */
4803 if (multi_present == 2)
4804 mask = (db[10 + offset] << 8) | db[11 + offset];
4808 for (i = 0; i < 16; i++) {
4809 if (mask & (1 << i))
4810 modes += add_3d_struct_modes(connector,
4817 offset += multi_len;
4819 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4821 struct drm_display_mode *newmode = NULL;
4822 unsigned int newflag = 0;
4823 bool detail_present;
4825 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4827 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4830 /* 2D_VIC_order_X */
4831 vic_index = db[8 + offset + i] >> 4;
4833 /* 3D_Structure_X */
4834 switch (db[8 + offset + i] & 0x0f) {
4836 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4839 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4843 if ((db[9 + offset + i] >> 4) == 1)
4844 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4849 newmode = drm_display_mode_from_vic_index(connector,
4855 newmode->flags |= newflag;
4856 drm_mode_probed_add(connector, newmode);
4867 info->has_hdmi_infoframe = true;
4872 cea_revision(const u8 *cea)
4875 * FIXME is this correct for the DispID variant?
4876 * The DispID spec doesn't really specify whether
4877 * this is the revision of the CEA extension or
4878 * the DispID CEA data block. And the only value
4879 * given as an example is 0.
4885 * CTA Data Block iterator.
4887 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4890 * struct cea_db *db:
4891 * struct cea_db_iter iter;
4893 * cea_db_iter_edid_begin(edid, &iter);
4894 * cea_db_iter_for_each(db, &iter) {
4895 * // do stuff with db
4897 * cea_db_iter_end(&iter);
4899 struct cea_db_iter {
4900 struct drm_edid_iter edid_iter;
4901 struct displayid_iter displayid_iter;
4903 /* Current Data Block Collection. */
4904 const u8 *collection;
4906 /* Current Data Block index in current collection. */
4909 /* End index in current collection. */
4913 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4919 static int cea_db_tag(const struct cea_db *db)
4921 return db->tag_length >> 5;
4924 static int cea_db_payload_len(const void *_db)
4926 /* FIXME: Transition to passing struct cea_db * everywhere. */
4927 const struct cea_db *db = _db;
4929 return db->tag_length & 0x1f;
4932 static const void *cea_db_data(const struct cea_db *db)
4937 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4939 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4940 cea_db_payload_len(db) >= 1 &&
4944 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4946 const u8 *data = cea_db_data(db);
4948 return cea_db_tag(db) == CTA_DB_VENDOR &&
4949 cea_db_payload_len(db) >= 3 &&
4950 oui(data[2], data[1], data[0]) == vendor_oui;
4953 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4954 struct cea_db_iter *iter)
4956 memset(iter, 0, sizeof(*iter));
4958 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4959 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4962 static const struct cea_db *
4963 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4965 const struct cea_db *db;
4967 if (!iter->collection)
4970 db = (const struct cea_db *)&iter->collection[iter->index];
4972 if (iter->index + sizeof(*db) <= iter->end &&
4973 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4981 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4983 static int cea_db_collection_size(const u8 *cta)
4987 if (d < 4 || d > 127)
4995 * - VESA E-EDID v1.4
4996 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4998 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5002 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5005 /* Only support CTA Extension revision 3+ */
5006 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5009 size = cea_db_collection_size(ext);
5014 iter->end = iter->index + size;
5024 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5025 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5027 * Note that the above do not specify any connection between DisplayID Data
5028 * Block revision and CTA Extension versions.
5030 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5032 const struct displayid_block *block;
5034 displayid_iter_for_each(block, &iter->displayid_iter) {
5035 if (block->tag != DATA_BLOCK_CTA)
5039 * The displayid iterator has already verified the block bounds
5040 * in displayid_iter_block().
5042 iter->index = sizeof(*block);
5043 iter->end = iter->index + block->num_bytes;
5051 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5053 const struct cea_db *db;
5055 if (iter->collection) {
5056 /* Current collection should always be valid. */
5057 db = __cea_db_iter_current_block(iter);
5059 iter->collection = NULL;
5063 /* Next block in CTA Data Block Collection */
5064 iter->index += sizeof(*db) + cea_db_payload_len(db);
5066 db = __cea_db_iter_current_block(iter);
5073 * Find the next CTA Data Block Collection. First iterate all
5074 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5076 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5077 * Extension, it's recommended that DisplayID extensions are
5078 * exposed after all of the CTA Extensions.
5080 iter->collection = __cea_db_iter_edid_next(iter);
5081 if (!iter->collection)
5082 iter->collection = __cea_db_iter_displayid_next(iter);
5084 if (!iter->collection)
5087 db = __cea_db_iter_current_block(iter);
5093 #define cea_db_iter_for_each(__db, __iter) \
5094 while (((__db) = __cea_db_iter_next(__iter)))
5096 static void cea_db_iter_end(struct cea_db_iter *iter)
5098 displayid_iter_end(&iter->displayid_iter);
5099 drm_edid_iter_end(&iter->edid_iter);
5101 memset(iter, 0, sizeof(*iter));
5104 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5106 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5107 cea_db_payload_len(db) >= 5;
5110 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5112 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5113 cea_db_payload_len(db) >= 7;
5116 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5118 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5119 cea_db_payload_len(db) >= 2;
5122 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5124 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5125 cea_db_payload_len(db) == 21;
5128 static bool cea_db_is_vcdb(const struct cea_db *db)
5130 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5131 cea_db_payload_len(db) == 2;
5134 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5136 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5137 cea_db_payload_len(db) >= 7;
5140 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5142 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5145 static bool cea_db_is_y420vdb(const struct cea_db *db)
5147 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5150 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5152 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5153 cea_db_payload_len(db) >= 3;
5157 * Get the HF-EEODB override extension block count from EDID.
5159 * The passed in EDID may be partially read, as long as it has at least two
5160 * blocks (base block and one extension block) if EDID extension count is > 0.
5162 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5163 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5164 * iterators instead.
5167 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5169 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5173 /* No extensions according to base block, no HF-EEODB. */
5174 if (!edid_extension_block_count(edid))
5177 /* HF-EEODB is always in the first EDID extension block only */
5178 cta = edid_extension_block_data(edid, 0);
5179 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5182 /* Need to have the data block collection, and at least 3 bytes. */
5183 if (cea_db_collection_size(cta) < 3)
5187 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5188 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5189 * through 6 of Block 1 of the E-EDID.
5191 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5197 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
5200 struct drm_display_info *info = &connector->display_info;
5201 struct drm_hdmi_info *hdmi = &info->hdmi;
5202 u8 map_len = cea_db_payload_len(db) - 1;
5207 /* All CEA modes support ycbcr420 sampling also.*/
5208 hdmi->y420_cmdb_map = U64_MAX;
5209 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5214 * This map indicates which of the existing CEA block modes
5215 * from VDB can support YCBCR420 output too. So if bit=0 is
5216 * set, first mode from VDB can support YCBCR420 output too.
5217 * We will parse and keep this map, before parsing VDB itself
5218 * to avoid going through the same block again and again.
5220 * Spec is not clear about max possible size of this block.
5221 * Clamping max bitmap block size at 8 bytes. Every byte can
5222 * address 8 CEA modes, in this way this map can address
5223 * 8*8 = first 64 SVDs.
5225 if (WARN_ON_ONCE(map_len > 8))
5228 for (count = 0; count < map_len; count++)
5229 map |= (u64)db[2 + count] << (8 * count);
5232 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5234 hdmi->y420_cmdb_map = map;
5237 static int add_cea_modes(struct drm_connector *connector,
5238 const struct drm_edid *drm_edid)
5240 const struct cea_db *db;
5241 struct cea_db_iter iter;
5244 cea_db_iter_edid_begin(drm_edid, &iter);
5245 cea_db_iter_for_each(db, &iter) {
5246 const u8 *hdmi = NULL, *video = NULL;
5247 u8 hdmi_len = 0, video_len = 0;
5249 if (cea_db_tag(db) == CTA_DB_VIDEO) {
5250 video = cea_db_data(db);
5251 video_len = cea_db_payload_len(db);
5252 modes += do_cea_modes(connector, video, video_len);
5253 } else if (cea_db_is_hdmi_vsdb(db)) {
5254 /* FIXME: Switch to use cea_db_data() */
5255 hdmi = (const u8 *)db;
5256 hdmi_len = cea_db_payload_len(db);
5257 } else if (cea_db_is_y420vdb(db)) {
5258 const u8 *vdb420 = cea_db_data(db) + 1;
5260 /* Add 4:2:0(only) modes present in EDID */
5261 modes += do_y420vdb_modes(connector, vdb420,
5262 cea_db_payload_len(db) - 1);
5266 * We parse the HDMI VSDB after having added the cea modes as we
5267 * will be patching their flags when the sink supports stereo
5271 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
5274 cea_db_iter_end(&iter);
5279 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5280 struct drm_display_mode *mode)
5282 const struct drm_display_mode *cea_mode;
5283 int clock1, clock2, clock;
5288 * allow 5kHz clock difference either way to account for
5289 * the 10kHz clock resolution limit of detailed timings.
5291 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5292 if (drm_valid_cea_vic(vic)) {
5294 cea_mode = cea_mode_for_vic(vic);
5295 clock1 = cea_mode->clock;
5296 clock2 = cea_mode_alternate_clock(cea_mode);
5298 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5299 if (drm_valid_hdmi_vic(vic)) {
5301 cea_mode = &edid_4k_modes[vic];
5302 clock1 = cea_mode->clock;
5303 clock2 = hdmi_mode_alternate_clock(cea_mode);
5309 /* pick whichever is closest */
5310 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5315 if (mode->clock == clock)
5318 drm_dbg_kms(connector->dev,
5319 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5320 connector->base.id, connector->name,
5321 type, vic, mode->clock, clock);
5322 mode->clock = clock;
5325 static void drm_calculate_luminance_range(struct drm_connector *connector)
5327 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5328 struct drm_luminance_range_info *luminance_range =
5329 &connector->display_info.luminance_range;
5330 static const u8 pre_computed_values[] = {
5331 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5332 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5334 u32 max_avg, min_cll, max, min, q, r;
5336 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5339 max_avg = hdr_metadata->max_fall;
5340 min_cll = hdr_metadata->min_cll;
5343 * From the specification (CTA-861-G), for calculating the maximum
5344 * luminance we need to use:
5345 * Luminance = 50*2**(CV/32)
5346 * Where CV is a one-byte value.
5347 * For calculating this expression we may need float point precision;
5348 * to avoid this complexity level, we take advantage that CV is divided
5349 * by a constant. From the Euclids division algorithm, we know that CV
5350 * can be written as: CV = 32*q + r. Next, we replace CV in the
5351 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5352 * need to pre-compute the value of r/32. For pre-computing the values
5353 * We just used the following Ruby line:
5354 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5355 * The results of the above expressions can be verified at
5356 * pre_computed_values.
5360 max = (1 << q) * pre_computed_values[r];
5362 /* min luminance: maxLum * (CV/255)^2 / 100 */
5363 q = DIV_ROUND_CLOSEST(min_cll, 255);
5364 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5366 luminance_range->min_luminance = min;
5367 luminance_range->max_luminance = max;
5370 static uint8_t eotf_supported(const u8 *edid_ext)
5372 return edid_ext[2] &
5373 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5374 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5375 BIT(HDMI_EOTF_SMPTE_ST2084) |
5376 BIT(HDMI_EOTF_BT_2100_HLG));
5379 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5381 return edid_ext[3] &
5382 BIT(HDMI_STATIC_METADATA_TYPE1);
5386 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5390 len = cea_db_payload_len(db);
5392 connector->hdr_sink_metadata.hdmi_type1.eotf =
5394 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5395 hdr_metadata_type(db);
5398 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5400 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5402 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5404 /* Calculate only when all values are available */
5405 drm_calculate_luminance_range(connector);
5410 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5412 u8 len = cea_db_payload_len(db);
5414 if (len >= 6 && (db[6] & (1 << 7)))
5415 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5417 connector->latency_present[0] = db[8] >> 7;
5418 connector->latency_present[1] = (db[8] >> 6) & 1;
5421 connector->video_latency[0] = db[9];
5423 connector->audio_latency[0] = db[10];
5425 connector->video_latency[1] = db[11];
5427 connector->audio_latency[1] = db[12];
5429 drm_dbg_kms(connector->dev,
5430 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5431 connector->base.id, connector->name,
5432 connector->latency_present[0], connector->latency_present[1],
5433 connector->video_latency[0], connector->video_latency[1],
5434 connector->audio_latency[0], connector->audio_latency[1]);
5438 monitor_name(const struct detailed_timing *timing, void *data)
5440 const char **res = data;
5442 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5445 *res = timing->data.other_data.data.str.str;
5448 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5450 const char *edid_name = NULL;
5453 if (!drm_edid || !name)
5456 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5457 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5458 if (edid_name[mnl] == 0x0a)
5461 name[mnl] = edid_name[mnl];
5468 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5469 * @edid: monitor EDID information
5470 * @name: pointer to a character array to hold the name of the monitor
5471 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5474 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5476 int name_length = 0;
5483 struct drm_edid drm_edid = {
5485 .size = edid_size(edid),
5488 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5489 memcpy(name, buf, name_length);
5492 name[name_length] = '\0';
5494 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5496 static void clear_eld(struct drm_connector *connector)
5498 memset(connector->eld, 0, sizeof(connector->eld));
5500 connector->latency_present[0] = false;
5501 connector->latency_present[1] = false;
5502 connector->video_latency[0] = 0;
5503 connector->audio_latency[0] = 0;
5504 connector->video_latency[1] = 0;
5505 connector->audio_latency[1] = 0;
5509 * drm_edid_to_eld - build ELD from EDID
5510 * @connector: connector corresponding to the HDMI/DP sink
5511 * @drm_edid: EDID to parse
5513 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5514 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5516 static void drm_edid_to_eld(struct drm_connector *connector,
5517 const struct drm_edid *drm_edid)
5519 const struct drm_display_info *info = &connector->display_info;
5520 const struct cea_db *db;
5521 struct cea_db_iter iter;
5522 uint8_t *eld = connector->eld;
5523 int total_sad_count = 0;
5526 clear_eld(connector);
5531 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5532 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5533 connector->base.id, connector->name,
5534 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5536 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5537 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5539 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5541 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5542 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5543 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5544 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5546 cea_db_iter_edid_begin(drm_edid, &iter);
5547 cea_db_iter_for_each(db, &iter) {
5548 const u8 *data = cea_db_data(db);
5549 int len = cea_db_payload_len(db);
5552 switch (cea_db_tag(db)) {
5554 /* Audio Data Block, contains SADs */
5555 sad_count = min(len / 3, 15 - total_sad_count);
5557 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5558 data, sad_count * 3);
5559 total_sad_count += sad_count;
5561 case CTA_DB_SPEAKER:
5562 /* Speaker Allocation Data Block */
5564 eld[DRM_ELD_SPEAKER] = data[0];
5567 /* HDMI Vendor-Specific Data Block */
5568 if (cea_db_is_hdmi_vsdb(db))
5569 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5575 cea_db_iter_end(&iter);
5577 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5579 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5580 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5581 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5583 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5585 eld[DRM_ELD_BASELINE_ELD_LEN] =
5586 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5588 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5589 connector->base.id, connector->name,
5590 drm_eld_size(eld), total_sad_count);
5593 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5594 struct cea_sad **sads)
5596 const struct cea_db *db;
5597 struct cea_db_iter iter;
5600 cea_db_iter_edid_begin(drm_edid, &iter);
5601 cea_db_iter_for_each(db, &iter) {
5602 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5605 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5606 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5609 for (j = 0; j < count; j++) {
5610 const u8 *sad = &db->data[j * 3];
5612 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5613 (*sads)[j].channels = sad[0] & 0x7;
5614 (*sads)[j].freq = sad[1] & 0x7F;
5615 (*sads)[j].byte2 = sad[2];
5620 cea_db_iter_end(&iter);
5622 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5628 * drm_edid_to_sad - extracts SADs from EDID
5629 * @edid: EDID to parse
5630 * @sads: pointer that will be set to the extracted SADs
5632 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5634 * Note: The returned pointer needs to be freed using kfree().
5636 * Return: The number of found SADs or negative number on error.
5638 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5640 struct drm_edid drm_edid;
5642 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5644 EXPORT_SYMBOL(drm_edid_to_sad);
5646 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5649 const struct cea_db *db;
5650 struct cea_db_iter iter;
5653 cea_db_iter_edid_begin(drm_edid, &iter);
5654 cea_db_iter_for_each(db, &iter) {
5655 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5656 cea_db_payload_len(db) == 3) {
5657 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5661 count = cea_db_payload_len(db);
5665 cea_db_iter_end(&iter);
5667 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5673 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5674 * @edid: EDID to parse
5675 * @sadb: pointer to the speaker block
5677 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5679 * Note: The returned pointer needs to be freed using kfree().
5681 * Return: The number of found Speaker Allocation Blocks or negative number on
5684 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5686 struct drm_edid drm_edid;
5688 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5691 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5694 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5695 * @connector: connector associated with the HDMI/DP sink
5696 * @mode: the display mode
5698 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5699 * the sink doesn't support audio or video.
5701 int drm_av_sync_delay(struct drm_connector *connector,
5702 const struct drm_display_mode *mode)
5704 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5707 if (!connector->latency_present[0])
5709 if (!connector->latency_present[1])
5712 a = connector->audio_latency[i];
5713 v = connector->video_latency[i];
5716 * HDMI/DP sink doesn't support audio or video?
5718 if (a == 255 || v == 255)
5722 * Convert raw EDID values to millisecond.
5723 * Treat unknown latency as 0ms.
5726 a = min(2 * (a - 1), 500);
5728 v = min(2 * (v - 1), 500);
5730 return max(v - a, 0);
5732 EXPORT_SYMBOL(drm_av_sync_delay);
5734 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5736 const struct cea_db *db;
5737 struct cea_db_iter iter;
5741 * Because HDMI identifier is in Vendor Specific Block,
5742 * search it from all data blocks of CEA extension.
5744 cea_db_iter_edid_begin(drm_edid, &iter);
5745 cea_db_iter_for_each(db, &iter) {
5746 if (cea_db_is_hdmi_vsdb(db)) {
5751 cea_db_iter_end(&iter);
5757 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5758 * @edid: monitor EDID information
5760 * Parse the CEA extension according to CEA-861-B.
5762 * Drivers that have added the modes parsed from EDID to drm_display_info
5763 * should use &drm_display_info.is_hdmi instead of calling this function.
5765 * Return: True if the monitor is HDMI, false if not or unknown.
5767 bool drm_detect_hdmi_monitor(const struct edid *edid)
5769 struct drm_edid drm_edid;
5771 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5773 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5775 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5777 struct drm_edid_iter edid_iter;
5778 const struct cea_db *db;
5779 struct cea_db_iter iter;
5781 bool has_audio = false;
5783 drm_edid_iter_begin(drm_edid, &edid_iter);
5784 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5785 if (edid_ext[0] == CEA_EXT) {
5786 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5791 drm_edid_iter_end(&edid_iter);
5794 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5798 cea_db_iter_edid_begin(drm_edid, &iter);
5799 cea_db_iter_for_each(db, &iter) {
5800 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5801 const u8 *data = cea_db_data(db);
5804 for (i = 0; i < cea_db_payload_len(db); i += 3)
5805 DRM_DEBUG_KMS("CEA audio format %d\n",
5806 (data[i] >> 3) & 0xf);
5811 cea_db_iter_end(&iter);
5818 * drm_detect_monitor_audio - check monitor audio capability
5819 * @edid: EDID block to scan
5821 * Monitor should have CEA extension block.
5822 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5823 * audio' only. If there is any audio extension block and supported
5824 * audio format, assume at least 'basic audio' support, even if 'basic
5825 * audio' is not defined in EDID.
5827 * Return: True if the monitor supports audio, false otherwise.
5829 bool drm_detect_monitor_audio(const struct edid *edid)
5831 struct drm_edid drm_edid;
5833 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5835 EXPORT_SYMBOL(drm_detect_monitor_audio);
5839 * drm_default_rgb_quant_range - default RGB quantization range
5840 * @mode: display mode
5842 * Determine the default RGB quantization range for the mode,
5843 * as specified in CEA-861.
5845 * Return: The default RGB quantization range for the mode
5847 enum hdmi_quantization_range
5848 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5850 /* All CEA modes other than VIC 1 use limited quantization range. */
5851 return drm_match_cea_mode(mode) > 1 ?
5852 HDMI_QUANTIZATION_RANGE_LIMITED :
5853 HDMI_QUANTIZATION_RANGE_FULL;
5855 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5857 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5859 struct drm_display_info *info = &connector->display_info;
5861 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5862 connector->base.id, connector->name, db[2]);
5864 if (db[2] & EDID_CEA_VCDB_QS)
5865 info->rgb_quant_range_selectable = true;
5869 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5871 switch (max_frl_rate) {
5874 *max_rate_per_lane = 3;
5878 *max_rate_per_lane = 6;
5882 *max_rate_per_lane = 6;
5886 *max_rate_per_lane = 8;
5890 *max_rate_per_lane = 10;
5894 *max_rate_per_lane = 12;
5899 *max_rate_per_lane = 0;
5903 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5907 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5909 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5910 hdmi->y420_dc_modes = dc_mask;
5913 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
5916 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5918 if (!hdmi_dsc->v_1p2)
5921 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5922 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5924 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5925 hdmi_dsc->bpc_supported = 16;
5926 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5927 hdmi_dsc->bpc_supported = 12;
5928 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5929 hdmi_dsc->bpc_supported = 10;
5931 /* Supports min 8 BPC if DSC 1.2 is supported*/
5932 hdmi_dsc->bpc_supported = 8;
5934 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
5936 u8 dsc_max_frl_rate;
5938 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5939 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5940 &hdmi_dsc->max_frl_rate_per_lane);
5942 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5944 switch (dsc_max_slices) {
5946 hdmi_dsc->max_slices = 1;
5947 hdmi_dsc->clk_per_slice = 340;
5950 hdmi_dsc->max_slices = 2;
5951 hdmi_dsc->clk_per_slice = 340;
5954 hdmi_dsc->max_slices = 4;
5955 hdmi_dsc->clk_per_slice = 340;
5958 hdmi_dsc->max_slices = 8;
5959 hdmi_dsc->clk_per_slice = 340;
5962 hdmi_dsc->max_slices = 8;
5963 hdmi_dsc->clk_per_slice = 400;
5966 hdmi_dsc->max_slices = 12;
5967 hdmi_dsc->clk_per_slice = 400;
5970 hdmi_dsc->max_slices = 16;
5971 hdmi_dsc->clk_per_slice = 400;
5975 hdmi_dsc->max_slices = 0;
5976 hdmi_dsc->clk_per_slice = 0;
5980 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
5981 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5984 /* Sink Capability Data Structure */
5985 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5988 struct drm_display_info *display = &connector->display_info;
5989 struct drm_hdmi_info *hdmi = &display->hdmi;
5990 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5991 int max_tmds_clock = 0;
5992 u8 max_frl_rate = 0;
5993 bool dsc_support = false;
5995 display->has_hdmi_infoframe = true;
5997 if (hf_scds[6] & 0x80) {
5998 hdmi->scdc.supported = true;
5999 if (hf_scds[6] & 0x40)
6000 hdmi->scdc.read_request = true;
6004 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6005 * And as per the spec, three factors confirm this:
6006 * * Availability of a HF-VSDB block in EDID (check)
6007 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6008 * * SCDC support available (let's check)
6009 * Lets check it out.
6013 struct drm_scdc *scdc = &hdmi->scdc;
6015 /* max clock is 5000 KHz times block value */
6016 max_tmds_clock = hf_scds[5] * 5000;
6018 if (max_tmds_clock > 340000) {
6019 display->max_tmds_clock = max_tmds_clock;
6022 if (scdc->supported) {
6023 scdc->scrambling.supported = true;
6025 /* Few sinks support scrambling for clocks < 340M */
6026 if ((hf_scds[6] & 0x8))
6027 scdc->scrambling.low_rates = true;
6032 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6033 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6034 &hdmi->max_frl_rate_per_lane);
6037 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6039 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6040 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6044 drm_dbg_kms(connector->dev,
6045 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6046 connector->base.id, connector->name,
6047 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6050 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6053 struct drm_display_info *info = &connector->display_info;
6054 unsigned int dc_bpc = 0;
6056 /* HDMI supports at least 8 bpc */
6059 if (cea_db_payload_len(hdmi) < 6)
6062 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6064 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6065 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6066 connector->base.id, connector->name);
6069 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6071 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6072 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6073 connector->base.id, connector->name);
6076 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6078 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6079 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6080 connector->base.id, connector->name);
6084 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6085 connector->base.id, connector->name);
6089 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6090 connector->base.id, connector->name, dc_bpc);
6093 /* YCRCB444 is optional according to spec. */
6094 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6095 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6096 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6097 connector->base.id, connector->name);
6101 * Spec says that if any deep color mode is supported at all,
6102 * then deep color 36 bit must be supported.
6104 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6105 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6106 connector->base.id, connector->name);
6111 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6113 struct drm_display_info *info = &connector->display_info;
6114 u8 len = cea_db_payload_len(db);
6116 info->is_hdmi = true;
6119 info->dvi_dual = db[6] & 1;
6121 info->max_tmds_clock = db[7] * 5000;
6123 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6124 connector->base.id, connector->name,
6125 info->dvi_dual, info->max_tmds_clock);
6127 drm_parse_hdmi_deep_color_info(connector, db);
6131 * See EDID extension for head-mounted and specialized monitors, specified at:
6132 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6134 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6137 struct drm_display_info *info = &connector->display_info;
6139 bool desktop_usage = db[5] & BIT(6);
6141 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6142 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6143 info->non_desktop = true;
6145 drm_dbg_kms(connector->dev,
6146 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6147 connector->base.id, connector->name, version, db[5]);
6150 static void drm_parse_cea_ext(struct drm_connector *connector,
6151 const struct drm_edid *drm_edid)
6153 struct drm_display_info *info = &connector->display_info;
6154 struct drm_edid_iter edid_iter;
6155 const struct cea_db *db;
6156 struct cea_db_iter iter;
6159 drm_edid_iter_begin(drm_edid, &edid_iter);
6160 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6161 if (edid_ext[0] != CEA_EXT)
6165 info->cea_rev = edid_ext[1];
6167 if (info->cea_rev != edid_ext[1])
6168 drm_dbg_kms(connector->dev,
6169 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6170 connector->base.id, connector->name,
6171 info->cea_rev, edid_ext[1]);
6173 /* The existence of a CTA extension should imply RGB support */
6174 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6175 if (edid_ext[3] & EDID_CEA_YCRCB444)
6176 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6177 if (edid_ext[3] & EDID_CEA_YCRCB422)
6178 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6180 drm_edid_iter_end(&edid_iter);
6182 cea_db_iter_edid_begin(drm_edid, &iter);
6183 cea_db_iter_for_each(db, &iter) {
6184 /* FIXME: convert parsers to use struct cea_db */
6185 const u8 *data = (const u8 *)db;
6187 if (cea_db_is_hdmi_vsdb(db))
6188 drm_parse_hdmi_vsdb_video(connector, data);
6189 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6190 cea_db_is_hdmi_forum_scdb(db))
6191 drm_parse_hdmi_forum_scds(connector, data);
6192 else if (cea_db_is_microsoft_vsdb(db))
6193 drm_parse_microsoft_vsdb(connector, data);
6194 else if (cea_db_is_y420cmdb(db))
6195 drm_parse_y420cmdb_bitmap(connector, data);
6196 else if (cea_db_is_vcdb(db))
6197 drm_parse_vcdb(connector, data);
6198 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6199 drm_parse_hdr_metadata_block(connector, data);
6201 cea_db_iter_end(&iter);
6205 void get_monitor_range(const struct detailed_timing *timing, void *c)
6207 struct detailed_mode_closure *closure = c;
6208 struct drm_display_info *info = &closure->connector->display_info;
6209 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6210 const struct detailed_non_pixel *data = &timing->data.other_data;
6211 const struct detailed_data_monitor_range *range = &data->data.range;
6212 const struct edid *edid = closure->drm_edid->edid;
6214 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6218 * These limits are used to determine the VRR refresh
6219 * rate range. Only the "range limits only" variant
6220 * of the range descriptor seems to guarantee that
6221 * any and all timings are accepted by the sink, as
6222 * opposed to just timings conforming to the indicated
6223 * formula (GTF/GTF2/CVT). Thus other variants of the
6224 * range descriptor are not accepted here.
6226 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6229 monitor_range->min_vfreq = range->min_vfreq;
6230 monitor_range->max_vfreq = range->max_vfreq;
6232 if (edid->revision >= 4) {
6233 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6234 monitor_range->min_vfreq += 255;
6235 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6236 monitor_range->max_vfreq += 255;
6240 static void drm_get_monitor_range(struct drm_connector *connector,
6241 const struct drm_edid *drm_edid)
6243 const struct drm_display_info *info = &connector->display_info;
6244 struct detailed_mode_closure closure = {
6245 .connector = connector,
6246 .drm_edid = drm_edid,
6249 if (drm_edid->edid->revision < 4)
6252 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6255 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6257 drm_dbg_kms(connector->dev,
6258 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6259 connector->base.id, connector->name,
6260 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6263 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6264 const struct displayid_block *block)
6266 struct displayid_vesa_vendor_specific_block *vesa =
6267 (struct displayid_vesa_vendor_specific_block *)block;
6268 struct drm_display_info *info = &connector->display_info;
6270 if (block->num_bytes < 3) {
6271 drm_dbg_kms(connector->dev,
6272 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6273 connector->base.id, connector->name, block->num_bytes);
6277 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6280 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6281 drm_dbg_kms(connector->dev,
6282 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6283 connector->base.id, connector->name);
6287 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6289 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6290 connector->base.id, connector->name);
6293 info->mso_stream_count = 0;
6296 info->mso_stream_count = 2; /* 2 or 4 links */
6299 info->mso_stream_count = 4; /* 4 links */
6303 if (!info->mso_stream_count) {
6304 info->mso_pixel_overlap = 0;
6308 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6309 if (info->mso_pixel_overlap > 8) {
6310 drm_dbg_kms(connector->dev,
6311 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6312 connector->base.id, connector->name,
6313 info->mso_pixel_overlap);
6314 info->mso_pixel_overlap = 8;
6317 drm_dbg_kms(connector->dev,
6318 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6319 connector->base.id, connector->name,
6320 info->mso_stream_count, info->mso_pixel_overlap);
6323 static void drm_update_mso(struct drm_connector *connector,
6324 const struct drm_edid *drm_edid)
6326 const struct displayid_block *block;
6327 struct displayid_iter iter;
6329 displayid_iter_edid_begin(drm_edid, &iter);
6330 displayid_iter_for_each(block, &iter) {
6331 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6332 drm_parse_vesa_mso_data(connector, block);
6334 displayid_iter_end(&iter);
6337 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6338 * all of the values which would have been set from EDID
6340 static void drm_reset_display_info(struct drm_connector *connector)
6342 struct drm_display_info *info = &connector->display_info;
6345 info->height_mm = 0;
6348 info->color_formats = 0;
6350 info->max_tmds_clock = 0;
6351 info->dvi_dual = false;
6352 info->is_hdmi = false;
6353 info->has_hdmi_infoframe = false;
6354 info->rgb_quant_range_selectable = false;
6355 memset(&info->hdmi, 0, sizeof(info->hdmi));
6357 info->edid_hdmi_rgb444_dc_modes = 0;
6358 info->edid_hdmi_ycbcr444_dc_modes = 0;
6360 info->non_desktop = 0;
6361 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6362 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6364 info->mso_stream_count = 0;
6365 info->mso_pixel_overlap = 0;
6368 static u32 update_display_info(struct drm_connector *connector,
6369 const struct drm_edid *drm_edid)
6371 struct drm_display_info *info = &connector->display_info;
6372 const struct edid *edid = drm_edid->edid;
6374 u32 quirks = edid_get_quirks(drm_edid);
6376 drm_reset_display_info(connector);
6378 info->width_mm = edid->width_cm * 10;
6379 info->height_mm = edid->height_cm * 10;
6381 drm_get_monitor_range(connector, drm_edid);
6383 if (edid->revision < 3)
6386 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6389 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6390 drm_parse_cea_ext(connector, drm_edid);
6393 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6395 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6396 * tells us to assume 8 bpc color depth if the EDID doesn't have
6397 * extensions which tell otherwise.
6399 if (info->bpc == 0 && edid->revision == 3 &&
6400 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6402 drm_dbg_kms(connector->dev,
6403 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6404 connector->base.id, connector->name, info->bpc);
6407 /* Only defined for 1.4 with digital displays */
6408 if (edid->revision < 4)
6411 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6412 case DRM_EDID_DIGITAL_DEPTH_6:
6415 case DRM_EDID_DIGITAL_DEPTH_8:
6418 case DRM_EDID_DIGITAL_DEPTH_10:
6421 case DRM_EDID_DIGITAL_DEPTH_12:
6424 case DRM_EDID_DIGITAL_DEPTH_14:
6427 case DRM_EDID_DIGITAL_DEPTH_16:
6430 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6436 drm_dbg_kms(connector->dev,
6437 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6438 connector->base.id, connector->name, info->bpc);
6440 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6441 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6442 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6443 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6445 drm_update_mso(connector, drm_edid);
6448 if (quirks & EDID_QUIRK_NON_DESKTOP) {
6449 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6450 connector->base.id, connector->name,
6451 info->non_desktop ? " (redundant quirk)" : "");
6452 info->non_desktop = true;
6458 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6459 struct displayid_detailed_timings_1 *timings,
6462 struct drm_display_mode *mode;
6463 unsigned pixel_clock = (timings->pixel_clock[0] |
6464 (timings->pixel_clock[1] << 8) |
6465 (timings->pixel_clock[2] << 16)) + 1;
6466 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6467 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6468 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6469 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6470 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6471 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6472 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6473 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6474 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6475 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6477 mode = drm_mode_create(dev);
6481 /* resolution is kHz for type VII, and 10 kHz for type I */
6482 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6483 mode->hdisplay = hactive;
6484 mode->hsync_start = mode->hdisplay + hsync;
6485 mode->hsync_end = mode->hsync_start + hsync_width;
6486 mode->htotal = mode->hdisplay + hblank;
6488 mode->vdisplay = vactive;
6489 mode->vsync_start = mode->vdisplay + vsync;
6490 mode->vsync_end = mode->vsync_start + vsync_width;
6491 mode->vtotal = mode->vdisplay + vblank;
6494 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6495 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6496 mode->type = DRM_MODE_TYPE_DRIVER;
6498 if (timings->flags & 0x80)
6499 mode->type |= DRM_MODE_TYPE_PREFERRED;
6500 drm_mode_set_name(mode);
6505 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6506 const struct displayid_block *block)
6508 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6511 struct drm_display_mode *newmode;
6513 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6514 /* blocks must be multiple of 20 bytes length */
6515 if (block->num_bytes % 20)
6518 num_timings = block->num_bytes / 20;
6519 for (i = 0; i < num_timings; i++) {
6520 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6522 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6526 drm_mode_probed_add(connector, newmode);
6532 static int add_displayid_detailed_modes(struct drm_connector *connector,
6533 const struct drm_edid *drm_edid)
6535 const struct displayid_block *block;
6536 struct displayid_iter iter;
6539 displayid_iter_edid_begin(drm_edid, &iter);
6540 displayid_iter_for_each(block, &iter) {
6541 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6542 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6543 num_modes += add_displayid_detailed_1_modes(connector, block);
6545 displayid_iter_end(&iter);
6550 static int _drm_edid_connector_update(struct drm_connector *connector,
6551 const struct drm_edid *drm_edid)
6557 drm_reset_display_info(connector);
6558 clear_eld(connector);
6563 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6564 * To avoid multiple parsing of same block, lets parse that map
6565 * from sink info, before parsing CEA modes.
6567 quirks = update_display_info(connector, drm_edid);
6569 /* Depends on info->cea_rev set by update_display_info() above */
6570 drm_edid_to_eld(connector, drm_edid);
6573 * EDID spec says modes should be preferred in this order:
6574 * - preferred detailed mode
6575 * - other detailed modes from base block
6576 * - detailed modes from extension blocks
6577 * - CVT 3-byte code modes
6578 * - standard timing codes
6579 * - established timing codes
6580 * - modes inferred from GTF or CVT range information
6582 * We get this pretty much right.
6584 * XXX order for additional mode types in extension blocks?
6586 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6587 num_modes += add_cvt_modes(connector, drm_edid);
6588 num_modes += add_standard_modes(connector, drm_edid);
6589 num_modes += add_established_modes(connector, drm_edid);
6590 num_modes += add_cea_modes(connector, drm_edid);
6591 num_modes += add_alternate_cea_modes(connector, drm_edid);
6592 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6593 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6594 num_modes += add_inferred_modes(connector, drm_edid);
6596 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6597 edid_fixup_preferred(connector, quirks);
6599 if (quirks & EDID_QUIRK_FORCE_6BPC)
6600 connector->display_info.bpc = 6;
6602 if (quirks & EDID_QUIRK_FORCE_8BPC)
6603 connector->display_info.bpc = 8;
6605 if (quirks & EDID_QUIRK_FORCE_10BPC)
6606 connector->display_info.bpc = 10;
6608 if (quirks & EDID_QUIRK_FORCE_12BPC)
6609 connector->display_info.bpc = 12;
6614 static void _drm_update_tile_info(struct drm_connector *connector,
6615 const struct drm_edid *drm_edid);
6617 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6618 const struct drm_edid *drm_edid)
6620 struct drm_device *dev = connector->dev;
6623 if (connector->edid_blob_ptr) {
6624 const struct edid *old_edid = connector->edid_blob_ptr->data;
6627 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6628 connector->epoch_counter++;
6629 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6630 connector->base.id, connector->name,
6631 connector->epoch_counter);
6636 ret = drm_property_replace_global_blob(dev,
6637 &connector->edid_blob_ptr,
6638 drm_edid ? drm_edid->size : 0,
6639 drm_edid ? drm_edid->edid : NULL,
6641 dev->mode_config.edid_property);
6643 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6644 connector->base.id, connector->name, ret);
6648 ret = drm_object_property_set_value(&connector->base,
6649 dev->mode_config.non_desktop_property,
6650 connector->display_info.non_desktop);
6652 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6653 connector->base.id, connector->name, ret);
6657 ret = drm_connector_set_tile_property(connector);
6659 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6660 connector->base.id, connector->name, ret);
6669 * drm_edid_connector_update - Update connector information from EDID
6670 * @connector: Connector
6673 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6674 * properties, etc. from the passed in EDID.
6676 * If EDID is NULL, reset the information.
6678 * Return: The number of modes added or 0 if we couldn't find any.
6680 int drm_edid_connector_update(struct drm_connector *connector,
6681 const struct drm_edid *drm_edid)
6685 count = _drm_edid_connector_update(connector, drm_edid);
6687 _drm_update_tile_info(connector, drm_edid);
6689 /* Note: Ignore errors for now. */
6690 _drm_edid_connector_property_update(connector, drm_edid);
6694 EXPORT_SYMBOL(drm_edid_connector_update);
6696 static int _drm_connector_update_edid_property(struct drm_connector *connector,
6697 const struct drm_edid *drm_edid)
6700 * Set the display info, using edid if available, otherwise resetting
6701 * the values to defaults. This duplicates the work done in
6702 * drm_add_edid_modes, but that function is not consistently called
6703 * before this one in all drivers and the computation is cheap enough
6704 * that it seems better to duplicate it rather than attempt to ensure
6705 * some arbitrary ordering of calls.
6708 update_display_info(connector, drm_edid);
6710 drm_reset_display_info(connector);
6712 _drm_update_tile_info(connector, drm_edid);
6714 return _drm_edid_connector_property_update(connector, drm_edid);
6718 * drm_connector_update_edid_property - update the edid property of a connector
6719 * @connector: drm connector
6720 * @edid: new value of the edid property
6722 * This function creates a new blob modeset object and assigns its id to the
6723 * connector's edid property.
6724 * Since we also parse tile information from EDID's displayID block, we also
6725 * set the connector's tile property here. See drm_connector_set_tile_property()
6728 * This function is deprecated. Use drm_edid_connector_update() instead.
6731 * Zero on success, negative errno on failure.
6733 int drm_connector_update_edid_property(struct drm_connector *connector,
6734 const struct edid *edid)
6736 struct drm_edid drm_edid;
6738 return _drm_connector_update_edid_property(connector,
6739 drm_edid_legacy_init(&drm_edid, edid));
6741 EXPORT_SYMBOL(drm_connector_update_edid_property);
6744 * drm_add_edid_modes - add modes from EDID data, if available
6745 * @connector: connector we're probing
6748 * Add the specified modes to the connector's mode list. Also fills out the
6749 * &drm_display_info structure and ELD in @connector with any information which
6750 * can be derived from the edid.
6752 * This function is deprecated. Use drm_edid_connector_update() instead.
6754 * Return: The number of modes added or 0 if we couldn't find any.
6756 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6758 struct drm_edid drm_edid;
6760 if (edid && !drm_edid_is_valid(edid)) {
6761 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6762 connector->base.id, connector->name);
6766 return _drm_edid_connector_update(connector,
6767 drm_edid_legacy_init(&drm_edid, edid));
6769 EXPORT_SYMBOL(drm_add_edid_modes);
6772 * drm_add_modes_noedid - add modes for the connectors without EDID
6773 * @connector: connector we're probing
6774 * @hdisplay: the horizontal display limit
6775 * @vdisplay: the vertical display limit
6777 * Add the specified modes to the connector's mode list. Only when the
6778 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6780 * Return: The number of modes added or 0 if we couldn't find any.
6782 int drm_add_modes_noedid(struct drm_connector *connector,
6783 int hdisplay, int vdisplay)
6785 int i, count, num_modes = 0;
6786 struct drm_display_mode *mode;
6787 struct drm_device *dev = connector->dev;
6789 count = ARRAY_SIZE(drm_dmt_modes);
6795 for (i = 0; i < count; i++) {
6796 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6798 if (hdisplay && vdisplay) {
6800 * Only when two are valid, they will be used to check
6801 * whether the mode should be added to the mode list of
6804 if (ptr->hdisplay > hdisplay ||
6805 ptr->vdisplay > vdisplay)
6808 if (drm_mode_vrefresh(ptr) > 61)
6810 mode = drm_mode_duplicate(dev, ptr);
6812 drm_mode_probed_add(connector, mode);
6818 EXPORT_SYMBOL(drm_add_modes_noedid);
6821 * drm_set_preferred_mode - Sets the preferred mode of a connector
6822 * @connector: connector whose mode list should be processed
6823 * @hpref: horizontal resolution of preferred mode
6824 * @vpref: vertical resolution of preferred mode
6826 * Marks a mode as preferred if it matches the resolution specified by @hpref
6829 void drm_set_preferred_mode(struct drm_connector *connector,
6830 int hpref, int vpref)
6832 struct drm_display_mode *mode;
6834 list_for_each_entry(mode, &connector->probed_modes, head) {
6835 if (mode->hdisplay == hpref &&
6836 mode->vdisplay == vpref)
6837 mode->type |= DRM_MODE_TYPE_PREFERRED;
6840 EXPORT_SYMBOL(drm_set_preferred_mode);
6842 static bool is_hdmi2_sink(const struct drm_connector *connector)
6845 * FIXME: sil-sii8620 doesn't have a connector around when
6846 * we need one, so we have to be prepared for a NULL connector.
6851 return connector->display_info.hdmi.scdc.supported ||
6852 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6855 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6856 const struct drm_display_mode *mode)
6858 bool has_hdmi_infoframe = connector ?
6859 connector->display_info.has_hdmi_infoframe : false;
6861 if (!has_hdmi_infoframe)
6864 /* No HDMI VIC when signalling 3D video format */
6865 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6868 return drm_match_hdmi_mode(mode);
6871 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
6872 const struct drm_display_mode *mode)
6877 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6878 * we should send its VIC in vendor infoframes, else send the
6879 * VIC in AVI infoframes. Lets check if this mode is present in
6880 * HDMI 1.4b 4K modes
6882 if (drm_mode_hdmi_vic(connector, mode))
6885 vic = drm_match_cea_mode(mode);
6888 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6889 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6890 * have to make sure we dont break HDMI 1.4 sinks.
6892 if (!is_hdmi2_sink(connector) && vic > 64)
6899 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6900 * data from a DRM display mode
6901 * @frame: HDMI AVI infoframe
6902 * @connector: the connector
6903 * @mode: DRM display mode
6905 * Return: 0 on success or a negative error code on failure.
6908 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
6909 const struct drm_connector *connector,
6910 const struct drm_display_mode *mode)
6912 enum hdmi_picture_aspect picture_aspect;
6915 if (!frame || !mode)
6918 hdmi_avi_infoframe_init(frame);
6920 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6921 frame->pixel_repeat = 1;
6923 vic = drm_mode_cea_vic(connector, mode);
6924 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
6926 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6929 * As some drivers don't support atomic, we can't use connector state.
6930 * So just initialize the frame with default values, just the same way
6931 * as it's done with other properties here.
6933 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6937 * Populate picture aspect ratio from either
6938 * user input (if specified) or from the CEA/HDMI mode lists.
6940 picture_aspect = mode->picture_aspect_ratio;
6941 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6943 picture_aspect = drm_get_cea_aspect_ratio(vic);
6945 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6949 * The infoframe can't convey anything but none, 4:3
6950 * and 16:9, so if the user has asked for anything else
6951 * we can only satisfy it by specifying the right VIC.
6953 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
6955 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6957 } else if (hdmi_vic) {
6958 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6964 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6967 frame->video_code = vic;
6968 frame->picture_aspect = picture_aspect;
6969 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
6970 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
6974 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
6977 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6978 * quantization range information
6979 * @frame: HDMI AVI infoframe
6980 * @connector: the connector
6981 * @mode: DRM display mode
6982 * @rgb_quant_range: RGB quantization range (Q)
6985 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6986 const struct drm_connector *connector,
6987 const struct drm_display_mode *mode,
6988 enum hdmi_quantization_range rgb_quant_range)
6990 const struct drm_display_info *info = &connector->display_info;
6994 * "A Source shall not send a non-zero Q value that does not correspond
6995 * to the default RGB Quantization Range for the transmitted Picture
6996 * unless the Sink indicates support for the Q bit in a Video
6997 * Capabilities Data Block."
6999 * HDMI 2.0 recommends sending non-zero Q when it does match the
7000 * default RGB quantization range for the mode, even when QS=0.
7002 if (info->rgb_quant_range_selectable ||
7003 rgb_quant_range == drm_default_rgb_quant_range(mode))
7004 frame->quantization_range = rgb_quant_range;
7006 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7010 * "When transmitting any RGB colorimetry, the Source should set the
7011 * YQ-field to match the RGB Quantization Range being transmitted
7012 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7013 * set YQ=1) and the Sink shall ignore the YQ-field."
7015 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7016 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7017 * good way to tell which version of CEA-861 the sink supports, so
7018 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7021 if (!is_hdmi2_sink(connector) ||
7022 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7023 frame->ycc_quantization_range =
7024 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7026 frame->ycc_quantization_range =
7027 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7029 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7031 static enum hdmi_3d_structure
7032 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7034 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7037 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7038 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7039 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7040 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7041 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7042 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7043 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7044 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7045 case DRM_MODE_FLAG_3D_L_DEPTH:
7046 return HDMI_3D_STRUCTURE_L_DEPTH;
7047 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7048 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7049 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7050 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7051 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7052 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7054 return HDMI_3D_STRUCTURE_INVALID;
7059 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7060 * data from a DRM display mode
7061 * @frame: HDMI vendor infoframe
7062 * @connector: the connector
7063 * @mode: DRM display mode
7065 * Note that there's is a need to send HDMI vendor infoframes only when using a
7066 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7067 * function will return -EINVAL, error that can be safely ignored.
7069 * Return: 0 on success or a negative error code on failure.
7072 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7073 const struct drm_connector *connector,
7074 const struct drm_display_mode *mode)
7077 * FIXME: sil-sii8620 doesn't have a connector around when
7078 * we need one, so we have to be prepared for a NULL connector.
7080 bool has_hdmi_infoframe = connector ?
7081 connector->display_info.has_hdmi_infoframe : false;
7084 if (!frame || !mode)
7087 if (!has_hdmi_infoframe)
7090 err = hdmi_vendor_infoframe_init(frame);
7095 * Even if it's not absolutely necessary to send the infoframe
7096 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7097 * know that the sink can handle it. This is based on a
7098 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7099 * have trouble realizing that they should switch from 3D to 2D
7100 * mode if the source simply stops sending the infoframe when
7101 * it wants to switch from 3D to 2D.
7103 frame->vic = drm_mode_hdmi_vic(connector, mode);
7104 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7108 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7110 static void drm_parse_tiled_block(struct drm_connector *connector,
7111 const struct displayid_block *block)
7113 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7115 u8 tile_v_loc, tile_h_loc;
7116 u8 num_v_tile, num_h_tile;
7117 struct drm_tile_group *tg;
7119 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7120 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7122 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7123 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7124 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7125 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7127 connector->has_tile = true;
7128 if (tile->tile_cap & 0x80)
7129 connector->tile_is_single_monitor = true;
7131 connector->num_h_tile = num_h_tile + 1;
7132 connector->num_v_tile = num_v_tile + 1;
7133 connector->tile_h_loc = tile_h_loc;
7134 connector->tile_v_loc = tile_v_loc;
7135 connector->tile_h_size = w + 1;
7136 connector->tile_v_size = h + 1;
7138 drm_dbg_kms(connector->dev,
7139 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7140 connector->base.id, connector->name,
7142 connector->tile_h_size, connector->tile_v_size,
7143 connector->num_h_tile, connector->num_v_tile,
7144 connector->tile_h_loc, connector->tile_v_loc,
7145 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7147 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7149 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7153 if (connector->tile_group != tg) {
7154 /* if we haven't got a pointer,
7155 take the reference, drop ref to old tile group */
7156 if (connector->tile_group)
7157 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7158 connector->tile_group = tg;
7160 /* if same tile group, then release the ref we just took. */
7161 drm_mode_put_tile_group(connector->dev, tg);
7165 static void _drm_update_tile_info(struct drm_connector *connector,
7166 const struct drm_edid *drm_edid)
7168 const struct displayid_block *block;
7169 struct displayid_iter iter;
7171 connector->has_tile = false;
7173 displayid_iter_edid_begin(drm_edid, &iter);
7174 displayid_iter_for_each(block, &iter) {
7175 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
7176 drm_parse_tiled_block(connector, block);
7178 displayid_iter_end(&iter);
7180 if (!connector->has_tile && connector->tile_group) {
7181 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7182 connector->tile_group = NULL;
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