drivers/gpu/drm/bridge/ite-it6505.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5 #include <linux/bits.h>
   6 #include <linux/delay.h>
   7 #include <linux/device.h>
   8 #include <linux/err.h>
   9 #include <linux/extcon.h>
  10 #include <linux/fs.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/i2c.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/types.h>
  20 #include <linux/wait.h>
  21
  22 #include <crypto/hash.h>
  23
  24 #include <drm/display/drm_dp_helper.h>
  25 #include <drm/display/drm_hdcp_helper.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_bridge.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_print.h>
  32 #include <drm/drm_probe_helper.h>
  33
  34 #include <sound/hdmi-codec.h>
  35
  36 #define REG_IC_VER 0x04
  37
  38 #define REG_RESET_CTRL 0x05
  39 #define VIDEO_RESET BIT(0)
  40 #define AUDIO_RESET BIT(1)
  41 #define ALL_LOGIC_RESET BIT(2)
  42 #define AUX_RESET BIT(3)
  43 #define HDCP_RESET BIT(4)
  44
  45 #define INT_STATUS_01 0x06
  46 #define INT_MASK_01 0x09
  47 #define INT_HPD_CHANGE 0
  48 #define INT_RECEIVE_HPD_IRQ 1
  49 #define INT_SCDT_CHANGE 2
  50 #define INT_HDCP_FAIL 3
  51 #define INT_HDCP_DONE 4
  52 #define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
  53 #define BIT_INT_HPD INT_HPD_CHANGE
  54 #define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
  55 #define BIT_INT_SCDT INT_SCDT_CHANGE
  56 #define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
  57 #define BIT_INT_HDCP_DONE INT_HDCP_DONE
  58
  59 #define INT_STATUS_02 0x07
  60 #define INT_MASK_02 0x0A
  61 #define INT_AUX_CMD_FAIL 0
  62 #define INT_HDCP_KSV_CHECK 1
  63 #define INT_AUDIO_FIFO_ERROR 2
  64 #define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
  65 #define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
  66 #define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
  67
  68 #define INT_STATUS_03 0x08
  69 #define INT_MASK_03 0x0B
  70 #define INT_LINK_TRAIN_FAIL 4
  71 #define INT_VID_FIFO_ERROR 5
  72 #define INT_IO_LATCH_FIFO_OVERFLOW 7
  73 #define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
  74 #define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
  75 #define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
  76
  77 #define REG_SYSTEM_STS 0x0D
  78 #define INT_STS BIT(0)
  79 #define HPD_STS BIT(1)
  80 #define VIDEO_STB BIT(2)
  81
  82 #define REG_LINK_TRAIN_STS 0x0E
  83 #define LINK_STATE_CR BIT(2)
  84 #define LINK_STATE_EQ BIT(3)
  85 #define LINK_STATE_NORP BIT(4)
  86
  87 #define REG_BANK_SEL 0x0F
  88 #define REG_CLK_CTRL0 0x10
  89 #define M_PCLK_DELAY 0x03
  90
  91 #define REG_AUX_OPT 0x11
  92 #define AUX_AUTO_RST BIT(0)
  93 #define AUX_FIX_FREQ BIT(3)
  94
  95 #define REG_DATA_CTRL0 0x12
  96 #define VIDEO_LATCH_EDGE BIT(4)
  97 #define ENABLE_PCLK_COUNTER BIT(7)
  98
  99 #define REG_PCLK_COUNTER_VALUE 0x13
 100
 101 #define REG_501_FIFO_CTRL 0x15
 102 #define RST_501_FIFO BIT(1)
 103
 104 #define REG_TRAIN_CTRL0 0x16
 105 #define FORCE_LBR BIT(0)
 106 #define LANE_COUNT_MASK 0x06
 107 #define LANE_SWAP BIT(3)
 108 #define SPREAD_AMP_5 BIT(4)
 109 #define FORCE_CR_DONE BIT(5)
 110 #define FORCE_EQ_DONE BIT(6)
 111
 112 #define REG_TRAIN_CTRL1 0x17
 113 #define AUTO_TRAIN BIT(0)
 114 #define MANUAL_TRAIN BIT(1)
 115 #define FORCE_RETRAIN BIT(2)
 116
 117 #define REG_AUX_CTRL 0x23
 118 #define CLR_EDID_FIFO BIT(0)
 119 #define AUX_USER_MODE BIT(1)
 120 #define AUX_NO_SEGMENT_WR BIT(6)
 121 #define AUX_EN_FIFO_READ BIT(7)
 122
 123 #define REG_AUX_ADR_0_7 0x24
 124 #define REG_AUX_ADR_8_15 0x25
 125 #define REG_AUX_ADR_16_19 0x26
 126 #define REG_AUX_OUT_DATA0 0x27
 127
 128 #define REG_AUX_CMD_REQ 0x2B
 129 #define AUX_BUSY BIT(5)
 130
 131 #define REG_AUX_DATA_0_7 0x2C
 132 #define REG_AUX_DATA_8_15 0x2D
 133 #define REG_AUX_DATA_16_23 0x2E
 134 #define REG_AUX_DATA_24_31 0x2F
 135
 136 #define REG_AUX_DATA_FIFO 0x2F
 137
 138 #define REG_AUX_ERROR_STS 0x9F
 139 #define M_AUX_REQ_FAIL 0x03
 140
 141 #define REG_HDCP_CTRL1 0x38
 142 #define HDCP_CP_ENABLE BIT(0)
 143
 144 #define REG_HDCP_TRIGGER 0x39
 145 #define HDCP_TRIGGER_START  BIT(0)
 146 #define HDCP_TRIGGER_CPIRQ  BIT(1)
 147 #define HDCP_TRIGGER_KSV_DONE  BIT(4)
 148 #define HDCP_TRIGGER_KSV_FAIL BIT(5)
 149
 150 #define REG_HDCP_CTRL2 0x3A
 151 #define HDCP_AN_SEL BIT(0)
 152 #define HDCP_AN_GEN BIT(1)
 153 #define HDCP_HW_HPDIRQ_ACT BIT(2)
 154 #define HDCP_EN_M0_READ BIT(5)
 155
 156 #define REG_M0_0_7 0x4C
 157 #define REG_AN_0_7 0x4C
 158 #define REG_SP_CTRL0 0x58
 159 #define REG_IP_CTRL1 0x59
 160 #define REG_IP_CTRL2 0x5A
 161
 162 #define REG_LINK_DRV 0x5C
 163 #define DRV_HS BIT(1)
 164
 165 #define REG_DRV_LN_DATA_SEL 0x5D
 166
 167 #define REG_AUX 0x5E
 168
 169 #define REG_VID_BUS_CTRL0 0x60
 170 #define IN_DDR BIT(2)
 171 #define DDR_CD (0x01 << 6)
 172
 173 #define REG_VID_BUS_CTRL1 0x61
 174 #define TX_FIFO_RESET BIT(1)
 175
 176 #define REG_INPUT_CTRL 0xA0
 177 #define INPUT_HSYNC_POL BIT(0)
 178 #define INPUT_VSYNC_POL BIT(2)
 179 #define INPUT_INTERLACED BIT(4)
 180
 181 #define REG_INPUT_HTOTAL 0xA1
 182 #define REG_INPUT_HACTIVE_START 0xA3
 183 #define REG_INPUT_HACTIVE_WIDTH 0xA5
 184 #define REG_INPUT_HFRONT_PORCH 0xA7
 185 #define REG_INPUT_HSYNC_WIDTH 0xA9
 186 #define REG_INPUT_VTOTAL 0xAB
 187 #define REG_INPUT_VACTIVE_START 0xAD
 188 #define REG_INPUT_VACTIVE_WIDTH 0xAF
 189 #define REG_INPUT_VFRONT_PORCH 0xB1
 190 #define REG_INPUT_VSYNC_WIDTH 0xB3
 191
 192 #define REG_AUDIO_SRC_CTRL 0xB8
 193 #define M_AUDIO_I2S_EN 0x0F
 194 #define EN_I2S0 BIT(0)
 195 #define EN_I2S1 BIT(1)
 196 #define EN_I2S2 BIT(2)
 197 #define EN_I2S3 BIT(3)
 198 #define AUDIO_FIFO_RESET BIT(7)
 199
 200 #define REG_AUDIO_FMT 0xB9
 201 #define REG_AUDIO_FIFO_SEL 0xBA
 202
 203 #define REG_AUDIO_CTRL0 0xBB
 204 #define AUDIO_FULL_PKT BIT(4)
 205 #define AUDIO_16B_BOUND BIT(5)
 206
 207 #define REG_AUDIO_CTRL1 0xBC
 208 #define REG_AUDIO_INPUT_FREQ 0xBE
 209
 210 #define REG_IEC958_STS0 0xBF
 211 #define REG_IEC958_STS1 0xC0
 212 #define REG_IEC958_STS2 0xC1
 213 #define REG_IEC958_STS3 0xC2
 214 #define REG_IEC958_STS4 0xC3
 215
 216 #define REG_HPD_IRQ_TIME 0xC9
 217 #define REG_AUX_DEBUG_MODE 0xCA
 218 #define REG_AUX_OPT2 0xCB
 219 #define REG_HDCP_OPT 0xCE
 220 #define REG_USER_DRV_PRE 0xCF
 221
 222 #define REG_DATA_MUTE_CTRL 0xD3
 223 #define ENABLE_ENHANCED_FRAME BIT(0)
 224 #define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
 225 #define EN_VID_MUTE BIT(4)
 226 #define EN_AUD_MUTE BIT(5)
 227
 228 #define REG_TIME_STMP_CTRL 0xD4
 229 #define EN_ENHANCE_VID_STMP BIT(0)
 230 #define EN_ENHANCE_AUD_STMP BIT(2)
 231 #define M_STAMP_STEP 0x30
 232 #define EN_SSC_GAT BIT(6)
 233
 234 #define REG_INFOFRAME_CTRL 0xE8
 235 #define EN_AVI_PKT BIT(0)
 236 #define EN_AUD_PKT BIT(1)
 237 #define EN_MPG_PKT BIT(2)
 238 #define EN_GEN_PKT BIT(3)
 239 #define EN_VID_TIME_STMP BIT(4)
 240 #define EN_AUD_TIME_STMP BIT(5)
 241 #define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
 242 #define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
 243
 244 #define REG_AUDIO_N_0_7 0xDE
 245 #define REG_AUDIO_N_8_15 0xDF
 246 #define REG_AUDIO_N_16_23 0xE0
 247
 248 #define REG_AVI_INFO_DB1 0xE9
 249 #define REG_AVI_INFO_DB2 0xEA
 250 #define REG_AVI_INFO_DB3 0xEB
 251 #define REG_AVI_INFO_DB4 0xEC
 252 #define REG_AVI_INFO_DB5 0xED
 253 #define REG_AVI_INFO_SUM 0xF6
 254
 255 #define REG_AUD_INFOFRAM_DB1 0xF7
 256 #define REG_AUD_INFOFRAM_DB2 0xF8
 257 #define REG_AUD_INFOFRAM_DB3 0xF9
 258 #define REG_AUD_INFOFRAM_DB4 0xFA
 259 #define REG_AUD_INFOFRAM_SUM 0xFB
 260
 261 /* the following six registers are in bank1 */
 262 #define REG_DRV_0_DB_800_MV 0x7E
 263 #define REG_PRE_0_DB_800_MV 0x7F
 264 #define REG_PRE_3P5_DB_800_MV 0x81
 265 #define REG_SSC_CTRL0 0x88
 266 #define REG_SSC_CTRL1 0x89
 267 #define REG_SSC_CTRL2 0x8A
 268
 269 #define RBR DP_LINK_BW_1_62
 270 #define HBR DP_LINK_BW_2_7
 271 #define HBR2 DP_LINK_BW_5_4
 272 #define HBR3 DP_LINK_BW_8_1
 273
 274 #define DPCD_V_1_1 0x11
 275 #define MISC_VERB 0xF0
 276 #define MISC_VERC 0x70
 277 #define I2S_INPUT_FORMAT_STANDARD 0
 278 #define I2S_INPUT_FORMAT_32BIT 1
 279 #define I2S_INPUT_LEFT_JUSTIFIED 0
 280 #define I2S_INPUT_RIGHT_JUSTIFIED 1
 281 #define I2S_DATA_1T_DELAY 0
 282 #define I2S_DATA_NO_DELAY 1
 283 #define I2S_WS_LEFT_CHANNEL 0
 284 #define I2S_WS_RIGHT_CHANNEL 1
 285 #define I2S_DATA_MSB_FIRST 0
 286 #define I2S_DATA_LSB_FIRST 1
 287 #define WORD_LENGTH_16BIT 0
 288 #define WORD_LENGTH_18BIT 1
 289 #define WORD_LENGTH_20BIT 2
 290 #define WORD_LENGTH_24BIT 3
 291 #define DEBUGFS_DIR_NAME "it6505-debugfs"
 292 #define READ_BUFFER_SIZE 400
 293
 294 /* Vendor option */
 295 #define HDCP_DESIRED 1
 296 #define MAX_LANE_COUNT 4
 297 #define MAX_LINK_RATE HBR
 298 #define AUTO_TRAIN_RETRY 3
 299 #define MAX_HDCP_DOWN_STREAM_COUNT 10
 300 #define MAX_CR_LEVEL 0x03
 301 #define MAX_EQ_LEVEL 0x03
 302 #define AUX_WAIT_TIMEOUT_MS 15
 303 #define AUX_FIFO_MAX_SIZE 32
 304 #define PIXEL_CLK_DELAY 1
 305 #define PIXEL_CLK_INVERSE 0
 306 #define ADJUST_PHASE_THRESHOLD 80000
 307 #define DPI_PIXEL_CLK_MAX 95000
 308 #define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
 309 #define DEFAULT_PWR_ON 0
 310 #define DEFAULT_DRV_HOLD 0
 311
 312 #define AUDIO_SELECT I2S
 313 #define AUDIO_TYPE LPCM
 314 #define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
 315 #define AUDIO_CHANNEL_COUNT 2
 316 #define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
 317 #define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
 318 #define I2S_DATA_DELAY I2S_DATA_1T_DELAY
 319 #define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
 320 #define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
 321 #define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
 322
 323 enum aux_cmd_type {
 324         CMD_AUX_NATIVE_READ = 0x0,
 325         CMD_AUX_NATIVE_WRITE = 0x5,
 326         CMD_AUX_I2C_EDID_READ = 0xB,
 327 };
 328
 329 enum aux_cmd_reply {
 330         REPLY_ACK,
 331         REPLY_NACK,
 332         REPLY_DEFER,
 333 };
 334
 335 enum link_train_status {
 336         LINK_IDLE,
 337         LINK_BUSY,
 338         LINK_OK,
 339 };
 340
 341 enum hdcp_state {
 342         HDCP_AUTH_IDLE,
 343         HDCP_AUTH_GOING,
 344         HDCP_AUTH_DONE,
 345 };
 346
 347 struct it6505_platform_data {
 348         struct regulator *pwr18;
 349         struct regulator *ovdd;
 350         struct gpio_desc *gpiod_reset;
 351 };
 352
 353 enum it6505_audio_select {
 354         I2S = 0,
 355         SPDIF,
 356 };
 357
 358 enum it6505_audio_sample_rate {
 359         SAMPLE_RATE_24K = 0x6,
 360         SAMPLE_RATE_32K = 0x3,
 361         SAMPLE_RATE_48K = 0x2,
 362         SAMPLE_RATE_96K = 0xA,
 363         SAMPLE_RATE_192K = 0xE,
 364         SAMPLE_RATE_44_1K = 0x0,
 365         SAMPLE_RATE_88_2K = 0x8,
 366         SAMPLE_RATE_176_4K = 0xC,
 367 };
 368
 369 enum it6505_audio_type {
 370         LPCM = 0,
 371         NLPCM,
 372         DSS,
 373 };
 374
 375 struct it6505_audio_data {
 376         enum it6505_audio_select select;
 377         enum it6505_audio_sample_rate sample_rate;
 378         enum it6505_audio_type type;
 379         u8 word_length;
 380         u8 channel_count;
 381         u8 i2s_input_format;
 382         u8 i2s_justified;
 383         u8 i2s_data_delay;
 384         u8 i2s_ws_channel;
 385         u8 i2s_data_sequence;
 386 };
 387
 388 struct it6505_audio_sample_rate_map {
 389         enum it6505_audio_sample_rate rate;
 390         int sample_rate_value;
 391 };
 392
 393 struct it6505_drm_dp_link {
 394         unsigned char revision;
 395         unsigned int rate;
 396         unsigned int num_lanes;
 397         unsigned long capabilities;
 398 };
 399
 400 struct debugfs_entries {
 401         char *name;
 402         const struct file_operations *fops;
 403 };
 404
 405 struct it6505 {
 406         struct drm_dp_aux aux;
 407         struct drm_bridge bridge;
 408         struct i2c_client *client;
 409         struct it6505_drm_dp_link link;
 410         struct it6505_platform_data pdata;
 411         /*
 412          * Mutex protects extcon and interrupt functions from interfering
 413          * each other.
 414          */
 415         struct mutex irq_lock;
 416         struct mutex extcon_lock;
 417         struct mutex mode_lock; /* used to bridge_detect */
 418         struct mutex aux_lock; /* used to aux data transfers */
 419         struct regmap *regmap;
 420         struct drm_display_mode source_output_mode;
 421         struct drm_display_mode video_info;
 422         struct notifier_block event_nb;
 423         struct extcon_dev *extcon;
 424         struct work_struct extcon_wq;
 425         int extcon_state;
 426         enum drm_connector_status connector_status;
 427         enum link_train_status link_state;
 428         struct work_struct link_works;
 429         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 430         u8 lane_count;
 431         u8 link_rate_bw_code;
 432         u8 sink_count;
 433         bool step_train;
 434         bool branch_device;
 435         bool enable_ssc;
 436         bool lane_swap_disabled;
 437         bool lane_swap;
 438         bool powered;
 439         bool hpd_state;
 440         u32 afe_setting;
 441         enum hdcp_state hdcp_status;
 442         struct delayed_work hdcp_work;
 443         struct work_struct hdcp_wait_ksv_list;
 444         struct completion extcon_completion;
 445         u8 auto_train_retry;
 446         bool hdcp_desired;
 447         bool is_repeater;
 448         u8 hdcp_down_stream_count;
 449         u8 bksvs[DRM_HDCP_KSV_LEN];
 450         u8 sha1_input[HDCP_SHA1_FIFO_LEN];
 451         bool enable_enhanced_frame;
 452         hdmi_codec_plugged_cb plugged_cb;
 453         struct device *codec_dev;
 454         struct delayed_work delayed_audio;
 455         struct it6505_audio_data audio;
 456         struct dentry *debugfs;
 457
 458         /* it6505 driver hold option */
 459         bool enable_drv_hold;
 460 };
 461
 462 struct it6505_step_train_para {
 463         u8 voltage_swing[MAX_LANE_COUNT];
 464         u8 pre_emphasis[MAX_LANE_COUNT];
 465 };
 466
 467 /*
 468  * Vendor option afe settings for different platforms
 469  * 0: without FPC cable
 470  * 1: with FPC cable
 471  */
 472
 473 static const u8 afe_setting_table[][3] = {
 474         {0x82, 0x00, 0x45},
 475         {0x93, 0x2A, 0x85}
 476 };
 477
 478 static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
 479         {SAMPLE_RATE_24K, 24000},
 480         {SAMPLE_RATE_32K, 32000},
 481         {SAMPLE_RATE_48K, 48000},
 482         {SAMPLE_RATE_96K, 96000},
 483         {SAMPLE_RATE_192K, 192000},
 484         {SAMPLE_RATE_44_1K, 44100},
 485         {SAMPLE_RATE_88_2K, 88200},
 486         {SAMPLE_RATE_176_4K, 176400},
 487 };
 488
 489 static const struct regmap_range it6505_bridge_volatile_ranges[] = {
 490         { .range_min = 0, .range_max = 0xFF },
 491 };
 492
 493 static const struct regmap_access_table it6505_bridge_volatile_table = {
 494         .yes_ranges = it6505_bridge_volatile_ranges,
 495         .n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
 496 };
 497
 498 static const struct regmap_config it6505_regmap_config = {
 499         .reg_bits = 8,
 500         .val_bits = 8,
 501         .volatile_table = &it6505_bridge_volatile_table,
 502         .cache_type = REGCACHE_NONE,
 503 };
 504
 505 static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
 506 {
 507         unsigned int value;
 508         int err;
 509         struct device *dev = &it6505->client->dev;
 510
 511         if (!it6505->powered)
 512                 return -ENODEV;
 513
 514         err = regmap_read(it6505->regmap, reg_addr, &value);
 515         if (err < 0) {
 516                 dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
 517                 return err;
 518         }
 519
 520         return value;
 521 }
 522
 523 static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
 524                         unsigned int reg_val)
 525 {
 526         int err;
 527         struct device *dev = &it6505->client->dev;
 528
 529         if (!it6505->powered)
 530                 return -ENODEV;
 531
 532         err = regmap_write(it6505->regmap, reg_addr, reg_val);
 533
 534         if (err < 0) {
 535                 dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
 536                         reg_addr, reg_val, err);
 537                 return err;
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
 544                            unsigned int mask, unsigned int value)
 545 {
 546         int err;
 547         struct device *dev = &it6505->client->dev;
 548
 549         if (!it6505->powered)
 550                 return -ENODEV;
 551
 552         err = regmap_update_bits(it6505->regmap, reg, mask, value);
 553         if (err < 0) {
 554                 dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
 555                         reg, value, mask, err);
 556                 return err;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
 563                                const char *prefix)
 564 {
 565         struct device *dev = &it6505->client->dev;
 566         int val;
 567
 568         if (!drm_debug_enabled(DRM_UT_DRIVER))
 569                 return;
 570
 571         val = it6505_read(it6505, reg);
 572         if (val < 0)
 573                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
 574                                      prefix, reg, val);
 575         else
 576                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
 577                                      val);
 578 }
 579
 580 static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
 581 {
 582         u8 value;
 583         int ret;
 584         struct device *dev = &it6505->client->dev;
 585
 586         ret = drm_dp_dpcd_readb(&it6505->aux, offset, &value);
 587         if (ret < 0) {
 588                 dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
 589                 return ret;
 590         }
 591         return value;
 592 }
 593
 594 static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
 595                              u8 datain)
 596 {
 597         int ret;
 598         struct device *dev = &it6505->client->dev;
 599
 600         ret = drm_dp_dpcd_writeb(&it6505->aux, offset, datain);
 601         if (ret < 0) {
 602                 dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
 603                 return ret;
 604         }
 605         return 0;
 606 }
 607
 608 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
 609 {
 610         int ret;
 611         struct device *dev = &it6505->client->dev;
 612
 613         ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);
 614
 615         if (ret < 0)
 616                 return ret;
 617
 618         DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
 619                              num, dpcd);
 620
 621         return 0;
 622 }
 623
 624 static void it6505_dump(struct it6505 *it6505)
 625 {
 626         unsigned int i, j;
 627         u8 regs[16];
 628         struct device *dev = &it6505->client->dev;
 629
 630         for (i = 0; i <= 0xff; i += 16) {
 631                 for (j = 0; j < 16; j++)
 632                         regs[j] = it6505_read(it6505, i + j);
 633
 634                 DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
 635         }
 636 }
 637
 638 static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
 639 {
 640         int reg_0d;
 641
 642         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
 643
 644         if (reg_0d < 0)
 645                 return false;
 646
 647         return reg_0d & HPD_STS;
 648 }
 649
 650 static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
 651 {
 652         int val0, val1;
 653
 654         val0 = it6505_read(it6505, reg);
 655         if (val0 < 0)
 656                 return val0;
 657
 658         val1 = it6505_read(it6505, reg + 1);
 659         if (val1 < 0)
 660                 return val1;
 661
 662         return (val1 << 8) | val0;
 663 }
 664
 665 static void it6505_calc_video_info(struct it6505 *it6505)
 666 {
 667         struct device *dev = &it6505->client->dev;
 668         int hsync_pol, vsync_pol, interlaced;
 669         int htotal, hdes, hdew, hfph, hsyncw;
 670         int vtotal, vdes, vdew, vfph, vsyncw;
 671         int rddata, i, pclk, sum = 0;
 672
 673         usleep_range(10000, 15000);
 674         rddata = it6505_read(it6505, REG_INPUT_CTRL);
 675         hsync_pol = rddata & INPUT_HSYNC_POL;
 676         vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
 677         interlaced = (rddata & INPUT_INTERLACED) >> 4;
 678
 679         htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
 680         hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
 681         hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
 682         hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
 683         hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
 684
 685         vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
 686         vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
 687         vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
 688         vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
 689         vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
 690
 691         DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
 692                              hsync_pol, vsync_pol, interlaced);
 693         DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
 694                              hdes, vdes);
 695
 696         for (i = 0; i < 3; i++) {
 697                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 698                                 ENABLE_PCLK_COUNTER);
 699                 usleep_range(10000, 15000);
 700                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 701                                 0x00);
 702                 rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
 703                          0xFFF;
 704
 705                 sum += rddata;
 706         }
 707
 708         if (sum == 0) {
 709                 DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
 710                 return;
 711         }
 712
 713         sum /= 3;
 714         pclk = 13500 * 2048 / sum;
 715         it6505->video_info.clock = pclk;
 716         it6505->video_info.hdisplay = hdew;
 717         it6505->video_info.hsync_start = hdew + hfph;
 718         it6505->video_info.hsync_end = hdew + hfph + hsyncw;
 719         it6505->video_info.htotal = htotal;
 720         it6505->video_info.vdisplay = vdew;
 721         it6505->video_info.vsync_start = vdew + vfph;
 722         it6505->video_info.vsync_end = vdew + vfph + vsyncw;
 723         it6505->video_info.vtotal = vtotal;
 724
 725         DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
 726                              DRM_MODE_ARG(&it6505->video_info));
 727 }
 728
 729 static int it6505_drm_dp_link_set_power(struct drm_dp_aux *aux,
 730                                         struct it6505_drm_dp_link *link,
 731                                         u8 mode)
 732 {
 733         u8 value;
 734         int err;
 735
 736         /* DP_SET_POWER register is only available on DPCD v1.1 and later */
 737         if (link->revision < DPCD_V_1_1)
 738                 return 0;
 739
 740         err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
 741         if (err < 0)
 742                 return err;
 743
 744         value &= ~DP_SET_POWER_MASK;
 745         value |= mode;
 746
 747         err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
 748         if (err < 0)
 749                 return err;
 750
 751         if (mode == DP_SET_POWER_D0) {
 752                 /*
 753                  * According to the DP 1.1 specification, a "Sink Device must
 754                  * exit the power saving state within 1 ms" (Section 2.5.3.1,
 755                  * Table 5-52, "Sink Control Field" (register 0x600).
 756                  */
 757                 usleep_range(1000, 2000);
 758         }
 759
 760         return 0;
 761 }
 762
 763 static void it6505_clear_int(struct it6505 *it6505)
 764 {
 765         it6505_write(it6505, INT_STATUS_01, 0xFF);
 766         it6505_write(it6505, INT_STATUS_02, 0xFF);
 767         it6505_write(it6505, INT_STATUS_03, 0xFF);
 768 }
 769
 770 static void it6505_int_mask_enable(struct it6505 *it6505)
 771 {
 772         it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
 773                      BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
 774                      BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
 775
 776         it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
 777                      BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
 778
 779         it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
 780                      BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
 781 }
 782
 783 static void it6505_int_mask_disable(struct it6505 *it6505)
 784 {
 785         it6505_write(it6505, INT_MASK_01, 0x00);
 786         it6505_write(it6505, INT_MASK_02, 0x00);
 787         it6505_write(it6505, INT_MASK_03, 0x00);
 788 }
 789
 790 static void it6505_lane_termination_on(struct it6505 *it6505)
 791 {
 792         int regcf;
 793
 794         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 795
 796         if (regcf == MISC_VERB)
 797                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x00);
 798
 799         if (regcf == MISC_VERC) {
 800                 if (it6505->lane_swap) {
 801                         switch (it6505->lane_count) {
 802                         case 1:
 803                         case 2:
 804                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 805                                                 0x0C, 0x08);
 806                                 break;
 807                         default:
 808                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 809                                                 0x0C, 0x0C);
 810                                 break;
 811                         }
 812                 } else {
 813                         switch (it6505->lane_count) {
 814                         case 1:
 815                         case 2:
 816                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 817                                                 0x0C, 0x04);
 818                                 break;
 819                         default:
 820                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 821                                                 0x0C, 0x0C);
 822                                 break;
 823                         }
 824                 }
 825         }
 826 }
 827
 828 static void it6505_lane_termination_off(struct it6505 *it6505)
 829 {
 830         int regcf;
 831
 832         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 833
 834         if (regcf == MISC_VERB)
 835                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 836
 837         if (regcf == MISC_VERC)
 838                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x0C, 0x00);
 839 }
 840
 841 static void it6505_lane_power_on(struct it6505 *it6505)
 842 {
 843         it6505_set_bits(it6505, REG_LINK_DRV, 0xF1,
 844                         (it6505->lane_swap ?
 845                                  GENMASK(7, 8 - it6505->lane_count) :
 846                                  GENMASK(3 + it6505->lane_count, 4)) |
 847                                 0x01);
 848 }
 849
 850 static void it6505_lane_power_off(struct it6505 *it6505)
 851 {
 852         it6505_set_bits(it6505, REG_LINK_DRV, 0xF0, 0x00);
 853 }
 854
 855 static void it6505_lane_off(struct it6505 *it6505)
 856 {
 857         it6505_lane_power_off(it6505);
 858         it6505_lane_termination_off(it6505);
 859 }
 860
 861 static void it6505_aux_termination_on(struct it6505 *it6505)
 862 {
 863         int regcf;
 864
 865         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 866
 867         if (regcf == MISC_VERB)
 868                 it6505_lane_termination_on(it6505);
 869
 870         if (regcf == MISC_VERC)
 871                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 872 }
 873
 874 static void it6505_aux_power_on(struct it6505 *it6505)
 875 {
 876         it6505_set_bits(it6505, REG_AUX, 0x02, 0x02);
 877 }
 878
 879 static void it6505_aux_on(struct it6505 *it6505)
 880 {
 881         it6505_aux_power_on(it6505);
 882         it6505_aux_termination_on(it6505);
 883 }
 884
 885 static void it6505_aux_reset(struct it6505 *it6505)
 886 {
 887         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
 888         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, 0x00);
 889 }
 890
 891 static void it6505_reset_logic(struct it6505 *it6505)
 892 {
 893         regmap_write(it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
 894         usleep_range(1000, 1500);
 895 }
 896
 897 static bool it6505_aux_op_finished(struct it6505 *it6505)
 898 {
 899         int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
 900
 901         if (reg2b < 0)
 902                 return false;
 903
 904         return (reg2b & AUX_BUSY) == 0;
 905 }
 906
 907 static int it6505_aux_wait(struct it6505 *it6505)
 908 {
 909         int status;
 910         unsigned long timeout;
 911         struct device *dev = &it6505->client->dev;
 912
 913         timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
 914
 915         while (!it6505_aux_op_finished(it6505)) {
 916                 if (time_after(jiffies, timeout)) {
 917                         dev_err(dev, "Timed out waiting AUX to finish");
 918                         return -ETIMEDOUT;
 919                 }
 920                 usleep_range(1000, 2000);
 921         }
 922
 923         status = it6505_read(it6505, REG_AUX_ERROR_STS);
 924         if (status < 0) {
 925                 dev_err(dev, "Failed to read AUX channel: %d", status);
 926                 return status;
 927         }
 928
 929         return 0;
 930 }
 931
 932 static ssize_t it6505_aux_operation(struct it6505 *it6505,
 933                                     enum aux_cmd_type cmd,
 934                                     unsigned int address, u8 *buffer,
 935                                     size_t size, enum aux_cmd_reply *reply)
 936 {
 937         int i, ret;
 938         bool aux_write_check = false;
 939
 940         if (!it6505_get_sink_hpd_status(it6505))
 941                 return -EIO;
 942
 943         /* set AUX user mode */
 944         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
 945
 946 aux_op_start:
 947         if (cmd == CMD_AUX_I2C_EDID_READ) {
 948                 /* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
 949                 size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
 950                 /* Enable AUX FIFO read back and clear FIFO */
 951                 it6505_set_bits(it6505, REG_AUX_CTRL,
 952                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 953                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
 954
 955                 it6505_set_bits(it6505, REG_AUX_CTRL,
 956                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 957                                 AUX_EN_FIFO_READ);
 958         } else {
 959                 /* The DP AUX transmit buffer has 4 bytes. */
 960                 size = min_t(size_t, size, 4);
 961                 it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
 962                                 AUX_NO_SEGMENT_WR);
 963         }
 964
 965         /* Start Address[7:0] */
 966         it6505_write(it6505, REG_AUX_ADR_0_7, (address >> 0) & 0xFF);
 967         /* Start Address[15:8] */
 968         it6505_write(it6505, REG_AUX_ADR_8_15, (address >> 8) & 0xFF);
 969         /* WriteNum[3:0]+StartAdr[19:16] */
 970         it6505_write(it6505, REG_AUX_ADR_16_19,
 971                      ((address >> 16) & 0x0F) | ((size - 1) << 4));
 972
 973         if (cmd == CMD_AUX_NATIVE_WRITE)
 974                 regmap_bulk_write(it6505->regmap, REG_AUX_OUT_DATA0, buffer,
 975                                   size);
 976
 977         /* Aux Fire */
 978         it6505_write(it6505, REG_AUX_CMD_REQ, cmd);
 979
 980         ret = it6505_aux_wait(it6505);
 981         if (ret < 0)
 982                 goto aux_op_err;
 983
 984         ret = it6505_read(it6505, REG_AUX_ERROR_STS);
 985         if (ret < 0)
 986                 goto aux_op_err;
 987
 988         switch ((ret >> 6) & 0x3) {
 989         case 0:
 990                 *reply = REPLY_ACK;
 991                 break;
 992         case 1:
 993                 *reply = REPLY_DEFER;
 994                 ret = -EAGAIN;
 995                 goto aux_op_err;
 996         case 2:
 997                 *reply = REPLY_NACK;
 998                 ret = -EIO;
 999                 goto aux_op_err;
1000         case 3:
1001                 ret = -ETIMEDOUT;
1002                 goto aux_op_err;
1003         }
1004
1005         /* Read back Native Write data */
1006         if (cmd == CMD_AUX_NATIVE_WRITE) {
1007                 aux_write_check = true;
1008                 cmd = CMD_AUX_NATIVE_READ;
1009                 goto aux_op_start;
1010         }
1011
1012         if (cmd == CMD_AUX_I2C_EDID_READ) {
1013                 for (i = 0; i < size; i++) {
1014                         ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1015                         if (ret < 0)
1016                                 goto aux_op_err;
1017                         buffer[i] = ret;
1018                 }
1019         } else {
1020                 for (i = 0; i < size; i++) {
1021                         ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1022                         if (ret < 0)
1023                                 goto aux_op_err;
1024
1025                         if (aux_write_check && buffer[size - 1 - i] != ret) {
1026                                 ret = -EINVAL;
1027                                 goto aux_op_err;
1028                         }
1029
1030                         buffer[size - 1 - i] = ret;
1031                 }
1032         }
1033
1034         ret = i;
1035
1036 aux_op_err:
1037         if (cmd == CMD_AUX_I2C_EDID_READ) {
1038                 /* clear AUX FIFO */
1039                 it6505_set_bits(it6505, REG_AUX_CTRL,
1040                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1041                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1042                 it6505_set_bits(it6505, REG_AUX_CTRL,
1043                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO, 0x00);
1044         }
1045
1046         /* Leave AUX user mode */
1047         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, 0);
1048
1049         return ret;
1050 }
1051
1052 static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1053                                       enum aux_cmd_type cmd,
1054                                       unsigned int address, u8 *buffer,
1055                                       size_t size, enum aux_cmd_reply *reply)
1056 {
1057         int i, ret_size, ret = 0, request_size;
1058
1059         mutex_lock(&it6505->aux_lock);
1060         for (i = 0; i < size; i += 4) {
1061                 request_size = min((int)size - i, 4);
1062                 ret_size = it6505_aux_operation(it6505, cmd, address + i,
1063                                                 buffer + i, request_size,
1064                                                 reply);
1065                 if (ret_size < 0) {
1066                         ret = ret_size;
1067                         goto aux_op_err;
1068                 }
1069
1070                 ret += ret_size;
1071         }
1072
1073 aux_op_err:
1074         mutex_unlock(&it6505->aux_lock);
1075         return ret;
1076 }
1077
1078 static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1079                                    struct drm_dp_aux_msg *msg)
1080 {
1081         struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1082         u8 cmd;
1083         bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1084         int ret;
1085         enum aux_cmd_reply reply;
1086
1087         /* IT6505 doesn't support arbitrary I2C read / write. */
1088         if (is_i2c)
1089                 return -EINVAL;
1090
1091         switch (msg->request) {
1092         case DP_AUX_NATIVE_READ:
1093                 cmd = CMD_AUX_NATIVE_READ;
1094                 break;
1095         case DP_AUX_NATIVE_WRITE:
1096                 cmd = CMD_AUX_NATIVE_WRITE;
1097                 break;
1098         default:
1099                 return -EINVAL;
1100         }
1101
1102         ret = it6505_aux_do_transfer(it6505, cmd, msg->address, msg->buffer,
1103                                      msg->size, &reply);
1104         if (ret < 0)
1105                 return ret;
1106
1107         switch (reply) {
1108         case REPLY_ACK:
1109                 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1110                 break;
1111         case REPLY_NACK:
1112                 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1113                 break;
1114         case REPLY_DEFER:
1115                 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1116                 break;
1117         }
1118
1119         return ret;
1120 }
1121
1122 static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1123                                  size_t len)
1124 {
1125         struct it6505 *it6505 = data;
1126         struct device *dev = &it6505->client->dev;
1127         enum aux_cmd_reply reply;
1128         int offset, ret, aux_retry = 100;
1129
1130         it6505_aux_reset(it6505);
1131         DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1132
1133         for (offset = 0; offset < EDID_LENGTH;) {
1134                 ret = it6505_aux_do_transfer(it6505, CMD_AUX_I2C_EDID_READ,
1135                                              block * EDID_LENGTH + offset,
1136                                              buf + offset, 8, &reply);
1137
1138                 if (ret < 0 && ret != -EAGAIN)
1139                         return ret;
1140
1141                 switch (reply) {
1142                 case REPLY_ACK:
1143                         DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1144                                              buf + offset);
1145                         offset += 8;
1146                         aux_retry = 100;
1147                         break;
1148                 case REPLY_NACK:
1149                         return -EIO;
1150                 case REPLY_DEFER:
1151                         msleep(20);
1152                         if (!(--aux_retry))
1153                                 return -EIO;
1154                 }
1155         }
1156
1157         return 0;
1158 }
1159
1160 static void it6505_variable_config(struct it6505 *it6505)
1161 {
1162         it6505->link_rate_bw_code = HBR;
1163         it6505->lane_count = MAX_LANE_COUNT;
1164         it6505->link_state = LINK_IDLE;
1165         it6505->hdcp_desired = HDCP_DESIRED;
1166         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1167         it6505->audio.select = AUDIO_SELECT;
1168         it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1169         it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1170         it6505->audio.type = AUDIO_TYPE;
1171         it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1172         it6505->audio.i2s_justified = I2S_JUSTIFIED;
1173         it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1174         it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1175         it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1176         it6505->audio.word_length = AUDIO_WORD_LENGTH;
1177         memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1178         memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1179 }
1180
1181 static int it6505_send_video_infoframe(struct it6505 *it6505,
1182                                        struct hdmi_avi_infoframe *frame)
1183 {
1184         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1185         int err;
1186         struct device *dev = &it6505->client->dev;
1187
1188         err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
1189         if (err < 0) {
1190                 dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1191                 return err;
1192         }
1193
1194         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, 0x00);
1195         if (err)
1196                 return err;
1197
1198         err = regmap_bulk_write(it6505->regmap, REG_AVI_INFO_DB1,
1199                                 buffer + HDMI_INFOFRAME_HEADER_SIZE,
1200                                 frame->length);
1201         if (err)
1202                 return err;
1203
1204         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1205                               EN_AVI_PKT);
1206         if (err)
1207                 return err;
1208
1209         return 0;
1210 }
1211
1212 static void it6505_get_extcon_property(struct it6505 *it6505)
1213 {
1214         int err;
1215         union extcon_property_value property;
1216         struct device *dev = &it6505->client->dev;
1217
1218         if (it6505->extcon && !it6505->lane_swap_disabled) {
1219                 err = extcon_get_property(it6505->extcon, EXTCON_DISP_DP,
1220                                           EXTCON_PROP_USB_TYPEC_POLARITY,
1221                                           &property);
1222                 if (err) {
1223                         dev_err(dev, "get property fail!");
1224                         return;
1225                 }
1226                 it6505->lane_swap = property.intval;
1227         }
1228 }
1229
1230 static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1231                                         const struct drm_display_mode *mode)
1232 {
1233         int clock = mode->clock;
1234
1235         it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1236                         clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1237         it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1238                         PIXEL_CLK_INVERSE << 4);
1239 }
1240
1241 static void it6505_link_reset_step_train(struct it6505 *it6505)
1242 {
1243         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1244                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1245         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1246                           DP_TRAINING_PATTERN_DISABLE);
1247 }
1248
1249 static void it6505_init(struct it6505 *it6505)
1250 {
1251         it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1252         it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1253         it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1254         it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1255         it6505_write(it6505, REG_VID_BUS_CTRL1, 0x01);
1256         it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1257
1258         /* chip internal setting, don't modify */
1259         it6505_write(it6505, REG_HPD_IRQ_TIME, 0xF5);
1260         it6505_write(it6505, REG_AUX_DEBUG_MODE, 0x4D);
1261         it6505_write(it6505, REG_AUX_OPT2, 0x17);
1262         it6505_write(it6505, REG_HDCP_OPT, 0x60);
1263         it6505_write(it6505, REG_DATA_MUTE_CTRL,
1264                      EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1265         it6505_write(it6505, REG_TIME_STMP_CTRL,
1266                      EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1267         it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00);
1268         it6505_write(it6505, REG_BANK_SEL, 0x01);
1269         it6505_write(it6505, REG_DRV_0_DB_800_MV,
1270                      afe_setting_table[it6505->afe_setting][0]);
1271         it6505_write(it6505, REG_PRE_0_DB_800_MV,
1272                      afe_setting_table[it6505->afe_setting][1]);
1273         it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1274                      afe_setting_table[it6505->afe_setting][2]);
1275         it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1276         it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1277         it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1278         it6505_write(it6505, REG_BANK_SEL, 0x00);
1279 }
1280
1281 static void it6505_video_disable(struct it6505 *it6505)
1282 {
1283         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1284         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1285         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1286 }
1287
1288 static void it6505_video_reset(struct it6505 *it6505)
1289 {
1290         it6505_link_reset_step_train(it6505);
1291         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1292         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1293         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1294         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1295         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);
1296         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);
1297 }
1298
1299 static void it6505_update_video_parameter(struct it6505 *it6505,
1300                                           const struct drm_display_mode *mode)
1301 {
1302         it6505_clk_phase_adjustment(it6505, mode);
1303         it6505_video_disable(it6505);
1304 }
1305
1306 static bool it6505_audio_input(struct it6505 *it6505)
1307 {
1308         int reg05, regbe;
1309
1310         reg05 = it6505_read(it6505, REG_RESET_CTRL);
1311         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1312         usleep_range(3000, 4000);
1313         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1314         it6505_write(it6505, REG_RESET_CTRL, reg05);
1315
1316         return regbe != 0xFF;
1317 }
1318
1319 static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1320 {
1321         enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1322         u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1323
1324         /* Channel Status */
1325         it6505_write(it6505, REG_IEC958_STS0, it6505->audio.type << 1);
1326         it6505_write(it6505, REG_IEC958_STS1, 0x00);
1327         it6505_write(it6505, REG_IEC958_STS2, 0x00);
1328         it6505_write(it6505, REG_IEC958_STS3, sample_rate);
1329         it6505_write(it6505, REG_IEC958_STS4, (~sample_rate << 4) |
1330                      audio_word_length_map[it6505->audio.word_length]);
1331 }
1332
1333 static void it6505_setup_audio_format(struct it6505 *it6505)
1334 {
1335         /* I2S MODE */
1336         it6505_write(it6505, REG_AUDIO_FMT,
1337                      (it6505->audio.word_length << 5) |
1338                      (it6505->audio.i2s_data_sequence << 4) |
1339                      (it6505->audio.i2s_ws_channel << 3) |
1340                      (it6505->audio.i2s_data_delay << 2) |
1341                      (it6505->audio.i2s_justified << 1) |
1342                      it6505->audio.i2s_input_format);
1343         if (it6505->audio.select == SPDIF) {
1344                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0x00);
1345                 /* 0x30 = 128*FS */
1346                 it6505_set_bits(it6505, REG_AUX_OPT, 0xF0, 0x30);
1347         } else {
1348                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0xE4);
1349         }
1350
1351         it6505_write(it6505, REG_AUDIO_CTRL0, 0x20);
1352         it6505_write(it6505, REG_AUDIO_CTRL1, 0x00);
1353 }
1354
1355 static void it6505_enable_audio_source(struct it6505 *it6505)
1356 {
1357         unsigned int audio_source_count;
1358
1359         audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1360                                  - 1;
1361
1362         audio_source_count |= it6505->audio.select << 4;
1363
1364         it6505_write(it6505, REG_AUDIO_SRC_CTRL, audio_source_count);
1365 }
1366
1367 static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1368 {
1369         struct device *dev = &it6505->client->dev;
1370         u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1371
1372         DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1373                              audio_info_ca[it6505->audio.channel_count - 1]);
1374
1375         it6505_write(it6505, REG_AUD_INFOFRAM_DB1, it6505->audio.channel_count
1376                      - 1);
1377         it6505_write(it6505, REG_AUD_INFOFRAM_DB2, 0x00);
1378         it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1379                      audio_info_ca[it6505->audio.channel_count - 1]);
1380         it6505_write(it6505, REG_AUD_INFOFRAM_DB4, 0x00);
1381         it6505_write(it6505, REG_AUD_INFOFRAM_SUM, 0x00);
1382
1383         /* Enable Audio InfoFrame */
1384         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1385                         EN_AUD_CTRL_PKT);
1386 }
1387
1388 static void it6505_disable_audio(struct it6505 *it6505)
1389 {
1390         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1391         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, 0x00);
1392         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, 0x00);
1393         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1394 }
1395
1396 static void it6505_enable_audio(struct it6505 *it6505)
1397 {
1398         struct device *dev = &it6505->client->dev;
1399         int regbe;
1400
1401         DRM_DEV_DEBUG_DRIVER(dev, "start");
1402         it6505_disable_audio(it6505);
1403
1404         it6505_setup_audio_channel_status(it6505);
1405         it6505_setup_audio_format(it6505);
1406         it6505_enable_audio_source(it6505);
1407         it6505_enable_audio_infoframe(it6505);
1408
1409         it6505_write(it6505, REG_AUDIO_N_0_7, 0x00);
1410         it6505_write(it6505, REG_AUDIO_N_8_15, 0x80);
1411         it6505_write(it6505, REG_AUDIO_N_16_23, 0x00);
1412
1413         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1414                         AUDIO_FIFO_RESET);
1415         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, 0x00);
1416         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1417         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1418         DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1419                              regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1420         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, 0x00);
1421 }
1422
1423 static bool it6505_use_step_train_check(struct it6505 *it6505)
1424 {
1425         if (it6505->link.revision >= 0x12)
1426                 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1427
1428         return true;
1429 }
1430
1431 static void it6505_parse_link_capabilities(struct it6505 *it6505)
1432 {
1433         struct device *dev = &it6505->client->dev;
1434         struct it6505_drm_dp_link *link = &it6505->link;
1435         int bcaps;
1436
1437         if (it6505->dpcd[0] == 0) {
1438                 dev_err(dev, "DPCD is not initialized");
1439                 return;
1440         }
1441
1442         memset(link, 0, sizeof(*link));
1443
1444         link->revision = it6505->dpcd[0];
1445         link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]);
1446         link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;
1447
1448         if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)
1449                 link->capabilities = DP_ENHANCED_FRAME_CAP;
1450
1451         DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1452                              link->revision >> 4, link->revision & 0x0F);
1453
1454         DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1455                              link->rate / 100000, link->rate / 1000 % 100);
1456
1457         it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link->rate);
1458         DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1459                              it6505->link_rate_bw_code);
1460         it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1461                                           MAX_LINK_RATE);
1462
1463         it6505->lane_count = link->num_lanes;
1464         DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1465                              it6505->lane_count);
1466         it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT);
1467
1468         it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
1469         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1470                              it6505->branch_device ? "" : "Not ");
1471
1472         it6505->enable_enhanced_frame = link->capabilities;
1473         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1474                              it6505->enable_enhanced_frame ? "" : "Not ");
1475
1476         it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1477                                 DP_MAX_DOWNSPREAD_0_5);
1478         DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1479                              it6505->enable_ssc ? "0.5" : "0",
1480                              it6505->enable_ssc ? "" : "Not ");
1481
1482         it6505->step_train = it6505_use_step_train_check(it6505);
1483         if (it6505->step_train)
1484                 DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1485
1486         bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1487         DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1488         if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1489                 it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1490                 DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1491                                      it6505->is_repeater ? "repeater" :
1492                                      "receiver");
1493         } else {
1494                 DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1495                 it6505->hdcp_desired = false;
1496         }
1497         DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1498                              it6505->hdcp_desired ? "desired" : "undesired");
1499 }
1500
1501 static void it6505_setup_ssc(struct it6505 *it6505)
1502 {
1503         it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1504                         it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1505         if (it6505->enable_ssc) {
1506                 it6505_write(it6505, REG_BANK_SEL, 0x01);
1507                 it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1508                 it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1509                 it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1510                 it6505_write(it6505, REG_BANK_SEL, 0x00);
1511                 it6505_write(it6505, REG_SP_CTRL0, 0x07);
1512                 it6505_write(it6505, REG_IP_CTRL1, 0x29);
1513                 it6505_write(it6505, REG_IP_CTRL2, 0x03);
1514                 /* Stamp Interrupt Step */
1515                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1516                                 0x10);
1517                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1518                                   DP_SPREAD_AMP_0_5);
1519         } else {
1520                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, 0x00);
1521                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1522                                 0x00);
1523         }
1524 }
1525
1526 static inline void it6505_link_rate_setup(struct it6505 *it6505)
1527 {
1528         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1529                         (it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1530         it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1531                         (it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1532 }
1533
1534 static void it6505_lane_count_setup(struct it6505 *it6505)
1535 {
1536         it6505_get_extcon_property(it6505);
1537         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1538                         it6505->lane_swap ? LANE_SWAP : 0x00);
1539         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1540                         (it6505->lane_count - 1) << 1);
1541 }
1542
1543 static void it6505_link_training_setup(struct it6505 *it6505)
1544 {
1545         struct device *dev = &it6505->client->dev;
1546
1547         if (it6505->enable_enhanced_frame)
1548                 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1549                                 ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1550
1551         it6505_link_rate_setup(it6505);
1552         it6505_lane_count_setup(it6505);
1553         it6505_setup_ssc(it6505);
1554         DRM_DEV_DEBUG_DRIVER(dev,
1555                              "%s, %d lanes, %sable ssc, %sable enhanced frame",
1556                              it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1557                              it6505->lane_count,
1558                              it6505->enable_ssc ? "en" : "dis",
1559                              it6505->enable_enhanced_frame ? "en" : "dis");
1560 }
1561
1562 static bool it6505_link_start_auto_train(struct it6505 *it6505)
1563 {
1564         int timeout = 500, link_training_state;
1565         bool state = false;
1566
1567         mutex_lock(&it6505->aux_lock);
1568         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1569                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1570         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1571         it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1572
1573         while (timeout > 0) {
1574                 usleep_range(1000, 2000);
1575                 link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1576
1577                 if (link_training_state > 0 &&
1578                     (link_training_state & LINK_STATE_NORP)) {
1579                         state = true;
1580                         goto unlock;
1581                 }
1582
1583                 timeout--;
1584         }
1585 unlock:
1586         mutex_unlock(&it6505->aux_lock);
1587
1588         return state;
1589 }
1590
1591 static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1592 {
1593         u8 values[2];
1594         int err;
1595         struct drm_dp_aux *aux = &it6505->aux;
1596
1597         values[0] = it6505->link_rate_bw_code;
1598         values[1] = it6505->lane_count;
1599
1600         if (it6505->enable_enhanced_frame)
1601                 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1602
1603         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
1604         if (err < 0)
1605                 return err;
1606
1607         return 0;
1608 }
1609
1610 static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1611 {
1612         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1613 }
1614
1615 static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1616 {
1617         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1618 }
1619
1620 static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1621                                                    u8 lane_count)
1622 {
1623         u8 i;
1624
1625         for (i = 0; i < lane_count; i++) {
1626                 if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1627                         return true;
1628         }
1629
1630         return false;
1631 }
1632
1633 static bool
1634 step_train_lane_voltage_para_set(struct it6505 *it6505,
1635                                  struct it6505_step_train_para
1636                                  *lane_voltage_pre_emphasis,
1637                                  u8 *lane_voltage_pre_emphasis_set)
1638 {
1639         u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1640         u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1641         u8 i;
1642
1643         for (i = 0; i < it6505->lane_count; i++) {
1644                 voltage_swing[i] &= 0x03;
1645                 lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1646                 if (it6505_check_voltage_swing_max(voltage_swing[i]))
1647                         lane_voltage_pre_emphasis_set[i] |=
1648                                 DP_TRAIN_MAX_SWING_REACHED;
1649
1650                 pre_emphasis[i] &= 0x03;
1651                 lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1652                         << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1653                 if (it6505_check_pre_emphasis_max(pre_emphasis[i]))
1654                         lane_voltage_pre_emphasis_set[i] |=
1655                                 DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1656                 it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1657                                   lane_voltage_pre_emphasis_set[i]);
1658
1659                 if (lane_voltage_pre_emphasis_set[i] !=
1660                     it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1661                         return false;
1662         }
1663
1664         return true;
1665 }
1666
1667 static bool
1668 it6505_step_cr_train(struct it6505 *it6505,
1669                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1670 {
1671         u8 loop_count = 0, i = 0, j;
1672         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1673         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1674         int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1675         const struct drm_dp_aux *aux = &it6505->aux;
1676
1677         it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1678                           it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1679         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1680                           DP_TRAINING_PATTERN_1);
1681
1682         while (loop_count < 5 && i < 10) {
1683                 i++;
1684                 if (!step_train_lane_voltage_para_set(it6505,
1685                                                       lane_voltage_pre_emphasis,
1686                                                       lane_level_config))
1687                         continue;
1688                 drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);
1689                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1690
1691                 if (drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) {
1692                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1693                                         FORCE_CR_DONE);
1694                         return true;
1695                 }
1696                 DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "cr not done");
1697
1698                 if (it6505_check_max_voltage_swing_reached(lane_level_config,
1699                                                            it6505->lane_count))
1700                         goto cr_train_fail;
1701
1702                 for (j = 0; j < it6505->lane_count; j++) {
1703                         lane_voltage_pre_emphasis->voltage_swing[j] =
1704                                 drm_dp_get_adjust_request_voltage(link_status,
1705                                                                   j) >>
1706                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1707                         lane_voltage_pre_emphasis->pre_emphasis[j] =
1708                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1709                                                                j) >>
1710                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1711                         if (voltage_swing_adjust ==
1712                              lane_voltage_pre_emphasis->voltage_swing[j] &&
1713                             pre_emphasis_adjust ==
1714                              lane_voltage_pre_emphasis->pre_emphasis[j]) {
1715                                 loop_count++;
1716                                 continue;
1717                         }
1718
1719                         voltage_swing_adjust =
1720                                 lane_voltage_pre_emphasis->voltage_swing[j];
1721                         pre_emphasis_adjust =
1722                                 lane_voltage_pre_emphasis->pre_emphasis[j];
1723                         loop_count = 0;
1724
1725                         if (voltage_swing_adjust + pre_emphasis_adjust >
1726                             MAX_EQ_LEVEL)
1727                                 lane_voltage_pre_emphasis->voltage_swing[j] =
1728                                         MAX_EQ_LEVEL -
1729                                         lane_voltage_pre_emphasis
1730                                                 ->pre_emphasis[j];
1731                 }
1732         }
1733
1734 cr_train_fail:
1735         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1736                           DP_TRAINING_PATTERN_DISABLE);
1737
1738         return false;
1739 }
1740
1741 static bool
1742 it6505_step_eq_train(struct it6505 *it6505,
1743                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1744 {
1745         u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1746         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1747         const struct drm_dp_aux *aux = &it6505->aux;
1748
1749         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1750                           DP_TRAINING_PATTERN_2);
1751
1752         while (loop_count < 6) {
1753                 loop_count++;
1754
1755                 if (!step_train_lane_voltage_para_set(it6505,
1756                                                       lane_voltage_pre_emphasis,
1757                                                       lane_level_config))
1758                         continue;
1759
1760                 drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);
1761                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1762
1763                 if (!drm_dp_clock_recovery_ok(link_status, it6505->lane_count))
1764                         goto eq_train_fail;
1765
1766                 if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
1767                         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1768                                           DP_TRAINING_PATTERN_DISABLE);
1769                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1770                                         FORCE_EQ_DONE);
1771                         return true;
1772                 }
1773                 DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "eq not done");
1774
1775                 for (i = 0; i < it6505->lane_count; i++) {
1776                         lane_voltage_pre_emphasis->voltage_swing[i] =
1777                                 drm_dp_get_adjust_request_voltage(link_status,
1778                                                                   i) >>
1779                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1780                         lane_voltage_pre_emphasis->pre_emphasis[i] =
1781                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1782                                                                i) >>
1783                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1784
1785                         if (lane_voltage_pre_emphasis->voltage_swing[i] +
1786                                     lane_voltage_pre_emphasis->pre_emphasis[i] >
1787                             MAX_EQ_LEVEL)
1788                                 lane_voltage_pre_emphasis->voltage_swing[i] =
1789                                         0x03 - lane_voltage_pre_emphasis
1790                                                        ->pre_emphasis[i];
1791                 }
1792         }
1793
1794 eq_train_fail:
1795         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1796                           DP_TRAINING_PATTERN_DISABLE);
1797         return false;
1798 }
1799
1800 static bool it6505_link_start_step_train(struct it6505 *it6505)
1801 {
1802         int err;
1803         struct it6505_step_train_para lane_voltage_pre_emphasis = {
1804                 .voltage_swing = { 0 },
1805                 .pre_emphasis = { 0 },
1806         };
1807
1808         DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "start");
1809         err = it6505_drm_dp_link_configure(it6505);
1810
1811         if (err < 0)
1812                 return false;
1813         if (!it6505_step_cr_train(it6505, &lane_voltage_pre_emphasis))
1814                 return false;
1815         if (!it6505_step_eq_train(it6505, &lane_voltage_pre_emphasis))
1816                 return false;
1817         return true;
1818 }
1819
1820 static bool it6505_get_video_status(struct it6505 *it6505)
1821 {
1822         int reg_0d;
1823
1824         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
1825
1826         if (reg_0d < 0)
1827                 return false;
1828
1829         return reg_0d & VIDEO_STB;
1830 }
1831
1832 static void it6505_reset_hdcp(struct it6505 *it6505)
1833 {
1834         it6505->hdcp_status = HDCP_AUTH_IDLE;
1835         /* Disable CP_Desired */
1836         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1837         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
1838 }
1839
1840 static void it6505_start_hdcp(struct it6505 *it6505)
1841 {
1842         struct device *dev = &it6505->client->dev;
1843
1844         DRM_DEV_DEBUG_DRIVER(dev, "start");
1845         it6505_reset_hdcp(it6505);
1846         queue_delayed_work(system_wq, &it6505->hdcp_work,
1847                            msecs_to_jiffies(2400));
1848 }
1849
1850 static void it6505_stop_hdcp(struct it6505 *it6505)
1851 {
1852         it6505_reset_hdcp(it6505);
1853         cancel_delayed_work(&it6505->hdcp_work);
1854 }
1855
1856 static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
1857 {
1858         int i, ones = 0;
1859
1860         /* KSV has 20 1's and 20 0's */
1861         for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
1862                 ones += hweight8(ksv[i]);
1863         if (ones != 20)
1864                 return false;
1865         return true;
1866 }
1867
1868 static void it6505_hdcp_part1_auth(struct it6505 *it6505)
1869 {
1870         struct device *dev = &it6505->client->dev;
1871         u8 hdcp_bcaps;
1872
1873         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, 0x00);
1874         /* Disable CP_Desired */
1875         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1876
1877         usleep_range(1000, 1500);
1878         hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1879         DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
1880                              hdcp_bcaps);
1881
1882         if (!hdcp_bcaps)
1883                 return;
1884
1885         /* clear the repeater List Chk Done and fail bit */
1886         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
1887                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
1888                         0x00);
1889
1890         /* Enable An Generator */
1891         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
1892         /* delay1ms(10);*/
1893         usleep_range(10000, 15000);
1894         /* Stop An Generator */
1895         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, 0x00);
1896
1897         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
1898
1899         it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
1900                         HDCP_TRIGGER_START);
1901
1902         it6505->hdcp_status = HDCP_AUTH_GOING;
1903 }
1904
1905 static int it6505_sha1_digest(struct it6505 *it6505, u8 *sha1_input,
1906                               unsigned int size, u8 *output_av)
1907 {
1908         struct shash_desc *desc;
1909         struct crypto_shash *tfm;
1910         int err;
1911         struct device *dev = &it6505->client->dev;
1912
1913         tfm = crypto_alloc_shash("sha1", 0, 0);
1914         if (IS_ERR(tfm)) {
1915                 dev_err(dev, "crypto_alloc_shash sha1 failed");
1916                 return PTR_ERR(tfm);
1917         }
1918         desc = kzalloc(sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
1919         if (!desc) {
1920                 crypto_free_shash(tfm);
1921                 return -ENOMEM;
1922         }
1923
1924         desc->tfm = tfm;
1925         err = crypto_shash_digest(desc, sha1_input, size, output_av);
1926         if (err)
1927                 dev_err(dev, "crypto_shash_digest sha1 failed");
1928
1929         crypto_free_shash(tfm);
1930         kfree(desc);
1931         return err;
1932 }
1933
1934 static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
1935 {
1936         struct device *dev = &it6505->client->dev;
1937         u8 binfo[2];
1938         int down_stream_count, i, err, msg_count = 0;
1939
1940         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, binfo,
1941                               ARRAY_SIZE(binfo));
1942
1943         if (err < 0) {
1944                 dev_err(dev, "Read binfo value Fail");
1945                 return err;
1946         }
1947
1948         down_stream_count = binfo[0] & 0x7F;
1949         DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
1950                              binfo);
1951
1952         if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
1953                 dev_err(dev, "HDCP max cascade device exceed");
1954                 return 0;
1955         }
1956
1957         if (!down_stream_count ||
1958             down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
1959                 dev_err(dev, "HDCP down stream count Error %d",
1960                         down_stream_count);
1961                 return 0;
1962         }
1963
1964         for (i = 0; i < down_stream_count; i++) {
1965                 err = it6505_get_dpcd(it6505, DP_AUX_HDCP_KSV_FIFO +
1966                                       (i % 3) * DRM_HDCP_KSV_LEN,
1967                                       sha1_input + msg_count,
1968                                       DRM_HDCP_KSV_LEN);
1969
1970                 if (err < 0)
1971                         return err;
1972
1973                 msg_count += 5;
1974         }
1975
1976         it6505->hdcp_down_stream_count = down_stream_count;
1977         sha1_input[msg_count++] = binfo[0];
1978         sha1_input[msg_count++] = binfo[1];
1979
1980         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
1981                         HDCP_EN_M0_READ);
1982
1983         err = regmap_bulk_read(it6505->regmap, REG_M0_0_7,
1984                                sha1_input + msg_count, 8);
1985
1986         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, 0x00);
1987
1988         if (err < 0) {
1989                 dev_err(dev, " Warning, Read M value Fail");
1990                 return err;
1991         }
1992
1993         msg_count += 8;
1994
1995         return msg_count;
1996 }
1997
1998 static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
1999 {
2000         struct device *dev = &it6505->client->dev;
2001         u8 av[5][4], bv[5][4];
2002         int i, err;
2003
2004         i = it6505_setup_sha1_input(it6505, it6505->sha1_input);
2005         if (i <= 0) {
2006                 dev_err(dev, "SHA-1 Input length error %d", i);
2007                 return false;
2008         }
2009
2010         it6505_sha1_digest(it6505, it6505->sha1_input, i, (u8 *)av);
2011
2012         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), (u8 *)bv,
2013                               sizeof(bv));
2014
2015         if (err < 0) {
2016                 dev_err(dev, "Read V' value Fail");
2017                 return false;
2018         }
2019
2020         for (i = 0; i < 5; i++)
2021                 if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2022                     bv[i][1] != av[i][2] || bv[i][0] != av[i][3])
2023                         return false;
2024
2025         DRM_DEV_DEBUG_DRIVER(dev, "V' all match!!");
2026         return true;
2027 }
2028
2029 static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2030 {
2031         struct it6505 *it6505 = container_of(work, struct it6505,
2032                                              hdcp_wait_ksv_list);
2033         struct device *dev = &it6505->client->dev;
2034         unsigned int timeout = 5000;
2035         u8 bstatus = 0;
2036         bool ksv_list_check;
2037
2038         timeout /= 20;
2039         while (timeout > 0) {
2040                 if (!it6505_get_sink_hpd_status(it6505))
2041                         return;
2042
2043                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2044
2045                 if (bstatus & DP_BSTATUS_READY)
2046                         break;
2047
2048                 msleep(20);
2049                 timeout--;
2050         }
2051
2052         if (timeout == 0) {
2053                 DRM_DEV_DEBUG_DRIVER(dev, "timeout and ksv list wait failed");
2054                 goto timeout;
2055         }
2056
2057         ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2058         DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2059                              ksv_list_check ? "pass" : "fail");
2060         if (ksv_list_check) {
2061                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2062                                 HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2063                 return;
2064         }
2065 timeout:
2066         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2067                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
2068                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL);
2069 }
2070
2071 static void it6505_hdcp_work(struct work_struct *work)
2072 {
2073         struct it6505 *it6505 = container_of(work, struct it6505,
2074                                              hdcp_work.work);
2075         struct device *dev = &it6505->client->dev;
2076         int ret;
2077         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2078
2079         DRM_DEV_DEBUG_DRIVER(dev, "start");
2080
2081         if (!it6505_get_sink_hpd_status(it6505))
2082                 return;
2083
2084         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2085         DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2086                              (int)sizeof(link_status), link_status);
2087
2088         if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
2089             !it6505_get_video_status(it6505)) {
2090                 DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2091                 return;
2092         }
2093
2094         ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, it6505->bksvs,
2095                               ARRAY_SIZE(it6505->bksvs));
2096         if (ret < 0) {
2097                 dev_err(dev, "fail to get bksv  ret: %d", ret);
2098                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2099                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2100         }
2101
2102         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2103                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2104
2105         if (!it6505_hdcp_is_ksv_valid(it6505->bksvs)) {
2106                 dev_err(dev, "Display Port bksv not valid");
2107                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2108                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2109         }
2110
2111         it6505_hdcp_part1_auth(it6505);
2112 }
2113
2114 static void it6505_show_hdcp_info(struct it6505 *it6505)
2115 {
2116         struct device *dev = &it6505->client->dev;
2117         int i;
2118         u8 *sha1 = it6505->sha1_input;
2119
2120         DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2121                              it6505->hdcp_status, it6505->is_repeater);
2122         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2123                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2124
2125         if (it6505->is_repeater) {
2126                 DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2127                                      it6505->hdcp_down_stream_count);
2128                 DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2129                                      (int)ARRAY_SIZE(it6505->sha1_input),
2130                                      it6505->sha1_input);
2131                 for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2132                         DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2133                                              DRM_HDCP_KSV_LEN, sha1);
2134                         sha1 += DRM_HDCP_KSV_LEN;
2135                 }
2136                 DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2137                                      sha1, sha1 + 2);
2138         }
2139 }
2140
2141 static void it6505_stop_link_train(struct it6505 *it6505)
2142 {
2143         it6505->link_state = LINK_IDLE;
2144         cancel_work_sync(&it6505->link_works);
2145         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2146 }
2147
2148 static void it6505_link_train_ok(struct it6505 *it6505)
2149 {
2150         struct device *dev = &it6505->client->dev;
2151
2152         it6505->link_state = LINK_OK;
2153         /* disalbe mute enable avi info frame */
2154         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, 0x00);
2155         it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2156                         EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2157
2158         if (it6505_audio_input(it6505)) {
2159                 DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2160                 it6505_enable_audio(it6505);
2161         }
2162
2163         if (it6505->hdcp_desired)
2164                 it6505_start_hdcp(it6505);
2165 }
2166
2167 static void it6505_link_step_train_process(struct it6505 *it6505)
2168 {
2169         struct device *dev = &it6505->client->dev;
2170         int ret, i, step_retry = 3;
2171
2172         DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2173
2174         if (it6505->sink_count == 0) {
2175                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2176                                      it6505->sink_count);
2177                 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2178                                 FORCE_EQ_DONE);
2179                 return;
2180         }
2181
2182         if (!it6505->step_train) {
2183                 DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2184                 return;
2185         }
2186
2187         /* step training start here */
2188         for (i = 0; i < step_retry; i++) {
2189                 it6505_link_reset_step_train(it6505);
2190                 ret = it6505_link_start_step_train(it6505);
2191                 DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2192                                      ret ? "pass" : "failed", i + 1);
2193                 if (ret) {
2194                         it6505_link_train_ok(it6505);
2195                         return;
2196                 }
2197         }
2198
2199         DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2200         it6505->link_state = LINK_IDLE;
2201         it6505_video_reset(it6505);
2202 }
2203
2204 static void it6505_link_training_work(struct work_struct *work)
2205 {
2206         struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2207         struct device *dev = &it6505->client->dev;
2208         int ret;
2209
2210         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2211                              it6505->sink_count);
2212
2213         if (!it6505_get_sink_hpd_status(it6505))
2214                 return;
2215
2216         it6505_link_training_setup(it6505);
2217         it6505_reset_hdcp(it6505);
2218         it6505_aux_reset(it6505);
2219
2220         if (it6505->auto_train_retry < 1) {
2221                 it6505_link_step_train_process(it6505);
2222                 return;
2223         }
2224
2225         ret = it6505_link_start_auto_train(it6505);
2226         DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2227                              ret ? "pass" : "failed", it6505->auto_train_retry);
2228         it6505->auto_train_retry--;
2229
2230         if (ret) {
2231                 it6505_link_train_ok(it6505);
2232                 return;
2233         }
2234
2235         it6505_dump(it6505);
2236 }
2237
2238 static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2239 {
2240         enum drm_connector_status status = it6505->connector_status;
2241
2242         if (it6505->plugged_cb && it6505->codec_dev)
2243                 it6505->plugged_cb(it6505->codec_dev,
2244                                    status == connector_status_connected);
2245 }
2246
2247 static int it6505_process_hpd_irq(struct it6505 *it6505)
2248 {
2249         struct device *dev = &it6505->client->dev;
2250         int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2251         u8 link_status[DP_LINK_STATUS_SIZE];
2252
2253         if (!it6505_get_sink_hpd_status(it6505)) {
2254                 DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2255                 it6505->sink_count = 0;
2256                 return 0;
2257         }
2258
2259         ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2260         if (ret < 0)
2261                 return ret;
2262
2263         dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2264         DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2265                              dpcd_sink_count, it6505->sink_count);
2266
2267         if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2268                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2269                 it6505->sink_count = dpcd_sink_count;
2270                 it6505_reset_logic(it6505);
2271                 it6505_int_mask_enable(it6505);
2272                 it6505_init(it6505);
2273                 return 0;
2274         }
2275
2276         dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2277         if (dp_irq_vector < 0)
2278                 return dp_irq_vector;
2279
2280         DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2281
2282         if (dp_irq_vector & DP_CP_IRQ) {
2283                 it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2284                                 HDCP_TRIGGER_CPIRQ);
2285
2286                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2287                 if (bstatus < 0)
2288                         return bstatus;
2289
2290                 DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2291         }
2292
2293         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2294         if (ret < 0) {
2295                 dev_err(dev, "Fail to read link status ret: %d", ret);
2296                 return ret;
2297         }
2298
2299         DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2300                              (int)ARRAY_SIZE(link_status), link_status);
2301
2302         if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
2303                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2304                 it6505_video_reset(it6505);
2305         }
2306
2307         return 0;
2308 }
2309
2310 static void it6505_irq_hpd(struct it6505 *it6505)
2311 {
2312         struct device *dev = &it6505->client->dev;
2313         int dp_sink_count;
2314
2315         it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2316         DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2317                              it6505->hpd_state ? "high" : "low");
2318
2319         if (it6505->hpd_state) {
2320                 wait_for_completion_timeout(&it6505->extcon_completion,
2321                                             msecs_to_jiffies(1000));
2322                 it6505_aux_on(it6505);
2323                 if (it6505->dpcd[0] == 0) {
2324                         it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
2325                                         ARRAY_SIZE(it6505->dpcd));
2326                         it6505_variable_config(it6505);
2327                         it6505_parse_link_capabilities(it6505);
2328                 }
2329                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2330
2331                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2332                                              DP_SET_POWER_D0);
2333                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2334                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2335
2336                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2337                                      it6505->sink_count);
2338
2339                 it6505_lane_termination_on(it6505);
2340                 it6505_lane_power_on(it6505);
2341
2342                 /*
2343                  * for some dongle which issue HPD_irq
2344                  * when sink count change from  0->1
2345                  * it6505 not able to receive HPD_IRQ
2346                  * if HW never go into trainig done
2347                  */
2348
2349                 if (it6505->branch_device && it6505->sink_count == 0)
2350                         schedule_work(&it6505->link_works);
2351
2352                 if (!it6505_get_video_status(it6505))
2353                         it6505_video_reset(it6505);
2354         } else {
2355                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2356
2357                 if (it6505->hdcp_desired)
2358                         it6505_stop_hdcp(it6505);
2359
2360                 it6505_video_disable(it6505);
2361                 it6505_disable_audio(it6505);
2362                 it6505_stop_link_train(it6505);
2363                 it6505_lane_off(it6505);
2364                 it6505_link_reset_step_train(it6505);
2365         }
2366
2367         if (it6505->bridge.dev)
2368                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2369 }
2370
2371 static void it6505_irq_hpd_irq(struct it6505 *it6505)
2372 {
2373         struct device *dev = &it6505->client->dev;
2374
2375         DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2376
2377         if (it6505_process_hpd_irq(it6505) < 0)
2378                 DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2379 }
2380
2381 static void it6505_irq_scdt(struct it6505 *it6505)
2382 {
2383         struct device *dev = &it6505->client->dev;
2384         bool data;
2385
2386         data = it6505_get_video_status(it6505);
2387         DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2388                              data ? "stable" : "unstable");
2389         it6505_calc_video_info(it6505);
2390         it6505_link_reset_step_train(it6505);
2391
2392         if (data)
2393                 schedule_work(&it6505->link_works);
2394 }
2395
2396 static void it6505_irq_hdcp_done(struct it6505 *it6505)
2397 {
2398         struct device *dev = &it6505->client->dev;
2399
2400         DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2401         it6505->hdcp_status = HDCP_AUTH_DONE;
2402         it6505_show_hdcp_info(it6505);
2403 }
2404
2405 static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2406 {
2407         struct device *dev = &it6505->client->dev;
2408
2409         DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2410         it6505->hdcp_status = HDCP_AUTH_IDLE;
2411         it6505_show_hdcp_info(it6505);
2412         it6505_start_hdcp(it6505);
2413 }
2414
2415 static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2416 {
2417         struct device *dev = &it6505->client->dev;
2418
2419         DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2420 }
2421
2422 static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2423 {
2424         struct device *dev = &it6505->client->dev;
2425
2426         DRM_DEV_DEBUG_DRIVER(dev, "HDCP event Interrupt");
2427         schedule_work(&it6505->hdcp_wait_ksv_list);
2428 }
2429
2430 static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2431 {
2432         struct device *dev = &it6505->client->dev;
2433
2434         DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2435
2436         if (it6505_audio_input(it6505))
2437                 it6505_enable_audio(it6505);
2438 }
2439
2440 static void it6505_irq_link_train_fail(struct it6505 *it6505)
2441 {
2442         struct device *dev = &it6505->client->dev;
2443
2444         DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2445         schedule_work(&it6505->link_works);
2446 }
2447
2448 static void it6505_irq_video_fifo_error(struct it6505 *it6505)
2449 {
2450         struct device *dev = &it6505->client->dev;
2451
2452         DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt");
2453         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2454         flush_work(&it6505->link_works);
2455         it6505_stop_hdcp(it6505);
2456         it6505_video_reset(it6505);
2457 }
2458
2459 static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505)
2460 {
2461         struct device *dev = &it6505->client->dev;
2462
2463         DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt");
2464         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2465         flush_work(&it6505->link_works);
2466         it6505_stop_hdcp(it6505);
2467         it6505_video_reset(it6505);
2468 }
2469
2470 static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2471 {
2472         return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2473 }
2474
2475 static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2476 {
2477         struct it6505 *it6505 = data;
2478         struct device *dev = &it6505->client->dev;
2479         static const struct {
2480                 int bit;
2481                 void (*handler)(struct it6505 *it6505);
2482         } irq_vec[] = {
2483                 { BIT_INT_HPD, it6505_irq_hpd },
2484                 { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2485                 { BIT_INT_SCDT, it6505_irq_scdt },
2486                 { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2487                 { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2488                 { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2489                 { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2490                 { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2491                 { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2492                 { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error },
2493                 { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow },
2494         };
2495         int int_status[3], i;
2496
2497         mutex_lock(&it6505->irq_lock);
2498
2499         if (it6505->enable_drv_hold || !it6505->powered)
2500                 goto unlock;
2501
2502         int_status[0] = it6505_read(it6505, INT_STATUS_01);
2503         int_status[1] = it6505_read(it6505, INT_STATUS_02);
2504         int_status[2] = it6505_read(it6505, INT_STATUS_03);
2505
2506         it6505_write(it6505, INT_STATUS_01, int_status[0]);
2507         it6505_write(it6505, INT_STATUS_02, int_status[1]);
2508         it6505_write(it6505, INT_STATUS_03, int_status[2]);
2509
2510         DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2511         DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2512         DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2513         it6505_debug_print(it6505, REG_SYSTEM_STS, "");
2514
2515         if (it6505_test_bit(irq_vec[0].bit, (unsigned int *)int_status))
2516                 irq_vec[0].handler(it6505);
2517
2518         if (!it6505->hpd_state)
2519                 goto unlock;
2520
2521         for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2522                 if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))
2523                         irq_vec[i].handler(it6505);
2524         }
2525
2526 unlock:
2527         mutex_unlock(&it6505->irq_lock);
2528
2529         return IRQ_HANDLED;
2530 }
2531
2532 static int it6505_poweron(struct it6505 *it6505)
2533 {
2534         struct device *dev = &it6505->client->dev;
2535         struct it6505_platform_data *pdata = &it6505->pdata;
2536         int err;
2537
2538         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2539
2540         if (it6505->powered) {
2541                 DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2542                 return 0;
2543         }
2544
2545         if (pdata->pwr18) {
2546                 err = regulator_enable(pdata->pwr18);
2547                 if (err) {
2548                         DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2549                                              err);
2550                         return err;
2551                 }
2552         }
2553
2554         if (pdata->ovdd) {
2555                 /* time interval between IVDD and OVDD at least be 1ms */
2556                 usleep_range(1000, 2000);
2557                 err = regulator_enable(pdata->ovdd);
2558                 if (err) {
2559                         regulator_disable(pdata->pwr18);
2560                         return err;
2561                 }
2562         }
2563         /* time interval between OVDD and SYSRSTN at least be 10ms */
2564         if (pdata->gpiod_reset) {
2565                 usleep_range(10000, 20000);
2566                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2567                 usleep_range(1000, 2000);
2568                 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2569                 usleep_range(10000, 20000);
2570         }
2571
2572         it6505->powered = true;
2573         it6505_reset_logic(it6505);
2574         it6505_int_mask_enable(it6505);
2575         it6505_init(it6505);
2576         it6505_lane_off(it6505);
2577
2578         return 0;
2579 }
2580
2581 static int it6505_poweroff(struct it6505 *it6505)
2582 {
2583         struct device *dev = &it6505->client->dev;
2584         struct it6505_platform_data *pdata = &it6505->pdata;
2585         int err;
2586
2587         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2588
2589         if (!it6505->powered) {
2590                 DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2591                 return 0;
2592         }
2593
2594         if (pdata->gpiod_reset)
2595                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2596
2597         if (pdata->pwr18) {
2598                 err = regulator_disable(pdata->pwr18);
2599                 if (err)
2600                         return err;
2601         }
2602
2603         if (pdata->ovdd) {
2604                 err = regulator_disable(pdata->ovdd);
2605                 if (err)
2606                         return err;
2607         }
2608
2609         it6505->powered = false;
2610         it6505->sink_count = 0;
2611
2612         return 0;
2613 }
2614
2615 static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2616 {
2617         struct device *dev = &it6505->client->dev;
2618         enum drm_connector_status status = connector_status_disconnected;
2619         int dp_sink_count;
2620
2621         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2622                              it6505->sink_count, it6505->powered);
2623
2624         mutex_lock(&it6505->mode_lock);
2625
2626         if (!it6505->powered)
2627                 goto unlock;
2628
2629         if (it6505->enable_drv_hold) {
2630                 status = it6505->hpd_state ? connector_status_connected :
2631                                              connector_status_disconnected;
2632                 goto unlock;
2633         }
2634
2635         if (it6505->hpd_state) {
2636                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2637                                              DP_SET_POWER_D0);
2638                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2639                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2640                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2641                                      it6505->sink_count, it6505->branch_device);
2642
2643                 if (it6505->branch_device) {
2644                         status = (it6505->sink_count != 0) ?
2645                                  connector_status_connected :
2646                                  connector_status_disconnected;
2647                 } else {
2648                         status = connector_status_connected;
2649                 }
2650         } else {
2651                 it6505->sink_count = 0;
2652                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2653         }
2654
2655 unlock:
2656         if (it6505->connector_status != status) {
2657                 it6505->connector_status = status;
2658                 it6505_plugged_status_to_codec(it6505);
2659         }
2660
2661         mutex_unlock(&it6505->mode_lock);
2662
2663         return status;
2664 }
2665
2666 static int it6505_extcon_notifier(struct notifier_block *self,
2667                                   unsigned long event, void *ptr)
2668 {
2669         struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2670
2671         schedule_work(&it6505->extcon_wq);
2672         return NOTIFY_DONE;
2673 }
2674
2675 static void it6505_extcon_work(struct work_struct *work)
2676 {
2677         struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2678         struct device *dev = &it6505->client->dev;
2679         int state, ret;
2680
2681         if (it6505->enable_drv_hold)
2682                 return;
2683
2684         mutex_lock(&it6505->extcon_lock);
2685
2686         state = extcon_get_state(it6505->extcon, EXTCON_DISP_DP);
2687         DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2688
2689         if (state == it6505->extcon_state || unlikely(state < 0))
2690                 goto unlock;
2691         it6505->extcon_state = state;
2692         if (state) {
2693                 DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2694                 msleep(100);
2695                 ret = pm_runtime_get_sync(dev);
2696
2697                 /*
2698                  * On system resume, extcon_work can be triggered before
2699                  * pm_runtime_force_resume re-enables runtime power management.
2700                  * Handling the error here to make sure the bridge is powered on.
2701                  */
2702                 if (ret < 0)
2703                         it6505_poweron(it6505);
2704
2705                 complete_all(&it6505->extcon_completion);
2706         } else {
2707                 DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2708                 pm_runtime_put_sync(dev);
2709                 reinit_completion(&it6505->extcon_completion);
2710
2711                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2712                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2713                 DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2714         }
2715
2716 unlock:
2717         mutex_unlock(&it6505->extcon_lock);
2718 }
2719
2720 static int it6505_use_notifier_module(struct it6505 *it6505)
2721 {
2722         int ret;
2723         struct device *dev = &it6505->client->dev;
2724
2725         it6505->event_nb.notifier_call = it6505_extcon_notifier;
2726         INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2727         ret = devm_extcon_register_notifier(&it6505->client->dev,
2728                                             it6505->extcon, EXTCON_DISP_DP,
2729                                             &it6505->event_nb);
2730         if (ret) {
2731                 dev_err(dev, "failed to register notifier for DP");
2732                 return ret;
2733         }
2734
2735         schedule_work(&it6505->extcon_wq);
2736
2737         return 0;
2738 }
2739
2740 static void it6505_remove_notifier_module(struct it6505 *it6505)
2741 {
2742         if (it6505->extcon) {
2743                 devm_extcon_unregister_notifier(&it6505->client->dev,
2744                                                 it6505->extcon, EXTCON_DISP_DP,
2745                                                 &it6505->event_nb);
2746
2747                 flush_work(&it6505->extcon_wq);
2748         }
2749 }
2750
2751 static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2752 {
2753         struct it6505 *it6505 = container_of(work, struct it6505,
2754                                              delayed_audio.work);
2755
2756         DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "start");
2757
2758         if (!it6505->powered)
2759                 return;
2760
2761         if (!it6505->enable_drv_hold)
2762                 it6505_enable_audio(it6505);
2763 }
2764
2765 static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2766                                                        struct hdmi_codec_params
2767                                                        *params)
2768 {
2769         struct device *dev = &it6505->client->dev;
2770         int i = 0;
2771
2772         DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2773                              params->sample_rate, params->sample_width,
2774                              params->cea.channels);
2775
2776         if (!it6505->bridge.encoder)
2777                 return -ENODEV;
2778
2779         if (params->cea.channels <= 1 || params->cea.channels > 8) {
2780                 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2781                                      it6505->audio.channel_count);
2782                 return -EINVAL;
2783         }
2784
2785         it6505->audio.channel_count = params->cea.channels;
2786
2787         while (i < ARRAY_SIZE(audio_sample_rate_map) &&
2788                params->sample_rate !=
2789                        audio_sample_rate_map[i].sample_rate_value) {
2790                 i++;
2791         }
2792         if (i == ARRAY_SIZE(audio_sample_rate_map)) {
2793                 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
2794                                      params->sample_rate);
2795                 return -EINVAL;
2796         }
2797         it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
2798
2799         switch (params->sample_width) {
2800         case 16:
2801                 it6505->audio.word_length = WORD_LENGTH_16BIT;
2802                 break;
2803         case 18:
2804                 it6505->audio.word_length = WORD_LENGTH_18BIT;
2805                 break;
2806         case 20:
2807                 it6505->audio.word_length = WORD_LENGTH_20BIT;
2808                 break;
2809         case 24:
2810         case 32:
2811                 it6505->audio.word_length = WORD_LENGTH_24BIT;
2812                 break;
2813         default:
2814                 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
2815                                      params->sample_width);
2816                 return -EINVAL;
2817         }
2818
2819         return 0;
2820 }
2821
2822 static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
2823 {
2824         struct it6505 *it6505 = dev_get_drvdata(dev);
2825
2826         if (it6505->powered)
2827                 it6505_disable_audio(it6505);
2828 }
2829
2830 static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
2831                                                        void *data,
2832                                                        hdmi_codec_plugged_cb fn,
2833                                                        struct device *codec_dev)
2834 {
2835         struct it6505 *it6505 = data;
2836
2837         it6505->plugged_cb = fn;
2838         it6505->codec_dev = codec_dev;
2839         it6505_plugged_status_to_codec(it6505);
2840
2841         return 0;
2842 }
2843
2844 static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
2845 {
2846         return container_of(bridge, struct it6505, bridge);
2847 }
2848
2849 static int it6505_bridge_attach(struct drm_bridge *bridge,
2850                                 enum drm_bridge_attach_flags flags)
2851 {
2852         struct it6505 *it6505 = bridge_to_it6505(bridge);
2853         struct device *dev = &it6505->client->dev;
2854         int ret;
2855
2856         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2857                 DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
2858                 return -EINVAL;
2859         }
2860
2861         if (!bridge->encoder) {
2862                 dev_err(dev, "Parent encoder object not found");
2863                 return -ENODEV;
2864         }
2865
2866         /* Register aux channel */
2867         it6505->aux.drm_dev = bridge->dev;
2868
2869         ret = drm_dp_aux_register(&it6505->aux);
2870
2871         if (ret < 0) {
2872                 dev_err(dev, "Failed to register aux: %d", ret);
2873                 return ret;
2874         }
2875
2876         if (it6505->extcon) {
2877                 ret = it6505_use_notifier_module(it6505);
2878                 if (ret < 0) {
2879                         dev_err(dev, "use notifier module failed");
2880                         return ret;
2881                 }
2882         }
2883
2884         return 0;
2885 }
2886
2887 static void it6505_bridge_detach(struct drm_bridge *bridge)
2888 {
2889         struct it6505 *it6505 = bridge_to_it6505(bridge);
2890
2891         flush_work(&it6505->link_works);
2892         it6505_remove_notifier_module(it6505);
2893 }
2894
2895 static enum drm_mode_status
2896 it6505_bridge_mode_valid(struct drm_bridge *bridge,
2897                          const struct drm_display_info *info,
2898                          const struct drm_display_mode *mode)
2899 {
2900         struct it6505 *it6505 = bridge_to_it6505(bridge);
2901
2902         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2903                 return MODE_NO_INTERLACE;
2904
2905         if (mode->clock > DPI_PIXEL_CLK_MAX)
2906                 return MODE_CLOCK_HIGH;
2907
2908         it6505->video_info.clock = mode->clock;
2909
2910         return MODE_OK;
2911 }
2912
2913 static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
2914                                         struct drm_bridge_state *old_state)
2915 {
2916         struct it6505 *it6505 = bridge_to_it6505(bridge);
2917         struct device *dev = &it6505->client->dev;
2918         struct drm_atomic_state *state = old_state->base.state;
2919         struct hdmi_avi_infoframe frame;
2920         struct drm_crtc_state *crtc_state;
2921         struct drm_connector_state *conn_state;
2922         struct drm_display_mode *mode;
2923         struct drm_connector *connector;
2924         int ret;
2925
2926         DRM_DEV_DEBUG_DRIVER(dev, "start");
2927
2928         connector = drm_atomic_get_new_connector_for_encoder(state,
2929                                                              bridge->encoder);
2930
2931         if (WARN_ON(!connector))
2932                 return;
2933
2934         conn_state = drm_atomic_get_new_connector_state(state, connector);
2935
2936         if (WARN_ON(!conn_state))
2937                 return;
2938
2939         crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
2940
2941         if (WARN_ON(!crtc_state))
2942                 return;
2943
2944         mode = &crtc_state->adjusted_mode;
2945
2946         if (WARN_ON(!mode))
2947                 return;
2948
2949         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2950                                                        connector,
2951                                                        mode);
2952         if (ret)
2953                 dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
2954
2955         it6505_update_video_parameter(it6505, mode);
2956
2957         ret = it6505_send_video_infoframe(it6505, &frame);
2958
2959         if (ret)
2960                 dev_err(dev, "Failed to send AVI infoframe: %d", ret);
2961
2962         it6505_int_mask_enable(it6505);
2963         it6505_video_reset(it6505);
2964
2965         it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2966                                      DP_SET_POWER_D0);
2967 }
2968
2969 static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
2970                                          struct drm_bridge_state *old_state)
2971 {
2972         struct it6505 *it6505 = bridge_to_it6505(bridge);
2973         struct device *dev = &it6505->client->dev;
2974
2975         DRM_DEV_DEBUG_DRIVER(dev, "start");
2976
2977         if (it6505->powered) {
2978                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2979                                              DP_SET_POWER_D3);
2980                 it6505_video_disable(it6505);
2981         }
2982 }
2983
2984 static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge,
2985                                             struct drm_bridge_state *old_state)
2986 {
2987         struct it6505 *it6505 = bridge_to_it6505(bridge);
2988         struct device *dev = &it6505->client->dev;
2989
2990         DRM_DEV_DEBUG_DRIVER(dev, "start");
2991
2992         pm_runtime_get_sync(dev);
2993 }
2994
2995 static void it6505_bridge_atomic_post_disable(struct drm_bridge *bridge,
2996                                               struct drm_bridge_state *old_state)
2997 {
2998         struct it6505 *it6505 = bridge_to_it6505(bridge);
2999         struct device *dev = &it6505->client->dev;
3000
3001         DRM_DEV_DEBUG_DRIVER(dev, "start");
3002
3003         pm_runtime_put_sync(dev);
3004 }
3005
3006 static enum drm_connector_status
3007 it6505_bridge_detect(struct drm_bridge *bridge)
3008 {
3009         struct it6505 *it6505 = bridge_to_it6505(bridge);
3010
3011         return it6505_detect(it6505);
3012 }
3013
3014 static struct edid *it6505_bridge_get_edid(struct drm_bridge *bridge,
3015                                            struct drm_connector *connector)
3016 {
3017         struct it6505 *it6505 = bridge_to_it6505(bridge);
3018         struct device *dev = &it6505->client->dev;
3019         struct edid *edid;
3020
3021         edid = drm_do_get_edid(connector, it6505_get_edid_block, it6505);
3022
3023         if (!edid) {
3024                 DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
3025                 return NULL;
3026         }
3027
3028         return edid;
3029 }
3030
3031 static const struct drm_bridge_funcs it6505_bridge_funcs = {
3032         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3033         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3034         .atomic_reset = drm_atomic_helper_bridge_reset,
3035         .attach = it6505_bridge_attach,
3036         .detach = it6505_bridge_detach,
3037         .mode_valid = it6505_bridge_mode_valid,
3038         .atomic_enable = it6505_bridge_atomic_enable,
3039         .atomic_disable = it6505_bridge_atomic_disable,
3040         .atomic_pre_enable = it6505_bridge_atomic_pre_enable,
3041         .atomic_post_disable = it6505_bridge_atomic_post_disable,
3042         .detect = it6505_bridge_detect,
3043         .get_edid = it6505_bridge_get_edid,
3044 };
3045
3046 static __maybe_unused int it6505_bridge_resume(struct device *dev)
3047 {
3048         struct it6505 *it6505 = dev_get_drvdata(dev);
3049
3050         return it6505_poweron(it6505);
3051 }
3052
3053 static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3054 {
3055         struct it6505 *it6505 = dev_get_drvdata(dev);
3056
3057         return it6505_poweroff(it6505);
3058 }
3059
3060 static const struct dev_pm_ops it6505_bridge_pm_ops = {
3061         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3062         SET_RUNTIME_PM_OPS(it6505_bridge_suspend, it6505_bridge_resume, NULL)
3063 };
3064
3065 static int it6505_init_pdata(struct it6505 *it6505)
3066 {
3067         struct it6505_platform_data *pdata = &it6505->pdata;
3068         struct device *dev = &it6505->client->dev;
3069
3070         /* 1.0V digital core power regulator  */
3071         pdata->pwr18 = devm_regulator_get(dev, "pwr18");
3072         if (IS_ERR(pdata->pwr18)) {
3073                 dev_err(dev, "pwr18 regulator not found");
3074                 return PTR_ERR(pdata->pwr18);
3075         }
3076
3077         pdata->ovdd = devm_regulator_get(dev, "ovdd");
3078         if (IS_ERR(pdata->ovdd)) {
3079                 dev_err(dev, "ovdd regulator not found");
3080                 return PTR_ERR(pdata->ovdd);
3081         }
3082
3083         pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3084         if (IS_ERR(pdata->gpiod_reset)) {
3085                 dev_err(dev, "gpiod_reset gpio not found");
3086                 return PTR_ERR(pdata->gpiod_reset);
3087         }
3088
3089         return 0;
3090 }
3091
3092 static void it6505_parse_dt(struct it6505 *it6505)
3093 {
3094         struct device *dev = &it6505->client->dev;
3095         u32 *afe_setting = &it6505->afe_setting;
3096
3097         it6505->lane_swap_disabled =
3098                 device_property_read_bool(dev, "no-laneswap");
3099
3100         if (it6505->lane_swap_disabled)
3101                 it6505->lane_swap = false;
3102
3103         if (device_property_read_u32(dev, "afe-setting", afe_setting) == 0) {
3104                 if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3105                         dev_err(dev, "afe setting error, use default");
3106                         *afe_setting = 0;
3107                 }
3108         } else {
3109                 *afe_setting = 0;
3110         }
3111         DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting);
3112 }
3113
3114 static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3115                                            size_t len, loff_t *ppos)
3116 {
3117         struct it6505 *it6505 = file->private_data;
3118         struct drm_display_mode *vid = &it6505->video_info;
3119         u8 read_buf[READ_BUFFER_SIZE];
3120         u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3121         ssize_t ret, count;
3122
3123         if (!it6505)
3124                 return -ENODEV;
3125
3126         it6505_calc_video_info(it6505);
3127         str += scnprintf(str, end - str, "---video timing---\n");
3128         str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
3129                          vid->clock / 1000, vid->clock % 1000);
3130         str += scnprintf(str, end - str, "HTotal:%d\n", vid->htotal);
3131         str += scnprintf(str, end - str, "HActive:%d\n", vid->hdisplay);
3132         str += scnprintf(str, end - str, "HFrontPorch:%d\n",
3133                          vid->hsync_start - vid->hdisplay);
3134         str += scnprintf(str, end - str, "HSyncWidth:%d\n",
3135                          vid->hsync_end - vid->hsync_start);
3136         str += scnprintf(str, end - str, "HBackPorch:%d\n",
3137                          vid->htotal - vid->hsync_end);
3138         str += scnprintf(str, end - str, "VTotal:%d\n", vid->vtotal);
3139         str += scnprintf(str, end - str, "VActive:%d\n", vid->vdisplay);
3140         str += scnprintf(str, end - str, "VFrontPorch:%d\n",
3141                          vid->vsync_start - vid->vdisplay);
3142         str += scnprintf(str, end - str, "VSyncWidth:%d\n",
3143                          vid->vsync_end - vid->vsync_start);
3144         str += scnprintf(str, end - str, "VBackPorch:%d\n",
3145                          vid->vtotal - vid->vsync_end);
3146
3147         count = str - read_buf;
3148         ret = simple_read_from_buffer(buf, len, ppos, read_buf, count);
3149
3150         return ret;
3151 }
3152
3153 static int force_power_on_off_debugfs_write(void *data, u64 value)
3154 {
3155         struct it6505 *it6505 = data;
3156
3157         if (!it6505)
3158                 return -ENODEV;
3159
3160         if (value)
3161                 it6505_poweron(it6505);
3162         else
3163                 it6505_poweroff(it6505);
3164
3165         return 0;
3166 }
3167
3168 static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3169 {
3170         struct it6505 *it6505 = data;
3171
3172         if (!it6505)
3173                 return -ENODEV;
3174
3175         *buf = it6505->enable_drv_hold;
3176
3177         return 0;
3178 }
3179
3180 static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3181 {
3182         struct it6505 *it6505 = data;
3183
3184         if (!it6505)
3185                 return -ENODEV;
3186
3187         it6505->enable_drv_hold = drv_hold;
3188
3189         if (it6505->enable_drv_hold) {
3190                 it6505_int_mask_disable(it6505);
3191         } else {
3192                 it6505_clear_int(it6505);
3193                 it6505_int_mask_enable(it6505);
3194
3195                 if (it6505->powered) {
3196                         it6505->connector_status =
3197                                         it6505_get_sink_hpd_status(it6505) ?
3198                                         connector_status_connected :
3199                                         connector_status_disconnected;
3200                 } else {
3201                         it6505->connector_status =
3202                                         connector_status_disconnected;
3203                 }
3204         }
3205
3206         return 0;
3207 }
3208
3209 static const struct file_operations receive_timing_fops = {
3210         .owner = THIS_MODULE,
3211         .open = simple_open,
3212         .read = receive_timing_debugfs_show,
3213         .llseek = default_llseek,
3214 };
3215
3216 DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3217                          force_power_on_off_debugfs_write, "%llu\n");
3218
3219 DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3220                          enable_drv_hold_debugfs_write, "%llu\n");
3221
3222 static const struct debugfs_entries debugfs_entry[] = {
3223         { "receive_timing", &receive_timing_fops },
3224         { "force_power_on_off", &fops_force_power },
3225         { "enable_drv_hold", &fops_enable_drv_hold },
3226         { NULL, NULL },
3227 };
3228
3229 static void debugfs_create_files(struct it6505 *it6505)
3230 {
3231         int i = 0;
3232
3233         while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3234                 debugfs_create_file(debugfs_entry[i].name, 0644,
3235                                     it6505->debugfs, it6505,
3236                                     debugfs_entry[i].fops);
3237                 i++;
3238         }
3239 }
3240
3241 static void debugfs_init(struct it6505 *it6505)
3242 {
3243         struct device *dev = &it6505->client->dev;
3244
3245         it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3246
3247         if (IS_ERR(it6505->debugfs)) {
3248                 dev_err(dev, "failed to create debugfs root");
3249                 return;
3250         }
3251
3252         debugfs_create_files(it6505);
3253 }
3254
3255 static void it6505_debugfs_remove(struct it6505 *it6505)
3256 {
3257         debugfs_remove_recursive(it6505->debugfs);
3258 }
3259
3260 static void it6505_shutdown(struct i2c_client *client)
3261 {
3262         struct it6505 *it6505 = dev_get_drvdata(&client->dev);
3263
3264         if (it6505->powered)
3265                 it6505_lane_off(it6505);
3266 }
3267
3268 static int it6505_i2c_probe(struct i2c_client *client,
3269                             const struct i2c_device_id *id)
3270 {
3271         struct it6505 *it6505;
3272         struct device *dev = &client->dev;
3273         struct extcon_dev *extcon;
3274         int err, intp_irq;
3275
3276         it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
3277         if (!it6505)
3278                 return -ENOMEM;
3279
3280         mutex_init(&it6505->irq_lock);
3281         mutex_init(&it6505->extcon_lock);
3282         mutex_init(&it6505->mode_lock);
3283         mutex_init(&it6505->aux_lock);
3284
3285         it6505->bridge.of_node = client->dev.of_node;
3286         it6505->connector_status = connector_status_disconnected;
3287         it6505->client = client;
3288         i2c_set_clientdata(client, it6505);
3289
3290         /* get extcon device from DTS */
3291         extcon = extcon_get_edev_by_phandle(dev, 0);
3292         if (PTR_ERR(extcon) == -EPROBE_DEFER)
3293                 return -EPROBE_DEFER;
3294         if (IS_ERR(extcon)) {
3295                 dev_err(dev, "can not get extcon device!");
3296                 return PTR_ERR(extcon);
3297         }
3298
3299         it6505->extcon = extcon;
3300
3301         it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3302         if (IS_ERR(it6505->regmap)) {
3303                 dev_err(dev, "regmap i2c init failed");
3304                 err = PTR_ERR(it6505->regmap);
3305                 return err;
3306         }
3307
3308         err = it6505_init_pdata(it6505);
3309         if (err) {
3310                 dev_err(dev, "Failed to initialize pdata: %d", err);
3311                 return err;
3312         }
3313
3314         it6505_parse_dt(it6505);
3315
3316         intp_irq = client->irq;
3317
3318         if (!intp_irq) {
3319                 dev_err(dev, "Failed to get INTP IRQ");
3320                 err = -ENODEV;
3321                 return err;
3322         }
3323
3324         err = devm_request_threaded_irq(&client->dev, intp_irq, NULL,
3325                                         it6505_int_threaded_handler,
3326                                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3327                                         "it6505-intp", it6505);
3328         if (err) {
3329                 dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3330                 return err;
3331         }
3332
3333         INIT_WORK(&it6505->link_works, it6505_link_training_work);
3334         INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3335         INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3336         init_completion(&it6505->extcon_completion);
3337         memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3338         it6505->powered = false;
3339         it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3340
3341         if (DEFAULT_PWR_ON)
3342                 it6505_poweron(it6505);
3343
3344         DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3345         debugfs_init(it6505);
3346         pm_runtime_enable(dev);
3347
3348         it6505->aux.name = "DP-AUX";
3349         it6505->aux.dev = dev;
3350         it6505->aux.transfer = it6505_aux_transfer;
3351         drm_dp_aux_init(&it6505->aux);
3352
3353         it6505->bridge.funcs = &it6505_bridge_funcs;
3354         it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3355         it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3356                              DRM_BRIDGE_OP_HPD;
3357         drm_bridge_add(&it6505->bridge);
3358
3359         return 0;
3360 }
3361
3362 static void it6505_i2c_remove(struct i2c_client *client)
3363 {
3364         struct it6505 *it6505 = i2c_get_clientdata(client);
3365
3366         drm_bridge_remove(&it6505->bridge);
3367         drm_dp_aux_unregister(&it6505->aux);
3368         it6505_debugfs_remove(it6505);
3369         it6505_poweroff(it6505);
3370 }
3371
3372 static const struct i2c_device_id it6505_id[] = {
3373         { "it6505", 0 },
3374         { }
3375 };
3376
3377 MODULE_DEVICE_TABLE(i2c, it6505_id);
3378
3379 static const struct of_device_id it6505_of_match[] = {
3380         { .compatible = "ite,it6505" },
3381         { }
3382 };
3383
3384 static struct i2c_driver it6505_i2c_driver = {
3385         .driver = {
3386                 .name = "it6505",
3387                 .of_match_table = it6505_of_match,
3388                 .pm = &it6505_bridge_pm_ops,
3389         },
3390         .probe = it6505_i2c_probe,
3391         .remove = it6505_i2c_remove,
3392         .shutdown = it6505_shutdown,
3393         .id_table = it6505_id,
3394 };
3395
3396 module_i2c_driver(it6505_i2c_driver);
3397
3398 MODULE_AUTHOR("Allen Chen <[email protected]>");
3399 MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3400 MODULE_LICENSE("GPL v2");