drivers/acpi/cppc_acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
   4  *
   5  * (C) Copyright 2014, 2015 Linaro Ltd.
   6  * Author: Ashwin Chaugule <[email protected]>
   7  *
   8  * CPPC describes a few methods for controlling CPU performance using
   9  * information from a per CPU table called CPC. This table is described in
  10  * the ACPI v5.0+ specification. The table consists of a list of
  11  * registers which may be memory mapped or hardware registers and also may
  12  * include some static integer values.
  13  *
  14  * CPU performance is on an abstract continuous scale as against a discretized
  15  * P-state scale which is tied to CPU frequency only. In brief, the basic
  16  * operation involves:
  17  *
  18  * - OS makes a CPU performance request. (Can provide min and max bounds)
  19  *
  20  * - Platform (such as BMC) is free to optimize request within requested bounds
  21  *   depending on power/thermal budgets etc.
  22  *
  23  * - Platform conveys its decision back to OS
  24  *
  25  * The communication between OS and platform occurs through another medium
  26  * called (PCC) Platform Communication Channel. This is a generic mailbox like
  27  * mechanism which includes doorbell semantics to indicate register updates.
  28  * See drivers/mailbox/pcc.c for details on PCC.
  29  *
  30  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  31  * above specifications.
  32  */
  33
  34 #define pr_fmt(fmt)     "ACPI CPPC: " fmt
  35
  36 #include <linux/delay.h>
  37 #include <linux/iopoll.h>
  38 #include <linux/ktime.h>
  39 #include <linux/rwsem.h>
  40 #include <linux/wait.h>
  41 #include <linux/topology.h>
  42
  43 #include <acpi/cppc_acpi.h>
  44
  45 struct cppc_pcc_data {
  46         struct pcc_mbox_chan *pcc_channel;
  47         void __iomem *pcc_comm_addr;
  48         bool pcc_channel_acquired;
  49         unsigned int deadline_us;
  50         unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
  51
  52         bool pending_pcc_write_cmd;     /* Any pending/batched PCC write cmds? */
  53         bool platform_owns_pcc;         /* Ownership of PCC subspace */
  54         unsigned int pcc_write_cnt;     /* Running count of PCC write commands */
  55
  56         /*
  57          * Lock to provide controlled access to the PCC channel.
  58          *
  59          * For performance critical usecases(currently cppc_set_perf)
  60          *      We need to take read_lock and check if channel belongs to OSPM
  61          * before reading or writing to PCC subspace
  62          *      We need to take write_lock before transferring the channel
  63          * ownership to the platform via a Doorbell
  64          *      This allows us to batch a number of CPPC requests if they happen
  65          * to originate in about the same time
  66          *
  67          * For non-performance critical usecases(init)
  68          *      Take write_lock for all purposes which gives exclusive access
  69          */
  70         struct rw_semaphore pcc_lock;
  71
  72         /* Wait queue for CPUs whose requests were batched */
  73         wait_queue_head_t pcc_write_wait_q;
  74         ktime_t last_cmd_cmpl_time;
  75         ktime_t last_mpar_reset;
  76         int mpar_count;
  77         int refcount;
  78 };
  79
  80 /* Array to represent the PCC channel per subspace ID */
  81 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
  82 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
  83 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
  84
  85 /*
  86  * The cpc_desc structure contains the ACPI register details
  87  * as described in the per CPU _CPC tables. The details
  88  * include the type of register (e.g. PCC, System IO, FFH etc.)
  89  * and destination addresses which lets us READ/WRITE CPU performance
  90  * information using the appropriate I/O methods.
  91  */
  92 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  93
  94 /* pcc mapped address + header size + offset within PCC subspace */
  95 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
  96                                                 0x8 + (offs))
  97
  98 /* Check if a CPC register is in PCC */
  99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&             \
 100                                 (cpc)->cpc_entry.reg.space_id ==        \
 101                                 ACPI_ADR_SPACE_PLATFORM_COMM)
 102
 103 /* Evaluates to True if reg is a NULL register descriptor */
 104 #define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \
 105                                 (reg)->address == 0 &&                  \
 106                                 (reg)->bit_width == 0 &&                \
 107                                 (reg)->bit_offset == 0 &&               \
 108                                 (reg)->access_width == 0)
 109
 110 /* Evaluates to True if an optional cpc field is supported */
 111 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?          \
 112                                 !!(cpc)->cpc_entry.int_value :          \
 113                                 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
 114 /*
 115  * Arbitrary Retries in case the remote processor is slow to respond
 116  * to PCC commands. Keeping it high enough to cover emulators where
 117  * the processors run painfully slow.
 118  */
 119 #define NUM_RETRIES 500ULL
 120
 121 #define OVER_16BTS_MASK ~0xFFFFULL
 122
 123 #define define_one_cppc_ro(_name)               \
 124 static struct kobj_attribute _name =            \
 125 __ATTR(_name, 0444, show_##_name, NULL)
 126
 127 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
 128
 129 #define show_cppc_data(access_fn, struct_name, member_name)             \
 130         static ssize_t show_##member_name(struct kobject *kobj,         \
 131                                 struct kobj_attribute *attr, char *buf) \
 132         {                                                               \
 133                 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);           \
 134                 struct struct_name st_name = {0};                       \
 135                 int ret;                                                \
 136                                                                         \
 137                 ret = access_fn(cpc_ptr->cpu_id, &st_name);             \
 138                 if (ret)                                                \
 139                         return ret;                                     \
 140                                                                         \
 141                 return scnprintf(buf, PAGE_SIZE, "%llu\n",              \
 142                                 (u64)st_name.member_name);              \
 143         }                                                               \
 144         define_one_cppc_ro(member_name)
 145
 146 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
 147 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
 148 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
 149 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
 150 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
 151 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
 152
 153 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
 154 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
 155
 156 static ssize_t show_feedback_ctrs(struct kobject *kobj,
 157                 struct kobj_attribute *attr, char *buf)
 158 {
 159         struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 160         struct cppc_perf_fb_ctrs fb_ctrs = {0};
 161         int ret;
 162
 163         ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
 164         if (ret)
 165                 return ret;
 166
 167         return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
 168                         fb_ctrs.reference, fb_ctrs.delivered);
 169 }
 170 define_one_cppc_ro(feedback_ctrs);
 171
 172 static struct attribute *cppc_attrs[] = {
 173         &feedback_ctrs.attr,
 174         &reference_perf.attr,
 175         &wraparound_time.attr,
 176         &highest_perf.attr,
 177         &lowest_perf.attr,
 178         &lowest_nonlinear_perf.attr,
 179         &nominal_perf.attr,
 180         &nominal_freq.attr,
 181         &lowest_freq.attr,
 182         NULL
 183 };
 184 ATTRIBUTE_GROUPS(cppc);
 185
 186 static struct kobj_type cppc_ktype = {
 187         .sysfs_ops = &kobj_sysfs_ops,
 188         .default_groups = cppc_groups,
 189 };
 190
 191 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
 192 {
 193         int ret, status;
 194         struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 195         struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 196                 pcc_ss_data->pcc_comm_addr;
 197
 198         if (!pcc_ss_data->platform_owns_pcc)
 199                 return 0;
 200
 201         /*
 202          * Poll PCC status register every 3us(delay_us) for maximum of
 203          * deadline_us(timeout_us) until PCC command complete bit is set(cond)
 204          */
 205         ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
 206                                         status & PCC_CMD_COMPLETE_MASK, 3,
 207                                         pcc_ss_data->deadline_us);
 208
 209         if (likely(!ret)) {
 210                 pcc_ss_data->platform_owns_pcc = false;
 211                 if (chk_err_bit && (status & PCC_ERROR_MASK))
 212                         ret = -EIO;
 213         }
 214
 215         if (unlikely(ret))
 216                 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
 217                        pcc_ss_id, ret);
 218
 219         return ret;
 220 }
 221
 222 /*
 223  * This function transfers the ownership of the PCC to the platform
 224  * So it must be called while holding write_lock(pcc_lock)
 225  */
 226 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
 227 {
 228         int ret = -EIO, i;
 229         struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 230         struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 231                 pcc_ss_data->pcc_comm_addr;
 232         unsigned int time_delta;
 233
 234         /*
 235          * For CMD_WRITE we know for a fact the caller should have checked
 236          * the channel before writing to PCC space
 237          */
 238         if (cmd == CMD_READ) {
 239                 /*
 240                  * If there are pending cpc_writes, then we stole the channel
 241                  * before write completion, so first send a WRITE command to
 242                  * platform
 243                  */
 244                 if (pcc_ss_data->pending_pcc_write_cmd)
 245                         send_pcc_cmd(pcc_ss_id, CMD_WRITE);
 246
 247                 ret = check_pcc_chan(pcc_ss_id, false);
 248                 if (ret)
 249                         goto end;
 250         } else /* CMD_WRITE */
 251                 pcc_ss_data->pending_pcc_write_cmd = FALSE;
 252
 253         /*
 254          * Handle the Minimum Request Turnaround Time(MRTT)
 255          * "The minimum amount of time that OSPM must wait after the completion
 256          * of a command before issuing the next command, in microseconds"
 257          */
 258         if (pcc_ss_data->pcc_mrtt) {
 259                 time_delta = ktime_us_delta(ktime_get(),
 260                                             pcc_ss_data->last_cmd_cmpl_time);
 261                 if (pcc_ss_data->pcc_mrtt > time_delta)
 262                         udelay(pcc_ss_data->pcc_mrtt - time_delta);
 263         }
 264
 265         /*
 266          * Handle the non-zero Maximum Periodic Access Rate(MPAR)
 267          * "The maximum number of periodic requests that the subspace channel can
 268          * support, reported in commands per minute. 0 indicates no limitation."
 269          *
 270          * This parameter should be ideally zero or large enough so that it can
 271          * handle maximum number of requests that all the cores in the system can
 272          * collectively generate. If it is not, we will follow the spec and just
 273          * not send the request to the platform after hitting the MPAR limit in
 274          * any 60s window
 275          */
 276         if (pcc_ss_data->pcc_mpar) {
 277                 if (pcc_ss_data->mpar_count == 0) {
 278                         time_delta = ktime_ms_delta(ktime_get(),
 279                                                     pcc_ss_data->last_mpar_reset);
 280                         if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
 281                                 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
 282                                          pcc_ss_id);
 283                                 ret = -EIO;
 284                                 goto end;
 285                         }
 286                         pcc_ss_data->last_mpar_reset = ktime_get();
 287                         pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
 288                 }
 289                 pcc_ss_data->mpar_count--;
 290         }
 291
 292         /* Write to the shared comm region. */
 293         writew_relaxed(cmd, &generic_comm_base->command);
 294
 295         /* Flip CMD COMPLETE bit */
 296         writew_relaxed(0, &generic_comm_base->status);
 297
 298         pcc_ss_data->platform_owns_pcc = true;
 299
 300         /* Ring doorbell */
 301         ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
 302         if (ret < 0) {
 303                 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
 304                        pcc_ss_id, cmd, ret);
 305                 goto end;
 306         }
 307
 308         /* wait for completion and check for PCC errro bit */
 309         ret = check_pcc_chan(pcc_ss_id, true);
 310
 311         if (pcc_ss_data->pcc_mrtt)
 312                 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
 313
 314         if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
 315                 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
 316         else
 317                 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
 318
 319 end:
 320         if (cmd == CMD_WRITE) {
 321                 if (unlikely(ret)) {
 322                         for_each_possible_cpu(i) {
 323                                 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
 324
 325                                 if (!desc)
 326                                         continue;
 327
 328                                 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
 329                                         desc->write_cmd_status = ret;
 330                         }
 331                 }
 332                 pcc_ss_data->pcc_write_cnt++;
 333                 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
 334         }
 335
 336         return ret;
 337 }
 338
 339 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
 340 {
 341         if (ret < 0)
 342                 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
 343                                 *(u16 *)msg, ret);
 344         else
 345                 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
 346                                 *(u16 *)msg, ret);
 347 }
 348
 349 static struct mbox_client cppc_mbox_cl = {
 350         .tx_done = cppc_chan_tx_done,
 351         .knows_txdone = true,
 352 };
 353
 354 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
 355 {
 356         int result = -EFAULT;
 357         acpi_status status = AE_OK;
 358         struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
 359         struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
 360         struct acpi_buffer state = {0, NULL};
 361         union acpi_object  *psd = NULL;
 362         struct acpi_psd_package *pdomain;
 363
 364         status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
 365                                             &buffer, ACPI_TYPE_PACKAGE);
 366         if (status == AE_NOT_FOUND)     /* _PSD is optional */
 367                 return 0;
 368         if (ACPI_FAILURE(status))
 369                 return -ENODEV;
 370
 371         psd = buffer.pointer;
 372         if (!psd || psd->package.count != 1) {
 373                 pr_debug("Invalid _PSD data\n");
 374                 goto end;
 375         }
 376
 377         pdomain = &(cpc_ptr->domain_info);
 378
 379         state.length = sizeof(struct acpi_psd_package);
 380         state.pointer = pdomain;
 381
 382         status = acpi_extract_package(&(psd->package.elements[0]),
 383                 &format, &state);
 384         if (ACPI_FAILURE(status)) {
 385                 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
 386                 goto end;
 387         }
 388
 389         if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
 390                 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
 391                 goto end;
 392         }
 393
 394         if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
 395                 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
 396                 goto end;
 397         }
 398
 399         if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
 400             pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
 401             pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
 402                 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
 403                 goto end;
 404         }
 405
 406         result = 0;
 407 end:
 408         kfree(buffer.pointer);
 409         return result;
 410 }
 411
 412 bool acpi_cpc_valid(void)
 413 {
 414         struct cpc_desc *cpc_ptr;
 415         int cpu;
 416
 417         for_each_present_cpu(cpu) {
 418                 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
 419                 if (!cpc_ptr)
 420                         return false;
 421         }
 422
 423         return true;
 424 }
 425 EXPORT_SYMBOL_GPL(acpi_cpc_valid);
 426
 427 /**
 428  * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
 429  * @cpu: Find all CPUs that share a domain with cpu.
 430  * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
 431  *
 432  *      Return: 0 for success or negative value for err.
 433  */
 434 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
 435 {
 436         struct cpc_desc *cpc_ptr, *match_cpc_ptr;
 437         struct acpi_psd_package *match_pdomain;
 438         struct acpi_psd_package *pdomain;
 439         int count_target, i;
 440
 441         /*
 442          * Now that we have _PSD data from all CPUs, let's setup P-state
 443          * domain info.
 444          */
 445         cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
 446         if (!cpc_ptr)
 447                 return -EFAULT;
 448
 449         pdomain = &(cpc_ptr->domain_info);
 450         cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
 451         if (pdomain->num_processors <= 1)
 452                 return 0;
 453
 454         /* Validate the Domain info */
 455         count_target = pdomain->num_processors;
 456         if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
 457                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 458         else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
 459                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
 460         else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
 461                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
 462
 463         for_each_possible_cpu(i) {
 464                 if (i == cpu)
 465                         continue;
 466
 467                 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
 468                 if (!match_cpc_ptr)
 469                         goto err_fault;
 470
 471                 match_pdomain = &(match_cpc_ptr->domain_info);
 472                 if (match_pdomain->domain != pdomain->domain)
 473                         continue;
 474
 475                 /* Here i and cpu are in the same domain */
 476                 if (match_pdomain->num_processors != count_target)
 477                         goto err_fault;
 478
 479                 if (pdomain->coord_type != match_pdomain->coord_type)
 480                         goto err_fault;
 481
 482                 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
 483         }
 484
 485         return 0;
 486
 487 err_fault:
 488         /* Assume no coordination on any error parsing domain info */
 489         cpumask_clear(cpu_data->shared_cpu_map);
 490         cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
 491         cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
 492
 493         return -EFAULT;
 494 }
 495 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 496
 497 static int register_pcc_channel(int pcc_ss_idx)
 498 {
 499         struct pcc_mbox_chan *pcc_chan;
 500         u64 usecs_lat;
 501
 502         if (pcc_ss_idx >= 0) {
 503                 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
 504
 505                 if (IS_ERR(pcc_chan)) {
 506                         pr_err("Failed to find PCC channel for subspace %d\n",
 507                                pcc_ss_idx);
 508                         return -ENODEV;
 509                 }
 510
 511                 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
 512                 /*
 513                  * cppc_ss->latency is just a Nominal value. In reality
 514                  * the remote processor could be much slower to reply.
 515                  * So add an arbitrary amount of wait on top of Nominal.
 516                  */
 517                 usecs_lat = NUM_RETRIES * pcc_chan->latency;
 518                 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
 519                 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
 520                 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
 521                 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
 522
 523                 pcc_data[pcc_ss_idx]->pcc_comm_addr =
 524                         acpi_os_ioremap(pcc_chan->shmem_base_addr,
 525                                         pcc_chan->shmem_size);
 526                 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
 527                         pr_err("Failed to ioremap PCC comm region mem for %d\n",
 528                                pcc_ss_idx);
 529                         return -ENOMEM;
 530                 }
 531
 532                 /* Set flag so that we don't come here for each CPU. */
 533                 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
 534         }
 535
 536         return 0;
 537 }
 538
 539 /**
 540  * cpc_ffh_supported() - check if FFH reading supported
 541  *
 542  * Check if the architecture has support for functional fixed hardware
 543  * read/write capability.
 544  *
 545  * Return: true for supported, false for not supported
 546  */
 547 bool __weak cpc_ffh_supported(void)
 548 {
 549         return false;
 550 }
 551
 552 /**
 553  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
 554  *
 555  * Check and allocate the cppc_pcc_data memory.
 556  * In some processor configurations it is possible that same subspace
 557  * is shared between multiple CPUs. This is seen especially in CPUs
 558  * with hardware multi-threading support.
 559  *
 560  * Return: 0 for success, errno for failure
 561  */
 562 static int pcc_data_alloc(int pcc_ss_id)
 563 {
 564         if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
 565                 return -EINVAL;
 566
 567         if (pcc_data[pcc_ss_id]) {
 568                 pcc_data[pcc_ss_id]->refcount++;
 569         } else {
 570                 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
 571                                               GFP_KERNEL);
 572                 if (!pcc_data[pcc_ss_id])
 573                         return -ENOMEM;
 574                 pcc_data[pcc_ss_id]->refcount++;
 575         }
 576
 577         return 0;
 578 }
 579
 580 /* Check if CPPC revision + num_ent combination is supported */
 581 static bool is_cppc_supported(int revision, int num_ent)
 582 {
 583         int expected_num_ent;
 584
 585         switch (revision) {
 586         case CPPC_V2_REV:
 587                 expected_num_ent = CPPC_V2_NUM_ENT;
 588                 break;
 589         case CPPC_V3_REV:
 590                 expected_num_ent = CPPC_V3_NUM_ENT;
 591                 break;
 592         default:
 593                 pr_debug("Firmware exports unsupported CPPC revision: %d\n",
 594                         revision);
 595                 return false;
 596         }
 597
 598         if (expected_num_ent != num_ent) {
 599                 pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n",
 600                         num_ent, expected_num_ent, revision);
 601                 return false;
 602         }
 603
 604         return true;
 605 }
 606
 607 /*
 608  * An example CPC table looks like the following.
 609  *
 610  *  Name (_CPC, Package() {
 611  *      17,                                                     // NumEntries
 612  *      1,                                                      // Revision
 613  *      ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)},    // Highest Performance
 614  *      ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)},    // Nominal Performance
 615  *      ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)},    // Lowest Nonlinear Performance
 616  *      ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)},    // Lowest Performance
 617  *      ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)},    // Guaranteed Performance Register
 618  *      ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)},    // Desired Performance Register
 619  *      ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
 620  *      ...
 621  *      ...
 622  *      ...
 623  *  }
 624  * Each Register() encodes how to access that specific register.
 625  * e.g. a sample PCC entry has the following encoding:
 626  *
 627  *  Register (
 628  *      PCC,    // AddressSpaceKeyword
 629  *      8,      // RegisterBitWidth
 630  *      8,      // RegisterBitOffset
 631  *      0x30,   // RegisterAddress
 632  *      9,      // AccessSize (subspace ID)
 633  *  )
 634  */
 635
 636 #ifndef init_freq_invariance_cppc
 637 static inline void init_freq_invariance_cppc(void) { }
 638 #endif
 639
 640 /**
 641  * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
 642  * @pr: Ptr to acpi_processor containing this CPU's logical ID.
 643  *
 644  *      Return: 0 for success or negative value for err.
 645  */
 646 int acpi_cppc_processor_probe(struct acpi_processor *pr)
 647 {
 648         struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
 649         union acpi_object *out_obj, *cpc_obj;
 650         struct cpc_desc *cpc_ptr;
 651         struct cpc_reg *gas_t;
 652         struct device *cpu_dev;
 653         acpi_handle handle = pr->handle;
 654         unsigned int num_ent, i, cpc_rev;
 655         int pcc_subspace_id = -1;
 656         acpi_status status;
 657         int ret = -EFAULT;
 658
 659         /* Parse the ACPI _CPC table for this CPU. */
 660         status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
 661                         ACPI_TYPE_PACKAGE);
 662         if (ACPI_FAILURE(status)) {
 663                 ret = -ENODEV;
 664                 goto out_buf_free;
 665         }
 666
 667         out_obj = (union acpi_object *) output.pointer;
 668
 669         cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
 670         if (!cpc_ptr) {
 671                 ret = -ENOMEM;
 672                 goto out_buf_free;
 673         }
 674
 675         /* First entry is NumEntries. */
 676         cpc_obj = &out_obj->package.elements[0];
 677         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 678                 num_ent = cpc_obj->integer.value;
 679         } else {
 680                 pr_debug("Unexpected entry type(%d) for NumEntries\n",
 681                                 cpc_obj->type);
 682                 goto out_free;
 683         }
 684         cpc_ptr->num_entries = num_ent;
 685
 686         /* Second entry should be revision. */
 687         cpc_obj = &out_obj->package.elements[1];
 688         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 689                 cpc_rev = cpc_obj->integer.value;
 690         } else {
 691                 pr_debug("Unexpected entry type(%d) for Revision\n",
 692                                 cpc_obj->type);
 693                 goto out_free;
 694         }
 695         cpc_ptr->version = cpc_rev;
 696
 697         if (!is_cppc_supported(cpc_rev, num_ent))
 698                 goto out_free;
 699
 700         /* Iterate through remaining entries in _CPC */
 701         for (i = 2; i < num_ent; i++) {
 702                 cpc_obj = &out_obj->package.elements[i];
 703
 704                 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 705                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
 706                         cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
 707                 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
 708                         gas_t = (struct cpc_reg *)
 709                                 cpc_obj->buffer.pointer;
 710
 711                         /*
 712                          * The PCC Subspace index is encoded inside
 713                          * the CPC table entries. The same PCC index
 714                          * will be used for all the PCC entries,
 715                          * so extract it only once.
 716                          */
 717                         if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 718                                 if (pcc_subspace_id < 0) {
 719                                         pcc_subspace_id = gas_t->access_width;
 720                                         if (pcc_data_alloc(pcc_subspace_id))
 721                                                 goto out_free;
 722                                 } else if (pcc_subspace_id != gas_t->access_width) {
 723                                         pr_debug("Mismatched PCC ids.\n");
 724                                         goto out_free;
 725                                 }
 726                         } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 727                                 if (gas_t->address) {
 728                                         void __iomem *addr;
 729
 730                                         addr = ioremap(gas_t->address, gas_t->bit_width/8);
 731                                         if (!addr)
 732                                                 goto out_free;
 733                                         cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
 734                                 }
 735                         } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
 736                                 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
 737                                         /*
 738                                          * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
 739                                          * SystemIO doesn't implement 64-bit
 740                                          * registers.
 741                                          */
 742                                         pr_debug("Invalid access width %d for SystemIO register\n",
 743                                                 gas_t->access_width);
 744                                         goto out_free;
 745                                 }
 746                                 if (gas_t->address & OVER_16BTS_MASK) {
 747                                         /* SystemIO registers use 16-bit integer addresses */
 748                                         pr_debug("Invalid IO port %llu for SystemIO register\n",
 749                                                 gas_t->address);
 750                                         goto out_free;
 751                                 }
 752                         } else {
 753                                 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
 754                                         /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
 755                                         pr_debug("Unsupported register type: %d\n", gas_t->space_id);
 756                                         goto out_free;
 757                                 }
 758                         }
 759
 760                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
 761                         memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
 762                 } else {
 763                         pr_debug("Err in entry:%d in CPC table of CPU:%d\n", i, pr->id);
 764                         goto out_free;
 765                 }
 766         }
 767         per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
 768
 769         /*
 770          * Initialize the remaining cpc_regs as unsupported.
 771          * Example: In case FW exposes CPPC v2, the below loop will initialize
 772          * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
 773          */
 774         for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
 775                 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
 776                 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
 777         }
 778
 779
 780         /* Store CPU Logical ID */
 781         cpc_ptr->cpu_id = pr->id;
 782
 783         /* Parse PSD data for this CPU */
 784         ret = acpi_get_psd(cpc_ptr, handle);
 785         if (ret)
 786                 goto out_free;
 787
 788         /* Register PCC channel once for all PCC subspace ID. */
 789         if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
 790                 ret = register_pcc_channel(pcc_subspace_id);
 791                 if (ret)
 792                         goto out_free;
 793
 794                 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
 795                 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
 796         }
 797
 798         /* Everything looks okay */
 799         pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
 800
 801         /* Add per logical CPU nodes for reading its feedback counters. */
 802         cpu_dev = get_cpu_device(pr->id);
 803         if (!cpu_dev) {
 804                 ret = -EINVAL;
 805                 goto out_free;
 806         }
 807
 808         /* Plug PSD data into this CPU's CPC descriptor. */
 809         per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
 810
 811         ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
 812                         "acpi_cppc");
 813         if (ret) {
 814                 per_cpu(cpc_desc_ptr, pr->id) = NULL;
 815                 kobject_put(&cpc_ptr->kobj);
 816                 goto out_free;
 817         }
 818
 819         init_freq_invariance_cppc();
 820
 821         kfree(output.pointer);
 822         return 0;
 823
 824 out_free:
 825         /* Free all the mapped sys mem areas for this CPU */
 826         for (i = 2; i < cpc_ptr->num_entries; i++) {
 827                 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 828
 829                 if (addr)
 830                         iounmap(addr);
 831         }
 832         kfree(cpc_ptr);
 833
 834 out_buf_free:
 835         kfree(output.pointer);
 836         return ret;
 837 }
 838 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 839
 840 /**
 841  * acpi_cppc_processor_exit - Cleanup CPC structs.
 842  * @pr: Ptr to acpi_processor containing this CPU's logical ID.
 843  *
 844  * Return: Void
 845  */
 846 void acpi_cppc_processor_exit(struct acpi_processor *pr)
 847 {
 848         struct cpc_desc *cpc_ptr;
 849         unsigned int i;
 850         void __iomem *addr;
 851         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
 852
 853         if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
 854                 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
 855                         pcc_data[pcc_ss_id]->refcount--;
 856                         if (!pcc_data[pcc_ss_id]->refcount) {
 857                                 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
 858                                 kfree(pcc_data[pcc_ss_id]);
 859                                 pcc_data[pcc_ss_id] = NULL;
 860                         }
 861                 }
 862         }
 863
 864         cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
 865         if (!cpc_ptr)
 866                 return;
 867
 868         /* Free all the mapped sys mem areas for this CPU */
 869         for (i = 2; i < cpc_ptr->num_entries; i++) {
 870                 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 871                 if (addr)
 872                         iounmap(addr);
 873         }
 874
 875         kobject_put(&cpc_ptr->kobj);
 876         kfree(cpc_ptr);
 877 }
 878 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
 879
 880 /**
 881  * cpc_read_ffh() - Read FFH register
 882  * @cpunum:     CPU number to read
 883  * @reg:        cppc register information
 884  * @val:        place holder for return value
 885  *
 886  * Read bit_width bits from a specified address and bit_offset
 887  *
 888  * Return: 0 for success and error code
 889  */
 890 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
 891 {
 892         return -ENOTSUPP;
 893 }
 894
 895 /**
 896  * cpc_write_ffh() - Write FFH register
 897  * @cpunum:     CPU number to write
 898  * @reg:        cppc register information
 899  * @val:        value to write
 900  *
 901  * Write value of bit_width bits to a specified address and bit_offset
 902  *
 903  * Return: 0 for success and error code
 904  */
 905 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
 906 {
 907         return -ENOTSUPP;
 908 }
 909
 910 /*
 911  * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
 912  * as fast as possible. We have already mapped the PCC subspace during init, so
 913  * we can directly write to it.
 914  */
 915
 916 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 917 {
 918         int ret_val = 0;
 919         void __iomem *vaddr = NULL;
 920         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 921         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 922
 923         if (reg_res->type == ACPI_TYPE_INTEGER) {
 924                 *val = reg_res->cpc_entry.int_value;
 925                 return ret_val;
 926         }
 927
 928         *val = 0;
 929
 930         if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
 931                 u32 width = 8 << (reg->access_width - 1);
 932                 u32 val_u32;
 933                 acpi_status status;
 934
 935                 status = acpi_os_read_port((acpi_io_address)reg->address,
 936                                            &val_u32, width);
 937                 if (ACPI_FAILURE(status)) {
 938                         pr_debug("Error: Failed to read SystemIO port %llx\n",
 939                                  reg->address);
 940                         return -EFAULT;
 941                 }
 942
 943                 *val = val_u32;
 944                 return 0;
 945         } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
 946                 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
 947         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 948                 vaddr = reg_res->sys_mem_vaddr;
 949         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 950                 return cpc_read_ffh(cpu, reg, val);
 951         else
 952                 return acpi_os_read_memory((acpi_physical_address)reg->address,
 953                                 val, reg->bit_width);
 954
 955         switch (reg->bit_width) {
 956         case 8:
 957                 *val = readb_relaxed(vaddr);
 958                 break;
 959         case 16:
 960                 *val = readw_relaxed(vaddr);
 961                 break;
 962         case 32:
 963                 *val = readl_relaxed(vaddr);
 964                 break;
 965         case 64:
 966                 *val = readq_relaxed(vaddr);
 967                 break;
 968         default:
 969                 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
 970                          reg->bit_width, pcc_ss_id);
 971                 ret_val = -EFAULT;
 972         }
 973
 974         return ret_val;
 975 }
 976
 977 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 978 {
 979         int ret_val = 0;
 980         void __iomem *vaddr = NULL;
 981         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 982         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 983
 984         if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
 985                 u32 width = 8 << (reg->access_width - 1);
 986                 acpi_status status;
 987
 988                 status = acpi_os_write_port((acpi_io_address)reg->address,
 989                                             (u32)val, width);
 990                 if (ACPI_FAILURE(status)) {
 991                         pr_debug("Error: Failed to write SystemIO port %llx\n",
 992                                  reg->address);
 993                         return -EFAULT;
 994                 }
 995
 996                 return 0;
 997         } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
 998                 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
 999         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1000                 vaddr = reg_res->sys_mem_vaddr;
1001         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1002                 return cpc_write_ffh(cpu, reg, val);
1003         else
1004                 return acpi_os_write_memory((acpi_physical_address)reg->address,
1005                                 val, reg->bit_width);
1006
1007         switch (reg->bit_width) {
1008         case 8:
1009                 writeb_relaxed(val, vaddr);
1010                 break;
1011         case 16:
1012                 writew_relaxed(val, vaddr);
1013                 break;
1014         case 32:
1015                 writel_relaxed(val, vaddr);
1016                 break;
1017         case 64:
1018                 writeq_relaxed(val, vaddr);
1019                 break;
1020         default:
1021                 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1022                          reg->bit_width, pcc_ss_id);
1023                 ret_val = -EFAULT;
1024                 break;
1025         }
1026
1027         return ret_val;
1028 }
1029
1030 static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
1031 {
1032         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1033         struct cpc_register_resource *reg;
1034
1035         if (!cpc_desc) {
1036                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1037                 return -ENODEV;
1038         }
1039
1040         reg = &cpc_desc->cpc_regs[reg_idx];
1041
1042         if (CPC_IN_PCC(reg)) {
1043                 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1044                 struct cppc_pcc_data *pcc_ss_data = NULL;
1045                 int ret = 0;
1046
1047                 if (pcc_ss_id < 0)
1048                         return -EIO;
1049
1050                 pcc_ss_data = pcc_data[pcc_ss_id];
1051
1052                 down_write(&pcc_ss_data->pcc_lock);
1053
1054                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1055                         cpc_read(cpunum, reg, perf);
1056                 else
1057                         ret = -EIO;
1058
1059                 up_write(&pcc_ss_data->pcc_lock);
1060
1061                 return ret;
1062         }
1063
1064         cpc_read(cpunum, reg, perf);
1065
1066         return 0;
1067 }
1068
1069 /**
1070  * cppc_get_desired_perf - Get the desired performance register value.
1071  * @cpunum: CPU from which to get desired performance.
1072  * @desired_perf: Return address.
1073  *
1074  * Return: 0 for success, -EIO otherwise.
1075  */
1076 int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1077 {
1078         return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
1079 }
1080 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1081
1082 /**
1083  * cppc_get_nominal_perf - Get the nominal performance register value.
1084  * @cpunum: CPU from which to get nominal performance.
1085  * @nominal_perf: Return address.
1086  *
1087  * Return: 0 for success, -EIO otherwise.
1088  */
1089 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1090 {
1091         return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
1092 }
1093
1094 /**
1095  * cppc_get_perf_caps - Get a CPU's performance capabilities.
1096  * @cpunum: CPU from which to get capabilities info.
1097  * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1098  *
1099  * Return: 0 for success with perf_caps populated else -ERRNO.
1100  */
1101 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1102 {
1103         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1104         struct cpc_register_resource *highest_reg, *lowest_reg,
1105                 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1106                 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1107         u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1108         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1109         struct cppc_pcc_data *pcc_ss_data = NULL;
1110         int ret = 0, regs_in_pcc = 0;
1111
1112         if (!cpc_desc) {
1113                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1114                 return -ENODEV;
1115         }
1116
1117         highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1118         lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1119         lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1120         nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1121         low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1122         nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1123         guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1124
1125         /* Are any of the regs PCC ?*/
1126         if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1127                 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1128                 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1129                 if (pcc_ss_id < 0) {
1130                         pr_debug("Invalid pcc_ss_id\n");
1131                         return -ENODEV;
1132                 }
1133                 pcc_ss_data = pcc_data[pcc_ss_id];
1134                 regs_in_pcc = 1;
1135                 down_write(&pcc_ss_data->pcc_lock);
1136                 /* Ring doorbell once to update PCC subspace */
1137                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1138                         ret = -EIO;
1139                         goto out_err;
1140                 }
1141         }
1142
1143         cpc_read(cpunum, highest_reg, &high);
1144         perf_caps->highest_perf = high;
1145
1146         cpc_read(cpunum, lowest_reg, &low);
1147         perf_caps->lowest_perf = low;
1148
1149         cpc_read(cpunum, nominal_reg, &nom);
1150         perf_caps->nominal_perf = nom;
1151
1152         if (guaranteed_reg->type != ACPI_TYPE_BUFFER  ||
1153             IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1154                 perf_caps->guaranteed_perf = 0;
1155         } else {
1156                 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1157                 perf_caps->guaranteed_perf = guaranteed;
1158         }
1159
1160         cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1161         perf_caps->lowest_nonlinear_perf = min_nonlinear;
1162
1163         if (!high || !low || !nom || !min_nonlinear)
1164                 ret = -EFAULT;
1165
1166         /* Read optional lowest and nominal frequencies if present */
1167         if (CPC_SUPPORTED(low_freq_reg))
1168                 cpc_read(cpunum, low_freq_reg, &low_f);
1169
1170         if (CPC_SUPPORTED(nom_freq_reg))
1171                 cpc_read(cpunum, nom_freq_reg, &nom_f);
1172
1173         perf_caps->lowest_freq = low_f;
1174         perf_caps->nominal_freq = nom_f;
1175
1176
1177 out_err:
1178         if (regs_in_pcc)
1179                 up_write(&pcc_ss_data->pcc_lock);
1180         return ret;
1181 }
1182 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1183
1184 /**
1185  * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1186  * @cpunum: CPU from which to read counters.
1187  * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1188  *
1189  * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1190  */
1191 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1192 {
1193         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1194         struct cpc_register_resource *delivered_reg, *reference_reg,
1195                 *ref_perf_reg, *ctr_wrap_reg;
1196         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1197         struct cppc_pcc_data *pcc_ss_data = NULL;
1198         u64 delivered, reference, ref_perf, ctr_wrap_time;
1199         int ret = 0, regs_in_pcc = 0;
1200
1201         if (!cpc_desc) {
1202                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1203                 return -ENODEV;
1204         }
1205
1206         delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1207         reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1208         ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1209         ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1210
1211         /*
1212          * If reference perf register is not supported then we should
1213          * use the nominal perf value
1214          */
1215         if (!CPC_SUPPORTED(ref_perf_reg))
1216                 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1217
1218         /* Are any of the regs PCC ?*/
1219         if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1220                 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1221                 if (pcc_ss_id < 0) {
1222                         pr_debug("Invalid pcc_ss_id\n");
1223                         return -ENODEV;
1224                 }
1225                 pcc_ss_data = pcc_data[pcc_ss_id];
1226                 down_write(&pcc_ss_data->pcc_lock);
1227                 regs_in_pcc = 1;
1228                 /* Ring doorbell once to update PCC subspace */
1229                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1230                         ret = -EIO;
1231                         goto out_err;
1232                 }
1233         }
1234
1235         cpc_read(cpunum, delivered_reg, &delivered);
1236         cpc_read(cpunum, reference_reg, &reference);
1237         cpc_read(cpunum, ref_perf_reg, &ref_perf);
1238
1239         /*
1240          * Per spec, if ctr_wrap_time optional register is unsupported, then the
1241          * performance counters are assumed to never wrap during the lifetime of
1242          * platform
1243          */
1244         ctr_wrap_time = (u64)(~((u64)0));
1245         if (CPC_SUPPORTED(ctr_wrap_reg))
1246                 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1247
1248         if (!delivered || !reference || !ref_perf) {
1249                 ret = -EFAULT;
1250                 goto out_err;
1251         }
1252
1253         perf_fb_ctrs->delivered = delivered;
1254         perf_fb_ctrs->reference = reference;
1255         perf_fb_ctrs->reference_perf = ref_perf;
1256         perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1257 out_err:
1258         if (regs_in_pcc)
1259                 up_write(&pcc_ss_data->pcc_lock);
1260         return ret;
1261 }
1262 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1263
1264 /**
1265  * cppc_set_enable - Set to enable CPPC on the processor by writing the
1266  * Continuous Performance Control package EnableRegister field.
1267  * @cpu: CPU for which to enable CPPC register.
1268  * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1269  *
1270  * Return: 0 for success, -ERRNO or -EIO otherwise.
1271  */
1272 int cppc_set_enable(int cpu, bool enable)
1273 {
1274         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1275         struct cpc_register_resource *enable_reg;
1276         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1277         struct cppc_pcc_data *pcc_ss_data = NULL;
1278         int ret = -EINVAL;
1279
1280         if (!cpc_desc) {
1281                 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1282                 return -EINVAL;
1283         }
1284
1285         enable_reg = &cpc_desc->cpc_regs[ENABLE];
1286
1287         if (CPC_IN_PCC(enable_reg)) {
1288
1289                 if (pcc_ss_id < 0)
1290                         return -EIO;
1291
1292                 ret = cpc_write(cpu, enable_reg, enable);
1293                 if (ret)
1294                         return ret;
1295
1296                 pcc_ss_data = pcc_data[pcc_ss_id];
1297
1298                 down_write(&pcc_ss_data->pcc_lock);
1299                 /* after writing CPC, transfer the ownership of PCC to platfrom */
1300                 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1301                 up_write(&pcc_ss_data->pcc_lock);
1302                 return ret;
1303         }
1304
1305         return cpc_write(cpu, enable_reg, enable);
1306 }
1307 EXPORT_SYMBOL_GPL(cppc_set_enable);
1308
1309 /**
1310  * cppc_set_perf - Set a CPU's performance controls.
1311  * @cpu: CPU for which to set performance controls.
1312  * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1313  *
1314  * Return: 0 for success, -ERRNO otherwise.
1315  */
1316 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1317 {
1318         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1319         struct cpc_register_resource *desired_reg;
1320         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1321         struct cppc_pcc_data *pcc_ss_data = NULL;
1322         int ret = 0;
1323
1324         if (!cpc_desc) {
1325                 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1326                 return -ENODEV;
1327         }
1328
1329         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1330
1331         /*
1332          * This is Phase-I where we want to write to CPC registers
1333          * -> We want all CPUs to be able to execute this phase in parallel
1334          *
1335          * Since read_lock can be acquired by multiple CPUs simultaneously we
1336          * achieve that goal here
1337          */
1338         if (CPC_IN_PCC(desired_reg)) {
1339                 if (pcc_ss_id < 0) {
1340                         pr_debug("Invalid pcc_ss_id\n");
1341                         return -ENODEV;
1342                 }
1343                 pcc_ss_data = pcc_data[pcc_ss_id];
1344                 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1345                 if (pcc_ss_data->platform_owns_pcc) {
1346                         ret = check_pcc_chan(pcc_ss_id, false);
1347                         if (ret) {
1348                                 up_read(&pcc_ss_data->pcc_lock);
1349                                 return ret;
1350                         }
1351                 }
1352                 /*
1353                  * Update the pending_write to make sure a PCC CMD_READ will not
1354                  * arrive and steal the channel during the switch to write lock
1355                  */
1356                 pcc_ss_data->pending_pcc_write_cmd = true;
1357                 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1358                 cpc_desc->write_cmd_status = 0;
1359         }
1360
1361         /*
1362          * Skip writing MIN/MAX until Linux knows how to come up with
1363          * useful values.
1364          */
1365         cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1366
1367         if (CPC_IN_PCC(desired_reg))
1368                 up_read(&pcc_ss_data->pcc_lock);        /* END Phase-I */
1369         /*
1370          * This is Phase-II where we transfer the ownership of PCC to Platform
1371          *
1372          * Short Summary: Basically if we think of a group of cppc_set_perf
1373          * requests that happened in short overlapping interval. The last CPU to
1374          * come out of Phase-I will enter Phase-II and ring the doorbell.
1375          *
1376          * We have the following requirements for Phase-II:
1377          *     1. We want to execute Phase-II only when there are no CPUs
1378          * currently executing in Phase-I
1379          *     2. Once we start Phase-II we want to avoid all other CPUs from
1380          * entering Phase-I.
1381          *     3. We want only one CPU among all those who went through Phase-I
1382          * to run phase-II
1383          *
1384          * If write_trylock fails to get the lock and doesn't transfer the
1385          * PCC ownership to the platform, then one of the following will be TRUE
1386          *     1. There is at-least one CPU in Phase-I which will later execute
1387          * write_trylock, so the CPUs in Phase-I will be responsible for
1388          * executing the Phase-II.
1389          *     2. Some other CPU has beaten this CPU to successfully execute the
1390          * write_trylock and has already acquired the write_lock. We know for a
1391          * fact it (other CPU acquiring the write_lock) couldn't have happened
1392          * before this CPU's Phase-I as we held the read_lock.
1393          *     3. Some other CPU executing pcc CMD_READ has stolen the
1394          * down_write, in which case, send_pcc_cmd will check for pending
1395          * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1396          * So this CPU can be certain that its request will be delivered
1397          *    So in all cases, this CPU knows that its request will be delivered
1398          * by another CPU and can return
1399          *
1400          * After getting the down_write we still need to check for
1401          * pending_pcc_write_cmd to take care of the following scenario
1402          *    The thread running this code could be scheduled out between
1403          * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1404          * could have delivered the request to Platform by triggering the
1405          * doorbell and transferred the ownership of PCC to platform. So this
1406          * avoids triggering an unnecessary doorbell and more importantly before
1407          * triggering the doorbell it makes sure that the PCC channel ownership
1408          * is still with OSPM.
1409          *   pending_pcc_write_cmd can also be cleared by a different CPU, if
1410          * there was a pcc CMD_READ waiting on down_write and it steals the lock
1411          * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1412          * case during a CMD_READ and if there are pending writes it delivers
1413          * the write command before servicing the read command
1414          */
1415         if (CPC_IN_PCC(desired_reg)) {
1416                 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1417                         /* Update only if there are pending write commands */
1418                         if (pcc_ss_data->pending_pcc_write_cmd)
1419                                 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1420                         up_write(&pcc_ss_data->pcc_lock);       /* END Phase-II */
1421                 } else
1422                         /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1423                         wait_event(pcc_ss_data->pcc_write_wait_q,
1424                                    cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1425
1426                 /* send_pcc_cmd updates the status in case of failure */
1427                 ret = cpc_desc->write_cmd_status;
1428         }
1429         return ret;
1430 }
1431 EXPORT_SYMBOL_GPL(cppc_set_perf);
1432
1433 /**
1434  * cppc_get_transition_latency - returns frequency transition latency in ns
1435  *
1436  * ACPI CPPC does not explicitly specify how a platform can specify the
1437  * transition latency for performance change requests. The closest we have
1438  * is the timing information from the PCCT tables which provides the info
1439  * on the number and frequency of PCC commands the platform can handle.
1440  */
1441 unsigned int cppc_get_transition_latency(int cpu_num)
1442 {
1443         /*
1444          * Expected transition latency is based on the PCCT timing values
1445          * Below are definition from ACPI spec:
1446          * pcc_nominal- Expected latency to process a command, in microseconds
1447          * pcc_mpar   - The maximum number of periodic requests that the subspace
1448          *              channel can support, reported in commands per minute. 0
1449          *              indicates no limitation.
1450          * pcc_mrtt   - The minimum amount of time that OSPM must wait after the
1451          *              completion of a command before issuing the next command,
1452          *              in microseconds.
1453          */
1454         unsigned int latency_ns = 0;
1455         struct cpc_desc *cpc_desc;
1456         struct cpc_register_resource *desired_reg;
1457         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1458         struct cppc_pcc_data *pcc_ss_data;
1459
1460         cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1461         if (!cpc_desc)
1462                 return CPUFREQ_ETERNAL;
1463
1464         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1465         if (!CPC_IN_PCC(desired_reg))
1466                 return CPUFREQ_ETERNAL;
1467
1468         if (pcc_ss_id < 0)
1469                 return CPUFREQ_ETERNAL;
1470
1471         pcc_ss_data = pcc_data[pcc_ss_id];
1472         if (pcc_ss_data->pcc_mpar)
1473                 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1474
1475         latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1476         latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1477
1478         return latency_ns;
1479 }
1480 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);