drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/module.h>
  30 #include <linux/pagemap.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-buf.h>
  33
  34 #include <drm/amdgpu_drm.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_exec.h>
  37 #include <drm/drm_gem_ttm_helper.h>
  38 #include <drm/ttm/ttm_tt.h>
  39
  40 #include "amdgpu.h"
  41 #include "amdgpu_display.h"
  42 #include "amdgpu_dma_buf.h"
  43 #include "amdgpu_hmm.h"
  44 #include "amdgpu_xgmi.h"
  45
  46 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
  47
  48 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
  49 {
  50         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
  51         struct drm_device *ddev = bo->base.dev;
  52         vm_fault_t ret;
  53         int idx;
  54
  55         ret = ttm_bo_vm_reserve(bo, vmf);
  56         if (ret)
  57                 return ret;
  58
  59         if (drm_dev_enter(ddev, &idx)) {
  60                 ret = amdgpu_bo_fault_reserve_notify(bo);
  61                 if (ret) {
  62                         drm_dev_exit(idx);
  63                         goto unlock;
  64                 }
  65
  66                 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
  67                                                TTM_BO_VM_NUM_PREFAULT);
  68
  69                 drm_dev_exit(idx);
  70         } else {
  71                 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
  72         }
  73         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
  74                 return ret;
  75
  76 unlock:
  77         dma_resv_unlock(bo->base.resv);
  78         return ret;
  79 }
  80
  81 static const struct vm_operations_struct amdgpu_gem_vm_ops = {
  82         .fault = amdgpu_gem_fault,
  83         .open = ttm_bo_vm_open,
  84         .close = ttm_bo_vm_close,
  85         .access = ttm_bo_vm_access
  86 };
  87
  88 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  89 {
  90         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  91
  92         if (robj) {
  93                 amdgpu_hmm_unregister(robj);
  94                 amdgpu_bo_unref(&robj);
  95         }
  96 }
  97
  98 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  99                              int alignment, u32 initial_domain,
 100                              u64 flags, enum ttm_bo_type type,
 101                              struct dma_resv *resv,
 102                              struct drm_gem_object **obj, int8_t xcp_id_plus1)
 103 {
 104         struct amdgpu_bo *bo;
 105         struct amdgpu_bo_user *ubo;
 106         struct amdgpu_bo_param bp;
 107         int r;
 108
 109         memset(&bp, 0, sizeof(bp));
 110         *obj = NULL;
 111         flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
 112
 113         bp.size = size;
 114         bp.byte_align = alignment;
 115         bp.type = type;
 116         bp.resv = resv;
 117         bp.preferred_domain = initial_domain;
 118         bp.flags = flags;
 119         bp.domain = initial_domain;
 120         bp.bo_ptr_size = sizeof(struct amdgpu_bo);
 121         bp.xcp_id_plus1 = xcp_id_plus1;
 122
 123         r = amdgpu_bo_create_user(adev, &bp, &ubo);
 124         if (r)
 125                 return r;
 126
 127         bo = &ubo->bo;
 128         *obj = &bo->tbo.base;
 129         (*obj)->funcs = &amdgpu_gem_object_funcs;
 130
 131         return 0;
 132 }
 133
 134 void amdgpu_gem_force_release(struct amdgpu_device *adev)
 135 {
 136         struct drm_device *ddev = adev_to_drm(adev);
 137         struct drm_file *file;
 138
 139         mutex_lock(&ddev->filelist_mutex);
 140
 141         list_for_each_entry(file, &ddev->filelist, lhead) {
 142                 struct drm_gem_object *gobj;
 143                 int handle;
 144
 145                 WARN_ONCE(1, "Still active user space clients!\n");
 146                 spin_lock(&file->table_lock);
 147                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 148                         WARN_ONCE(1, "And also active allocations!\n");
 149                         drm_gem_object_put(gobj);
 150                 }
 151                 idr_destroy(&file->object_idr);
 152                 spin_unlock(&file->table_lock);
 153         }
 154
 155         mutex_unlock(&ddev->filelist_mutex);
 156 }
 157
 158 /*
 159  * Call from drm_gem_handle_create which appear in both new and open ioctl
 160  * case.
 161  */
 162 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
 163                                   struct drm_file *file_priv)
 164 {
 165         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 166         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 167         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 168         struct amdgpu_vm *vm = &fpriv->vm;
 169         struct amdgpu_bo_va *bo_va;
 170         struct mm_struct *mm;
 171         int r;
 172
 173         mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
 174         if (mm && mm != current->mm)
 175                 return -EPERM;
 176
 177         if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
 178             abo->tbo.base.resv != vm->root.bo->tbo.base.resv)
 179                 return -EPERM;
 180
 181         r = amdgpu_bo_reserve(abo, false);
 182         if (r)
 183                 return r;
 184
 185         bo_va = amdgpu_vm_bo_find(vm, abo);
 186         if (!bo_va)
 187                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 188         else
 189                 ++bo_va->ref_count;
 190         amdgpu_bo_unreserve(abo);
 191
 192         /* Validate and add eviction fence to DMABuf imports with dynamic
 193          * attachment in compute VMs. Re-validation will be done by
 194          * amdgpu_vm_validate. Fences are on the reservation shared with the
 195          * export, which is currently required to be validated and fenced
 196          * already by amdgpu_amdkfd_gpuvm_restore_process_bos.
 197          *
 198          * Nested locking below for the case that a GEM object is opened in
 199          * kfd_mem_export_dmabuf. Since the lock below is only taken for imports,
 200          * but not for export, this is a different lock class that cannot lead to
 201          * circular lock dependencies.
 202          */
 203         if (!vm->is_compute_context || !vm->process_info)
 204                 return 0;
 205         if (!obj->import_attach ||
 206             !dma_buf_is_dynamic(obj->import_attach->dmabuf))
 207                 return 0;
 208         mutex_lock_nested(&vm->process_info->lock, 1);
 209         if (!WARN_ON(!vm->process_info->eviction_fence)) {
 210                 r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT,
 211                                                         &vm->process_info->eviction_fence->base);
 212                 if (r) {
 213                         struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
 214
 215                         dev_warn(adev->dev, "validate_and_fence failed: %d\n", r);
 216                         if (ti) {
 217                                 dev_warn(adev->dev, "pid %d\n", ti->pid);
 218                                 amdgpu_vm_put_task_info(ti);
 219                         }
 220                 }
 221         }
 222         mutex_unlock(&vm->process_info->lock);
 223
 224         return r;
 225 }
 226
 227 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
 228                                     struct drm_file *file_priv)
 229 {
 230         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 231         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 232         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 233         struct amdgpu_vm *vm = &fpriv->vm;
 234
 235         struct dma_fence *fence = NULL;
 236         struct amdgpu_bo_va *bo_va;
 237         struct drm_exec exec;
 238         long r;
 239
 240         drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
 241         drm_exec_until_all_locked(&exec) {
 242                 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
 243                 drm_exec_retry_on_contention(&exec);
 244                 if (unlikely(r))
 245                         goto out_unlock;
 246
 247                 r = amdgpu_vm_lock_pd(vm, &exec, 0);
 248                 drm_exec_retry_on_contention(&exec);
 249                 if (unlikely(r))
 250                         goto out_unlock;
 251         }
 252
 253         bo_va = amdgpu_vm_bo_find(vm, bo);
 254         if (!bo_va || --bo_va->ref_count)
 255                 goto out_unlock;
 256
 257         amdgpu_vm_bo_del(adev, bo_va);
 258         if (!amdgpu_vm_ready(vm))
 259                 goto out_unlock;
 260
 261         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 262         if (unlikely(r < 0))
 263                 dev_err(adev->dev, "failed to clear page "
 264                         "tables on GEM object close (%ld)\n", r);
 265         if (r || !fence)
 266                 goto out_unlock;
 267
 268         amdgpu_bo_fence(bo, fence, true);
 269         dma_fence_put(fence);
 270
 271 out_unlock:
 272         if (r)
 273                 dev_err(adev->dev, "leaking bo va (%ld)\n", r);
 274         drm_exec_fini(&exec);
 275 }
 276
 277 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
 278 {
 279         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 280
 281         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 282                 return -EPERM;
 283         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 284                 return -EPERM;
 285
 286         /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
 287          * for debugger access to invisible VRAM. Should have used MAP_SHARED
 288          * instead. Clearing VM_MAYWRITE prevents the mapping from ever
 289          * becoming writable and makes is_cow_mapping(vm_flags) false.
 290          */
 291         if (is_cow_mapping(vma->vm_flags) &&
 292             !(vma->vm_flags & VM_ACCESS_FLAGS))
 293                 vm_flags_clear(vma, VM_MAYWRITE);
 294
 295         return drm_gem_ttm_mmap(obj, vma);
 296 }
 297
 298 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
 299         .free = amdgpu_gem_object_free,
 300         .open = amdgpu_gem_object_open,
 301         .close = amdgpu_gem_object_close,
 302         .export = amdgpu_gem_prime_export,
 303         .vmap = drm_gem_ttm_vmap,
 304         .vunmap = drm_gem_ttm_vunmap,
 305         .mmap = amdgpu_gem_object_mmap,
 306         .vm_ops = &amdgpu_gem_vm_ops,
 307 };
 308
 309 /*
 310  * GEM ioctls.
 311  */
 312 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 313                             struct drm_file *filp)
 314 {
 315         struct amdgpu_device *adev = drm_to_adev(dev);
 316         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 317         struct amdgpu_vm *vm = &fpriv->vm;
 318         union drm_amdgpu_gem_create *args = data;
 319         uint64_t flags = args->in.domain_flags;
 320         uint64_t size = args->in.bo_size;
 321         struct dma_resv *resv = NULL;
 322         struct drm_gem_object *gobj;
 323         uint32_t handle, initial_domain;
 324         int r;
 325
 326         /* reject DOORBELLs until userspace code to use it is available */
 327         if (args->in.domains & AMDGPU_GEM_DOMAIN_DOORBELL)
 328                 return -EINVAL;
 329
 330         /* reject invalid gem flags */
 331         if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 332                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 333                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 334                       AMDGPU_GEM_CREATE_VRAM_CLEARED |
 335                       AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
 336                       AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
 337                       AMDGPU_GEM_CREATE_ENCRYPTED |
 338                       AMDGPU_GEM_CREATE_DISCARDABLE))
 339                 return -EINVAL;
 340
 341         /* reject invalid gem domains */
 342         if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
 343                 return -EINVAL;
 344
 345         if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
 346                 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
 347                 return -EINVAL;
 348         }
 349
 350         /* create a gem object to contain this object in */
 351         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 352             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 353                 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 354                         /* if gds bo is created from user space, it must be
 355                          * passed to bo list
 356                          */
 357                         DRM_ERROR("GDS bo cannot be per-vm-bo\n");
 358                         return -EINVAL;
 359                 }
 360                 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 361         }
 362
 363         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 364                 r = amdgpu_bo_reserve(vm->root.bo, false);
 365                 if (r)
 366                         return r;
 367
 368                 resv = vm->root.bo->tbo.base.resv;
 369         }
 370
 371         initial_domain = (u32)(0xffffffff & args->in.domains);
 372 retry:
 373         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 374                                      initial_domain,
 375                                      flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);
 376         if (r && r != -ERESTARTSYS) {
 377                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
 378                         flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 379                         goto retry;
 380                 }
 381
 382                 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
 383                         initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
 384                         goto retry;
 385                 }
 386                 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
 387                                 size, initial_domain, args->in.alignment, r);
 388         }
 389
 390         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 391                 if (!r) {
 392                         struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
 393
 394                         abo->parent = amdgpu_bo_ref(vm->root.bo);
 395                 }
 396                 amdgpu_bo_unreserve(vm->root.bo);
 397         }
 398         if (r)
 399                 return r;
 400
 401         r = drm_gem_handle_create(filp, gobj, &handle);
 402         /* drop reference from allocate - handle holds it now */
 403         drm_gem_object_put(gobj);
 404         if (r)
 405                 return r;
 406
 407         memset(args, 0, sizeof(*args));
 408         args->out.handle = handle;
 409         return 0;
 410 }
 411
 412 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 413                              struct drm_file *filp)
 414 {
 415         struct ttm_operation_ctx ctx = { true, false };
 416         struct amdgpu_device *adev = drm_to_adev(dev);
 417         struct drm_amdgpu_gem_userptr *args = data;
 418         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 419         struct drm_gem_object *gobj;
 420         struct hmm_range *range;
 421         struct amdgpu_bo *bo;
 422         uint32_t handle;
 423         int r;
 424
 425         args->addr = untagged_addr(args->addr);
 426
 427         if (offset_in_page(args->addr | args->size))
 428                 return -EINVAL;
 429
 430         /* reject unknown flag values */
 431         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 432             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 433             AMDGPU_GEM_USERPTR_REGISTER))
 434                 return -EINVAL;
 435
 436         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 437              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 438
 439                 /* if we want to write to it we must install a MMU notifier */
 440                 return -EACCES;
 441         }
 442
 443         /* create a gem object to contain this object in */
 444         r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
 445                                      0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
 446         if (r)
 447                 return r;
 448
 449         bo = gem_to_amdgpu_bo(gobj);
 450         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
 451         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 452         r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
 453         if (r)
 454                 goto release_object;
 455
 456         r = amdgpu_hmm_register(bo, args->addr);
 457         if (r)
 458                 goto release_object;
 459
 460         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 461                 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
 462                                                  &range);
 463                 if (r)
 464                         goto release_object;
 465
 466                 r = amdgpu_bo_reserve(bo, true);
 467                 if (r)
 468                         goto user_pages_done;
 469
 470                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 471                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 472                 amdgpu_bo_unreserve(bo);
 473                 if (r)
 474                         goto user_pages_done;
 475         }
 476
 477         r = drm_gem_handle_create(filp, gobj, &handle);
 478         if (r)
 479                 goto user_pages_done;
 480
 481         args->handle = handle;
 482
 483 user_pages_done:
 484         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
 485                 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
 486
 487 release_object:
 488         drm_gem_object_put(gobj);
 489
 490         return r;
 491 }
 492
 493 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 494                           struct drm_device *dev,
 495                           uint32_t handle, uint64_t *offset_p)
 496 {
 497         struct drm_gem_object *gobj;
 498         struct amdgpu_bo *robj;
 499
 500         gobj = drm_gem_object_lookup(filp, handle);
 501         if (!gobj)
 502                 return -ENOENT;
 503
 504         robj = gem_to_amdgpu_bo(gobj);
 505         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 506             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 507                 drm_gem_object_put(gobj);
 508                 return -EPERM;
 509         }
 510         *offset_p = amdgpu_bo_mmap_offset(robj);
 511         drm_gem_object_put(gobj);
 512         return 0;
 513 }
 514
 515 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 516                           struct drm_file *filp)
 517 {
 518         union drm_amdgpu_gem_mmap *args = data;
 519         uint32_t handle = args->in.handle;
 520
 521         memset(args, 0, sizeof(*args));
 522         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 523 }
 524
 525 /**
 526  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 527  *
 528  * @timeout_ns: timeout in ns
 529  *
 530  * Calculate the timeout in jiffies from an absolute timeout in ns.
 531  */
 532 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 533 {
 534         unsigned long timeout_jiffies;
 535         ktime_t timeout;
 536
 537         /* clamp timeout if it's to large */
 538         if (((int64_t)timeout_ns) < 0)
 539                 return MAX_SCHEDULE_TIMEOUT;
 540
 541         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 542         if (ktime_to_ns(timeout) < 0)
 543                 return 0;
 544
 545         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 546         /*  clamp timeout to avoid unsigned-> signed overflow */
 547         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT)
 548                 return MAX_SCHEDULE_TIMEOUT - 1;
 549
 550         return timeout_jiffies;
 551 }
 552
 553 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 554                               struct drm_file *filp)
 555 {
 556         union drm_amdgpu_gem_wait_idle *args = data;
 557         struct drm_gem_object *gobj;
 558         struct amdgpu_bo *robj;
 559         uint32_t handle = args->in.handle;
 560         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 561         int r = 0;
 562         long ret;
 563
 564         gobj = drm_gem_object_lookup(filp, handle);
 565         if (!gobj)
 566                 return -ENOENT;
 567
 568         robj = gem_to_amdgpu_bo(gobj);
 569         ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
 570                                     true, timeout);
 571
 572         /* ret == 0 means not signaled,
 573          * ret > 0 means signaled
 574          * ret < 0 means interrupted before timeout
 575          */
 576         if (ret >= 0) {
 577                 memset(args, 0, sizeof(*args));
 578                 args->out.status = (ret == 0);
 579         } else
 580                 r = ret;
 581
 582         drm_gem_object_put(gobj);
 583         return r;
 584 }
 585
 586 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 587                                 struct drm_file *filp)
 588 {
 589         struct drm_amdgpu_gem_metadata *args = data;
 590         struct drm_gem_object *gobj;
 591         struct amdgpu_bo *robj;
 592         int r = -1;
 593
 594         DRM_DEBUG("%d\n", args->handle);
 595         gobj = drm_gem_object_lookup(filp, args->handle);
 596         if (gobj == NULL)
 597                 return -ENOENT;
 598         robj = gem_to_amdgpu_bo(gobj);
 599
 600         r = amdgpu_bo_reserve(robj, false);
 601         if (unlikely(r != 0))
 602                 goto out;
 603
 604         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 605                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 606                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 607                                            sizeof(args->data.data),
 608                                            &args->data.data_size_bytes,
 609                                            &args->data.flags);
 610         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 611                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 612                         r = -EINVAL;
 613                         goto unreserve;
 614                 }
 615                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 616                 if (!r)
 617                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 618                                                    args->data.data_size_bytes,
 619                                                    args->data.flags);
 620         }
 621
 622 unreserve:
 623         amdgpu_bo_unreserve(robj);
 624 out:
 625         drm_gem_object_put(gobj);
 626         return r;
 627 }
 628
 629 /**
 630  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 631  *
 632  * @adev: amdgpu_device pointer
 633  * @vm: vm to update
 634  * @bo_va: bo_va to update
 635  * @operation: map, unmap or clear
 636  *
 637  * Update the bo_va directly after setting its address. Errors are not
 638  * vital here, so they are not reported back to userspace.
 639  */
 640 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 641                                     struct amdgpu_vm *vm,
 642                                     struct amdgpu_bo_va *bo_va,
 643                                     uint32_t operation)
 644 {
 645         int r;
 646
 647         if (!amdgpu_vm_ready(vm))
 648                 return;
 649
 650         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 651         if (r)
 652                 goto error;
 653
 654         if (operation == AMDGPU_VA_OP_MAP ||
 655             operation == AMDGPU_VA_OP_REPLACE) {
 656                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 657                 if (r)
 658                         goto error;
 659         }
 660
 661         r = amdgpu_vm_update_pdes(adev, vm, false);
 662
 663 error:
 664         if (r && r != -ERESTARTSYS)
 665                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 666 }
 667
 668 /**
 669  * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
 670  *
 671  * @adev: amdgpu_device pointer
 672  * @flags: GEM UAPI flags
 673  *
 674  * Returns the GEM UAPI flags mapped into hardware for the ASIC.
 675  */
 676 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
 677 {
 678         uint64_t pte_flag = 0;
 679
 680         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 681                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 682         if (flags & AMDGPU_VM_PAGE_READABLE)
 683                 pte_flag |= AMDGPU_PTE_READABLE;
 684         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 685                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 686         if (flags & AMDGPU_VM_PAGE_PRT)
 687                 pte_flag |= AMDGPU_PTE_PRT;
 688         if (flags & AMDGPU_VM_PAGE_NOALLOC)
 689                 pte_flag |= AMDGPU_PTE_NOALLOC;
 690
 691         if (adev->gmc.gmc_funcs->map_mtype)
 692                 pte_flag |= amdgpu_gmc_map_mtype(adev,
 693                                                  flags & AMDGPU_VM_MTYPE_MASK);
 694
 695         return pte_flag;
 696 }
 697
 698 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 699                           struct drm_file *filp)
 700 {
 701         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 702                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 703                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
 704                 AMDGPU_VM_PAGE_NOALLOC;
 705         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 706                 AMDGPU_VM_PAGE_PRT;
 707
 708         struct drm_amdgpu_gem_va *args = data;
 709         struct drm_gem_object *gobj;
 710         struct amdgpu_device *adev = drm_to_adev(dev);
 711         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 712         struct amdgpu_bo *abo;
 713         struct amdgpu_bo_va *bo_va;
 714         struct drm_exec exec;
 715         uint64_t va_flags;
 716         uint64_t vm_size;
 717         int r = 0;
 718
 719         if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) {
 720                 dev_dbg(dev->dev,
 721                         "va_address 0x%llx is in reserved area 0x%llx\n",
 722                         args->va_address, AMDGPU_VA_RESERVED_BOTTOM);
 723                 return -EINVAL;
 724         }
 725
 726         if (args->va_address >= AMDGPU_GMC_HOLE_START &&
 727             args->va_address < AMDGPU_GMC_HOLE_END) {
 728                 dev_dbg(dev->dev,
 729                         "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n",
 730                         args->va_address, AMDGPU_GMC_HOLE_START,
 731                         AMDGPU_GMC_HOLE_END);
 732                 return -EINVAL;
 733         }
 734
 735         args->va_address &= AMDGPU_GMC_HOLE_MASK;
 736
 737         vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 738         vm_size -= AMDGPU_VA_RESERVED_TOP;
 739         if (args->va_address + args->map_size > vm_size) {
 740                 dev_dbg(dev->dev,
 741                         "va_address 0x%llx is in top reserved area 0x%llx\n",
 742                         args->va_address + args->map_size, vm_size);
 743                 return -EINVAL;
 744         }
 745
 746         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 747                 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
 748                         args->flags);
 749                 return -EINVAL;
 750         }
 751
 752         switch (args->operation) {
 753         case AMDGPU_VA_OP_MAP:
 754         case AMDGPU_VA_OP_UNMAP:
 755         case AMDGPU_VA_OP_CLEAR:
 756         case AMDGPU_VA_OP_REPLACE:
 757                 break;
 758         default:
 759                 dev_dbg(dev->dev, "unsupported operation %d\n",
 760                         args->operation);
 761                 return -EINVAL;
 762         }
 763
 764         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 765             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 766                 gobj = drm_gem_object_lookup(filp, args->handle);
 767                 if (gobj == NULL)
 768                         return -ENOENT;
 769                 abo = gem_to_amdgpu_bo(gobj);
 770         } else {
 771                 gobj = NULL;
 772                 abo = NULL;
 773         }
 774
 775         drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
 776                       DRM_EXEC_IGNORE_DUPLICATES, 0);
 777         drm_exec_until_all_locked(&exec) {
 778                 if (gobj) {
 779                         r = drm_exec_lock_obj(&exec, gobj);
 780                         drm_exec_retry_on_contention(&exec);
 781                         if (unlikely(r))
 782                                 goto error;
 783                 }
 784
 785                 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
 786                 drm_exec_retry_on_contention(&exec);
 787                 if (unlikely(r))
 788                         goto error;
 789         }
 790
 791         if (abo) {
 792                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 793                 if (!bo_va) {
 794                         r = -ENOENT;
 795                         goto error;
 796                 }
 797         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 798                 bo_va = fpriv->prt_va;
 799         } else {
 800                 bo_va = NULL;
 801         }
 802
 803         switch (args->operation) {
 804         case AMDGPU_VA_OP_MAP:
 805                 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
 806                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 807                                      args->offset_in_bo, args->map_size,
 808                                      va_flags);
 809                 break;
 810         case AMDGPU_VA_OP_UNMAP:
 811                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 812                 break;
 813
 814         case AMDGPU_VA_OP_CLEAR:
 815                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 816                                                 args->va_address,
 817                                                 args->map_size);
 818                 break;
 819         case AMDGPU_VA_OP_REPLACE:
 820                 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
 821                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 822                                              args->offset_in_bo, args->map_size,
 823                                              va_flags);
 824                 break;
 825         default:
 826                 break;
 827         }
 828         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm)
 829                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
 830                                         args->operation);
 831
 832 error:
 833         drm_exec_fini(&exec);
 834         drm_gem_object_put(gobj);
 835         return r;
 836 }
 837
 838 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 839                         struct drm_file *filp)
 840 {
 841         struct amdgpu_device *adev = drm_to_adev(dev);
 842         struct drm_amdgpu_gem_op *args = data;
 843         struct drm_gem_object *gobj;
 844         struct amdgpu_vm_bo_base *base;
 845         struct amdgpu_bo *robj;
 846         int r;
 847
 848         gobj = drm_gem_object_lookup(filp, args->handle);
 849         if (!gobj)
 850                 return -ENOENT;
 851
 852         robj = gem_to_amdgpu_bo(gobj);
 853
 854         r = amdgpu_bo_reserve(robj, false);
 855         if (unlikely(r))
 856                 goto out;
 857
 858         switch (args->op) {
 859         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 860                 struct drm_amdgpu_gem_create_in info;
 861                 void __user *out = u64_to_user_ptr(args->value);
 862
 863                 info.bo_size = robj->tbo.base.size;
 864                 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
 865                 info.domains = robj->preferred_domains;
 866                 info.domain_flags = robj->flags;
 867                 amdgpu_bo_unreserve(robj);
 868                 if (copy_to_user(out, &info, sizeof(info)))
 869                         r = -EFAULT;
 870                 break;
 871         }
 872         case AMDGPU_GEM_OP_SET_PLACEMENT:
 873                 if (robj->tbo.base.import_attach &&
 874                     args->value & AMDGPU_GEM_DOMAIN_VRAM) {
 875                         r = -EINVAL;
 876                         amdgpu_bo_unreserve(robj);
 877                         break;
 878                 }
 879                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 880                         r = -EPERM;
 881                         amdgpu_bo_unreserve(robj);
 882                         break;
 883                 }
 884                 for (base = robj->vm_bo; base; base = base->next)
 885                         if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
 886                                 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
 887                                 r = -EINVAL;
 888                                 amdgpu_bo_unreserve(robj);
 889                                 goto out;
 890                         }
 891
 892
 893                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 894                                                         AMDGPU_GEM_DOMAIN_GTT |
 895                                                         AMDGPU_GEM_DOMAIN_CPU);
 896                 robj->allowed_domains = robj->preferred_domains;
 897                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 898                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 899
 900                 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
 901                         amdgpu_vm_bo_invalidate(adev, robj, true);
 902
 903                 amdgpu_bo_unreserve(robj);
 904                 break;
 905         default:
 906                 amdgpu_bo_unreserve(robj);
 907                 r = -EINVAL;
 908         }
 909
 910 out:
 911         drm_gem_object_put(gobj);
 912         return r;
 913 }
 914
 915 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
 916                                   int width,
 917                                   int cpp,
 918                                   bool tiled)
 919 {
 920         int aligned = width;
 921         int pitch_mask = 0;
 922
 923         switch (cpp) {
 924         case 1:
 925                 pitch_mask = 255;
 926                 break;
 927         case 2:
 928                 pitch_mask = 127;
 929                 break;
 930         case 3:
 931         case 4:
 932                 pitch_mask = 63;
 933                 break;
 934         }
 935
 936         aligned += pitch_mask;
 937         aligned &= ~pitch_mask;
 938         return aligned * cpp;
 939 }
 940
 941 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 942                             struct drm_device *dev,
 943                             struct drm_mode_create_dumb *args)
 944 {
 945         struct amdgpu_device *adev = drm_to_adev(dev);
 946         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 947         struct drm_gem_object *gobj;
 948         uint32_t handle;
 949         u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 950                     AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 951                     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 952         u32 domain;
 953         int r;
 954
 955         /*
 956          * The buffer returned from this function should be cleared, but
 957          * it can only be done if the ring is enabled or we'll fail to
 958          * create the buffer.
 959          */
 960         if (adev->mman.buffer_funcs_enabled)
 961                 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
 962
 963         args->pitch = amdgpu_gem_align_pitch(adev, args->width,
 964                                              DIV_ROUND_UP(args->bpp, 8), 0);
 965         args->size = (u64)args->pitch * args->height;
 966         args->size = ALIGN(args->size, PAGE_SIZE);
 967         domain = amdgpu_bo_get_preferred_domain(adev,
 968                                 amdgpu_display_supported_domains(adev, flags));
 969         r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
 970                                      ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
 971         if (r)
 972                 return -ENOMEM;
 973
 974         r = drm_gem_handle_create(file_priv, gobj, &handle);
 975         /* drop reference from allocate - handle holds it now */
 976         drm_gem_object_put(gobj);
 977         if (r)
 978                 return r;
 979
 980         args->handle = handle;
 981         return 0;
 982 }
 983
 984 #if defined(CONFIG_DEBUG_FS)
 985 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
 986 {
 987         struct amdgpu_device *adev = m->private;
 988         struct drm_device *dev = adev_to_drm(adev);
 989         struct drm_file *file;
 990         int r;
 991
 992         r = mutex_lock_interruptible(&dev->filelist_mutex);
 993         if (r)
 994                 return r;
 995
 996         list_for_each_entry(file, &dev->filelist, lhead) {
 997                 struct task_struct *task;
 998                 struct drm_gem_object *gobj;
 999                 struct pid *pid;
1000                 int id;
1001
1002                 /*
1003                  * Although we have a valid reference on file->pid, that does
1004                  * not guarantee that the task_struct who called get_pid() is
1005                  * still alive (e.g. get_pid(current) => fork() => exit()).
1006                  * Therefore, we need to protect this ->comm access using RCU.
1007                  */
1008                 rcu_read_lock();
1009                 pid = rcu_dereference(file->pid);
1010                 task = pid_task(pid, PIDTYPE_TGID);
1011                 seq_printf(m, "pid %8d command %s:\n", pid_nr(pid),
1012                            task ? task->comm : "<unknown>");
1013                 rcu_read_unlock();
1014
1015                 spin_lock(&file->table_lock);
1016                 idr_for_each_entry(&file->object_idr, gobj, id) {
1017                         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
1018
1019                         amdgpu_bo_print_info(id, bo, m);
1020                 }
1021                 spin_unlock(&file->table_lock);
1022         }
1023
1024         mutex_unlock(&dev->filelist_mutex);
1025         return 0;
1026 }
1027
1028 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
1029
1030 #endif
1031
1032 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
1033 {
1034 #if defined(CONFIG_DEBUG_FS)
1035         struct drm_minor *minor = adev_to_drm(adev)->primary;
1036         struct dentry *root = minor->debugfs_root;
1037
1038         debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1039                             &amdgpu_debugfs_gem_info_fops);
1040 #endif
1041 }