drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string.h>
  27 #include <linux/acpi.h>
  28 #include <linux/i2c.h>
  29
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_edid.h>
  34
  35 #include "dm_services.h"
  36 #include "amdgpu.h"
  37 #include "dc.h"
  38 #include "amdgpu_dm.h"
  39 #include "amdgpu_dm_irq.h"
  40 #include "amdgpu_dm_mst_types.h"
  41 #include "dpcd_defs.h"
  42 #include "dc/inc/core_types.h"
  43
  44 #include "dm_helpers.h"
  45 #include "ddc_service_types.h"
  46
  47 static u32 edid_extract_panel_id(struct edid *edid)
  48 {
  49         return (u32)edid->mfg_id[0] << 24   |
  50                (u32)edid->mfg_id[1] << 16   |
  51                (u32)EDID_PRODUCT_ID(edid);
  52 }
  53
  54 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
  55 {
  56         uint32_t panel_id = edid_extract_panel_id(edid);
  57
  58         switch (panel_id) {
  59         /* Workaround for some monitors which does not work well with FAMS */
  60         case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
  61         case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
  62         case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
  63                 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
  64                 edid_caps->panel_patch.disable_fams = true;
  65                 break;
  66         default:
  67                 return;
  68         }
  69 }
  70
  71 /**
  72  * dm_helpers_parse_edid_caps() - Parse edid caps
  73  *
  74  * @link: current detected link
  75  * @edid:       [in] pointer to edid
  76  * @edid_caps:  [in] pointer to edid caps
  77  *
  78  * Return: void
  79  */
  80 enum dc_edid_status dm_helpers_parse_edid_caps(
  81                 struct dc_link *link,
  82                 const struct dc_edid *edid,
  83                 struct dc_edid_caps *edid_caps)
  84 {
  85         struct amdgpu_dm_connector *aconnector = link->priv;
  86         struct drm_connector *connector = &aconnector->base;
  87         struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
  88         struct cea_sad *sads;
  89         int sad_count = -1;
  90         int sadb_count = -1;
  91         int i = 0;
  92         uint8_t *sadb = NULL;
  93
  94         enum dc_edid_status result = EDID_OK;
  95
  96         if (!edid_caps || !edid)
  97                 return EDID_BAD_INPUT;
  98
  99         if (!drm_edid_is_valid(edid_buf))
 100                 result = EDID_BAD_CHECKSUM;
 101
 102         edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
 103                                         ((uint16_t) edid_buf->mfg_id[1])<<8;
 104         edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
 105                                         ((uint16_t) edid_buf->prod_code[1])<<8;
 106         edid_caps->serial_number = edid_buf->serial;
 107         edid_caps->manufacture_week = edid_buf->mfg_week;
 108         edid_caps->manufacture_year = edid_buf->mfg_year;
 109
 110         drm_edid_get_monitor_name(edid_buf,
 111                                   edid_caps->display_name,
 112                                   AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
 113
 114         edid_caps->edid_hdmi = connector->display_info.is_hdmi;
 115
 116         sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
 117         if (sad_count <= 0)
 118                 return result;
 119
 120         edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
 121         for (i = 0; i < edid_caps->audio_mode_count; ++i) {
 122                 struct cea_sad *sad = &sads[i];
 123
 124                 edid_caps->audio_modes[i].format_code = sad->format;
 125                 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
 126                 edid_caps->audio_modes[i].sample_rate = sad->freq;
 127                 edid_caps->audio_modes[i].sample_size = sad->byte2;
 128         }
 129
 130         sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
 131
 132         if (sadb_count < 0) {
 133                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
 134                 sadb_count = 0;
 135         }
 136
 137         if (sadb_count)
 138                 edid_caps->speaker_flags = sadb[0];
 139         else
 140                 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 141
 142         apply_edid_quirks(edid_buf, edid_caps);
 143
 144         kfree(sads);
 145         kfree(sadb);
 146
 147         return result;
 148 }
 149
 150 static void
 151 fill_dc_mst_payload_table_from_drm(struct dc_link *link,
 152                                    bool enable,
 153                                    struct drm_dp_mst_atomic_payload *target_payload,
 154                                    struct dc_dp_mst_stream_allocation_table *table)
 155 {
 156         struct dc_dp_mst_stream_allocation_table new_table = { 0 };
 157         struct dc_dp_mst_stream_allocation *sa;
 158         struct link_mst_stream_allocation_table copy_of_link_table =
 159                                                                                 link->mst_stream_alloc_table;
 160
 161         int i;
 162         int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
 163         struct link_mst_stream_allocation *dc_alloc;
 164
 165         /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
 166         if (enable) {
 167                 dc_alloc =
 168                 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
 169                 dc_alloc->vcp_id = target_payload->vcpi;
 170                 dc_alloc->slot_count = target_payload->time_slots;
 171         } else {
 172                 for (i = 0; i < copy_of_link_table.stream_count; i++) {
 173                         dc_alloc =
 174                         &copy_of_link_table.stream_allocations[i];
 175
 176                         if (dc_alloc->vcp_id == target_payload->vcpi) {
 177                                 dc_alloc->vcp_id = 0;
 178                                 dc_alloc->slot_count = 0;
 179                                 break;
 180                         }
 181                 }
 182                 ASSERT(i != copy_of_link_table.stream_count);
 183         }
 184
 185         /* Fill payload info*/
 186         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 187                 dc_alloc =
 188                         &copy_of_link_table.stream_allocations[i];
 189                 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
 190                         sa = &new_table.stream_allocations[new_table.stream_count];
 191                         sa->slot_count = dc_alloc->slot_count;
 192                         sa->vcp_id = dc_alloc->vcp_id;
 193                         new_table.stream_count++;
 194                 }
 195         }
 196
 197         /* Overwrite the old table */
 198         *table = new_table;
 199 }
 200
 201 void dm_helpers_dp_update_branch_info(
 202         struct dc_context *ctx,
 203         const struct dc_link *link)
 204 {}
 205
 206 static void dm_helpers_construct_old_payload(
 207                         struct drm_dp_mst_topology_mgr *mgr,
 208                         struct drm_dp_mst_topology_state *mst_state,
 209                         struct drm_dp_mst_atomic_payload *new_payload,
 210                         struct drm_dp_mst_atomic_payload *old_payload)
 211 {
 212         struct drm_dp_mst_atomic_payload *pos;
 213         int pbn_per_slot = mst_state->pbn_div;
 214         u8 next_payload_vc_start = mgr->next_start_slot;
 215         u8 payload_vc_start = new_payload->vc_start_slot;
 216         u8 allocated_time_slots;
 217
 218         *old_payload = *new_payload;
 219
 220         /* Set correct time_slots/PBN of old payload.
 221          * other fields (delete & dsc_enabled) in
 222          * struct drm_dp_mst_atomic_payload are don't care fields
 223          * while calling drm_dp_remove_payload_part2()
 224          */
 225         list_for_each_entry(pos, &mst_state->payloads, next) {
 226                 if (pos != new_payload &&
 227                     pos->vc_start_slot > payload_vc_start &&
 228                     pos->vc_start_slot < next_payload_vc_start)
 229                         next_payload_vc_start = pos->vc_start_slot;
 230         }
 231
 232         allocated_time_slots = next_payload_vc_start - payload_vc_start;
 233
 234         old_payload->time_slots = allocated_time_slots;
 235         old_payload->pbn = allocated_time_slots * pbn_per_slot;
 236 }
 237
 238 /*
 239  * Writes payload allocation table in immediate downstream device.
 240  */
 241 bool dm_helpers_dp_mst_write_payload_allocation_table(
 242                 struct dc_context *ctx,
 243                 const struct dc_stream_state *stream,
 244                 struct dc_dp_mst_stream_allocation_table *proposed_table,
 245                 bool enable)
 246 {
 247         struct amdgpu_dm_connector *aconnector;
 248         struct drm_dp_mst_topology_state *mst_state;
 249         struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
 250         struct drm_dp_mst_topology_mgr *mst_mgr;
 251
 252         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 253         /* Accessing the connector state is required for vcpi_slots allocation
 254          * and directly relies on behaviour in commit check
 255          * that blocks before commit guaranteeing that the state
 256          * is not gonna be swapped while still in use in commit tail
 257          */
 258
 259         if (!aconnector || !aconnector->mst_root)
 260                 return false;
 261
 262         mst_mgr = &aconnector->mst_root->mst_mgr;
 263         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 264         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 265
 266         if (enable) {
 267                 target_payload = new_payload;
 268
 269                 /* It's OK for this to fail */
 270                 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
 271         } else {
 272                 /* construct old payload by VCPI*/
 273                 dm_helpers_construct_old_payload(mst_mgr, mst_state,
 274                                                  new_payload, &old_payload);
 275                 target_payload = &old_payload;
 276
 277                 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload);
 278         }
 279
 280         /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 281          * AUX message. The sequence is slot 1-63 allocated sequence for each
 282          * stream. AMD ASIC stream slot allocation should follow the same
 283          * sequence. copy DRM MST allocation to dc
 284          */
 285         fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
 286
 287         return true;
 288 }
 289
 290 /*
 291  * poll pending down reply
 292  */
 293 void dm_helpers_dp_mst_poll_pending_down_reply(
 294         struct dc_context *ctx,
 295         const struct dc_link *link)
 296 {}
 297
 298 /*
 299  * Clear payload allocation table before enable MST DP link.
 300  */
 301 void dm_helpers_dp_mst_clear_payload_allocation_table(
 302         struct dc_context *ctx,
 303         const struct dc_link *link)
 304 {}
 305
 306 /*
 307  * Polls for ACT (allocation change trigger) handled and sends
 308  * ALLOCATE_PAYLOAD message.
 309  */
 310 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 311                 struct dc_context *ctx,
 312                 const struct dc_stream_state *stream)
 313 {
 314         struct amdgpu_dm_connector *aconnector;
 315         struct drm_dp_mst_topology_mgr *mst_mgr;
 316         int ret;
 317
 318         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 319
 320         if (!aconnector || !aconnector->mst_root)
 321                 return ACT_FAILED;
 322
 323         mst_mgr = &aconnector->mst_root->mst_mgr;
 324
 325         if (!mst_mgr->mst_state)
 326                 return ACT_FAILED;
 327
 328         ret = drm_dp_check_act_status(mst_mgr);
 329
 330         if (ret)
 331                 return ACT_FAILED;
 332
 333         return ACT_SUCCESS;
 334 }
 335
 336 bool dm_helpers_dp_mst_send_payload_allocation(
 337                 struct dc_context *ctx,
 338                 const struct dc_stream_state *stream,
 339                 bool enable)
 340 {
 341         struct amdgpu_dm_connector *aconnector;
 342         struct drm_dp_mst_topology_state *mst_state;
 343         struct drm_dp_mst_topology_mgr *mst_mgr;
 344         struct drm_dp_mst_atomic_payload *new_payload, old_payload;
 345         enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
 346         enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 347         int ret = 0;
 348
 349         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 350
 351         if (!aconnector || !aconnector->mst_root)
 352                 return false;
 353
 354         mst_mgr = &aconnector->mst_root->mst_mgr;
 355         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 356
 357         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 358
 359         if (!enable) {
 360                 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 361                 clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
 362         }
 363
 364         if (enable) {
 365                 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload);
 366         } else {
 367                 dm_helpers_construct_old_payload(mst_mgr, mst_state,
 368                                                  new_payload, &old_payload);
 369                 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload);
 370         }
 371
 372         if (ret) {
 373                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 374                         set_flag, false);
 375         } else {
 376                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 377                         set_flag, true);
 378                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 379                         clr_flag, false);
 380         }
 381
 382         return true;
 383 }
 384
 385 void dm_dtn_log_begin(struct dc_context *ctx,
 386         struct dc_log_buffer_ctx *log_ctx)
 387 {
 388         static const char msg[] = "[dtn begin]\n";
 389
 390         if (!log_ctx) {
 391                 pr_info("%s", msg);
 392                 return;
 393         }
 394
 395         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 396 }
 397
 398 __printf(3, 4)
 399 void dm_dtn_log_append_v(struct dc_context *ctx,
 400         struct dc_log_buffer_ctx *log_ctx,
 401         const char *msg, ...)
 402 {
 403         va_list args;
 404         size_t total;
 405         int n;
 406
 407         if (!log_ctx) {
 408                 /* No context, redirect to dmesg. */
 409                 struct va_format vaf;
 410
 411                 vaf.fmt = msg;
 412                 vaf.va = &args;
 413
 414                 va_start(args, msg);
 415                 pr_info("%pV", &vaf);
 416                 va_end(args);
 417
 418                 return;
 419         }
 420
 421         /* Measure the output. */
 422         va_start(args, msg);
 423         n = vsnprintf(NULL, 0, msg, args);
 424         va_end(args);
 425
 426         if (n <= 0)
 427                 return;
 428
 429         /* Reallocate the string buffer as needed. */
 430         total = log_ctx->pos + n + 1;
 431
 432         if (total > log_ctx->size) {
 433                 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
 434
 435                 if (buf) {
 436                         memcpy(buf, log_ctx->buf, log_ctx->pos);
 437                         kfree(log_ctx->buf);
 438
 439                         log_ctx->buf = buf;
 440                         log_ctx->size = total;
 441                 }
 442         }
 443
 444         if (!log_ctx->buf)
 445                 return;
 446
 447         /* Write the formatted string to the log buffer. */
 448         va_start(args, msg);
 449         n = vscnprintf(
 450                 log_ctx->buf + log_ctx->pos,
 451                 log_ctx->size - log_ctx->pos,
 452                 msg,
 453                 args);
 454         va_end(args);
 455
 456         if (n > 0)
 457                 log_ctx->pos += n;
 458 }
 459
 460 void dm_dtn_log_end(struct dc_context *ctx,
 461         struct dc_log_buffer_ctx *log_ctx)
 462 {
 463         static const char msg[] = "[dtn end]\n";
 464
 465         if (!log_ctx) {
 466                 pr_info("%s", msg);
 467                 return;
 468         }
 469
 470         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 471 }
 472
 473 bool dm_helpers_dp_mst_start_top_mgr(
 474                 struct dc_context *ctx,
 475                 const struct dc_link *link,
 476                 bool boot)
 477 {
 478         struct amdgpu_dm_connector *aconnector = link->priv;
 479         int ret;
 480
 481         if (!aconnector) {
 482                 DRM_ERROR("Failed to find connector for link!");
 483                 return false;
 484         }
 485
 486         if (boot) {
 487                 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
 488                                         aconnector, aconnector->base.base.id);
 489                 return true;
 490         }
 491
 492         DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 493                         aconnector, aconnector->base.base.id);
 494
 495         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 496         if (ret < 0) {
 497                 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
 498                 return false;
 499         }
 500
 501         DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
 502                 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
 503
 504         return true;
 505 }
 506
 507 bool dm_helpers_dp_mst_stop_top_mgr(
 508                 struct dc_context *ctx,
 509                 struct dc_link *link)
 510 {
 511         struct amdgpu_dm_connector *aconnector = link->priv;
 512
 513         if (!aconnector) {
 514                 DRM_ERROR("Failed to find connector for link!");
 515                 return false;
 516         }
 517
 518         DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
 519                         aconnector, aconnector->base.base.id);
 520
 521         if (aconnector->mst_mgr.mst_state == true) {
 522                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 523                 link->cur_link_settings.lane_count = 0;
 524         }
 525
 526         return false;
 527 }
 528
 529 bool dm_helpers_dp_read_dpcd(
 530                 struct dc_context *ctx,
 531                 const struct dc_link *link,
 532                 uint32_t address,
 533                 uint8_t *data,
 534                 uint32_t size)
 535 {
 536
 537         struct amdgpu_dm_connector *aconnector = link->priv;
 538
 539         if (!aconnector) {
 540                 DC_LOG_DC("Failed to find connector for link!\n");
 541                 return false;
 542         }
 543
 544         return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
 545                                 size) == size;
 546 }
 547
 548 bool dm_helpers_dp_write_dpcd(
 549                 struct dc_context *ctx,
 550                 const struct dc_link *link,
 551                 uint32_t address,
 552                 const uint8_t *data,
 553                 uint32_t size)
 554 {
 555         struct amdgpu_dm_connector *aconnector = link->priv;
 556
 557         if (!aconnector) {
 558                 DRM_ERROR("Failed to find connector for link!");
 559                 return false;
 560         }
 561
 562         return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
 563                         address, (uint8_t *)data, size) > 0;
 564 }
 565
 566 bool dm_helpers_submit_i2c(
 567                 struct dc_context *ctx,
 568                 const struct dc_link *link,
 569                 struct i2c_command *cmd)
 570 {
 571         struct amdgpu_dm_connector *aconnector = link->priv;
 572         struct i2c_msg *msgs;
 573         int i = 0;
 574         int num = cmd->number_of_payloads;
 575         bool result;
 576
 577         if (!aconnector) {
 578                 DRM_ERROR("Failed to find connector for link!");
 579                 return false;
 580         }
 581
 582         msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
 583
 584         if (!msgs)
 585                 return false;
 586
 587         for (i = 0; i < num; i++) {
 588                 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 589                 msgs[i].addr = cmd->payloads[i].address;
 590                 msgs[i].len = cmd->payloads[i].length;
 591                 msgs[i].buf = cmd->payloads[i].data;
 592         }
 593
 594         result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
 595
 596         kfree(msgs);
 597
 598         return result;
 599 }
 600
 601 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
 602                 bool is_write_cmd,
 603                 unsigned char cmd,
 604                 unsigned int length,
 605                 unsigned int offset,
 606                 unsigned char *data)
 607 {
 608         bool success = false;
 609         unsigned char rc_data[16] = {0};
 610         unsigned char rc_offset[4] = {0};
 611         unsigned char rc_length[2] = {0};
 612         unsigned char rc_cmd = 0;
 613         unsigned char rc_result = 0xFF;
 614         unsigned char i = 0;
 615         int ret;
 616
 617         if (is_write_cmd) {
 618                 // write rc data
 619                 memmove(rc_data, data, length);
 620                 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
 621         }
 622
 623         // write rc offset
 624         rc_offset[0] = (unsigned char) offset & 0xFF;
 625         rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
 626         rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
 627         rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
 628         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
 629
 630         // write rc length
 631         rc_length[0] = (unsigned char) length & 0xFF;
 632         rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
 633         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
 634
 635         // write rc cmd
 636         rc_cmd = cmd | 0x80;
 637         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 638
 639         if (ret < 0) {
 640                 DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);
 641                 return false;
 642         }
 643
 644         // poll until active is 0
 645         for (i = 0; i < 10; i++) {
 646                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 647                 if (rc_cmd == cmd)
 648                         // active is 0
 649                         break;
 650                 msleep(10);
 651         }
 652
 653         // read rc result
 654         drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
 655         success = (rc_result == 0);
 656
 657         if (success && !is_write_cmd) {
 658                 // read rc data
 659                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
 660         }
 661
 662         DC_LOG_DC("%s: success = %d\n", __func__, success);
 663
 664         return success;
 665 }
 666
 667 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
 668 {
 669         unsigned char data[16] = {0};
 670
 671         DC_LOG_DC("Start %s\n", __func__);
 672
 673         // Step 2
 674         data[0] = 'P';
 675         data[1] = 'R';
 676         data[2] = 'I';
 677         data[3] = 'U';
 678         data[4] = 'S';
 679
 680         if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
 681                 return;
 682
 683         // Step 3 and 4
 684         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 685                 return;
 686
 687         data[0] &= (~(1 << 1)); // set bit 1 to 0
 688         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 689                 return;
 690
 691         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 692                 return;
 693
 694         data[0] &= (~(1 << 1)); // set bit 1 to 0
 695         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
 696                 return;
 697
 698         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 699                 return;
 700
 701         data[0] &= (~(1 << 1)); // set bit 1 to 0
 702         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 703                 return;
 704
 705         // Step 3 and 5
 706         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 707                 return;
 708
 709         data[0] |= (1 << 1); // set bit 1 to 1
 710         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 711                 return;
 712
 713         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 714                 return;
 715
 716         data[0] |= (1 << 1); // set bit 1 to 1
 717
 718         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 719                 return;
 720
 721         data[0] |= (1 << 1); // set bit 1 to 1
 722         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 723                 return;
 724
 725         // Step 6
 726         if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
 727                 return;
 728
 729         DC_LOG_DC("Done %s\n", __func__);
 730 }
 731
 732 /* MST Dock */
 733 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 734
 735 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 736                 struct drm_dp_aux *aux,
 737                 const struct dc_stream_state *stream,
 738                 bool enable)
 739 {
 740         uint8_t ret = 0;
 741
 742         DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n");
 743
 744         if (enable) {
 745                 /* When DSC is enabled on previous boot and reboot with the hub,
 746                  * there is a chance that Synaptics hub gets stuck during reboot sequence.
 747                  * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
 748                  */
 749                 if (!stream->link->link_status.link_active &&
 750                         memcmp(stream->link->dpcd_caps.branch_dev_name,
 751                                 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
 752                         apply_synaptics_fifo_reset_wa(aux);
 753
 754                 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 755                 DRM_INFO("Send DSC enable to synaptics\n");
 756
 757         } else {
 758                 /* Synaptics hub not support virtual dpcd,
 759                  * external monitor occur garbage while disable DSC,
 760                  * Disable DSC only when entire link status turn to false,
 761                  */
 762                 if (!stream->link->link_status.link_active) {
 763                         ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 764                         DRM_INFO("Send DSC disable to synaptics\n");
 765                 }
 766         }
 767
 768         return ret;
 769 }
 770
 771 bool dm_helpers_dp_write_dsc_enable(
 772                 struct dc_context *ctx,
 773                 const struct dc_stream_state *stream,
 774                 bool enable)
 775 {
 776         static const uint8_t DSC_DISABLE;
 777         static const uint8_t DSC_DECODING = 0x01;
 778         static const uint8_t DSC_PASSTHROUGH = 0x02;
 779
 780         struct amdgpu_dm_connector *aconnector;
 781         struct drm_dp_mst_port *port;
 782         uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
 783         uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
 784         uint8_t ret = 0;
 785
 786         if (!stream)
 787                 return false;
 788
 789         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 790                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 791
 792                 if (!aconnector->dsc_aux)
 793                         return false;
 794
 795                 // apply w/a to synaptics
 796                 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
 797                     (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
 798                         return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 799                                 aconnector->dsc_aux, stream, enable_dsc);
 800
 801                 port = aconnector->mst_output_port;
 802
 803                 if (enable) {
 804                         if (port->passthrough_aux) {
 805                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 806                                                         DP_DSC_ENABLE,
 807                                                         &enable_passthrough, 1);
 808                                 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
 809                                           ret);
 810                         }
 811
 812                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 813                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 814                         DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n",
 815                                   (port->passthrough_aux) ? "remote RX" :
 816                                   "virtual dpcd",
 817                                   ret);
 818                 } else {
 819                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 820                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 821                         DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n",
 822                                   (port->passthrough_aux) ? "remote RX" :
 823                                   "virtual dpcd",
 824                                   ret);
 825
 826                         if (port->passthrough_aux) {
 827                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 828                                                         DP_DSC_ENABLE,
 829                                                         &enable_passthrough, 1);
 830                                 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
 831                                           ret);
 832                         }
 833                 }
 834         }
 835
 836         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
 837                 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
 838                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 839                         DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable");
 840                 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
 841                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 842                         DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable");
 843                 }
 844         }
 845
 846         return ret;
 847 }
 848
 849 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 850 {
 851         bool dp_sink_present;
 852         struct amdgpu_dm_connector *aconnector = link->priv;
 853
 854         if (!aconnector) {
 855                 BUG_ON("Failed to find connector for link!");
 856                 return true;
 857         }
 858
 859         mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
 860         dp_sink_present = dc_link_is_dp_sink_present(link);
 861         mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
 862         return dp_sink_present;
 863 }
 864
 865 enum dc_edid_status dm_helpers_read_local_edid(
 866                 struct dc_context *ctx,
 867                 struct dc_link *link,
 868                 struct dc_sink *sink)
 869 {
 870         struct amdgpu_dm_connector *aconnector = link->priv;
 871         struct drm_connector *connector = &aconnector->base;
 872         struct i2c_adapter *ddc;
 873         int retry = 3;
 874         enum dc_edid_status edid_status;
 875         struct edid *edid;
 876
 877         if (link->aux_mode)
 878                 ddc = &aconnector->dm_dp_aux.aux.ddc;
 879         else
 880                 ddc = &aconnector->i2c->base;
 881
 882         /* some dongles read edid incorrectly the first time,
 883          * do check sum and retry to make sure read correct edid.
 884          */
 885         do {
 886
 887                 edid = drm_get_edid(&aconnector->base, ddc);
 888
 889                 /* DP Compliance Test 4.2.2.6 */
 890                 if (link->aux_mode && connector->edid_corrupt)
 891                         drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
 892
 893                 if (!edid && connector->edid_corrupt) {
 894                         connector->edid_corrupt = false;
 895                         return EDID_BAD_CHECKSUM;
 896                 }
 897
 898                 if (!edid)
 899                         return EDID_NO_RESPONSE;
 900
 901                 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
 902                 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
 903
 904                 /* We don't need the original edid anymore */
 905                 kfree(edid);
 906
 907                 edid_status = dm_helpers_parse_edid_caps(
 908                                                 link,
 909                                                 &sink->dc_edid,
 910                                                 &sink->edid_caps);
 911
 912         } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
 913
 914         if (edid_status != EDID_OK)
 915                 DRM_ERROR("EDID err: %d, on connector: %s",
 916                                 edid_status,
 917                                 aconnector->base.name);
 918         if (link->aux_mode) {
 919                 union test_request test_request = {0};
 920                 union test_response test_response = {0};
 921
 922                 dm_helpers_dp_read_dpcd(ctx,
 923                                         link,
 924                                         DP_TEST_REQUEST,
 925                                         &test_request.raw,
 926                                         sizeof(union test_request));
 927
 928                 if (!test_request.bits.EDID_READ)
 929                         return edid_status;
 930
 931                 test_response.bits.EDID_CHECKSUM_WRITE = 1;
 932
 933                 dm_helpers_dp_write_dpcd(ctx,
 934                                         link,
 935                                         DP_TEST_EDID_CHECKSUM,
 936                                         &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
 937                                         1);
 938
 939                 dm_helpers_dp_write_dpcd(ctx,
 940                                         link,
 941                                         DP_TEST_RESPONSE,
 942                                         &test_response.raw,
 943                                         sizeof(test_response));
 944
 945         }
 946
 947         return edid_status;
 948 }
 949 int dm_helper_dmub_aux_transfer_sync(
 950                 struct dc_context *ctx,
 951                 const struct dc_link *link,
 952                 struct aux_payload *payload,
 953                 enum aux_return_code_type *operation_result)
 954 {
 955         return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
 956                         operation_result);
 957 }
 958
 959 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
 960                 const struct dc_link *link,
 961                 struct set_config_cmd_payload *payload,
 962                 enum set_config_status *operation_result)
 963 {
 964         return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
 965                         operation_result);
 966 }
 967
 968 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 969 {
 970         /* TODO: something */
 971 }
 972
 973 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
 974 {
 975         // TODO:
 976         //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
 977 }
 978
 979 void dm_helpers_init_panel_settings(
 980         struct dc_context *ctx,
 981         struct dc_panel_config *panel_config,
 982         struct dc_sink *sink)
 983 {
 984         // Extra Panel Power Sequence
 985         panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 986         panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
 987         panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
 988         panel_config->pps.extra_post_t7_ms = 0;
 989         panel_config->pps.extra_pre_t11_ms = 0;
 990         panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
 991         panel_config->pps.extra_post_OUI_ms = 0;
 992         // Feature DSC
 993         panel_config->dsc.disable_dsc_edp = false;
 994         panel_config->dsc.force_dsc_edp_policy = 0;
 995 }
 996
 997 void dm_helpers_override_panel_settings(
 998         struct dc_context *ctx,
 999         struct dc_panel_config *panel_config)
1000 {
1001         // Feature DSC
1002         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1003                 panel_config->dsc.disable_dsc_edp = true;
1004 }
1005
1006 void *dm_helpers_allocate_gpu_mem(
1007                 struct dc_context *ctx,
1008                 enum dc_gpu_mem_alloc_type type,
1009                 size_t size,
1010                 long long *addr)
1011 {
1012         struct amdgpu_device *adev = ctx->driver_context;
1013         struct dal_allocation *da;
1014         u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
1015                 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
1016         int ret;
1017
1018         da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
1019         if (!da)
1020                 return NULL;
1021
1022         ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
1023                                       domain, &da->bo,
1024                                       &da->gpu_addr, &da->cpu_ptr);
1025
1026         *addr = da->gpu_addr;
1027
1028         if (ret) {
1029                 kfree(da);
1030                 return NULL;
1031         }
1032
1033         /* add da to list in dm */
1034         list_add(&da->list, &adev->dm.da_list);
1035
1036         return da->cpu_ptr;
1037 }
1038
1039 void dm_helpers_free_gpu_mem(
1040                 struct dc_context *ctx,
1041                 enum dc_gpu_mem_alloc_type type,
1042                 void *pvMem)
1043 {
1044         struct amdgpu_device *adev = ctx->driver_context;
1045         struct dal_allocation *da;
1046
1047         /* walk the da list in DM */
1048         list_for_each_entry(da, &adev->dm.da_list, list) {
1049                 if (pvMem == da->cpu_ptr) {
1050                         amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
1051                         list_del(&da->list);
1052                         kfree(da);
1053                         break;
1054                 }
1055         }
1056 }
1057
1058 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
1059 {
1060         enum dc_irq_source irq_source;
1061         bool ret;
1062
1063         irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
1064
1065         ret = dc_interrupt_set(ctx->dc, irq_source, enable);
1066
1067         DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1068                          enable ? "en" : "dis", ret);
1069         return ret;
1070 }
1071
1072 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1073 {
1074         /* TODO: virtual DPCD */
1075         struct dc_link *link = stream->link;
1076         union down_spread_ctrl old_downspread;
1077         union down_spread_ctrl new_downspread;
1078
1079         if (link->aux_access_disabled)
1080                 return;
1081
1082         if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1083                                      &old_downspread.raw,
1084                                      sizeof(old_downspread)))
1085                 return;
1086
1087         new_downspread.raw = old_downspread.raw;
1088         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1089                 (stream->ignore_msa_timing_param) ? 1 : 0;
1090
1091         if (new_downspread.raw != old_downspread.raw)
1092                 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1093                                          &new_downspread.raw,
1094                                          sizeof(new_downspread));
1095 }
1096
1097 bool dm_helpers_dp_handle_test_pattern_request(
1098                 struct dc_context *ctx,
1099                 const struct dc_link *link,
1100                 union link_test_pattern dpcd_test_pattern,
1101                 union test_misc dpcd_test_params)
1102 {
1103         enum dp_test_pattern test_pattern;
1104         enum dp_test_pattern_color_space test_pattern_color_space =
1105                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1106         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1107         enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1108         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1109         struct pipe_ctx *pipe_ctx = NULL;
1110         struct amdgpu_dm_connector *aconnector = link->priv;
1111         int i;
1112
1113         for (i = 0; i < MAX_PIPES; i++) {
1114                 if (pipes[i].stream == NULL)
1115                         continue;
1116
1117                 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1118                         !pipes[i].prev_odm_pipe) {
1119                         pipe_ctx = &pipes[i];
1120                         break;
1121                 }
1122         }
1123
1124         if (pipe_ctx == NULL)
1125                 return false;
1126
1127         switch (dpcd_test_pattern.bits.PATTERN) {
1128         case LINK_TEST_PATTERN_COLOR_RAMP:
1129                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1130         break;
1131         case LINK_TEST_PATTERN_VERTICAL_BARS:
1132                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1133         break; /* black and white */
1134         case LINK_TEST_PATTERN_COLOR_SQUARES:
1135                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1136                                 TEST_DYN_RANGE_VESA ?
1137                                 DP_TEST_PATTERN_COLOR_SQUARES :
1138                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1139         break;
1140         default:
1141                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1142         break;
1143         }
1144
1145         if (dpcd_test_params.bits.CLR_FORMAT == 0)
1146                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1147         else
1148                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1149                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1150                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1151
1152         switch (dpcd_test_params.bits.BPC) {
1153         case 0: // 6 bits
1154                 requestColorDepth = COLOR_DEPTH_666;
1155                 break;
1156         case 1: // 8 bits
1157                 requestColorDepth = COLOR_DEPTH_888;
1158                 break;
1159         case 2: // 10 bits
1160                 requestColorDepth = COLOR_DEPTH_101010;
1161                 break;
1162         case 3: // 12 bits
1163                 requestColorDepth = COLOR_DEPTH_121212;
1164                 break;
1165         default:
1166                 break;
1167         }
1168
1169         switch (dpcd_test_params.bits.CLR_FORMAT) {
1170         case 0:
1171                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1172                 break;
1173         case 1:
1174                 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1175                 break;
1176         case 2:
1177                 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1178                 break;
1179         default:
1180                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1181                 break;
1182         }
1183
1184         if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1185                 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1186                 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1187                 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1188                 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d  %d\n",
1189                                 __func__,
1190                                 pipe_ctx->stream->timing.display_color_depth,
1191                                 pipe_ctx->stream->timing.pixel_encoding,
1192                                 requestColorDepth,
1193                                 requestPixelEncoding);
1194                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1195                 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1196
1197                 dc_link_update_dsc_config(pipe_ctx);
1198
1199                 aconnector->timing_changed = true;
1200                 /* store current timing */
1201                 if (aconnector->timing_requested)
1202                         *aconnector->timing_requested = pipe_ctx->stream->timing;
1203                 else
1204                         DC_LOG_ERROR("%s: timing storage failed\n", __func__);
1205
1206         }
1207
1208         dc_link_dp_set_test_pattern(
1209                 (struct dc_link *) link,
1210                 test_pattern,
1211                 test_pattern_color_space,
1212                 NULL,
1213                 NULL,
1214                 0);
1215
1216         return false;
1217 }
1218
1219 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1220 {
1221        // TODO
1222 }
1223
1224 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1225 {
1226         /* TODO: add periodic detection implementation */
1227 }
1228
1229 void dm_helpers_dp_mst_update_branch_bandwidth(
1230                 struct dc_context *ctx,
1231                 struct dc_link *link)
1232 {
1233         // TODO
1234 }
1235
1236 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1237 {
1238         bool ret_val = false;
1239
1240         switch (branch_dev_id) {
1241         case DP_BRANCH_DEVICE_ID_0060AD:
1242         case DP_BRANCH_DEVICE_ID_00E04C:
1243         case DP_BRANCH_DEVICE_ID_90CC24:
1244                 ret_val = true;
1245                 break;
1246         default:
1247                 break;
1248         }
1249
1250         return ret_val;
1251 }
1252
1253 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1254 {
1255         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1256         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1257
1258         switch (dpcd_caps->dongle_type) {
1259         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1260                 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1261                         dpcd_caps->allow_invalid_MSA_timing_param == true &&
1262                         dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1263                         as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1264                 break;
1265         default:
1266                 break;
1267         }
1268
1269         return as_type;
1270 }