drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include "amdgpu_display.h"
  33 #include <asm/div64.h>
  34
  35 #include <linux/pci.h>
  36 #include <linux/pm_runtime.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_edid.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_fb_helper.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_vblank.h>
  43
  44 static void amdgpu_display_flip_callback(struct dma_fence *f,
  45                                          struct dma_fence_cb *cb)
  46 {
  47         struct amdgpu_flip_work *work =
  48                 container_of(cb, struct amdgpu_flip_work, cb);
  49
  50         dma_fence_put(f);
  51         schedule_work(&work->flip_work.work);
  52 }
  53
  54 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
  55                                              struct dma_fence **f)
  56 {
  57         struct dma_fence *fence= *f;
  58
  59         if (fence == NULL)
  60                 return false;
  61
  62         *f = NULL;
  63
  64         if (!dma_fence_add_callback(fence, &work->cb,
  65                                     amdgpu_display_flip_callback))
  66                 return true;
  67
  68         dma_fence_put(fence);
  69         return false;
  70 }
  71
  72 static void amdgpu_display_flip_work_func(struct work_struct *__work)
  73 {
  74         struct delayed_work *delayed_work =
  75                 container_of(__work, struct delayed_work, work);
  76         struct amdgpu_flip_work *work =
  77                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
  78         struct amdgpu_device *adev = work->adev;
  79         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
  80
  81         struct drm_crtc *crtc = &amdgpu_crtc->base;
  82         unsigned long flags;
  83         unsigned i;
  84         int vpos, hpos;
  85
  86         for (i = 0; i < work->shared_count; ++i)
  87                 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
  88                         return;
  89
  90         /* Wait until we're out of the vertical blank period before the one
  91          * targeted by the flip
  92          */
  93         if (amdgpu_crtc->enabled &&
  94             (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
  95                                                 &vpos, &hpos, NULL, NULL,
  96                                                 &crtc->hwmode)
  97              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
  98             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
  99             (int)(work->target_vblank -
 100                   amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 101                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 102                 return;
 103         }
 104
 105         /* We borrow the event spin lock for protecting flip_status */
 106         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 107
 108         /* Do the flip (mmio) */
 109         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 110
 111         /* Set the flip status */
 112         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 113         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 114
 115
 116         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 117                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 118
 119 }
 120
 121 /*
 122  * Handle unpin events outside the interrupt handler proper.
 123  */
 124 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 125 {
 126         struct amdgpu_flip_work *work =
 127                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 128         int r;
 129
 130         /* unpin of the old buffer */
 131         r = amdgpu_bo_reserve(work->old_abo, true);
 132         if (likely(r == 0)) {
 133                 amdgpu_bo_unpin(work->old_abo);
 134                 amdgpu_bo_unreserve(work->old_abo);
 135         } else
 136                 DRM_ERROR("failed to reserve buffer after flip\n");
 137
 138         amdgpu_bo_unref(&work->old_abo);
 139         kfree(work->shared);
 140         kfree(work);
 141 }
 142
 143 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 144                                 struct drm_framebuffer *fb,
 145                                 struct drm_pending_vblank_event *event,
 146                                 uint32_t page_flip_flags, uint32_t target,
 147                                 struct drm_modeset_acquire_ctx *ctx)
 148 {
 149         struct drm_device *dev = crtc->dev;
 150         struct amdgpu_device *adev = drm_to_adev(dev);
 151         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 152         struct drm_gem_object *obj;
 153         struct amdgpu_flip_work *work;
 154         struct amdgpu_bo *new_abo;
 155         unsigned long flags;
 156         u64 tiling_flags;
 157         int i, r;
 158
 159         work = kzalloc(sizeof *work, GFP_KERNEL);
 160         if (work == NULL)
 161                 return -ENOMEM;
 162
 163         INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 164         INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 165
 166         work->event = event;
 167         work->adev = adev;
 168         work->crtc_id = amdgpu_crtc->crtc_id;
 169         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 170
 171         /* schedule unpin of the old buffer */
 172         obj = crtc->primary->fb->obj[0];
 173
 174         /* take a reference to the old object */
 175         work->old_abo = gem_to_amdgpu_bo(obj);
 176         amdgpu_bo_ref(work->old_abo);
 177
 178         obj = fb->obj[0];
 179         new_abo = gem_to_amdgpu_bo(obj);
 180
 181         /* pin the new buffer */
 182         r = amdgpu_bo_reserve(new_abo, false);
 183         if (unlikely(r != 0)) {
 184                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 185                 goto cleanup;
 186         }
 187
 188         if (!adev->enable_virtual_display) {
 189                 r = amdgpu_bo_pin(new_abo,
 190                                   amdgpu_display_supported_domains(adev, new_abo->flags));
 191                 if (unlikely(r != 0)) {
 192                         DRM_ERROR("failed to pin new abo buffer before flip\n");
 193                         goto unreserve;
 194                 }
 195         }
 196
 197         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 198         if (unlikely(r != 0)) {
 199                 DRM_ERROR("%p bind failed\n", new_abo);
 200                 goto unpin;
 201         }
 202
 203         /* TODO: Unify this with other drivers */
 204         r = dma_resv_get_fences(new_abo->tbo.base.resv, true,
 205                                 &work->shared_count,
 206                                 &work->shared);
 207         if (unlikely(r != 0)) {
 208                 DRM_ERROR("failed to get fences for buffer\n");
 209                 goto unpin;
 210         }
 211
 212         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 213         amdgpu_bo_unreserve(new_abo);
 214
 215         if (!adev->enable_virtual_display)
 216                 work->base = amdgpu_bo_gpu_offset(new_abo);
 217         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 218                 amdgpu_get_vblank_counter_kms(crtc);
 219
 220         /* we borrow the event spin lock for protecting flip_wrok */
 221         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 222         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 223                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 224                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 225                 r = -EBUSY;
 226                 goto pflip_cleanup;
 227         }
 228
 229         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 230         amdgpu_crtc->pflip_works = work;
 231
 232
 233         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 234                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 235         /* update crtc fb */
 236         crtc->primary->fb = fb;
 237         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 238         amdgpu_display_flip_work_func(&work->flip_work.work);
 239         return 0;
 240
 241 pflip_cleanup:
 242         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 243                 DRM_ERROR("failed to reserve new abo in error path\n");
 244                 goto cleanup;
 245         }
 246 unpin:
 247         if (!adev->enable_virtual_display)
 248                 amdgpu_bo_unpin(new_abo);
 249
 250 unreserve:
 251         amdgpu_bo_unreserve(new_abo);
 252
 253 cleanup:
 254         amdgpu_bo_unref(&work->old_abo);
 255         for (i = 0; i < work->shared_count; ++i)
 256                 dma_fence_put(work->shared[i]);
 257         kfree(work->shared);
 258         kfree(work);
 259
 260         return r;
 261 }
 262
 263 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 264                                    struct drm_modeset_acquire_ctx *ctx)
 265 {
 266         struct drm_device *dev;
 267         struct amdgpu_device *adev;
 268         struct drm_crtc *crtc;
 269         bool active = false;
 270         int ret;
 271
 272         if (!set || !set->crtc)
 273                 return -EINVAL;
 274
 275         dev = set->crtc->dev;
 276
 277         ret = pm_runtime_get_sync(dev->dev);
 278         if (ret < 0)
 279                 goto out;
 280
 281         ret = drm_crtc_helper_set_config(set, ctx);
 282
 283         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 284                 if (crtc->enabled)
 285                         active = true;
 286
 287         pm_runtime_mark_last_busy(dev->dev);
 288
 289         adev = drm_to_adev(dev);
 290         /* if we have active crtcs and we don't have a power ref,
 291            take the current one */
 292         if (active && !adev->have_disp_power_ref) {
 293                 adev->have_disp_power_ref = true;
 294                 return ret;
 295         }
 296         /* if we have no active crtcs, then drop the power ref
 297            we got before */
 298         if (!active && adev->have_disp_power_ref) {
 299                 pm_runtime_put_autosuspend(dev->dev);
 300                 adev->have_disp_power_ref = false;
 301         }
 302
 303 out:
 304         /* drop the power reference we got coming in here */
 305         pm_runtime_put_autosuspend(dev->dev);
 306         return ret;
 307 }
 308
 309 static const char *encoder_names[41] = {
 310         "NONE",
 311         "INTERNAL_LVDS",
 312         "INTERNAL_TMDS1",
 313         "INTERNAL_TMDS2",
 314         "INTERNAL_DAC1",
 315         "INTERNAL_DAC2",
 316         "INTERNAL_SDVOA",
 317         "INTERNAL_SDVOB",
 318         "SI170B",
 319         "CH7303",
 320         "CH7301",
 321         "INTERNAL_DVO1",
 322         "EXTERNAL_SDVOA",
 323         "EXTERNAL_SDVOB",
 324         "TITFP513",
 325         "INTERNAL_LVTM1",
 326         "VT1623",
 327         "HDMI_SI1930",
 328         "HDMI_INTERNAL",
 329         "INTERNAL_KLDSCP_TMDS1",
 330         "INTERNAL_KLDSCP_DVO1",
 331         "INTERNAL_KLDSCP_DAC1",
 332         "INTERNAL_KLDSCP_DAC2",
 333         "SI178",
 334         "MVPU_FPGA",
 335         "INTERNAL_DDI",
 336         "VT1625",
 337         "HDMI_SI1932",
 338         "DP_AN9801",
 339         "DP_DP501",
 340         "INTERNAL_UNIPHY",
 341         "INTERNAL_KLDSCP_LVTMA",
 342         "INTERNAL_UNIPHY1",
 343         "INTERNAL_UNIPHY2",
 344         "NUTMEG",
 345         "TRAVIS",
 346         "INTERNAL_VCE",
 347         "INTERNAL_UNIPHY3",
 348         "HDMI_ANX9805",
 349         "INTERNAL_AMCLK",
 350         "VIRTUAL",
 351 };
 352
 353 static const char *hpd_names[6] = {
 354         "HPD1",
 355         "HPD2",
 356         "HPD3",
 357         "HPD4",
 358         "HPD5",
 359         "HPD6",
 360 };
 361
 362 void amdgpu_display_print_display_setup(struct drm_device *dev)
 363 {
 364         struct drm_connector *connector;
 365         struct amdgpu_connector *amdgpu_connector;
 366         struct drm_encoder *encoder;
 367         struct amdgpu_encoder *amdgpu_encoder;
 368         struct drm_connector_list_iter iter;
 369         uint32_t devices;
 370         int i = 0;
 371
 372         drm_connector_list_iter_begin(dev, &iter);
 373         DRM_INFO("AMDGPU Display Connectors\n");
 374         drm_for_each_connector_iter(connector, &iter) {
 375                 amdgpu_connector = to_amdgpu_connector(connector);
 376                 DRM_INFO("Connector %d:\n", i);
 377                 DRM_INFO("  %s\n", connector->name);
 378                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 379                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 380                 if (amdgpu_connector->ddc_bus) {
 381                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 382                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 383                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 384                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 385                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 386                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 387                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 388                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 389                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 390                         if (amdgpu_connector->router.ddc_valid)
 391                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 392                                          amdgpu_connector->router.ddc_mux_control_pin,
 393                                          amdgpu_connector->router.ddc_mux_state);
 394                         if (amdgpu_connector->router.cd_valid)
 395                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 396                                          amdgpu_connector->router.cd_mux_control_pin,
 397                                          amdgpu_connector->router.cd_mux_state);
 398                 } else {
 399                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 400                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 401                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 402                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 403                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 404                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 405                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n");
 406                 }
 407                 DRM_INFO("  Encoders:\n");
 408                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 409                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 410                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 411                         if (devices) {
 412                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 413                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 414                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 415                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 416                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 417                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 418                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 419                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 420                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 421                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 422                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 423                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 424                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 425                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 426                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 427                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 428                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 429                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 430                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 431                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 432                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 433                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 434                         }
 435                 }
 436                 i++;
 437         }
 438         drm_connector_list_iter_end(&iter);
 439 }
 440
 441 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 442                               bool use_aux)
 443 {
 444         u8 out = 0x0;
 445         u8 buf[8];
 446         int ret;
 447         struct i2c_msg msgs[] = {
 448                 {
 449                         .addr = DDC_ADDR,
 450                         .flags = 0,
 451                         .len = 1,
 452                         .buf = &out,
 453                 },
 454                 {
 455                         .addr = DDC_ADDR,
 456                         .flags = I2C_M_RD,
 457                         .len = 8,
 458                         .buf = buf,
 459                 }
 460         };
 461
 462         /* on hw with routers, select right port */
 463         if (amdgpu_connector->router.ddc_valid)
 464                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 465
 466         if (use_aux) {
 467                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 468         } else {
 469                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 470         }
 471
 472         if (ret != 2)
 473                 /* Couldn't find an accessible DDC on this connector */
 474                 return false;
 475         /* Probe also for valid EDID header
 476          * EDID header starts with:
 477          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 478          * Only the first 6 bytes must be valid as
 479          * drm_edid_block_valid() can fix the last 2 bytes */
 480         if (drm_edid_header_is_valid(buf) < 6) {
 481                 /* Couldn't find an accessible EDID on this
 482                  * connector */
 483                 return false;
 484         }
 485         return true;
 486 }
 487
 488 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 489         .destroy = drm_gem_fb_destroy,
 490         .create_handle = drm_gem_fb_create_handle,
 491 };
 492
 493 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 494                                           uint64_t bo_flags)
 495 {
 496         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 497
 498 #if defined(CONFIG_DRM_AMD_DC)
 499         /*
 500          * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 501          * is not supported for this board. But this mapping is required
 502          * to avoid hang caused by placement of scanout BO in GTT on certain
 503          * APUs. So force the BO placement to VRAM in case this architecture
 504          * will not allow USWC mappings.
 505          * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
 506          */
 507         if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 508             amdgpu_bo_support_uswc(bo_flags) &&
 509             amdgpu_device_asic_has_dc_support(adev->asic_type)) {
 510                 switch (adev->asic_type) {
 511                 case CHIP_CARRIZO:
 512                 case CHIP_STONEY:
 513                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 514                         break;
 515                 case CHIP_RAVEN:
 516                         /* enable S/G on PCO and RV2 */
 517                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
 518                             (adev->apu_flags & AMD_APU_IS_PICASSO))
 519                                 domain |= AMDGPU_GEM_DOMAIN_GTT;
 520                         break;
 521                 case CHIP_RENOIR:
 522                 case CHIP_VANGOGH:
 523                 case CHIP_YELLOW_CARP:
 524                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 525                         break;
 526
 527                 default:
 528                         break;
 529                 }
 530         }
 531 #endif
 532
 533         return domain;
 534 }
 535
 536 static const struct drm_format_info dcc_formats[] = {
 537         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 538           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 539          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 540           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 541         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 542           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 543            .has_alpha = true, },
 544         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 545           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 546           .has_alpha = true, },
 547         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
 548           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 549           .has_alpha = true, },
 550         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
 551           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 552         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
 553           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 554         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
 555           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 556           .has_alpha = true, },
 557         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
 558           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 559           .has_alpha = true, },
 560         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
 561           .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 562 };
 563
 564 static const struct drm_format_info dcc_retile_formats[] = {
 565         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 566           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 567          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 568           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 569         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 570           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 571            .has_alpha = true, },
 572         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 573           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 574           .has_alpha = true, },
 575         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
 576           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 577           .has_alpha = true, },
 578         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
 579           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 580         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
 581           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 582         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
 583           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 584           .has_alpha = true, },
 585         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
 586           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 587           .has_alpha = true, },
 588         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
 589           .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 590 };
 591
 592 static const struct drm_format_info *
 593 lookup_format_info(const struct drm_format_info formats[],
 594                   int num_formats, u32 format)
 595 {
 596         int i;
 597
 598         for (i = 0; i < num_formats; i++) {
 599                 if (formats[i].format == format)
 600                         return &formats[i];
 601         }
 602
 603         return NULL;
 604 }
 605
 606 const struct drm_format_info *
 607 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
 608 {
 609         if (!IS_AMD_FMT_MOD(modifier))
 610                 return NULL;
 611
 612         if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
 613                 return lookup_format_info(dcc_retile_formats,
 614                                           ARRAY_SIZE(dcc_retile_formats),
 615                                           format);
 616
 617         if (AMD_FMT_MOD_GET(DCC, modifier))
 618                 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
 619                                           format);
 620
 621         /* returning NULL will cause the default format structs to be used. */
 622         return NULL;
 623 }
 624
 625
 626 /*
 627  * Tries to extract the renderable DCC offset from the opaque metadata attached
 628  * to the buffer.
 629  */
 630 static int
 631 extract_render_dcc_offset(struct amdgpu_device *adev,
 632                           struct drm_gem_object *obj,
 633                           uint64_t *offset)
 634 {
 635         struct amdgpu_bo *rbo;
 636         int r = 0;
 637         uint32_t metadata[10]; /* Something that fits a descriptor + header. */
 638         uint32_t size;
 639
 640         rbo = gem_to_amdgpu_bo(obj);
 641         r = amdgpu_bo_reserve(rbo, false);
 642
 643         if (unlikely(r)) {
 644                 /* Don't show error message when returning -ERESTARTSYS */
 645                 if (r != -ERESTARTSYS)
 646                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 647                 return r;
 648         }
 649
 650         r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
 651         amdgpu_bo_unreserve(rbo);
 652
 653         if (r)
 654                 return r;
 655
 656         /*
 657          * The first word is the metadata version, and we need space for at least
 658          * the version + pci vendor+device id + 8 words for a descriptor.
 659          */
 660         if (size < 40  || metadata[0] != 1)
 661                 return -EINVAL;
 662
 663         if (adev->family >= AMDGPU_FAMILY_NV) {
 664                 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
 665                 *offset = ((u64)metadata[9] << 16u) |
 666                           ((metadata[8] & 0xFF000000u) >> 16);
 667         } else {
 668                 /* resource word 5/7 META_DATA_ADDRESS */
 669                 *offset = ((u64)metadata[9] << 8u) |
 670                           ((u64)(metadata[7] & 0x1FE0000u) << 23);
 671         }
 672
 673         return 0;
 674 }
 675
 676 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 677 {
 678         struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 679         uint64_t modifier = 0;
 680
 681         if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 682                 modifier = DRM_FORMAT_MOD_LINEAR;
 683         } else {
 684                 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 685                 bool has_xor = swizzle >= 16;
 686                 int block_size_bits;
 687                 int version;
 688                 int pipe_xor_bits = 0;
 689                 int bank_xor_bits = 0;
 690                 int packers = 0;
 691                 int rb = 0;
 692                 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
 693                 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 694
 695                 switch (swizzle >> 2) {
 696                 case 0: /* 256B */
 697                         block_size_bits = 8;
 698                         break;
 699                 case 1: /* 4KiB */
 700                 case 5: /* 4KiB _X */
 701                         block_size_bits = 12;
 702                         break;
 703                 case 2: /* 64KiB */
 704                 case 4: /* 64 KiB _T */
 705                 case 6: /* 64 KiB _X */
 706                         block_size_bits = 16;
 707                         break;
 708                 default:
 709                         /* RESERVED or VAR */
 710                         return -EINVAL;
 711                 }
 712
 713                 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 714                         version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 715                 else if (adev->family == AMDGPU_FAMILY_NV)
 716                         version = AMD_FMT_MOD_TILE_VER_GFX10;
 717                 else
 718                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 719
 720                 switch (swizzle & 3) {
 721                 case 0: /* Z microtiling */
 722                         return -EINVAL;
 723                 case 1: /* S microtiling */
 724                         if (!has_xor)
 725                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 726                         break;
 727                 case 2:
 728                         if (!has_xor && afb->base.format->cpp[0] != 4)
 729                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 730                         break;
 731                 case 3:
 732                         break;
 733                 }
 734
 735                 if (has_xor) {
 736                         switch (version) {
 737                         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 738                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 739                                 packers = min(block_size_bits - 8 - pipe_xor_bits,
 740                                               ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 741                                 break;
 742                         case AMD_FMT_MOD_TILE_VER_GFX10:
 743                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 744                                 break;
 745                         case AMD_FMT_MOD_TILE_VER_GFX9:
 746                                 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
 747                                      ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
 748                                 pipe_xor_bits = min(block_size_bits - 8, pipes +
 749                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 750                                 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 751                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 752                                 break;
 753                         }
 754                 }
 755
 756                 modifier = AMD_FMT_MOD |
 757                            AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 758                            AMD_FMT_MOD_SET(TILE_VERSION, version) |
 759                            AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 760                            AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 761                            AMD_FMT_MOD_SET(PACKERS, packers);
 762
 763                 if (dcc_offset != 0) {
 764                         bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 765                         bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 766                         const struct drm_format_info *format_info;
 767                         u64 render_dcc_offset;
 768
 769                         /* Enable constant encode on RAVEN2 and later. */
 770                         bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
 771                                                    (adev->asic_type == CHIP_RAVEN &&
 772                                                     adev->external_rev_id >= 0x81);
 773
 774                         int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 775                                               dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 776                                               AMD_FMT_MOD_DCC_BLOCK_256B;
 777
 778                         modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 779                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 780                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 781                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 782                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 783
 784                         afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 785                         afb->base.pitches[1] =
 786                                 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 787
 788                         /*
 789                          * If the userspace driver uses retiling the tiling flags do not contain
 790                          * info on the renderable DCC buffer. Luckily the opaque metadata contains
 791                          * the info so we can try to extract it. The kernel does not use this info
 792                          * but we should convert it to a modifier plane for getfb2, so the
 793                          * userspace driver that gets it doesn't have to juggle around another DCC
 794                          * plane internally.
 795                          */
 796                         if (extract_render_dcc_offset(adev, afb->base.obj[0],
 797                                                       &render_dcc_offset) == 0 &&
 798                             render_dcc_offset != 0 &&
 799                             render_dcc_offset != afb->base.offsets[1] &&
 800                             render_dcc_offset < UINT_MAX) {
 801                                 uint32_t dcc_block_bits;  /* of base surface data */
 802
 803                                 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
 804                                 afb->base.offsets[2] = render_dcc_offset;
 805
 806                                 if (adev->family >= AMDGPU_FAMILY_NV) {
 807                                         int extra_pipe = 0;
 808
 809                                         if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 810                                             pipes == packers && pipes > 1)
 811                                                 extra_pipe = 1;
 812
 813                                         dcc_block_bits = max(20, 16 + pipes + extra_pipe);
 814                                 } else {
 815                                         modifier |= AMD_FMT_MOD_SET(RB, rb) |
 816                                                     AMD_FMT_MOD_SET(PIPE, pipes);
 817                                         dcc_block_bits = max(20, 18 + rb);
 818                                 }
 819
 820                                 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
 821                                 afb->base.pitches[2] = ALIGN(afb->base.width,
 822                                                              1u << ((dcc_block_bits + 1) / 2));
 823                         }
 824                         format_info = amdgpu_lookup_format_info(afb->base.format->format,
 825                                                                 modifier);
 826                         if (!format_info)
 827                                 return -EINVAL;
 828
 829                         afb->base.format = format_info;
 830                 }
 831         }
 832
 833         afb->base.modifier = modifier;
 834         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 835         return 0;
 836 }
 837
 838 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
 839 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
 840 {
 841         u64 micro_tile_mode;
 842
 843         /* Zero swizzle mode means linear */
 844         if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
 845                 return 0;
 846
 847         micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
 848         switch (micro_tile_mode) {
 849         case 0: /* DISPLAY */
 850         case 3: /* RENDER */
 851                 return 0;
 852         default:
 853                 drm_dbg_kms(afb->base.dev,
 854                             "Micro tile mode %llu not supported for scanout\n",
 855                             micro_tile_mode);
 856                 return -EINVAL;
 857         }
 858 }
 859
 860 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
 861                                  unsigned int *width, unsigned int *height)
 862 {
 863         unsigned int cpp_log2 = ilog2(cpp);
 864         unsigned int pixel_log2 = block_log2 - cpp_log2;
 865         unsigned int width_log2 = (pixel_log2 + 1) / 2;
 866         unsigned int height_log2 = pixel_log2 - width_log2;
 867
 868         *width = 1 << width_log2;
 869         *height = 1 << height_log2;
 870 }
 871
 872 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
 873                                        bool pipe_aligned)
 874 {
 875         unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
 876
 877         switch (ver) {
 878         case AMD_FMT_MOD_TILE_VER_GFX9: {
 879                 /*
 880                  * TODO: for pipe aligned we may need to check the alignment of the
 881                  * total size of the surface, which may need to be bigger than the
 882                  * natural alignment due to some HW workarounds
 883                  */
 884                 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
 885         }
 886         case AMD_FMT_MOD_TILE_VER_GFX10:
 887         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: {
 888                 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 889
 890                 if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
 891                     AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
 892                         ++pipes_log2;
 893
 894                 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
 895         }
 896         default:
 897                 return 0;
 898         }
 899 }
 900
 901 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
 902                                        const struct drm_format_info *format,
 903                                        unsigned int block_width, unsigned int block_height,
 904                                        unsigned int block_size_log2)
 905 {
 906         unsigned int width = rfb->base.width /
 907                 ((plane && plane < format->num_planes) ? format->hsub : 1);
 908         unsigned int height = rfb->base.height /
 909                 ((plane && plane < format->num_planes) ? format->vsub : 1);
 910         unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
 911         unsigned int block_pitch = block_width * cpp;
 912         unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
 913         unsigned int block_size = 1 << block_size_log2;
 914         uint64_t size;
 915
 916         if (rfb->base.pitches[plane] % block_pitch) {
 917                 drm_dbg_kms(rfb->base.dev,
 918                             "pitch %d for plane %d is not a multiple of block pitch %d\n",
 919                             rfb->base.pitches[plane], plane, block_pitch);
 920                 return -EINVAL;
 921         }
 922         if (rfb->base.pitches[plane] < min_pitch) {
 923                 drm_dbg_kms(rfb->base.dev,
 924                             "pitch %d for plane %d is less than minimum pitch %d\n",
 925                             rfb->base.pitches[plane], plane, min_pitch);
 926                 return -EINVAL;
 927         }
 928
 929         /* Force at least natural alignment. */
 930         if (rfb->base.offsets[plane] % block_size) {
 931                 drm_dbg_kms(rfb->base.dev,
 932                             "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
 933                             rfb->base.offsets[plane], plane, block_size);
 934                 return -EINVAL;
 935         }
 936
 937         size = rfb->base.offsets[plane] +
 938                 (uint64_t)rfb->base.pitches[plane] / block_pitch *
 939                 block_size * DIV_ROUND_UP(height, block_height);
 940
 941         if (rfb->base.obj[0]->size < size) {
 942                 drm_dbg_kms(rfb->base.dev,
 943                             "BO size 0x%zx is less than 0x%llx required for plane %d\n",
 944                             rfb->base.obj[0]->size, size, plane);
 945                 return -EINVAL;
 946         }
 947
 948         return 0;
 949 }
 950
 951
 952 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
 953 {
 954         const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
 955         uint64_t modifier = rfb->base.modifier;
 956         int ret;
 957         unsigned int i, block_width, block_height, block_size_log2;
 958
 959         if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
 960                 return 0;
 961
 962         for (i = 0; i < format_info->num_planes; ++i) {
 963                 if (modifier == DRM_FORMAT_MOD_LINEAR) {
 964                         block_width = 256 / format_info->cpp[i];
 965                         block_height = 1;
 966                         block_size_log2 = 8;
 967                 } else {
 968                         int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
 969
 970                         switch ((swizzle & ~3) + 1) {
 971                         case DC_SW_256B_S:
 972                                 block_size_log2 = 8;
 973                                 break;
 974                         case DC_SW_4KB_S:
 975                         case DC_SW_4KB_S_X:
 976                                 block_size_log2 = 12;
 977                                 break;
 978                         case DC_SW_64KB_S:
 979                         case DC_SW_64KB_S_T:
 980                         case DC_SW_64KB_S_X:
 981                                 block_size_log2 = 16;
 982                                 break;
 983                         default:
 984                                 drm_dbg_kms(rfb->base.dev,
 985                                             "Swizzle mode with unknown block size: %d\n", swizzle);
 986                                 return -EINVAL;
 987                         }
 988
 989                         get_block_dimensions(block_size_log2, format_info->cpp[i],
 990                                              &block_width, &block_height);
 991                 }
 992
 993                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
 994                                                   block_width, block_height, block_size_log2);
 995                 if (ret)
 996                         return ret;
 997         }
 998
 999         if (AMD_FMT_MOD_GET(DCC, modifier)) {
1000                 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1001                         block_size_log2 = get_dcc_block_size(modifier, false, false);
1002                         get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1003                                              &block_width, &block_height);
1004                         ret = amdgpu_display_verify_plane(rfb, i, format_info,
1005                                                           block_width, block_height,
1006                                                           block_size_log2);
1007                         if (ret)
1008                                 return ret;
1009
1010                         ++i;
1011                         block_size_log2 = get_dcc_block_size(modifier, true, true);
1012                 } else {
1013                         bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1014
1015                         block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1016                 }
1017                 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1018                                      &block_width, &block_height);
1019                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1020                                                   block_width, block_height, block_size_log2);
1021                 if (ret)
1022                         return ret;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1029                                       uint64_t *tiling_flags, bool *tmz_surface)
1030 {
1031         struct amdgpu_bo *rbo;
1032         int r;
1033
1034         if (!amdgpu_fb) {
1035                 *tiling_flags = 0;
1036                 *tmz_surface = false;
1037                 return 0;
1038         }
1039
1040         rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1041         r = amdgpu_bo_reserve(rbo, false);
1042
1043         if (unlikely(r)) {
1044                 /* Don't show error message when returning -ERESTARTSYS */
1045                 if (r != -ERESTARTSYS)
1046                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1047                 return r;
1048         }
1049
1050         if (tiling_flags)
1051                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1052
1053         if (tmz_surface)
1054                 *tmz_surface = amdgpu_bo_encrypted(rbo);
1055
1056         amdgpu_bo_unreserve(rbo);
1057
1058         return r;
1059 }
1060
1061 int amdgpu_display_gem_fb_init(struct drm_device *dev,
1062                                struct amdgpu_framebuffer *rfb,
1063                                const struct drm_mode_fb_cmd2 *mode_cmd,
1064                                struct drm_gem_object *obj)
1065 {
1066         int ret;
1067
1068         rfb->base.obj[0] = obj;
1069         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1070
1071         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1072         if (ret)
1073                 goto err;
1074
1075         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1076         if (ret)
1077                 goto err;
1078
1079         return 0;
1080 err:
1081         drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
1082         rfb->base.obj[0] = NULL;
1083         return ret;
1084 }
1085
1086 int amdgpu_display_gem_fb_verify_and_init(
1087         struct drm_device *dev, struct amdgpu_framebuffer *rfb,
1088         struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
1089         struct drm_gem_object *obj)
1090 {
1091         int ret;
1092
1093         rfb->base.obj[0] = obj;
1094         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1095         /* Verify that the modifier is supported. */
1096         if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1097                                       mode_cmd->modifier[0])) {
1098                 drm_dbg_kms(dev,
1099                             "unsupported pixel format %p4cc / modifier 0x%llx\n",
1100                             &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1101
1102                 ret = -EINVAL;
1103                 goto err;
1104         }
1105
1106         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1107         if (ret)
1108                 goto err;
1109
1110         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1111         if (ret)
1112                 goto err;
1113
1114         return 0;
1115 err:
1116         drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1117         rfb->base.obj[0] = NULL;
1118         return ret;
1119 }
1120
1121 int amdgpu_display_framebuffer_init(struct drm_device *dev,
1122                                     struct amdgpu_framebuffer *rfb,
1123                                     const struct drm_mode_fb_cmd2 *mode_cmd,
1124                                     struct drm_gem_object *obj)
1125 {
1126         struct amdgpu_device *adev = drm_to_adev(dev);
1127         int ret, i;
1128
1129         /*
1130          * This needs to happen before modifier conversion as that might change
1131          * the number of planes.
1132          */
1133         for (i = 1; i < rfb->base.format->num_planes; ++i) {
1134                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1135                         drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1136                                     i, mode_cmd->handles[0], mode_cmd->handles[i]);
1137                         ret = -EINVAL;
1138                         return ret;
1139                 }
1140         }
1141
1142         ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1143         if (ret)
1144                 return ret;
1145
1146         if (dev->mode_config.fb_modifiers_not_supported) {
1147                 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1148                               "GFX9+ requires FB check based on format modifier\n");
1149                 ret = check_tiling_flags_gfx6(rfb);
1150                 if (ret)
1151                         return ret;
1152         }
1153
1154         if (!dev->mode_config.fb_modifiers_not_supported &&
1155             !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1156                 ret = convert_tiling_flags_to_modifier(rfb);
1157                 if (ret) {
1158                         drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1159                                     rfb->tiling_flags);
1160                         return ret;
1161                 }
1162         }
1163
1164         ret = amdgpu_display_verify_sizes(rfb);
1165         if (ret)
1166                 return ret;
1167
1168         for (i = 0; i < rfb->base.format->num_planes; ++i) {
1169                 drm_gem_object_get(rfb->base.obj[0]);
1170                 rfb->base.obj[i] = rfb->base.obj[0];
1171         }
1172
1173         return 0;
1174 }
1175
1176 struct drm_framebuffer *
1177 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1178                                        struct drm_file *file_priv,
1179                                        const struct drm_mode_fb_cmd2 *mode_cmd)
1180 {
1181         struct amdgpu_framebuffer *amdgpu_fb;
1182         struct drm_gem_object *obj;
1183         struct amdgpu_bo *bo;
1184         uint32_t domains;
1185         int ret;
1186
1187         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1188         if (obj ==  NULL) {
1189                 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
1190                             "can't create framebuffer\n", mode_cmd->handles[0]);
1191                 return ERR_PTR(-ENOENT);
1192         }
1193
1194         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1195         bo = gem_to_amdgpu_bo(obj);
1196         domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1197         if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1198                 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1199                 drm_gem_object_put(obj);
1200                 return ERR_PTR(-EINVAL);
1201         }
1202
1203         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1204         if (amdgpu_fb == NULL) {
1205                 drm_gem_object_put(obj);
1206                 return ERR_PTR(-ENOMEM);
1207         }
1208
1209         ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1210                                                     mode_cmd, obj);
1211         if (ret) {
1212                 kfree(amdgpu_fb);
1213                 drm_gem_object_put(obj);
1214                 return ERR_PTR(ret);
1215         }
1216
1217         drm_gem_object_put(obj);
1218         return &amdgpu_fb->base;
1219 }
1220
1221 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1222         .fb_create = amdgpu_display_user_framebuffer_create,
1223         .output_poll_changed = drm_fb_helper_output_poll_changed,
1224 };
1225
1226 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1227 {       { UNDERSCAN_OFF, "off" },
1228         { UNDERSCAN_ON, "on" },
1229         { UNDERSCAN_AUTO, "auto" },
1230 };
1231
1232 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1233 {       { AMDGPU_AUDIO_DISABLE, "off" },
1234         { AMDGPU_AUDIO_ENABLE, "on" },
1235         { AMDGPU_AUDIO_AUTO, "auto" },
1236 };
1237
1238 /* XXX support different dither options? spatial, temporal, both, etc. */
1239 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1240 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
1241         { AMDGPU_FMT_DITHER_ENABLE, "on" },
1242 };
1243
1244 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1245 {
1246         int sz;
1247
1248         adev->mode_info.coherent_mode_property =
1249                 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1250         if (!adev->mode_info.coherent_mode_property)
1251                 return -ENOMEM;
1252
1253         adev->mode_info.load_detect_property =
1254                 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1255         if (!adev->mode_info.load_detect_property)
1256                 return -ENOMEM;
1257
1258         drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1259
1260         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1261         adev->mode_info.underscan_property =
1262                 drm_property_create_enum(adev_to_drm(adev), 0,
1263                                          "underscan",
1264                                          amdgpu_underscan_enum_list, sz);
1265
1266         adev->mode_info.underscan_hborder_property =
1267                 drm_property_create_range(adev_to_drm(adev), 0,
1268                                           "underscan hborder", 0, 128);
1269         if (!adev->mode_info.underscan_hborder_property)
1270                 return -ENOMEM;
1271
1272         adev->mode_info.underscan_vborder_property =
1273                 drm_property_create_range(adev_to_drm(adev), 0,
1274                                           "underscan vborder", 0, 128);
1275         if (!adev->mode_info.underscan_vborder_property)
1276                 return -ENOMEM;
1277
1278         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1279         adev->mode_info.audio_property =
1280                 drm_property_create_enum(adev_to_drm(adev), 0,
1281                                          "audio",
1282                                          amdgpu_audio_enum_list, sz);
1283
1284         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1285         adev->mode_info.dither_property =
1286                 drm_property_create_enum(adev_to_drm(adev), 0,
1287                                          "dither",
1288                                          amdgpu_dither_enum_list, sz);
1289
1290         if (amdgpu_device_has_dc_support(adev)) {
1291                 adev->mode_info.abm_level_property =
1292                         drm_property_create_range(adev_to_drm(adev), 0,
1293                                                   "abm level", 0, 4);
1294                 if (!adev->mode_info.abm_level_property)
1295                         return -ENOMEM;
1296         }
1297
1298         return 0;
1299 }
1300
1301 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1302 {
1303         /* adjustment options for the display watermarks */
1304         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1305                 adev->mode_info.disp_priority = 0;
1306         else
1307                 adev->mode_info.disp_priority = amdgpu_disp_priority;
1308
1309 }
1310
1311 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1312 {
1313         /* try and guess if this is a tv or a monitor */
1314         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1315             (mode->vdisplay == 576) || /* 576p */
1316             (mode->vdisplay == 720) || /* 720p */
1317             (mode->vdisplay == 1080)) /* 1080p */
1318                 return true;
1319         else
1320                 return false;
1321 }
1322
1323 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1324                                         const struct drm_display_mode *mode,
1325                                         struct drm_display_mode *adjusted_mode)
1326 {
1327         struct drm_device *dev = crtc->dev;
1328         struct drm_encoder *encoder;
1329         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1330         struct amdgpu_encoder *amdgpu_encoder;
1331         struct drm_connector *connector;
1332         u32 src_v = 1, dst_v = 1;
1333         u32 src_h = 1, dst_h = 1;
1334
1335         amdgpu_crtc->h_border = 0;
1336         amdgpu_crtc->v_border = 0;
1337
1338         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1339                 if (encoder->crtc != crtc)
1340                         continue;
1341                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1342                 connector = amdgpu_get_connector_for_encoder(encoder);
1343
1344                 /* set scaling */
1345                 if (amdgpu_encoder->rmx_type == RMX_OFF)
1346                         amdgpu_crtc->rmx_type = RMX_OFF;
1347                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1348                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1349                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1350                 else
1351                         amdgpu_crtc->rmx_type = RMX_OFF;
1352                 /* copy native mode */
1353                 memcpy(&amdgpu_crtc->native_mode,
1354                        &amdgpu_encoder->native_mode,
1355                        sizeof(struct drm_display_mode));
1356                 src_v = crtc->mode.vdisplay;
1357                 dst_v = amdgpu_crtc->native_mode.vdisplay;
1358                 src_h = crtc->mode.hdisplay;
1359                 dst_h = amdgpu_crtc->native_mode.hdisplay;
1360
1361                 /* fix up for overscan on hdmi */
1362                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1363                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1364                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1365                       connector->display_info.is_hdmi &&
1366                       amdgpu_display_is_hdtv_mode(mode)))) {
1367                         if (amdgpu_encoder->underscan_hborder != 0)
1368                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1369                         else
1370                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1371                         if (amdgpu_encoder->underscan_vborder != 0)
1372                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1373                         else
1374                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1375                         amdgpu_crtc->rmx_type = RMX_FULL;
1376                         src_v = crtc->mode.vdisplay;
1377                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1378                         src_h = crtc->mode.hdisplay;
1379                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1380                 }
1381         }
1382         if (amdgpu_crtc->rmx_type != RMX_OFF) {
1383                 fixed20_12 a, b;
1384                 a.full = dfixed_const(src_v);
1385                 b.full = dfixed_const(dst_v);
1386                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1387                 a.full = dfixed_const(src_h);
1388                 b.full = dfixed_const(dst_h);
1389                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1390         } else {
1391                 amdgpu_crtc->vsc.full = dfixed_const(1);
1392                 amdgpu_crtc->hsc.full = dfixed_const(1);
1393         }
1394         return true;
1395 }
1396
1397 /*
1398  * Retrieve current video scanout position of crtc on a given gpu, and
1399  * an optional accurate timestamp of when query happened.
1400  *
1401  * \param dev Device to query.
1402  * \param pipe Crtc to query.
1403  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1404  *              For driver internal use only also supports these flags:
1405  *
1406  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1407  *              of a fudged earlier start of vblank.
1408  *
1409  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1410  *              fudged earlier start of vblank in *vpos and the distance
1411  *              to true start of vblank in *hpos.
1412  *
1413  * \param *vpos Location where vertical scanout position should be stored.
1414  * \param *hpos Location where horizontal scanout position should go.
1415  * \param *stime Target location for timestamp taken immediately before
1416  *               scanout position query. Can be NULL to skip timestamp.
1417  * \param *etime Target location for timestamp taken immediately after
1418  *               scanout position query. Can be NULL to skip timestamp.
1419  *
1420  * Returns vpos as a positive number while in active scanout area.
1421  * Returns vpos as a negative number inside vblank, counting the number
1422  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1423  * until start of active scanout / end of vblank."
1424  *
1425  * \return Flags, or'ed together as follows:
1426  *
1427  * DRM_SCANOUTPOS_VALID = Query successful.
1428  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1429  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1430  * this flag means that returned position may be offset by a constant but
1431  * unknown small number of scanlines wrt. real scanout position.
1432  *
1433  */
1434 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1435                         unsigned int pipe, unsigned int flags, int *vpos,
1436                         int *hpos, ktime_t *stime, ktime_t *etime,
1437                         const struct drm_display_mode *mode)
1438 {
1439         u32 vbl = 0, position = 0;
1440         int vbl_start, vbl_end, vtotal, ret = 0;
1441         bool in_vbl = true;
1442
1443         struct amdgpu_device *adev = drm_to_adev(dev);
1444
1445         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1446
1447         /* Get optional system timestamp before query. */
1448         if (stime)
1449                 *stime = ktime_get();
1450
1451         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1452                 ret |= DRM_SCANOUTPOS_VALID;
1453
1454         /* Get optional system timestamp after query. */
1455         if (etime)
1456                 *etime = ktime_get();
1457
1458         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1459
1460         /* Decode into vertical and horizontal scanout position. */
1461         *vpos = position & 0x1fff;
1462         *hpos = (position >> 16) & 0x1fff;
1463
1464         /* Valid vblank area boundaries from gpu retrieved? */
1465         if (vbl > 0) {
1466                 /* Yes: Decode. */
1467                 ret |= DRM_SCANOUTPOS_ACCURATE;
1468                 vbl_start = vbl & 0x1fff;
1469                 vbl_end = (vbl >> 16) & 0x1fff;
1470         }
1471         else {
1472                 /* No: Fake something reasonable which gives at least ok results. */
1473                 vbl_start = mode->crtc_vdisplay;
1474                 vbl_end = 0;
1475         }
1476
1477         /* Called from driver internal vblank counter query code? */
1478         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1479             /* Caller wants distance from real vbl_start in *hpos */
1480             *hpos = *vpos - vbl_start;
1481         }
1482
1483         /* Fudge vblank to start a few scanlines earlier to handle the
1484          * problem that vblank irqs fire a few scanlines before start
1485          * of vblank. Some driver internal callers need the true vblank
1486          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1487          *
1488          * The cause of the "early" vblank irq is that the irq is triggered
1489          * by the line buffer logic when the line buffer read position enters
1490          * the vblank, whereas our crtc scanout position naturally lags the
1491          * line buffer read position.
1492          */
1493         if (!(flags & USE_REAL_VBLANKSTART))
1494                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1495
1496         /* Test scanout position against vblank region. */
1497         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1498                 in_vbl = false;
1499
1500         /* In vblank? */
1501         if (in_vbl)
1502             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1503
1504         /* Called from driver internal vblank counter query code? */
1505         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1506                 /* Caller wants distance from fudged earlier vbl_start */
1507                 *vpos -= vbl_start;
1508                 return ret;
1509         }
1510
1511         /* Check if inside vblank area and apply corrective offsets:
1512          * vpos will then be >=0 in video scanout area, but negative
1513          * within vblank area, counting down the number of lines until
1514          * start of scanout.
1515          */
1516
1517         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1518         if (in_vbl && (*vpos >= vbl_start)) {
1519                 vtotal = mode->crtc_vtotal;
1520
1521                 /* With variable refresh rate displays the vpos can exceed
1522                  * the vtotal value. Clamp to 0 to return -vbl_end instead
1523                  * of guessing the remaining number of lines until scanout.
1524                  */
1525                 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1526         }
1527
1528         /* Correct for shifted end of vbl at vbl_end. */
1529         *vpos = *vpos - vbl_end;
1530
1531         return ret;
1532 }
1533
1534 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1535 {
1536         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1537                 return AMDGPU_CRTC_IRQ_NONE;
1538
1539         switch (crtc) {
1540         case 0:
1541                 return AMDGPU_CRTC_IRQ_VBLANK1;
1542         case 1:
1543                 return AMDGPU_CRTC_IRQ_VBLANK2;
1544         case 2:
1545                 return AMDGPU_CRTC_IRQ_VBLANK3;
1546         case 3:
1547                 return AMDGPU_CRTC_IRQ_VBLANK4;
1548         case 4:
1549                 return AMDGPU_CRTC_IRQ_VBLANK5;
1550         case 5:
1551                 return AMDGPU_CRTC_IRQ_VBLANK6;
1552         default:
1553                 return AMDGPU_CRTC_IRQ_NONE;
1554         }
1555 }
1556
1557 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1558                         bool in_vblank_irq, int *vpos,
1559                         int *hpos, ktime_t *stime, ktime_t *etime,
1560                         const struct drm_display_mode *mode)
1561 {
1562         struct drm_device *dev = crtc->dev;
1563         unsigned int pipe = crtc->index;
1564
1565         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1566                                                   stime, etime, mode);
1567 }
1568
1569 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1570 {
1571         struct drm_device *dev = adev_to_drm(adev);
1572         struct drm_crtc *crtc;
1573         struct drm_connector *connector;
1574         struct drm_connector_list_iter iter;
1575         int r;
1576
1577         /* turn off display hw */
1578         drm_modeset_lock_all(dev);
1579         drm_connector_list_iter_begin(dev, &iter);
1580         drm_for_each_connector_iter(connector, &iter)
1581                 drm_helper_connector_dpms(connector,
1582                                           DRM_MODE_DPMS_OFF);
1583         drm_connector_list_iter_end(&iter);
1584         drm_modeset_unlock_all(dev);
1585         /* unpin the front buffers and cursors */
1586         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1587                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1588                 struct drm_framebuffer *fb = crtc->primary->fb;
1589                 struct amdgpu_bo *robj;
1590
1591                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1592                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1593                         r = amdgpu_bo_reserve(aobj, true);
1594                         if (r == 0) {
1595                                 amdgpu_bo_unpin(aobj);
1596                                 amdgpu_bo_unreserve(aobj);
1597                         }
1598                 }
1599
1600                 if (fb == NULL || fb->obj[0] == NULL) {
1601                         continue;
1602                 }
1603                 robj = gem_to_amdgpu_bo(fb->obj[0]);
1604                 r = amdgpu_bo_reserve(robj, true);
1605                 if (r == 0) {
1606                         amdgpu_bo_unpin(robj);
1607                         amdgpu_bo_unreserve(robj);
1608                 }
1609         }
1610         return 0;
1611 }
1612
1613 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1614 {
1615         struct drm_device *dev = adev_to_drm(adev);
1616         struct drm_connector *connector;
1617         struct drm_connector_list_iter iter;
1618         struct drm_crtc *crtc;
1619         int r;
1620
1621         /* pin cursors */
1622         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1623                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1624
1625                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1626                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1627                         r = amdgpu_bo_reserve(aobj, true);
1628                         if (r == 0) {
1629                                 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1630                                 if (r != 0)
1631                                         dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1632                                 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1633                                 amdgpu_bo_unreserve(aobj);
1634                         }
1635                 }
1636         }
1637
1638         drm_helper_resume_force_mode(dev);
1639
1640         /* turn on display hw */
1641         drm_modeset_lock_all(dev);
1642
1643         drm_connector_list_iter_begin(dev, &iter);
1644         drm_for_each_connector_iter(connector, &iter)
1645                 drm_helper_connector_dpms(connector,
1646                                           DRM_MODE_DPMS_ON);
1647         drm_connector_list_iter_end(&iter);
1648
1649         drm_modeset_unlock_all(dev);
1650
1651         return 0;
1652 }
1653