drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <[email protected]>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 bool intel_format_is_yuv(u32 format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51         case DRM_FORMAT_NV12:
  52                 return true;
  53         default:
  54                 return false;
  55         }
  56 }
  57
  58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  59                              int usecs)
  60 {
  61         /* paranoia */
  62         if (!adjusted_mode->crtc_htotal)
  63                 return 1;
  64
  65         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  66                             1000 * adjusted_mode->crtc_htotal);
  67 }
  68
  69 /* FIXME: We should instead only take spinlocks once for the entire update
  70  * instead of once per mmio. */
  71 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  72 #define VBLANK_EVASION_TIME_US 250
  73 #else
  74 #define VBLANK_EVASION_TIME_US 100
  75 #endif
  76
  77 /**
  78  * intel_pipe_update_start() - start update of a set of display registers
  79  * @new_crtc_state: the new crtc state
  80  *
  81  * Mark the start of an update to pipe registers that should be updated
  82  * atomically regarding vblank. If the next vblank will happens within
  83  * the next 100 us, this function waits until the vblank passes.
  84  *
  85  * After a successful call to this function, interrupts will be disabled
  86  * until a subsequent call to intel_pipe_update_end(). That is done to
  87  * avoid random delays.
  88  */
  89 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  90 {
  91         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  92         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  93         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  94         long timeout = msecs_to_jiffies_timeout(1);
  95         int scanline, min, max, vblank_start;
  96         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  97         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  98                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  99         DEFINE_WAIT(wait);
 100
 101         vblank_start = adjusted_mode->crtc_vblank_start;
 102         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 103                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
 104
 105         /* FIXME needs to be calibrated sensibly */
 106         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
 107                                                       VBLANK_EVASION_TIME_US);
 108         max = vblank_start - 1;
 109
 110         if (min <= 0 || max <= 0)
 111                 goto irq_disable;
 112
 113         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 114                 goto irq_disable;
 115
 116         /*
 117          * Wait for psr to idle out after enabling the VBL interrupts
 118          * VBL interrupts will start the PSR exit and prevent a PSR
 119          * re-entry as well.
 120          */
 121         if (CAN_PSR(dev_priv) && intel_psr_wait_for_idle(dev_priv))
 122                 DRM_ERROR("PSR idle timed out, atomic update may fail\n");
 123
 124         local_irq_disable();
 125
 126         crtc->debug.min_vbl = min;
 127         crtc->debug.max_vbl = max;
 128         trace_i915_pipe_update_start(crtc);
 129
 130         for (;;) {
 131                 /*
 132                  * prepare_to_wait() has a memory barrier, which guarantees
 133                  * other CPUs can see the task state update by the time we
 134                  * read the scanline.
 135                  */
 136                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 137
 138                 scanline = intel_get_crtc_scanline(crtc);
 139                 if (scanline < min || scanline > max)
 140                         break;
 141
 142                 if (!timeout) {
 143                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 144                                   pipe_name(crtc->pipe));
 145                         break;
 146                 }
 147
 148                 local_irq_enable();
 149
 150                 timeout = schedule_timeout(timeout);
 151
 152                 local_irq_disable();
 153         }
 154
 155         finish_wait(wq, &wait);
 156
 157         drm_crtc_vblank_put(&crtc->base);
 158
 159         /*
 160          * On VLV/CHV DSI the scanline counter would appear to
 161          * increment approx. 1/3 of a scanline before start of vblank.
 162          * The registers still get latched at start of vblank however.
 163          * This means we must not write any registers on the first
 164          * line of vblank (since not the whole line is actually in
 165          * vblank). And unfortunately we can't use the interrupt to
 166          * wait here since it will fire too soon. We could use the
 167          * frame start interrupt instead since it will fire after the
 168          * critical scanline, but that would require more changes
 169          * in the interrupt code. So for now we'll just do the nasty
 170          * thing and poll for the bad scanline to pass us by.
 171          *
 172          * FIXME figure out if BXT+ DSI suffers from this as well
 173          */
 174         while (need_vlv_dsi_wa && scanline == vblank_start)
 175                 scanline = intel_get_crtc_scanline(crtc);
 176
 177         crtc->debug.scanline_start = scanline;
 178         crtc->debug.start_vbl_time = ktime_get();
 179         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 180
 181         trace_i915_pipe_update_vblank_evaded(crtc);
 182         return;
 183
 184 irq_disable:
 185         local_irq_disable();
 186 }
 187
 188 /**
 189  * intel_pipe_update_end() - end update of a set of display registers
 190  * @new_crtc_state: the new crtc state
 191  *
 192  * Mark the end of an update started with intel_pipe_update_start(). This
 193  * re-enables interrupts and verifies the update was actually completed
 194  * before a vblank.
 195  */
 196 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 197 {
 198         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 199         enum pipe pipe = crtc->pipe;
 200         int scanline_end = intel_get_crtc_scanline(crtc);
 201         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 202         ktime_t end_vbl_time = ktime_get();
 203         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 204
 205         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 206
 207         /* We're still in the vblank-evade critical section, this can't race.
 208          * Would be slightly nice to just grab the vblank count and arm the
 209          * event outside of the critical section - the spinlock might spin for a
 210          * while ... */
 211         if (new_crtc_state->base.event) {
 212                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 213
 214                 spin_lock(&crtc->base.dev->event_lock);
 215                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 216                 spin_unlock(&crtc->base.dev->event_lock);
 217
 218                 new_crtc_state->base.event = NULL;
 219         }
 220
 221         local_irq_enable();
 222
 223         if (intel_vgpu_active(dev_priv))
 224                 return;
 225
 226         if (crtc->debug.start_vbl_count &&
 227             crtc->debug.start_vbl_count != end_vbl_count) {
 228                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 229                           pipe_name(pipe), crtc->debug.start_vbl_count,
 230                           end_vbl_count,
 231                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 232                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 233                           crtc->debug.scanline_start, scanline_end);
 234         }
 235 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 236         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 237                  VBLANK_EVASION_TIME_US)
 238                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 239                          pipe_name(pipe),
 240                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 241                          VBLANK_EVASION_TIME_US);
 242 #endif
 243 }
 244
 245 void
 246 skl_update_plane(struct intel_plane *plane,
 247                  const struct intel_crtc_state *crtc_state,
 248                  const struct intel_plane_state *plane_state)
 249 {
 250         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 251         const struct drm_framebuffer *fb = plane_state->base.fb;
 252         enum plane_id plane_id = plane->id;
 253         enum pipe pipe = plane->pipe;
 254         u32 plane_ctl = plane_state->ctl;
 255         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 256         u32 surf_addr = plane_state->main.offset;
 257         unsigned int rotation = plane_state->base.rotation;
 258         u32 stride = skl_plane_stride(fb, 0, rotation);
 259         u32 aux_stride = skl_plane_stride(fb, 1, rotation);
 260         int crtc_x = plane_state->base.dst.x1;
 261         int crtc_y = plane_state->base.dst.y1;
 262         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 263         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 264         uint32_t x = plane_state->main.x;
 265         uint32_t y = plane_state->main.y;
 266         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 267         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 268         unsigned long irqflags;
 269
 270         /* Sizes are 0 based */
 271         src_w--;
 272         src_h--;
 273         crtc_w--;
 274         crtc_h--;
 275
 276         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 277
 278         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 279                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 280                               plane_state->color_ctl);
 281
 282         if (key->flags) {
 283                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 284                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 285                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 286         }
 287
 288         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 289         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 290         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 291         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 292                       (plane_state->aux.offset - surf_addr) | aux_stride);
 293         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 294                       (plane_state->aux.y << 16) | plane_state->aux.x);
 295
 296         /* program plane scaler */
 297         if (plane_state->scaler_id >= 0) {
 298                 int scaler_id = plane_state->scaler_id;
 299                 const struct intel_scaler *scaler =
 300                         &crtc_state->scaler_state.scalers[scaler_id];
 301                 u16 y_hphase, uv_rgb_hphase;
 302                 u16 y_vphase, uv_rgb_vphase;
 303
 304                 /* TODO: handle sub-pixel coordinates */
 305                 if (fb->format->format == DRM_FORMAT_NV12) {
 306                         y_hphase = skl_scaler_calc_phase(1, false);
 307                         y_vphase = skl_scaler_calc_phase(1, false);
 308
 309                         /* MPEG2 chroma siting convention */
 310                         uv_rgb_hphase = skl_scaler_calc_phase(2, true);
 311                         uv_rgb_vphase = skl_scaler_calc_phase(2, false);
 312                 } else {
 313                         /* not used */
 314                         y_hphase = 0;
 315                         y_vphase = 0;
 316
 317                         uv_rgb_hphase = skl_scaler_calc_phase(1, false);
 318                         uv_rgb_vphase = skl_scaler_calc_phase(1, false);
 319                 }
 320
 321                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 322                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 323                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 324                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
 325                               PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 326                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
 327                               PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 328                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 329                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 330                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 331
 332                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 333         } else {
 334                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 335         }
 336
 337         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 338         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 339                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 340         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 341
 342         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 343 }
 344
 345 void
 346 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 347 {
 348         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 349         enum plane_id plane_id = plane->id;
 350         enum pipe pipe = plane->pipe;
 351         unsigned long irqflags;
 352
 353         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 354
 355         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 356
 357         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 358         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 359
 360         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 361 }
 362
 363 bool
 364 skl_plane_get_hw_state(struct intel_plane *plane,
 365                        enum pipe *pipe)
 366 {
 367         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 368         enum intel_display_power_domain power_domain;
 369         enum plane_id plane_id = plane->id;
 370         bool ret;
 371
 372         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 373         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 374                 return false;
 375
 376         ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
 377
 378         *pipe = plane->pipe;
 379
 380         intel_display_power_put(dev_priv, power_domain);
 381
 382         return ret;
 383 }
 384
 385 static void
 386 chv_update_csc(const struct intel_plane_state *plane_state)
 387 {
 388         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 389         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 390         const struct drm_framebuffer *fb = plane_state->base.fb;
 391         enum plane_id plane_id = plane->id;
 392         /*
 393          * |r|   | c0 c1 c2 |   |cr|
 394          * |g| = | c3 c4 c5 | x |y |
 395          * |b|   | c6 c7 c8 |   |cb|
 396          *
 397          * Coefficients are s3.12.
 398          *
 399          * Cb and Cr apparently come in as signed already, and
 400          * we always get full range data in on account of CLRC0/1.
 401          */
 402         static const s16 csc_matrix[][9] = {
 403                 /* BT.601 full range YCbCr -> full range RGB */
 404                 [DRM_COLOR_YCBCR_BT601] = {
 405                          5743, 4096,     0,
 406                         -2925, 4096, -1410,
 407                             0, 4096,  7258,
 408                 },
 409                 /* BT.709 full range YCbCr -> full range RGB */
 410                 [DRM_COLOR_YCBCR_BT709] = {
 411                          6450, 4096,     0,
 412                         -1917, 4096,  -767,
 413                             0, 4096,  7601,
 414                 },
 415         };
 416         const s16 *csc = csc_matrix[plane_state->base.color_encoding];
 417
 418         /* Seems RGB data bypasses the CSC always */
 419         if (!intel_format_is_yuv(fb->format->format))
 420                 return;
 421
 422         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 423         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 424         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 425
 426         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
 427         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
 428         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
 429         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
 430         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
 431
 432         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
 433         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 434         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 435
 436         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 437         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 438         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 439 }
 440
 441 #define SIN_0 0
 442 #define COS_0 1
 443
 444 static void
 445 vlv_update_clrc(const struct intel_plane_state *plane_state)
 446 {
 447         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 448         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 449         const struct drm_framebuffer *fb = plane_state->base.fb;
 450         enum pipe pipe = plane->pipe;
 451         enum plane_id plane_id = plane->id;
 452         int contrast, brightness, sh_scale, sh_sin, sh_cos;
 453
 454         if (intel_format_is_yuv(fb->format->format) &&
 455             plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
 456                 /*
 457                  * Expand limited range to full range:
 458                  * Contrast is applied first and is used to expand Y range.
 459                  * Brightness is applied second and is used to remove the
 460                  * offset from Y. Saturation/hue is used to expand CbCr range.
 461                  */
 462                 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
 463                 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
 464                 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
 465                 sh_sin = SIN_0 * sh_scale;
 466                 sh_cos = COS_0 * sh_scale;
 467         } else {
 468                 /* Pass-through everything. */
 469                 contrast = 1 << 6;
 470                 brightness = 0;
 471                 sh_scale = 1 << 7;
 472                 sh_sin = SIN_0 * sh_scale;
 473                 sh_cos = COS_0 * sh_scale;
 474         }
 475
 476         /* FIXME these register are single buffered :( */
 477         I915_WRITE_FW(SPCLRC0(pipe, plane_id),
 478                       SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
 479         I915_WRITE_FW(SPCLRC1(pipe, plane_id),
 480                       SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
 481 }
 482
 483 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 484                           const struct intel_plane_state *plane_state)
 485 {
 486         const struct drm_framebuffer *fb = plane_state->base.fb;
 487         unsigned int rotation = plane_state->base.rotation;
 488         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 489         u32 sprctl;
 490
 491         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 492
 493         switch (fb->format->format) {
 494         case DRM_FORMAT_YUYV:
 495                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 496                 break;
 497         case DRM_FORMAT_YVYU:
 498                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 499                 break;
 500         case DRM_FORMAT_UYVY:
 501                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 502                 break;
 503         case DRM_FORMAT_VYUY:
 504                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 505                 break;
 506         case DRM_FORMAT_RGB565:
 507                 sprctl |= SP_FORMAT_BGR565;
 508                 break;
 509         case DRM_FORMAT_XRGB8888:
 510                 sprctl |= SP_FORMAT_BGRX8888;
 511                 break;
 512         case DRM_FORMAT_ARGB8888:
 513                 sprctl |= SP_FORMAT_BGRA8888;
 514                 break;
 515         case DRM_FORMAT_XBGR2101010:
 516                 sprctl |= SP_FORMAT_RGBX1010102;
 517                 break;
 518         case DRM_FORMAT_ABGR2101010:
 519                 sprctl |= SP_FORMAT_RGBA1010102;
 520                 break;
 521         case DRM_FORMAT_XBGR8888:
 522                 sprctl |= SP_FORMAT_RGBX8888;
 523                 break;
 524         case DRM_FORMAT_ABGR8888:
 525                 sprctl |= SP_FORMAT_RGBA8888;
 526                 break;
 527         default:
 528                 MISSING_CASE(fb->format->format);
 529                 return 0;
 530         }
 531
 532         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 533                 sprctl |= SP_YUV_FORMAT_BT709;
 534
 535         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 536                 sprctl |= SP_TILED;
 537
 538         if (rotation & DRM_MODE_ROTATE_180)
 539                 sprctl |= SP_ROTATE_180;
 540
 541         if (rotation & DRM_MODE_REFLECT_X)
 542                 sprctl |= SP_MIRROR;
 543
 544         if (key->flags & I915_SET_COLORKEY_SOURCE)
 545                 sprctl |= SP_SOURCE_KEY;
 546
 547         return sprctl;
 548 }
 549
 550 static void
 551 vlv_update_plane(struct intel_plane *plane,
 552                  const struct intel_crtc_state *crtc_state,
 553                  const struct intel_plane_state *plane_state)
 554 {
 555         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 556         const struct drm_framebuffer *fb = plane_state->base.fb;
 557         enum pipe pipe = plane->pipe;
 558         enum plane_id plane_id = plane->id;
 559         u32 sprctl = plane_state->ctl;
 560         u32 sprsurf_offset = plane_state->main.offset;
 561         u32 linear_offset;
 562         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 563         int crtc_x = plane_state->base.dst.x1;
 564         int crtc_y = plane_state->base.dst.y1;
 565         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 566         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 567         uint32_t x = plane_state->main.x;
 568         uint32_t y = plane_state->main.y;
 569         unsigned long irqflags;
 570
 571         /* Sizes are 0 based */
 572         crtc_w--;
 573         crtc_h--;
 574
 575         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 576
 577         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 578
 579         vlv_update_clrc(plane_state);
 580
 581         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 582                 chv_update_csc(plane_state);
 583
 584         if (key->flags) {
 585                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 586                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 587                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 588         }
 589         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 590         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 591
 592         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 593                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 594         else
 595                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 596
 597         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 598
 599         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 600         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 601         I915_WRITE_FW(SPSURF(pipe, plane_id),
 602                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 603         POSTING_READ_FW(SPSURF(pipe, plane_id));
 604
 605         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 606 }
 607
 608 static void
 609 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 610 {
 611         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 612         enum pipe pipe = plane->pipe;
 613         enum plane_id plane_id = plane->id;
 614         unsigned long irqflags;
 615
 616         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 617
 618         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 619
 620         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 621         POSTING_READ_FW(SPSURF(pipe, plane_id));
 622
 623         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 624 }
 625
 626 static bool
 627 vlv_plane_get_hw_state(struct intel_plane *plane,
 628                        enum pipe *pipe)
 629 {
 630         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 631         enum intel_display_power_domain power_domain;
 632         enum plane_id plane_id = plane->id;
 633         bool ret;
 634
 635         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 636         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 637                 return false;
 638
 639         ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
 640
 641         *pipe = plane->pipe;
 642
 643         intel_display_power_put(dev_priv, power_domain);
 644
 645         return ret;
 646 }
 647
 648 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 649                           const struct intel_plane_state *plane_state)
 650 {
 651         struct drm_i915_private *dev_priv =
 652                 to_i915(plane_state->base.plane->dev);
 653         const struct drm_framebuffer *fb = plane_state->base.fb;
 654         unsigned int rotation = plane_state->base.rotation;
 655         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 656         u32 sprctl;
 657
 658         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 659
 660         if (IS_IVYBRIDGE(dev_priv))
 661                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 662
 663         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 664                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 665
 666         switch (fb->format->format) {
 667         case DRM_FORMAT_XBGR8888:
 668                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 669                 break;
 670         case DRM_FORMAT_XRGB8888:
 671                 sprctl |= SPRITE_FORMAT_RGBX888;
 672                 break;
 673         case DRM_FORMAT_YUYV:
 674                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 675                 break;
 676         case DRM_FORMAT_YVYU:
 677                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 678                 break;
 679         case DRM_FORMAT_UYVY:
 680                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 681                 break;
 682         case DRM_FORMAT_VYUY:
 683                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 684                 break;
 685         default:
 686                 MISSING_CASE(fb->format->format);
 687                 return 0;
 688         }
 689
 690         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 691                 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
 692
 693         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 694                 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
 695
 696         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 697                 sprctl |= SPRITE_TILED;
 698
 699         if (rotation & DRM_MODE_ROTATE_180)
 700                 sprctl |= SPRITE_ROTATE_180;
 701
 702         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 703                 sprctl |= SPRITE_DEST_KEY;
 704         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 705                 sprctl |= SPRITE_SOURCE_KEY;
 706
 707         return sprctl;
 708 }
 709
 710 static void
 711 ivb_update_plane(struct intel_plane *plane,
 712                  const struct intel_crtc_state *crtc_state,
 713                  const struct intel_plane_state *plane_state)
 714 {
 715         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 716         const struct drm_framebuffer *fb = plane_state->base.fb;
 717         enum pipe pipe = plane->pipe;
 718         u32 sprctl = plane_state->ctl, sprscale = 0;
 719         u32 sprsurf_offset = plane_state->main.offset;
 720         u32 linear_offset;
 721         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 722         int crtc_x = plane_state->base.dst.x1;
 723         int crtc_y = plane_state->base.dst.y1;
 724         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 725         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 726         uint32_t x = plane_state->main.x;
 727         uint32_t y = plane_state->main.y;
 728         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 729         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 730         unsigned long irqflags;
 731
 732         /* Sizes are 0 based */
 733         src_w--;
 734         src_h--;
 735         crtc_w--;
 736         crtc_h--;
 737
 738         if (crtc_w != src_w || crtc_h != src_h)
 739                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 740
 741         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 742
 743         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 744
 745         if (key->flags) {
 746                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 747                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 748                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 749         }
 750
 751         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 752         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 753
 754         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 755          * register */
 756         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 757                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 758         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 759                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 760         else
 761                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 762
 763         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 764         if (plane->can_scale)
 765                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 766         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 767         I915_WRITE_FW(SPRSURF(pipe),
 768                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 769         POSTING_READ_FW(SPRSURF(pipe));
 770
 771         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 772 }
 773
 774 static void
 775 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 776 {
 777         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 778         enum pipe pipe = plane->pipe;
 779         unsigned long irqflags;
 780
 781         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 782
 783         I915_WRITE_FW(SPRCTL(pipe), 0);
 784         /* Can't leave the scaler enabled... */
 785         if (plane->can_scale)
 786                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 787
 788         I915_WRITE_FW(SPRSURF(pipe), 0);
 789         POSTING_READ_FW(SPRSURF(pipe));
 790
 791         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 792 }
 793
 794 static bool
 795 ivb_plane_get_hw_state(struct intel_plane *plane,
 796                        enum pipe *pipe)
 797 {
 798         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 799         enum intel_display_power_domain power_domain;
 800         bool ret;
 801
 802         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 803         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 804                 return false;
 805
 806         ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
 807
 808         *pipe = plane->pipe;
 809
 810         intel_display_power_put(dev_priv, power_domain);
 811
 812         return ret;
 813 }
 814
 815 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 816                           const struct intel_plane_state *plane_state)
 817 {
 818         struct drm_i915_private *dev_priv =
 819                 to_i915(plane_state->base.plane->dev);
 820         const struct drm_framebuffer *fb = plane_state->base.fb;
 821         unsigned int rotation = plane_state->base.rotation;
 822         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 823         u32 dvscntr;
 824
 825         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 826
 827         if (IS_GEN6(dev_priv))
 828                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 829
 830         switch (fb->format->format) {
 831         case DRM_FORMAT_XBGR8888:
 832                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 833                 break;
 834         case DRM_FORMAT_XRGB8888:
 835                 dvscntr |= DVS_FORMAT_RGBX888;
 836                 break;
 837         case DRM_FORMAT_YUYV:
 838                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 839                 break;
 840         case DRM_FORMAT_YVYU:
 841                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 842                 break;
 843         case DRM_FORMAT_UYVY:
 844                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 845                 break;
 846         case DRM_FORMAT_VYUY:
 847                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 848                 break;
 849         default:
 850                 MISSING_CASE(fb->format->format);
 851                 return 0;
 852         }
 853
 854         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 855                 dvscntr |= DVS_YUV_FORMAT_BT709;
 856
 857         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 858                 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
 859
 860         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 861                 dvscntr |= DVS_TILED;
 862
 863         if (rotation & DRM_MODE_ROTATE_180)
 864                 dvscntr |= DVS_ROTATE_180;
 865
 866         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 867                 dvscntr |= DVS_DEST_KEY;
 868         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 869                 dvscntr |= DVS_SOURCE_KEY;
 870
 871         return dvscntr;
 872 }
 873
 874 static void
 875 g4x_update_plane(struct intel_plane *plane,
 876                  const struct intel_crtc_state *crtc_state,
 877                  const struct intel_plane_state *plane_state)
 878 {
 879         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 880         const struct drm_framebuffer *fb = plane_state->base.fb;
 881         enum pipe pipe = plane->pipe;
 882         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 883         u32 dvssurf_offset = plane_state->main.offset;
 884         u32 linear_offset;
 885         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 886         int crtc_x = plane_state->base.dst.x1;
 887         int crtc_y = plane_state->base.dst.y1;
 888         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 889         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 890         uint32_t x = plane_state->main.x;
 891         uint32_t y = plane_state->main.y;
 892         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 893         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 894         unsigned long irqflags;
 895
 896         /* Sizes are 0 based */
 897         src_w--;
 898         src_h--;
 899         crtc_w--;
 900         crtc_h--;
 901
 902         if (crtc_w != src_w || crtc_h != src_h)
 903                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 904
 905         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 906
 907         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 908
 909         if (key->flags) {
 910                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 911                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 912                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 913         }
 914
 915         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 916         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 917
 918         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 919                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 920         else
 921                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 922
 923         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 924         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 925         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 926         I915_WRITE_FW(DVSSURF(pipe),
 927                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 928         POSTING_READ_FW(DVSSURF(pipe));
 929
 930         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 931 }
 932
 933 static void
 934 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 935 {
 936         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 937         enum pipe pipe = plane->pipe;
 938         unsigned long irqflags;
 939
 940         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 941
 942         I915_WRITE_FW(DVSCNTR(pipe), 0);
 943         /* Disable the scaler */
 944         I915_WRITE_FW(DVSSCALE(pipe), 0);
 945
 946         I915_WRITE_FW(DVSSURF(pipe), 0);
 947         POSTING_READ_FW(DVSSURF(pipe));
 948
 949         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 950 }
 951
 952 static bool
 953 g4x_plane_get_hw_state(struct intel_plane *plane,
 954                        enum pipe *pipe)
 955 {
 956         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 957         enum intel_display_power_domain power_domain;
 958         bool ret;
 959
 960         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 961         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 962                 return false;
 963
 964         ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
 965
 966         *pipe = plane->pipe;
 967
 968         intel_display_power_put(dev_priv, power_domain);
 969
 970         return ret;
 971 }
 972
 973 static int
 974 intel_check_sprite_plane(struct intel_plane *plane,
 975                          struct intel_crtc_state *crtc_state,
 976                          struct intel_plane_state *state)
 977 {
 978         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 979         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 980         struct drm_framebuffer *fb = state->base.fb;
 981         int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
 982         int max_scale, min_scale;
 983         bool can_scale;
 984         int ret;
 985         uint32_t pixel_format = 0;
 986
 987         if (!fb) {
 988                 state->base.visible = false;
 989                 return 0;
 990         }
 991
 992         /* Don't modify another pipe's plane */
 993         if (plane->pipe != crtc->pipe) {
 994                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 995                 return -EINVAL;
 996         }
 997
 998         /* FIXME check all gen limits */
 999         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > max_stride) {
1000                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
1001                 return -EINVAL;
1002         }
1003
1004         /* setup can_scale, min_scale, max_scale */
1005         if (INTEL_GEN(dev_priv) >= 9) {
1006                 if (state->base.fb)
1007                         pixel_format = state->base.fb->format->format;
1008                 /* use scaler when colorkey is not required */
1009                 if (!state->ckey.flags) {
1010                         can_scale = 1;
1011                         min_scale = 1;
1012                         max_scale =
1013                                 skl_max_scale(crtc, crtc_state, pixel_format);
1014                 } else {
1015                         can_scale = 0;
1016                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
1017                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
1018                 }
1019         } else {
1020                 can_scale = plane->can_scale;
1021                 max_scale = plane->max_downscale << 16;
1022                 min_scale = plane->can_scale ? 1 : (1 << 16);
1023         }
1024
1025         ret = drm_atomic_helper_check_plane_state(&state->base,
1026                                                   &crtc_state->base,
1027                                                   min_scale, max_scale,
1028                                                   true, true);
1029         if (ret)
1030                 return ret;
1031
1032         if (state->base.visible) {
1033                 struct drm_rect *src = &state->base.src;
1034                 struct drm_rect *dst = &state->base.dst;
1035                 unsigned int crtc_w = drm_rect_width(dst);
1036                 unsigned int crtc_h = drm_rect_height(dst);
1037                 uint32_t src_x, src_y, src_w, src_h;
1038
1039                 /*
1040                  * Hardware doesn't handle subpixel coordinates.
1041                  * Adjust to (macro)pixel boundary, but be careful not to
1042                  * increase the source viewport size, because that could
1043                  * push the downscaling factor out of bounds.
1044                  */
1045                 src_x = src->x1 >> 16;
1046                 src_w = drm_rect_width(src) >> 16;
1047                 src_y = src->y1 >> 16;
1048                 src_h = drm_rect_height(src) >> 16;
1049
1050                 src->x1 = src_x << 16;
1051                 src->x2 = (src_x + src_w) << 16;
1052                 src->y1 = src_y << 16;
1053                 src->y2 = (src_y + src_h) << 16;
1054
1055                 if (intel_format_is_yuv(fb->format->format) &&
1056                     fb->format->format != DRM_FORMAT_NV12 &&
1057                     (src_x % 2 || src_w % 2)) {
1058                         DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
1059                                       src_x, src_w);
1060                         return -EINVAL;
1061                 }
1062
1063                 /* Check size restrictions when scaling */
1064                 if (src_w != crtc_w || src_h != crtc_h) {
1065                         unsigned int width_bytes;
1066                         int cpp = fb->format->cpp[0];
1067
1068                         WARN_ON(!can_scale);
1069
1070                         width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1071
1072                         /* FIXME interlacing min height is 6 */
1073                         if (INTEL_GEN(dev_priv) < 9 && (
1074                              src_w < 3 || src_h < 3 ||
1075                              src_w > 2048 || src_h > 2048 ||
1076                              crtc_w < 3 || crtc_h < 3 ||
1077                              width_bytes > 4096 || fb->pitches[0] > 4096)) {
1078                                 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1079                                 return -EINVAL;
1080                         }
1081                 }
1082         }
1083
1084         if (INTEL_GEN(dev_priv) >= 9) {
1085                 ret = skl_check_plane_surface(crtc_state, state);
1086                 if (ret)
1087                         return ret;
1088
1089                 state->ctl = skl_plane_ctl(crtc_state, state);
1090         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1091                 ret = i9xx_check_plane_surface(state);
1092                 if (ret)
1093                         return ret;
1094
1095                 state->ctl = vlv_sprite_ctl(crtc_state, state);
1096         } else if (INTEL_GEN(dev_priv) >= 7) {
1097                 ret = i9xx_check_plane_surface(state);
1098                 if (ret)
1099                         return ret;
1100
1101                 state->ctl = ivb_sprite_ctl(crtc_state, state);
1102         } else {
1103                 ret = i9xx_check_plane_surface(state);
1104                 if (ret)
1105                         return ret;
1106
1107                 state->ctl = g4x_sprite_ctl(crtc_state, state);
1108         }
1109
1110         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1111                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
1112
1113         return 0;
1114 }
1115
1116 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
1117 {
1118         return INTEL_GEN(dev_priv) >= 9;
1119 }
1120
1121 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
1122                                  const struct drm_intel_sprite_colorkey *set)
1123 {
1124         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1125         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1126         struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1127
1128         *key = *set;
1129
1130         /*
1131          * We want src key enabled on the
1132          * sprite and not on the primary.
1133          */
1134         if (plane->id == PLANE_PRIMARY &&
1135             set->flags & I915_SET_COLORKEY_SOURCE)
1136                 key->flags = 0;
1137
1138         /*
1139          * On SKL+ we want dst key enabled on
1140          * the primary and not on the sprite.
1141          */
1142         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
1143             set->flags & I915_SET_COLORKEY_DESTINATION)
1144                 key->flags = 0;
1145 }
1146
1147 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1148                                     struct drm_file *file_priv)
1149 {
1150         struct drm_i915_private *dev_priv = to_i915(dev);
1151         struct drm_intel_sprite_colorkey *set = data;
1152         struct drm_plane *plane;
1153         struct drm_plane_state *plane_state;
1154         struct drm_atomic_state *state;
1155         struct drm_modeset_acquire_ctx ctx;
1156         int ret = 0;
1157
1158         /* ignore the pointless "none" flag */
1159         set->flags &= ~I915_SET_COLORKEY_NONE;
1160
1161         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1162                 return -EINVAL;
1163
1164         /* Make sure we don't try to enable both src & dest simultaneously */
1165         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1166                 return -EINVAL;
1167
1168         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1169             set->flags & I915_SET_COLORKEY_DESTINATION)
1170                 return -EINVAL;
1171
1172         plane = drm_plane_find(dev, file_priv, set->plane_id);
1173         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1174                 return -ENOENT;
1175
1176         /*
1177          * SKL+ only plane 2 can do destination keying against plane 1.
1178          * Also multiple planes can't do destination keying on the same
1179          * pipe simultaneously.
1180          */
1181         if (INTEL_GEN(dev_priv) >= 9 &&
1182             to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
1183             set->flags & I915_SET_COLORKEY_DESTINATION)
1184                 return -EINVAL;
1185
1186         drm_modeset_acquire_init(&ctx, 0);
1187
1188         state = drm_atomic_state_alloc(plane->dev);
1189         if (!state) {
1190                 ret = -ENOMEM;
1191                 goto out;
1192         }
1193         state->acquire_ctx = &ctx;
1194
1195         while (1) {
1196                 plane_state = drm_atomic_get_plane_state(state, plane);
1197                 ret = PTR_ERR_OR_ZERO(plane_state);
1198                 if (!ret)
1199                         intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1200
1201                 /*
1202                  * On some platforms we have to configure
1203                  * the dst colorkey on the primary plane.
1204                  */
1205                 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
1206                         struct intel_crtc *crtc =
1207                                 intel_get_crtc_for_pipe(dev_priv,
1208                                                         to_intel_plane(plane)->pipe);
1209
1210                         plane_state = drm_atomic_get_plane_state(state,
1211                                                                  crtc->base.primary);
1212                         ret = PTR_ERR_OR_ZERO(plane_state);
1213                         if (!ret)
1214                                 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1215                 }
1216
1217                 if (!ret)
1218                         ret = drm_atomic_commit(state);
1219
1220                 if (ret != -EDEADLK)
1221                         break;
1222
1223                 drm_atomic_state_clear(state);
1224                 drm_modeset_backoff(&ctx);
1225         }
1226
1227         drm_atomic_state_put(state);
1228 out:
1229         drm_modeset_drop_locks(&ctx);
1230         drm_modeset_acquire_fini(&ctx);
1231         return ret;
1232 }
1233
1234 static const uint32_t g4x_plane_formats[] = {
1235         DRM_FORMAT_XRGB8888,
1236         DRM_FORMAT_YUYV,
1237         DRM_FORMAT_YVYU,
1238         DRM_FORMAT_UYVY,
1239         DRM_FORMAT_VYUY,
1240 };
1241
1242 static const uint64_t i9xx_plane_format_modifiers[] = {
1243         I915_FORMAT_MOD_X_TILED,
1244         DRM_FORMAT_MOD_LINEAR,
1245         DRM_FORMAT_MOD_INVALID
1246 };
1247
1248 static const uint32_t snb_plane_formats[] = {
1249         DRM_FORMAT_XBGR8888,
1250         DRM_FORMAT_XRGB8888,
1251         DRM_FORMAT_YUYV,
1252         DRM_FORMAT_YVYU,
1253         DRM_FORMAT_UYVY,
1254         DRM_FORMAT_VYUY,
1255 };
1256
1257 static const uint32_t vlv_plane_formats[] = {
1258         DRM_FORMAT_RGB565,
1259         DRM_FORMAT_ABGR8888,
1260         DRM_FORMAT_ARGB8888,
1261         DRM_FORMAT_XBGR8888,
1262         DRM_FORMAT_XRGB8888,
1263         DRM_FORMAT_XBGR2101010,
1264         DRM_FORMAT_ABGR2101010,
1265         DRM_FORMAT_YUYV,
1266         DRM_FORMAT_YVYU,
1267         DRM_FORMAT_UYVY,
1268         DRM_FORMAT_VYUY,
1269 };
1270
1271 static uint32_t skl_plane_formats[] = {
1272         DRM_FORMAT_RGB565,
1273         DRM_FORMAT_ABGR8888,
1274         DRM_FORMAT_ARGB8888,
1275         DRM_FORMAT_XBGR8888,
1276         DRM_FORMAT_XRGB8888,
1277         DRM_FORMAT_YUYV,
1278         DRM_FORMAT_YVYU,
1279         DRM_FORMAT_UYVY,
1280         DRM_FORMAT_VYUY,
1281 };
1282
1283 static uint32_t skl_planar_formats[] = {
1284         DRM_FORMAT_RGB565,
1285         DRM_FORMAT_ABGR8888,
1286         DRM_FORMAT_ARGB8888,
1287         DRM_FORMAT_XBGR8888,
1288         DRM_FORMAT_XRGB8888,
1289         DRM_FORMAT_YUYV,
1290         DRM_FORMAT_YVYU,
1291         DRM_FORMAT_UYVY,
1292         DRM_FORMAT_VYUY,
1293         DRM_FORMAT_NV12,
1294 };
1295
1296 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1297         I915_FORMAT_MOD_Yf_TILED,
1298         I915_FORMAT_MOD_Y_TILED,
1299         I915_FORMAT_MOD_X_TILED,
1300         DRM_FORMAT_MOD_LINEAR,
1301         DRM_FORMAT_MOD_INVALID
1302 };
1303
1304 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1305         I915_FORMAT_MOD_Yf_TILED_CCS,
1306         I915_FORMAT_MOD_Y_TILED_CCS,
1307         I915_FORMAT_MOD_Yf_TILED,
1308         I915_FORMAT_MOD_Y_TILED,
1309         I915_FORMAT_MOD_X_TILED,
1310         DRM_FORMAT_MOD_LINEAR,
1311         DRM_FORMAT_MOD_INVALID
1312 };
1313
1314 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1315                                             u32 format, u64 modifier)
1316 {
1317         switch (modifier) {
1318         case DRM_FORMAT_MOD_LINEAR:
1319         case I915_FORMAT_MOD_X_TILED:
1320                 break;
1321         default:
1322                 return false;
1323         }
1324
1325         switch (format) {
1326         case DRM_FORMAT_XRGB8888:
1327         case DRM_FORMAT_YUYV:
1328         case DRM_FORMAT_YVYU:
1329         case DRM_FORMAT_UYVY:
1330         case DRM_FORMAT_VYUY:
1331                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1332                     modifier == I915_FORMAT_MOD_X_TILED)
1333                         return true;
1334                 /* fall through */
1335         default:
1336                 return false;
1337         }
1338 }
1339
1340 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1341                                             u32 format, u64 modifier)
1342 {
1343         switch (modifier) {
1344         case DRM_FORMAT_MOD_LINEAR:
1345         case I915_FORMAT_MOD_X_TILED:
1346                 break;
1347         default:
1348                 return false;
1349         }
1350
1351         switch (format) {
1352         case DRM_FORMAT_XRGB8888:
1353         case DRM_FORMAT_XBGR8888:
1354         case DRM_FORMAT_YUYV:
1355         case DRM_FORMAT_YVYU:
1356         case DRM_FORMAT_UYVY:
1357         case DRM_FORMAT_VYUY:
1358                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1359                     modifier == I915_FORMAT_MOD_X_TILED)
1360                         return true;
1361                 /* fall through */
1362         default:
1363                 return false;
1364         }
1365 }
1366
1367 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1368                                             u32 format, u64 modifier)
1369 {
1370         switch (modifier) {
1371         case DRM_FORMAT_MOD_LINEAR:
1372         case I915_FORMAT_MOD_X_TILED:
1373                 break;
1374         default:
1375                 return false;
1376         }
1377
1378         switch (format) {
1379         case DRM_FORMAT_RGB565:
1380         case DRM_FORMAT_ABGR8888:
1381         case DRM_FORMAT_ARGB8888:
1382         case DRM_FORMAT_XBGR8888:
1383         case DRM_FORMAT_XRGB8888:
1384         case DRM_FORMAT_XBGR2101010:
1385         case DRM_FORMAT_ABGR2101010:
1386         case DRM_FORMAT_YUYV:
1387         case DRM_FORMAT_YVYU:
1388         case DRM_FORMAT_UYVY:
1389         case DRM_FORMAT_VYUY:
1390                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1391                     modifier == I915_FORMAT_MOD_X_TILED)
1392                         return true;
1393                 /* fall through */
1394         default:
1395                 return false;
1396         }
1397 }
1398
1399 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1400                                            u32 format, u64 modifier)
1401 {
1402         struct intel_plane *plane = to_intel_plane(_plane);
1403
1404         switch (modifier) {
1405         case DRM_FORMAT_MOD_LINEAR:
1406         case I915_FORMAT_MOD_X_TILED:
1407         case I915_FORMAT_MOD_Y_TILED:
1408         case I915_FORMAT_MOD_Yf_TILED:
1409                 break;
1410         case I915_FORMAT_MOD_Y_TILED_CCS:
1411         case I915_FORMAT_MOD_Yf_TILED_CCS:
1412                 if (!plane->has_ccs)
1413                         return false;
1414                 break;
1415         default:
1416                 return false;
1417         }
1418
1419         switch (format) {
1420         case DRM_FORMAT_XRGB8888:
1421         case DRM_FORMAT_XBGR8888:
1422         case DRM_FORMAT_ARGB8888:
1423         case DRM_FORMAT_ABGR8888:
1424                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
1425                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
1426                         return true;
1427                 /* fall through */
1428         case DRM_FORMAT_RGB565:
1429         case DRM_FORMAT_XRGB2101010:
1430         case DRM_FORMAT_XBGR2101010:
1431         case DRM_FORMAT_YUYV:
1432         case DRM_FORMAT_YVYU:
1433         case DRM_FORMAT_UYVY:
1434         case DRM_FORMAT_VYUY:
1435         case DRM_FORMAT_NV12:
1436                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1437                         return true;
1438                 /* fall through */
1439         case DRM_FORMAT_C8:
1440                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1441                     modifier == I915_FORMAT_MOD_X_TILED ||
1442                     modifier == I915_FORMAT_MOD_Y_TILED)
1443                         return true;
1444                 /* fall through */
1445         default:
1446                 return false;
1447         }
1448 }
1449
1450 static const struct drm_plane_funcs g4x_sprite_funcs = {
1451         .update_plane = drm_atomic_helper_update_plane,
1452         .disable_plane = drm_atomic_helper_disable_plane,
1453         .destroy = intel_plane_destroy,
1454         .atomic_get_property = intel_plane_atomic_get_property,
1455         .atomic_set_property = intel_plane_atomic_set_property,
1456         .atomic_duplicate_state = intel_plane_duplicate_state,
1457         .atomic_destroy_state = intel_plane_destroy_state,
1458         .format_mod_supported = g4x_sprite_format_mod_supported,
1459 };
1460
1461 static const struct drm_plane_funcs snb_sprite_funcs = {
1462         .update_plane = drm_atomic_helper_update_plane,
1463         .disable_plane = drm_atomic_helper_disable_plane,
1464         .destroy = intel_plane_destroy,
1465         .atomic_get_property = intel_plane_atomic_get_property,
1466         .atomic_set_property = intel_plane_atomic_set_property,
1467         .atomic_duplicate_state = intel_plane_duplicate_state,
1468         .atomic_destroy_state = intel_plane_destroy_state,
1469         .format_mod_supported = snb_sprite_format_mod_supported,
1470 };
1471
1472 static const struct drm_plane_funcs vlv_sprite_funcs = {
1473         .update_plane = drm_atomic_helper_update_plane,
1474         .disable_plane = drm_atomic_helper_disable_plane,
1475         .destroy = intel_plane_destroy,
1476         .atomic_get_property = intel_plane_atomic_get_property,
1477         .atomic_set_property = intel_plane_atomic_set_property,
1478         .atomic_duplicate_state = intel_plane_duplicate_state,
1479         .atomic_destroy_state = intel_plane_destroy_state,
1480         .format_mod_supported = vlv_sprite_format_mod_supported,
1481 };
1482
1483 static const struct drm_plane_funcs skl_plane_funcs = {
1484         .update_plane = drm_atomic_helper_update_plane,
1485         .disable_plane = drm_atomic_helper_disable_plane,
1486         .destroy = intel_plane_destroy,
1487         .atomic_get_property = intel_plane_atomic_get_property,
1488         .atomic_set_property = intel_plane_atomic_set_property,
1489         .atomic_duplicate_state = intel_plane_duplicate_state,
1490         .atomic_destroy_state = intel_plane_destroy_state,
1491         .format_mod_supported = skl_plane_format_mod_supported,
1492 };
1493
1494 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1495                        enum pipe pipe, enum plane_id plane_id)
1496 {
1497         if (plane_id == PLANE_CURSOR)
1498                 return false;
1499
1500         if (INTEL_GEN(dev_priv) >= 10)
1501                 return true;
1502
1503         if (IS_GEMINILAKE(dev_priv))
1504                 return pipe != PIPE_C;
1505
1506         return pipe != PIPE_C &&
1507                 (plane_id == PLANE_PRIMARY ||
1508                  plane_id == PLANE_SPRITE0);
1509 }
1510
1511 struct intel_plane *
1512 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1513                           enum pipe pipe, int plane)
1514 {
1515         struct intel_plane *intel_plane = NULL;
1516         struct intel_plane_state *state = NULL;
1517         const struct drm_plane_funcs *plane_funcs;
1518         unsigned long possible_crtcs;
1519         const uint32_t *plane_formats;
1520         const uint64_t *modifiers;
1521         unsigned int supported_rotations;
1522         int num_plane_formats;
1523         int ret;
1524
1525         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1526         if (!intel_plane) {
1527                 ret = -ENOMEM;
1528                 goto fail;
1529         }
1530
1531         state = intel_create_plane_state(&intel_plane->base);
1532         if (!state) {
1533                 ret = -ENOMEM;
1534                 goto fail;
1535         }
1536         intel_plane->base.state = &state->base;
1537
1538         if (INTEL_GEN(dev_priv) >= 9) {
1539                 intel_plane->can_scale = true;
1540                 state->scaler_id = -1;
1541
1542                 intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
1543                                                          PLANE_SPRITE0 + plane);
1544
1545                 intel_plane->update_plane = skl_update_plane;
1546                 intel_plane->disable_plane = skl_disable_plane;
1547                 intel_plane->get_hw_state = skl_plane_get_hw_state;
1548
1549                 if (skl_plane_has_planar(dev_priv, pipe,
1550                                          PLANE_SPRITE0 + plane)) {
1551                         plane_formats = skl_planar_formats;
1552                         num_plane_formats = ARRAY_SIZE(skl_planar_formats);
1553                 } else {
1554                         plane_formats = skl_plane_formats;
1555                         num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1556                 }
1557
1558                 if (intel_plane->has_ccs)
1559                         modifiers = skl_plane_format_modifiers_ccs;
1560                 else
1561                         modifiers = skl_plane_format_modifiers_noccs;
1562
1563                 plane_funcs = &skl_plane_funcs;
1564         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1565                 intel_plane->can_scale = false;
1566                 intel_plane->max_downscale = 1;
1567
1568                 intel_plane->update_plane = vlv_update_plane;
1569                 intel_plane->disable_plane = vlv_disable_plane;
1570                 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1571
1572                 plane_formats = vlv_plane_formats;
1573                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1574                 modifiers = i9xx_plane_format_modifiers;
1575
1576                 plane_funcs = &vlv_sprite_funcs;
1577         } else if (INTEL_GEN(dev_priv) >= 7) {
1578                 if (IS_IVYBRIDGE(dev_priv)) {
1579                         intel_plane->can_scale = true;
1580                         intel_plane->max_downscale = 2;
1581                 } else {
1582                         intel_plane->can_scale = false;
1583                         intel_plane->max_downscale = 1;
1584                 }
1585
1586                 intel_plane->update_plane = ivb_update_plane;
1587                 intel_plane->disable_plane = ivb_disable_plane;
1588                 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1589
1590                 plane_formats = snb_plane_formats;
1591                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1592                 modifiers = i9xx_plane_format_modifiers;
1593
1594                 plane_funcs = &snb_sprite_funcs;
1595         } else {
1596                 intel_plane->can_scale = true;
1597                 intel_plane->max_downscale = 16;
1598
1599                 intel_plane->update_plane = g4x_update_plane;
1600                 intel_plane->disable_plane = g4x_disable_plane;
1601                 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1602
1603                 modifiers = i9xx_plane_format_modifiers;
1604                 if (IS_GEN6(dev_priv)) {
1605                         plane_formats = snb_plane_formats;
1606                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1607
1608                         plane_funcs = &snb_sprite_funcs;
1609                 } else {
1610                         plane_formats = g4x_plane_formats;
1611                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1612
1613                         plane_funcs = &g4x_sprite_funcs;
1614                 }
1615         }
1616
1617         if (INTEL_GEN(dev_priv) >= 9) {
1618                 supported_rotations =
1619                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1620                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1621         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1622                 supported_rotations =
1623                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1624                         DRM_MODE_REFLECT_X;
1625         } else {
1626                 supported_rotations =
1627                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1628         }
1629
1630         intel_plane->pipe = pipe;
1631         intel_plane->i9xx_plane = plane;
1632         intel_plane->id = PLANE_SPRITE0 + plane;
1633         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1634         intel_plane->check_plane = intel_check_sprite_plane;
1635
1636         possible_crtcs = (1 << pipe);
1637
1638         if (INTEL_GEN(dev_priv) >= 9)
1639                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1640                                                possible_crtcs, plane_funcs,
1641                                                plane_formats, num_plane_formats,
1642                                                modifiers,
1643                                                DRM_PLANE_TYPE_OVERLAY,
1644                                                "plane %d%c", plane + 2, pipe_name(pipe));
1645         else
1646                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1647                                                possible_crtcs, plane_funcs,
1648                                                plane_formats, num_plane_formats,
1649                                                modifiers,
1650                                                DRM_PLANE_TYPE_OVERLAY,
1651                                                "sprite %c", sprite_name(pipe, plane));
1652         if (ret)
1653                 goto fail;
1654
1655         drm_plane_create_rotation_property(&intel_plane->base,
1656                                            DRM_MODE_ROTATE_0,
1657                                            supported_rotations);
1658
1659         drm_plane_create_color_properties(&intel_plane->base,
1660                                           BIT(DRM_COLOR_YCBCR_BT601) |
1661                                           BIT(DRM_COLOR_YCBCR_BT709),
1662                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1663                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1664                                           DRM_COLOR_YCBCR_BT709,
1665                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1666
1667         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1668
1669         return intel_plane;
1670
1671 fail:
1672         kfree(state);
1673         kfree(intel_plane);
1674
1675         return ERR_PTR(ret);
1676 }